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    The Next Generation Challenge for

    Software Defined Radio

    Mark Woh1, Sangwon Seo1, Hyunseok Lee1, Yuan Lin1,

    Scott Mahlke1, Trevor Mudge1, Chaitali Chakrabarti2, Krisztian Flautner3

    1

    Advanced Computer Architecture Lab, University of Michigan2Department of Electrical Engineering, Arizona State University3ARM, Ltd.

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    3G Wireless

    Large Coverage

    Outdoor - High Mobility

    Up to 14Mbps

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    Expected Wireless Growth

    The growth of wireless will require more bandwidth

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    4G Wireless

    What we need

    Adaptive high performance transmission system

    Great candidate for SDR

    Large Coverage 100Mbps Coverage

    Outdoor - High Mobility

    Macro CellsPico Cells

    Isolated HotSpots 1Gbps Coverage

    Indoor Very Low Mobility

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    Next Generation Wireless 4G

    MIMO

    decoder

    DEMOD

    (OFDM)

    Channel

    Decoder

    MIMOencoder

    MOD(OFDM)

    ChannelEncoder

    .

    ..

    ..

    .

    IFFT

    FFT STBC

    VBLAST

    ..

    .

    Turbo code

    LDPC code

    TX

    RX

    Antenna

    .

    ..

    3 Major Components to 4G

    Modulation/Demodulation

    Multiple-Input Multiple-Out (MIMO)

    Channel Decoder/Encoders

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    Modulation - OFDM

    0 fsc Nfsc

    ..

    -Nfsc -fsc

    Properties of OFDM-High Spectral Efficiency

    -Low Intersymbol Intereference

    -Flat Fading Subcarriers

    Can sustain high data rates with

    multiple users

    Can be implemented with IFFT/FFT

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    Major Component of Modulation FFT/IFFT

    Very wide data level parallelism

    Requires complex operations

    complex

    mult

    x[1]

    eiw

    complex

    add

    complex

    sub

    x[0]

    X[1]

    X[0]

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    MIMO (Multiple Input Multiple Out)

    Previously we used single antenna systems

    Now we use multiple antennas to increase the channel

    capacity

    Diversity - High Reliability

    Space Time Block Codes (STBC)

    Multiplexing High Throughput

    Vertical-BLAST (V-BLAST)

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    Space Time Block Codes (STBC)

    CombinerChannel

    Estimation

    Channel

    Estimation

    Tx1 Tx2Transmit Antennas

    x[1]

    -x[2]*

    x[2]

    x[1]*

    h11 h22

    h21 h12

    Channel

    Rx1 Rx2

    Time

    Receive Antennas

    n11

    n12

    n21

    n22

    ~x[1]

    ~x[2]

    h11

    h12 h22

    h21

    Noise

    y11 = h11x[1] + h12x[2] + n11

    y12 = -h11x[2]* + h12x[1]* + n12

    y21 = h21x[1] + h22x[2] + n21

    y22 = -h21x[2]* + h22x[1]* + n22

    Received

    Signal

    ~x[1] = h11*y11 + h12y12* + h21*y21 + h22y22*

    ~x[2] = h12*y11 - h11y12* + h22*y21 - h21y22*

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    STBC

    Requires complex operations

    Low Data Movement

    Highly parallelizable

    Complex

    MultiplyAccumulate

    Channel

    Estimation

    h22 h21 h12 h11

    y21 y11

    y22* y12*

    Receiver Antenna 1 and 2

    ~x[1] ~x[2]

    Conjugate

    +Negation

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    Vertical-BLAST (V-BLAST)

    S/P

    Mod

    Mod

    V-Blast

    Detector

    Demod

    Demod

    M Transmitters R Receivers

    1 2 3 4 1 2 3 4 1 2 3 4

    5 6 7 8 5 6 7 8 5 6 7 8

    9 10 11 12 9 10 11 12 9 10 11 12

    13 14 15 16 13 14 15 16 13 14 15 16

    Data Stream of 4 TxLinear Combination

    of Data

    Channel

    Estimation

    Nulling

    Vector

    1 2 3 4

    Subtract

    Strong Signal

    Repeat

    Strongest

    Signal

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    V-BLAST

    Implementation Based on Square Root Method for V-BLAST

    Original requires repeated pseudo-inverse calculation for finding the

    strongest signal

    This algorithm has reduces complexity

    Complexity

    Requires matrix operations on complex numbers

    Many Matrix Transformations

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    Channel Decoding

    3G Technologies in 4G

    Viterbi

    Turbo Decoder

    New to 4G

    LDPC

    Better performance characteristics compared to Turbo and Viterbi

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    LDPC

    0 1 0 1 1 0 0 1

    1 1 1 0 0 1 0 0

    0 0 1 0 0 1 1 1

    1 0 0 1 1 0 1 0

    H =

    E0

    L0 L1 L2 L3

    E1 E2 E3

    L4 L5 L6 L7

    L Node Original Value Message from Check Nodes Decision

    L0

    L1

    L2

    L3

    L4

    L5

    L6

    L7

    1

    1

    0

    1

    0

    1

    0

    1

    E1 0 E3 1 1

    0

    0

    1

    0

    1

    0

    1

    E0 0 E1 0

    E1 1 E2 0

    E0 0 E3 1

    E0 1 E3 0

    E1 0 E2 1

    E2 0 E3 0

    E0 1 E2 1

    E0

    L0

    L1

    L2

    L3

    E1 E2 E3

    L4

    L5

    L6

    L7

    1 1 0 01 1 0 1

    E0

    L0

    L1

    L2

    L3

    E1 E2 E3

    0

    L4

    L5

    L6

    L7

    1 1 0 01 1 0 1

    Message Sent = [ 1 0 0 1 0 1 0 1 ]

    Message Recieved = [ 1 1 0 1 0 1 0 1 ]

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    LDPC

    Min-Sum Decoding Used

    Regular LDPC code

    Can get benefit from Wide SIMD

    Can do the Bit Node and Check Node

    Alignment of Check and Bit nodes is a problem

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    SODA PE Architecture

    SIMD

    Reg.

    FileE

    X

    SIMD

    ALU+

    Mult

    SIMD

    Shuffle

    Net-

    work

    (SSN)

    W

    B

    Scalar

    ALU

    W

    B

    E

    X

    Scalar

    RF

    Local

    SIMD

    Memory

    Local

    Scalar

    Memory

    S

    T

    V

    AGU

    RFE

    X

    W

    B

    AGU

    ALU

    1. SIMD pipeline

    2. Scalar pipeline

    4. AGU pipeline

    V

    T

    S

    Pred.

    Regs

    W

    B

    SIMD

    to

    Scalar

    (VtoS)ALU

    RF

    DMA

    Global

    Memory

    SODA

    DSP

    5. DMA

    3. Local

    memory

    SystemInterconnect

    SIMD 32 Wide, 16-bit datapath, Predicate Execution

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    Key 4Galgorithms

    100 Mbps 1 GbpsMCycle/s MCycle/s

    FFT 2x360 4x360

    IFFT 2x360 4x360

    STBC 240 -

    V-BLAST - 1900

    LDPC 7700 4x18500

    4G Workload on SODA

    100 Mbps 4G requires 8Ghz SODA PE

    1 Gbps 4G requires 20Ghz SODA PE

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    SODA With Technology Scaling

    0

    500

    1000

    1500

    2000

    2500

    3000

    3500

    4000

    180nm 130nm 90nm 65nm 45nm 32nm 22nm

    Frequency(Mhz)

    0

    0.1

    0.2

    0.3

    0.4

    0.5

    0.6

    0.7

    0.8

    Power(W)

    ITRS Scaled Frequency Fixed Scaled Frequency Scaled Power

    180nm 130nm 90nm 65nm 45nm 32nm 22nm

    Vdd (V) 1.8 1.3 1.1 1.1 1 0.9 0.8

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    We cant do any of 4G with technology scaling on one core

    Would 8GHz cores even be an energy efficient solution?

    What about 1Gbps?

    Are we ever going to get a 20GHz core?

    Cannot rely on technology scaling to give us 4G for free

    4G SDR will require algorithmic and architectural innovations

    SDR Challenges In 4G

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    4G Algorithm-Architectural Co-design

    Architectural improvements (SODA II)

    Specialized functional units

    CISC-like complex arithmetic operations

    Specialized data movement hardware

    Less strain on the memory system

    Wider SIMD

    How wide can we go? More PEs

    What does the interconnect look like?

    Algorithmic optimization through parallelization

    Reduce intra-kernel communication Reduce memory accesses

    Arithmetic is much cheaper than data movement

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    Thanks

    Questions?

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    Successive Cancelling for V-BLAST

    V-BLAST successive interference cancelling (SIC)

    The ith ZF-nulling vectorwi is defined as the uniqueminimum-norm vector satisfying

    Orthogonal to the subspace spanned by the contributions to yi due

    to the symbols not yet estimated and cancelled and is given by theith row of H

    ~

    Al ti S h

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    Alamouti Scheme

    Assumption: the channel remains unchanged over two consecutive symbols Rate = 1

    Diversity order = 2

    Simple decoding

    Ad t f S ft D fi d R di

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    Advantages of Software Defined Radio

    Multi-mode operations

    Lower costs

    Faster time to market

    Prototyping and bug fixes

    Chip volumes

    Longevity of platforms

    Enables future wireless communication

    innovations

    Cognitive radio

    UWB EDGE 802.16a

    802.16aBluetooth

    802.11b WCDMA 802.11n

    SDR