Mwe/IFF/1 High-speed Addition with Bipolar Digital Circuits Matthew W. Ernest Rensselaer Polytechnic Institute.

mwe/IFF/1

High-speed Addition with Bipolar Digital Circuits

Matthew W. Ernest

Rensselaer Polytechnic Institute

mwe/IFF/2

Carry types: Carry Select• Compute possible results

in parallel• Select when actual carry-

in available• Requires internal carry

for blocks, e.g. ripple• Delay: O(f(n/b) +b)• Area: O(f(n/b)b+b) • Affected by block sizing

0

1

0

1

mwe/IFF/3

1

0

1

0

0123456

t

b7 …

b4

b7 …

b4

Carry Select Delay Path

• t=0..4: Each block operates in parallel

• t=5: Carry-out of first block selected by carry-in, no activity in second block

• t=6: Carry-out of second block selected by carry-out of first

mwe/IFF/4

0123456

t

1

0

1

0

b88 …

b4

b7 …

b4

Lengthening non-critical paths• t=0..4: Each block operates

in parallel• t=5: Carry-out of first

block selected by carry-in, additional bit handled during delay

• t=6: Carry-out of lengthened second block selected by carry-out of first

mwe/IFF/5

Given: td = tg ci + N tm

If: tg ci+1 tg ci + tm

Define: s = ci+1 - ci tmtg

Carry Select Delay

• td: delay of circuit• tg: delay of gate• tm: delay of mux• N: # of stages• ci: bits in stage i

mwe/IFF/6

td / tg = 2 B s + s/2

N = td / tg - s/2 ±(td / tg - s/2)2 - 2 B ss

c1 =tdtg- Ns

Minimizing delay via stage size

mwe/IFF/7

Carry Types: Block carry look-ahead

• A block propagates a carry if all bits in the block propagate a carry

• A block generates a carry if a bit generates a carry and all succeeding bits propagate

• Delay: O(log n)

• Area: O(n log n)

mwe/IFF/8

Carry vs. Pseudocarry

Cout=Gn+ Pn• Gn-1 +…+Pn• Pn-1• ... P0• Cin

If G=A•Band P=A+Bthen

G=G•PCout= Pn•Gn+ Pn• Gn-1 +…+Pn• Pn-1• ... P0• Cin

Cout= Pn(Gn+ Gn-1 +…+Pn-1• ... P0• Cin)Cout= Pn•Hn

Hn =Gn+ Gn-1 +…+Pn-1• ... P0• Cin

mwe/IFF/9

Block Generate:Gi•j

0= Gij + Pi

jGij-1i + … + Pi

jPij-1iPi

j-2i•••Gi0

If G=A•Band P=A+Bthen

G=G•PGi•j

0= PijGi

j + PijGi

j-1i + … + PijPi

j-1iPij-2i•••Gi

0

Gi•j0= Pi

j(Gij + Gi

j-1i + … + Pij-1iPi

j-2i•••Gi0)

Hi•j0= Gi

j + Gij-1i + … + Pi

j-1iPij-2i•••Gi

0

Deriving Block Pseudocarry from Carry Lookahead Terms

mwe/IFF/10

H2s= G1

s+1 + G1s

Hi+js= Hj

s+i + Ijs+i-1•Hi

s

Hi+j+ks= Hk

s+I+j + Iks+I+j-1•Hj

s+i + Iks+I+j-1• Ij

s+i-1•His

Ip+qt= Iq

t+p•Ipt

Ip+q+rt= Ir

t+q+p•Iqt+p•Ip

t

Generalized Pseudocarry Equations

mwe/IFF/11

Sn=AnBnCn-1

IfTn=AnBn

Cm= Pm•Hm

thenSn=TnPn-1Hn-1

Generating Sums Using Pseudocarry

mwe/IFF/12

Pseudocarry BlocksH2

sH2

s H2s

H2s H2

sH2

s H2s

H2s H2

sH2

s H2s

H2s H2

sH2

s H2s

H2s H2

sH2

s H2s

H2s H2

sH2

s H2s

H2s H2

sH2

s H2s

H2s H2

sH2

s H2s

H2s

H6s

H6s H6

sH6

s H6s

H6s H6

sH6

s H6s

H6s

H18s

H18s H14

sH14

s

H32s

H32s

mwe/IFF/13

CML/ECL Current Steering Gates

mwe/IFF/14

Single-ended vs. Double-ended

•Any function of inputs•Fan-in limited by supply voltage

•Limited to simple functions•Large fan-in

mwe/IFF/15

Look-ahead gate w/ fully differential logic

Hn

In

Hn-1 Hn-1

In

Hn

Hn Hn

In In

Hn-1 Hn-1

Hn-2 Hn-2

In-1 In-1

mwe/IFF/16

Mixed input look-ahead gates

Hn

In

Hn-1

In

HnVr Vr • In(Hn+ Hn-1) + In•Hn

• Hn+ In•Hn-1

• Two series-gated levels for three inputs

mwe/IFF/17

Hn Hn

InIn

Hn-1 Hn-1Hn-2

In-1 In-1

Hn

Mixed input look-ahead gates

• In In-1(Hn+ Hn-1 + Hn-2) + In

In-1(Hn+ Hn-1) + In• In-1• Hn

• Hn+ In•Hn-1 + In• In-1• Hn-2

• Three series-gated levels for five inputs

mwe/IFF/18

Adder comparision

Bits Rip

ple

CSelA B C CLA

PC

LA

32 32 12 12 9 6 5

64 64 20 16 12 7 6

mwe/IFF/19

Pseudocarry Tree Oscillator

B A

Cin

Cout

32

031

1

1 Select

mwe/IFF/20

Carry Tree High-speed Output

2 x 165 ps

mwe/IFF/21

Comparisons of Published AddersReference Type Size Gate

DelaysTime

Zimmerman96 Carry 32 5 -

Stelling96 Adder 62(32) 12.5(12?) -

Wang97 Adder 32 3 2.7 ns

Chang98 Adder 64(32) 27(19.5) -

Silberman98 Fixed-point

64 - 550- ps

Aipperspach99 Adder 64 - 660 ps

mwe/IFF/22

Minimize/Balance Wiring Length

Cartesian Alignment

mwe/IFF/23

Minimize/Balance Wire Length

Isometric Alignment

mwe/IFF/24

Cascode Output Stage

• Eliminates capacitive coupling between input and output• Shortens rise time, but increases delay