Multiport Serial Communication Interface Controller ABSTRACT: Most digital messages are vastly longer than the just a few bits. Because it is neither practical nor economic to transfer all bits of a long message simultaneously the message is broken into small parts & transmitted sequentially. This project deals with the designing of the Programmable Serial Communication Interface IP core. In general, micro controllers have a single non-programmable serial port. The project here designs a multi-channel (eight serial ports) serial port interface to the host processor/controller which contains the logic for multiplexing many serial ports on one side to the available single serial port of the micro controller/processor other side. This design even includes the Synchronization between Transmitter and Receiver blocks, Accessing the devices with software programming(Masking/Unmasking),Programmable number of channels and baud rate generator, Data integration-Error handling method (CRC generation/check),TXFIFO and RXFIFO data buffering mechanism and Packet based transmission and reception with protocol implementation. Serial Port Architecture mainly consists of the blocks Such as Transmitter framer Block Receiver framer Block, Transmitter State Machine Controller (TSMC), Receiver State Machine Controller (RSMC), Tx/Rx Control & Status Logic, TX & Rx FIFO interfacing Logic, Baud Rate Generator, and Receiver Synchronization. Dept Of ECE, SITS, Khammam 1
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Multiport Serial Communication Interface Controller
ABSTRACT:
Most digital messages are vastly longer than the just a few bits. Because it
is neither practical nor economic to transfer all bits of a long message
simultaneously the message is broken into small parts & transmitted sequentially.
This project deals with the designing of the Programmable Serial Communication
Interface IP core. In general, micro controllers have a single non-programmable serial
port. The project here designs a multi-channel (eight serial ports) serial port
interface to the host processor/controller which contains the logic for multiplexing
many serial ports on one side to the available single serial port of the micro
controller/processor other side. This design even includes the Synchronization
between Transmitter and Receiver blocks, Accessing the devices with software
programming(Masking/Unmasking),Programmable number of channels and baud
rate generator, Data integration-Error handling method (CRC
generation/check),TXFIFO and RXFIFO data buffering mechanism and Packet based
transmission and reception with protocol implementation. Serial Port Architecture
mainly consists of the blocks Such as Transmitter framer Block Receiver framer
Block, Transmitter State Machine Controller (TSMC), Receiver State Machine
Controller (RSMC), Tx/Rx Control & Status Logic, TX & Rx FIFO interfacing Logic, Baud
Rate Generator, and Receiver Synchronization.
The overall System Architecture will be designed using HDL language
and simulation, synthesis and FPGA implementation (Translation, Mapping, Placing
and Routing) will be done using various FPGA based EDA Tools.
INDEX
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Multiport Serial Communication Interface Controller
P.NO
1. INTRODUCTION 3-20
1.1 Data Communication 3
1.2 Parallel Communication 4
1.3 Serial Communication 8
1.4 SPI Devices 15
2. INTRODUCTION TO VERILOG & VLSI 21-42
3. ARCHITECTURE OF THE PROJECT 43
4. MODULES 44-59
4.1 FIFO 44
4.2 Multiplexer/De Multiplexer 46
4.3 Parallel to Serial converter 49
4.4 Serial to Parallel converter 51
4.5 CRC 53
4.6 DLC 56
4.7 SMC 56
5. RESULT DISCUSSION 60-78
5.1 Simulation Result
5.2 Synthesis Result
5.3 RTL Schematic View
6. ADVANTAGES & DISADVANTAGES 79
7. CONCLUSION & FURTHER SCOPE 80
8. REFERENCES 81
1. INTRODUCTION:
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1.1 Data Communication:
The distance over which data moves within a computer may vary from a few
thousandths of an inch, as is the case within a single IC chip, to as much as several
feet along the back-plane of the main circuit board. Over such small distances,
digital data may be transmitted as direct, two-level electrical signals over simple
copper conductors. Except for the fastest computers, circuit designers are not very
concerned about the shape of the conductor or the analog characteristics of signal
transmission. Frequently, however, data must be sent beyond the local circuitry that
constitutes a computer. In many cases, the distances involved may be enormous.
Unfortunately, as the distance between the source of a message and its destination
increases, accurate transmission becomes increasingly difficult. This results from the
electrical distortion of signals traveling through long conductors, and from noise
added to the signal as it propagates through a transmission medium. Although some
precautions must be taken for data exchange within a computer, the biggest
problems occur when data is transferred to devices outside the computer's circuitry.
In this case, distortion and noise can become so severe that information is lost. Data
Communications concerns the transmission of digital messages to devices external
to the message source. "External" devices are generally thought of as being
independently powered circuitry that exists beyond the chassis of a computer or
other digital message source. As a rule, the maximum permissible transmission rate
of a message is directly proportional to signal power and inversely proportional to
channel noise. It is the aim of any communications system to provide the highest
possible transmission rate at the lowest possible power and with the least possible
noise.
1.1.1 Communications Channels:
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Multiport Serial Communication Interface Controller
A communications channel is a pathway over which information can
be conveyed. A physical wire that connects communicating devices may define it, or
by a radio, laser, or other radiated energy source that has no obvious physical
presence. Information sent through a communications channel has a source from
which the information originates, and a destination to which the information is
delivered. Although information originates from a single source, there may be more
than one destination, depending upon how many receive stations are linked to the
channel and how much energy the transmitted signal possesses.
In a digital communications channel, the information is represented by individual
data bits, which may be encapsulated into multibit message units. A byte, which
consists of eight bits, is an example of a message unit that may be conveyed
through a digital communications channel. A collection of bytes may itself be
grouped into a frame or other higher-level message unit. Such multiple levels of
encapsulation facilitate the handling of messages in a complex data communications
network.
1.2 Parallel Communication:
In parallel communications there are more wires running between the
two systems and therefore both the spatial (which wire) and temporal (when)
dimensions are available for the data. In a parallel communication problem there is
just as great a need for a protocol and flow control as in the case of serial
communications. Parallel communications however tends to have a greater
emphasis on flow control or "handshaking" for a variety of reasons. The need for
handshakes is really a property of the fact that two devices are running
asynchronously to each other and therefore it is necessary to be able to
communicate the fact that the data is ready/taken to the other device. A handshake
may be "tighter" or "looser" depending upon the circumstances. The simplest idea
of a parallel handshake is a device which puts a line up when it is ready with data
(Data Ready or DR) and then waits for the interrogating device to take the data. It
must then immediately remove the request; otherwise the interrogator may well try
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Multiport Serial Communication Interface Controller
to read the data again. Thus the regime is as shown in the diagram. Now in some
devices it is reasonably easy to see whether the data has been read, particularly if
you have access to the computer bus signals and can see whether a read has been
done on the appropriate location. However if the bus signals are not available then
some other means must be invoked, i.e. another communication line, "Data Taken"
(DT), to tell the device that data has been taken.
Figure: parallel communication (http://googlepages/parallelcommunication)
Parallel ports were originally developed by IBM as a way to connect a printer to a PC.
When IBM was in the process of designing the PC, the company wanted the
computer to work with printers offered by Centronics, a top printer manufacturer at
the time. IBM decided not to use the same port interface on the computer that
Centronics used on the printer. Instead, IBM engineers coupled a 25-pin connector,
DB-25, with a 36-pin Centronics connector to create a special cable to connect the
printer to the computer. Other printer manufacturers ended up adopting the
Getronics interface, making this strange hybrid cable an unlikely de facto standard.
When a PC sends data to a printer or other device using a parallel port, it sends 8
bits of data (1byte) at a time. These 8 bits are transmitted parallel to each other. The
standard parallel port is capable of sending 50 to 100 kilobytes of data per second.
1.2.1 Types of parallel port:
At the present time it is known four types of parallel port:
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Standard parallel port (SPP)
Parallel port PS/2 (bidirectional)
Enhanced Parallel Port (EPP)
Extend Capability Port (ECP)
SPP/EPP/ECP:
The original specification for parallel ports was unidirectional, meaning that
data only traveled in one direction for each pin. With the introduction of the PS/2 in
1987, IBM offered a new bidirectional parallel port design. This mode is commonly
known as Standard Parallel Port (SPP) and has completely replaced the original
design. Bidirectional communication allows each device to receive data as well as
transmit it. Many devices use the eight pins (2 through 9) originally designated for
data. Using the same eight pins limits communication to half-duplex, meaning that
information can only travel in one direction at a time. But pins 18 through 25,
originally just used as grounds, can be used as data pins also. This allows for full-
duplex (both directions at the same time) communication.
Enhanced Parallel Port (EPP):
It was created by Intel, Xircom, and Zenith in 1991. EPP allows for much
more data, 500 kilobytes (KB) to 2 megabytes (MB), to be transferred each second. It
was targeted specifically for non-printer devices that would attach to the parallel
port; particularly storage devices that needed the highest possible transfer rate close
on the heels of the introduction of EPP.
Extended Capabilities Port (ECP):
Microsoft and Hewlett Packard jointly announced a specification called
Extended Capabilities Port (ECP) in 1992. While EPP was geared toward other
devices, ECP was designed to provide improved speed and functionality for printers.
In 1994, the IEEE 1284 standard was released. It included the two specifications for
parallel port devices, EPP and ECP. In order for them to work, both the operating
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Multiport Serial Communication Interface Controller
system and the device must support the required specification. This is seldom a
problem today since most computers support SPP, ECP and EPP and will detect which
mode needs to be used, depending on the attached device. If you need to manually
select a mode, you can do so through the BIOS (Basic Input/output System) on most
computers.
1.2.2 Advantages of Parallel Data Transmission:
Fastest form of transmission -- able to send multiple bits simultaneously
Doesn’t require high frequency of operation
1.2.3 Disadvantages of Parallel Data Transmission:
Requires separate lines for each bit of a word
Costly to run long distances due to multiple wires
Suffers from electromagnetic interference
Cable lengths more limited than a serial cable
1.2.4 Applications:
Parallel ports can be used to connect a host of popular computer peripherals:
such as prints, scanners, CD burners, external hard drives, Iomega zip, network
adapters, and tape backup drives.
1.3 Serial Communication:
Serial is a device communication protocol that is standard on almost
every PC. Do not confuse it with universal serial bus (USB). Most computers include
two EIA-232 based serial ports. Serial is also a common communication protocol for
instrumentation in many devices, and numerous GPIB-compatible devices come with
an EIA-232 port. Furthermore, you can use serial communication for data acquisition
in conjunction with a remote sampling device. Note that EIA-232 and EIA-485/422.
The concept of serial communication is simple. The serial port sends and receives
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bytes of information one bit at a time. Although this is slower than parallel
communication, which allows the transmission of an entire byte at once, it is simpler
and you can use it over longer distances. For example, the IEEE 488 specifications
for parallel communication state that the cabling between equipment can be no
more than 20m (65ft) total, with no more than 2m (6.5ft) between any two devices;
serial, however, can extend as much as 1200ft. typically, engineers use serial to
transmit ASCII data. They complete communication using three transmission lines --
ground, transmit, and receive. Because serial is asynchronous, the port can transmit
data on one line while receiving data on another. Other lines are available for
handshaking but are not required. The important serial characteristics are baud rate,
data bits, stop bits, and parity. For two ports to communicate, these parameters
must match:
1) Baud rate is a speed measurement for communication that indicates the number
of bit transfers per second. For example, 300 baud is 300 bits per second. When
engineers refer to a clock cycle, they mean the baud rate, so if the protocol calls
for a 4800 baud rate, the clock is running at 4800 Hz. This means that the serial
port is sampling the data line at 4800 Hz. Common baud rates for telephone lines
are 14400, 28800, and 33600. Baud rates greater than these are possible, but
these rates reduce the distance by which engineers can separate devices. They
use these high baud rates for device communication where the devices are
located together, as is typically the case with GPIB devices.
2) Data bits are a measurement of the actual data bits in a transmission. When the
computer sends a frame of information, the amount of actual data may not be a
full 8 bits. Standard values for frames are 5, 7, and 8 bits. Which setting you
choose depends on what information you are transferring. For example, standard
ASCII has values from 0 to 127 (7 bits). Extended ASCII uses 0 to 255 (8 bits). If
the data you are transferring is standard ASCII, sending 7 bits of data per frame is
sufficient for communication. A frame refers to a single byte transfer, including
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start/stop bits, data bits, and parity. Because the number of actual bits depends
on the protocol selected, you can use the term "frame" to cover all instances.
3) Stop bits are used to signal the end of communication for a single frame. Typical
values are 1, 1.5, and 2 bits. Because the data is clocked across the lines and
each device has its own clock, it is possible for the two devices to become slightly
out of sync. Therefore, the stop bits not only indicate the end of transmission but
also give the computers some room for error in the clock speeds. The more bits
used for stop bits, the greater the lenience in synchronizing the different clocks,
but the slower the data transmission rate.
4) Parity is a simple form of error checking used in serial communication. There are
four types of parity -- even, odd, marked, and spaced. You also can use no parity.
For even and odd parity, the serial port sets the parity bit (the last bit after the
data bits) to a value to ensure that the transmission has an even or odd number
of logic-high bits. For example, if the data is 011, for even parity, the parity bit is
0 to keep the number of logic-high bits even. If the parity is odd, the parity bit is
1, resulting in 3 logic-high bits. Marked and spaced parity does not actually check
the data bits but simply sets the parity bit high for marked parity or low for
spaced parity. This allows the receiving device to know the state of a bit so the
device can determine if noise is corrupting the data or if the transmitting and
receiving device clocks are out of sync.
Serial communications send a single bit at a time between computers. This only
requires a single communication channel, as opposed to 8 channels to send a byte.
With only one channel the costs are lower, but the communication rates are slower.
The communication channels are often wire based, but they may also be can be
optical and radio. Figure 48 shows some of the standard electrical connections. RS-
232c is the most common standard that is based on a voltage change levels. At the
sending computer an input will either be true or false. The line driver will convert a
false value in to a Txd voltage between +3V to +15V, true will be between -3V to -
15V. A cable connects the Txd and com on the sending computer to the Rxd and
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com inputs on the receiving computer. The receiver converts the positive and
negative voltages back to logic voltage levels in the receiving computer. The cable
length is limited to 50 feet to reduce the effects of electrical noise. When RS-232 is
used on the factory floor, care is required to reduce the effects of electrical noise -
careful grounding and shielded cables are often used.
1.3.1 Types of Serial communication:
Any communications channel has a direction associated with it:
Fig: Types of channel (http://googlepages/serialcommunication)
The message source is the transmitter, and the destination is the receiver
Simplex Channel:
A channel whose direction of transmission is unchanging is
referred to as a simplex channel.For example, a radio station is a simplex
channel because it always transmits the signal to its listener and never
allows them to transmit back.
Half-duplex Channel :
It is a single physical channel in which the direction may be
reversed. Messages may flow in two directions, but never at the same time,
in a half duplex system. In a telephone call, one party speaks while the other
listens. After a pause, the other party speaks and the first party listens.
Speaking simultaneously results in garbled sound that cannot be understood.
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Full-duplex Channel :
It allows simultaneous message exchange in both directions. It
really consists of two simplex channels, a forward channel and a reverse
channel, linking the same points. The transmission rate of the reverse
channel may be slower if it is used only for flow control of the forward
channel.
1.3.2 Asynchronous vs. Synchronous Transmission:
Serialized data is not generally sent at a uniform rate through a channel.
Instead, there is usually a burst of regularly spaced binary data bits followed by a
pause, after which the data flow resumes. Packets of binary data are sent in this
manner, possibly with variable-length pauses between packets, until the message
has been fully transmitted. In order for the receiving end to know the proper
moment to read individual binary bits from the channel, it must know exactly
when a packet begins and how much time elapses between bits. When this timing
information is known, the receiver is said to be synchronized with the transmitter,
and accurate data transfer becomes possible. Failure to remain synchronized
throughout a transmission will cause data to be corrupted or lost.
Two basic techniques are employed to ensure correct synchronization. In
synchronous systems, separate channels are used to transmit data and timing
information. The timing channel transmits clock pulses to the receiver. Upon
receipt of a clock pulse, the receiver reads the data channel and latches the bit
value found on the channel at that moment. The data channel is not read again
until the next clock pulse arrives. Because the transmitter originates both the
data and the timing pulses, the receiver will read the data channel only when told
to do so by the transmitter (via the clock pulse), and synchronization is
guaranteed. Techniques exist to merge the timing signal with the data so that
only a single channel is required. This is especially useful when synchronous
transmissions are to be sent through a modem. Two methods in which a data
signal is self-timed are no return-to-zero and biphase Manchester coding. These
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both refer to methods for encoding a data stream into an electrical waveform for
transmission.
In asynchronous systems, a separate timing channel is not used. The
transmitter and receiver must be preset in advance to an agreed-upon baud rate.
A very accurate local oscillator within the receiver will then generate an internal
clock signal that is equal to the transmitters within a fraction of a percent. For the
most common serial protocol, data is sent in small packets of 10 or 11 bits, eight
of which constitute message information. When the channel is idle, the signal
voltage corresponds to a continuous logic '1'. A data packet always begins with a
logic '0' (the start bit) to signal the receiver that a transmission is starting. The
start bit triggers an internal timer in the receiver that generates the needed clock
pulses. Following the start bit, eight bits of message data are sent bit by bit at the
agreed upon baud rate. The packet is concluded with a parity bit and stop bit. One
complete packet is illustrated below:
The packet length is short in asynchronous systems to minimize the risk that the
local oscillators in the receiver and transmitter will drift apart. When high-quality
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crystal oscillators are used, synchronization can be guaranteed over an 11-bit period.
Every time a new packet is sent, the start bit resets the synchronization, so the
pause between packets can be arbitrarily long. Note that the EIA232 standard
defines electrical, timing, and mechanical characteristics of a serial interface.
However, it does not include the asynchronous serial protocol shown in the previous
figure, or the ASCII alphabet described next.
1.3.3 Hand shaking:
Handshaking is a procedure used to check the link between DTE & DCE
before transmitting of data. Data is transmitted and received on pins 2 and 3
respectively (for both types 25 & 9 pin).
1. DTE would request to send data to DCE (RTS).
2. The DCE will indicate to DTE that it is ready and clear to send data (CTS).
Both RTS and CTS therefore used to control data flow between DTE & DCE. Data Set
Ready (DSR) is an indication from the DCE (i.e., the modem) that it is ON. Similarly,
DTR (i.e., the PC) indicates to the Data Set that the DTE is on. Data Carrier Detect
(CD) indicates that a good carrier is being received from the remote modem.
1.3.4 Baud rate :
Baud rate is a measurement of transmission speed in asynchronous
communication, it represents the number of bits that are actually being sent over
the serial link. The Baud count includes the overhead bits Start, Stop and Parity that
are generated by the sending UART and removed by the receiving UART.
1.3.5 Type of cables:
(A) Modem Cable:
A normal modem cable runs straight through with pin 1 to pin 1, pin 2 to pin 2
etc. The end that will be connected to the terminal or PC is a female connector, and
the end that will be connected to the modem is male connector.
(B) Null Modem Cables:
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Multiport Serial Communication Interface Controller
When you need to connect two equipments with both (DTE) or both (DCE), for
example connecting two PC's, then in this case you have to use the cable with below
pin connection (25 to 25). And this is called Null modem cable.
1.3.6 Advantages of serial communication:
One of the advantages is transmission distance, serial link can send data to a
remote device more far then parallel link. Also the cable connection of serial link is
simpler then parallel link and uses less number of wires. Serial link is used also for
Infrared communication, now many devices such as laptops & printers can
communicate via inferred link.
1.4 Serial Peripheral Interface (SPI):
The Serial Peripheral Interface is used primarily for a synchronous
serial communication of host processor and peripherals. In the standard
configuration for a slave device (see illustration 1), two control and two data lines
are used. The data output SDO serves on the one hand the reading back of data,
offers however also the possibility to cascade several devices. The data output of the
preceding device then forms the data input for the next IC.
fig1: SPI slave
There is a MASTER and a SLAVE mode. The MASTER device provides the clock signal
and determines the state of the chip select lines, i.e. it activates the SLAVE it wants
to communicate with. CS and SCKL are therefore outputs.
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The SLAVE device receives the clock and chip select from the
MASTER, CS and SCKL are therefore inputs. This means there is one master, while
the number of slaves is only limited by the number of chip selects. A SPI device can
be a simple shift register up to an independent subsystem. The basic principle of a
shift register is always present. Command codes as well as data values are serially
transferred, pumped into a shift register and are then internally available for parallel
processing. Here we already see an important point that must be considered in the
philosophy of SPI bus systems: The length of the shift registers is not fixed, but can
differ from device to device. Normally the shift registers are 8Bit or integral multiples
of it. Of course there also exist shift registers with an odd number of bits. For
example two cascaded 9Bit EEPROMs can store 18Bit data. The micro controller
configured as a slave behaves like a normal peripheral device. The second possibility
works with several masters and is therefore named multi-master protocol. Each
micro processor has the possibility to take the roll of the master and to address
another micro processor. One controller must permanently provide a clock signal.
The MC68HC11 provides hardware error recognition, useful in multiple-master
systems. There are two SPI system errors. The first occurs if several SPI devices want
to become master at the same time. The other is a collision error that occurs for
example when SPI devices work with different polarities. More details can be found in
the MC68HC11 manual.
1.4.1 UART:
The Universal Asynchronous Receiver Transmitter (UART) is a popular and
widely-used device for data communication in the field of telecommunication. There
are different versions of UARTs in the industry. Some of them contain FIFOs for the
receiver/transmitter data buffering and some of them have the 9 Data bits mode
(Start bit + 9Data bits + Parity + Stop bits). This application note describes a fully
configurable UART optimized for and implemented in a variety of Lattice devices,
which have superior performance and architecture compared to existing
semiconductor ASSPs (application-specific standard products).
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This UART reference design contains a receiver and a transmitter. The receiver
performs serial-to-parallel conversion on the asynchronous data frame received from
the serial data input SIN. The transmitter performs parallel-to serial conversion on
the 8-bit data received from the CPU. In order to synchronize the asynchronous serial
data and to insure the data integrity, Start, Parity and Stop bits are added to the
serial data. An example of the UART frame format is shown in Figure 1 below.
This design can also be instantiated many times to get multiple UARTs in the same device. For
easily embedding the design into a larger implementation, instead of using tri-state buffers, the
bi-directional data bus is separated into two buses, DIN and DOUT. The transmitter and receiver
both share a common internal Clk16X clock. This internal clock which needs to be 16 times of
the desired baud rate clock frequency is obtained from the on-board clock through the MCLK
input directly. However, when implementing the design into is MACH™ 5000VG devices, the
Clk16X clock can be generated flexibly through the isMACH 5000VG on-chip PLL by using
MCLK as the PLL reference clock input.
1.4.2 USB:
A core team from Compaq, Hewlett Packard, Intel, Lucent, Microsoft, NEC and
Philips is leading the development of the USB Specification, version 2.0 that will
increase data throughput by a factor of 40. This backwards-compatible extension of
the USB 1.1 specification uses the same cables, connectors and software interfaces
so the user will see no change in the usage model. They will, however, benefit from
an additional range of higher performance peripherals, such as video-conferencing
cameras, next-generation scanners and printers, and fast storage devices, with the
same ease-of-use features as today’s USB peripherals.
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Impact to Use:
From a user’s perspective, USB 2.0 is just like USB, but with much
higher Bandwidth. It will look the same and behave the same, but with a
larger choice of More interesting, higher performance devices available. Also,
all of the USB Peripherals the user has already purchased will work in a USB
2.0-capable System.
Impact to PC Manufacturer:
USB 2.0 will provide system manufacturers the ability to connect to high
Performance peripherals in the least expensive way. The additional
performance Capabilities of USB 2.0 can be added with little impact to overall
system cost. Indeed, high-bandwidth interfaces such as SCSI adapters may
no longer be required in some systems, leading to a net saving of system
cost. Simple construction will result since only USB connectors will be needed
on many futures PCs. Today’s ubiquitous USB connectors will become USB
2.0, superseding USB 1.1.
Impact to Peripheral Manufacturer:
Today’s USB devices will operate with full compatibility in a USB 2.0
system. Peripherals, while enabling retail products to transition with the
installed base. Support of USB 2.0 is recommended for hubs and higher
bandwidth peripherals. Designing a USB 2.0 peripheral will be a similar
engineering effort to that of designing a USB 1.1 peripheral. Some low-speed
peripherals, such as HID devices, may never be redesigned to support the
USB 2.0 high-speed capability in order to maintain the absolute lowest cost.
The Universal Serial Bus was originally developed in 1995 by many of the same
industry leading companies currently working on USB 2.0. The major goal of USB was
to define an external expansion bus which makes adding peripherals to a PC as easy
as hooking up a telephone to a wall-jack. The program’s driving goals were ease-of-
use and low cost. These were enabled with external expansion architecture, as
shown in Figure 1, which highlights:
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PC host controller hardware and software,
Robust connectors and cable assemblies,
Peripheral friendly master-slave protocols,
Expandable through multi-port hubs.
An understanding of the roles of each of the major elements within a USB 1.1 system
will better show the evolutionary step that USB 2.0 provides.
Role of Host PC hardware and software:
The role of the system software is to provide a uniform view of IO system
for all applications software. It hides hardware implementation details so that
application software is more portable. For the USB IO subsystem in particular, it
manages the dynamic attach and detach of peripherals. This phase, called
enumeration, involves communicating with the peripheral to discover the identity
of a device driver that it should load, if not already loaded. A unique address is
assigned to each peripheral during enumeration to be used for run-time data
transfers. During run-time the host PC initiates transactions to specific
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peripherals, and each peripheral accepts its transactions and responds
accordingly. Additionally the host PC software incorporates the peripheral into the
system power management scheme and can manage overall system power
without user interaction.
Role of the hub:
Besides the obvious role of providing additional connectivity for USB
peripherals, a hub provides managed power to attached peripherals. It recognizes
dynamic attachment of a peripheral and provides at least 0.5W of power per
peripheral during initialization. Under control of the host PC software, the hub may
provide more device power, up to a maximum of 2.5W, for peripheral operation. A
newly attached hub will be assigned its unique address, and hubs may be
cascaded up to five levels deep. During run-time a hub operates as a bi-
directional repeater and will repeat USB signals as required on upstream (towards
the host) and downstream (towards the device) cables. The hub also monitors
these signals and handles transactions addressed to it. All other transactions are
repeated to attach devices. A hub supports both 12Mb/s (full-speed) and 1.5Mbs
(low speed) peripherals.
Role of the peripheral:
All USB peripherals are slaves that obey a defined protocol. They must
react to request transactions sent from the host PC. The peripheral responds to
control transactions that, for example, request detailed information about the
device and its configuration. The peripheral sends and receives data to/from the
host using a standard USB data format. This standardized data movement to/from
the PC host and interpretation by the peripheral gives USB its enormous flexibility
with little PC host software changes. USB 1.1 peripherals can operate at 12Mb/s or
1.5Mb/s.
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Multiport Serial Communication Interface Controller
2. INTRODUCTION TO VERILOG & VLSI:
2.1 INTRODUCTION TO VLSI:-
The first digital circuit was designed by using electronic
components like vacuum tubes and transistors. Later Integrated Circuits (ICs) were
invented, where a designer can be able to place digital circuits on a chip consists of
less than 10 gates for an IC called SSI (Small Scale Integration) scale. With the
advent of new fabrication techniques designer can place more than 100 gates on
an IC called MSI (Medium Scale Integration). Using design at this level, one can
create digital sub blocks (adders, multiplexes, counters, registers, and etc.) on an
IC. This level is LSI (Large Scale Integration), using this scale of integration people
succeeded to make digital subsystems (Microprocessor, I/O peripheral devices and
etc.) on a chip. At this point design process started getting very complicated. i.e.,
manually conversion from schematic level to gate level or gate level to layout level
was becoming somewhat lengthy process and verifying the functionality of digital
circuits at various levels became critical.
With advent of new technology, i.e., CMOS (Complementary Metal Oxide
Semiconductor) process technology, one can fabricate a chip contains more than
Million of gates. At this point design process still became critical, because of
manual converting the design from one level to other. Using latest CAD tools could
solve the problem. Existence of logic synthesis tools design engineer can easily
translate to higher-level design description to lower levels. This way of designing
(using CAD tools) is certainly a revolution in electronic industry. This may be
leading to development of sophisticated electronic products for both consumer as
well as business. Designing Systems using Hardware always gives best results
when compared to software (like Speed Reliability, performance and etc.,) Using
Dept Of ECE, SITS, Khammam 20
Specifications
Behavioral Description
r
Simulation
Simulation
avioralSynthesis
Logic Synthesis
Gate Level Net list
Constraints
Constraints
Lib
AutomaticP&R
Layout
Logic simulation
Fabrication
LayOut Management
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CMOS VLSI Design methodology designer could design and fabricate ICs without
spending much time when compared to traditional way of designing.
2.1.1 IC DESIGN FLOW:
Fig. 2.1: IC Design Flow
Dept Of ECE, SITS, Khammam 21
SPECIFICATION
Behavioral simulation
Behavioral
Simulation
RTL Description
Functionlsimulation
Lib
Gate level netlist
Layout
Logic
simulation
Multiport Serial Communication Interface Controller
2.1.2 FPGA:
A field-programmable gate array (FPGA) is an integrated circuit
designed to be configured by the customer or designer after manufacturing—hence
"field-programmable". The FPGA configuration is generally specified using a
hardware description language (HDL), similar to that used for an application-specific
integrated circuit (ASIC).
FPGAs contain programmable logic components called "logic blocks", and a
hierarchy of reconfigurable interconnects that allow the blocks to be "wired
together"— somewhat like a one-chip programmable breadboard. Logic blocks can
be configured to perform complex combinational functions. In most FPGAs, the logic
blocks also include memory elements, which may be simple flip-flops or more
complete blocks of memory. FPGA provides its user a way to configure:
1. The intersection between the logic blocks and
2. The function of each logic block.
Logic block of an FPGA can be configured in such a way that it can provide
functionality as simple as that of transistor or as complex as that of a
microprocessor. It can used to implement different combinations of combinational
and sequential logic functions. Logic blocks of an FPGA can be implemented by any
of the following:
1. Transistor pairs
2. Combinational gates like basic NAND gates or XOR gates
N-input Lookup tables
3. Multiplexers
4. Wide fan-in AND-OR structure.
Dept Of ECE, SITS, Khammam 22
Multiport Serial Communication Interface Controller
Fig: Simplified internal architecture of FPGA(http://googlepages/introduction to vlsi)
Routing in FPGAs consists of wire segments of varying lengths which can be
interconnected via electrically programmable switches.
2.1.3 FPGA Design Flow:
The ISE™ design flow comprises the following steps: design entry, design
synthesis, design implementation, and Xilinx® device programming. Design
verification, which includes both functional verification and timing verification, takes
places at different points during the design flow. This section describes what to do
during each step. For additional details on each design step, click a box in the