Multiplexer

T.Y.E.II. /1 Multiplexers AND Demultiplexer N.Kapoor --1 MULTIPLEXER (Many into One) The function performed by a multiplexer is to select 1 out of N input data sources and to transmit the selected data to a single information channel. An electronic multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal.It is a combinational circuit & is used in designing digital circuits. The logic system for a N to 1 line data selector- multiplexer is as shown. There will be m select signals such that N 2m .By selecting proper select code one of the line will be connected to the output line. A enable or strobe input signal is also used to cascade different multiplexers ,which is normally low. N input signals 1 output signal

MULTIPLEXER

m control (select) signals 4:1Multiplexer :Truth table & circuit for 4:1 multiplexer is as shown. Sometimes it is desired to use the circuit only during certain intervals of time. In such applications an additional input, called a strobe or Enable is added to each gate. All strobe inputs are tied together and are excited by a binary signal G, If G = 0, gate is enabled and multiplexing takes place. This AND-OR logic is equivalent to the NAND-NAND logic. S1 0 0 1 1S1 S0 G

S0 0 1 0 1S1

Y Io I1 I2 I3S0 G

I0

I0

I1

I1

YI2 I2

Y

I3

I3

WORKING Only one of the 4 bits D0 to D3 is transmitted to the output. Which one depends on the value of S1 & S0, the control inputs. If S1S0=00 the 1st AND gate is enabled while all other AND gates are disabled. data bit D0 is transmitted to the output, thus Y=D0.If the control signal is 10 , all the gates are disabled except 2nd AND gate, thus Y = D1 & so on.Thus control signal determines which of the input data bit is to be transmitted to the output. In place of OR gate if NOR gate is used, Y = Dn . List of ICs which provide multiplexing The 7400 series has several ICs that contain multiplexer(s): S.No.IC No. Function Output State 1 74157 Quad 2:1 mux.Output same as input given 2 74158 Quad 2:1 mux.Output is inverted input 3 74153 Dual 4:1 mux. Output same as input 4 74352 Dual 4:1 mux. Output is inverted input 5 74151A8:1 mux. Both outputs available (i.e., complementary outputs) 6 74151 8:1 mux. Output is inverted input 7 74150 16:1 mux. Output is inverted input 16:1 Multiplexer Ic 74150 is 16:1 multiplexer. It has inverted output. WORKING The 74150 is a 16 : 1 TTL multiplexer with the pin diagram shown in fig. As shown in table a low strobe enables the multiplexer, so that o/p Y equals the complement of the input data bit Y = Dn

T.Y.E.II. /1 Multiplexers AND Demultiplexer N.Kapoor --2 Only one of the 16 bits D0 to D15 is transmitted to the output. Which one depends on the value of ABCD, the control inputs. If ABCD=0000 the data bit D0 is transmitted to the output, thus Y=D0.If the control nibble is 1010 Y = D10 . Thus control nibble determines which of the input data bit is to be transmitted to the output. Strobe L L L L L L L L L L L L L L L L H ABCD LLLL L LLH LLHL LLHL LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH XXXX y D0 D1 D2 D3 D4 D5 D6 D7 D8 D7 D10 D11 D12 D13 D14 D15 H

MULTIPLEXER LOGIC Any given truth table can be implemented using multiplexer, the method is called multiplexer solution. Advantages: 1)Simplification 2) It minimizes the IC package counts. 3)Logic design is simplified. Method 1: used is SOP: 1)Locate 1 in the truth table corresponding to each minterm ,& identify the decimal number.The input Line corresponding to these numbers are connected to Vcc. 2)All other lines are connected to logic 0 i.e. GND. 3)Now inputs are applied as select signals. For example consider the truth table for the expression f(A,B,C,D)= (0,1,4,5,6,7,9,10,11,12,15) given below, using 74150 it can be implemented as Since D0 = 1= 0 , D1 = 1 = 0 , D2 = 0 = 1 & so on data inputs are wired as shown. Since any truth table can be implemented using 74150, it is called universal logic ckt. The bubble on pin 9 multiplexer is active when stroke is low, i.e. stoke is active low signal. A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y=Dn 1 1 0 0 1 1 1 1 0 1 1 1 1 0 0 1 5V 11 13 14 15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GND Method 2: 16:1multiplexing can be implemented using 8:1multiplexer.consider the truth table. 1)The truth table is partitioned as shown. 2)The relationship between input D & output Y for each group is observed. 3)There will be one of the for values 0,1,D or D.These are written in the truth table. Now A,B & C are connected to S2,S1, & S0 and connections are connected according to truth table as shown. T.Y.E.II. /1 Multiplexers AND Demultiplexer N.Kapoor --3 24 VCC

10 Y 74150 9Strobe 12

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Y 1 1 0 0 1 1 1 1 0 1 1 1 1 0 0 1

A 0 0 0 0 1 1 1 1

Inputs B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Output Y 1 0 1 1 D 1 D D

D

G D0 D1 D2 D3 D4 D5 D6 D7 A S2 B S1 C S0

Y W

V1 5

Multiplexer Tree: If multiplexer with required no of input lines is not available as IC then Ics with small no of input lines can be connected using enable/strobe inputs to get the required input lines. For ex. If we need 32:1 multiplexing but largest available IC is 16:1 then we can combine 16:1 to get 32:1 in following two ways. First; Using 2 16:1 multiplexer & OR gate Second : Using 2 16:1 multiplexer & 2:1multiplexer

Data inputs

LSBD C B

E

Data inputs

T.Y.E.II. /1 Multiplexers AND Demultiplexer N.Kapoor --4 DEMULTIPLEXER (One - into many) A demultiplexer is a system for transmitting a binary signal serial data on one of N lines, the particular line being selected by means of an address (select signal). The demultiplexing system is as shown below :--Data In put DEMULTIPLEXER Out put Enable S

Select inputs 1:4 Demultiplexer using Logic Gates

Demultiplexer Symbol

Truth Table is: Address Output selected a b 0 0 A 0 1 B 1 0 C 1 1 D Thus if address is 00 then output line A is connected to the input line.Thus A=Input Data &B,C &D equals to 0. If address is 10 then output line C is connected to the input line.Thus C=Input Data &A,B &D equals to 0& so on. Standard Demultiplexer IC packages available are the TTL 74LS138 1 to 8-output demultiplexer, the TTL 74LS139 Dual 1-to-4 output demultiplexer or the CMOS CD4514 1-to-16 output demultiplexer. Another type of demultiplexer is the 24-pin, 74LS154 which is a 4-bit to 16-line demultiplexer/decoder. Here the individual output positions are selected using a 4-bit binary coded input. Like multiplexers, demultiplexers can also be cascaded together to form higher order demultiplexers. 74LS154 -1-to-16 output demultiplexer : WORKING when enable signal is 0 the S is complement of the data. S = D . Truth - Table for Ic 74154 is as shown

G1 G2 D C B L L L L L L L L L L L L L L L L L H H L L L L L L L L L L L L L L L L H L H L L L L L L L L H H H H H H H H X X X L L L L H H H H L L L L H H H H X X X L L H H L L H H L L H H L L H H X X X

A L H L H L H L H L H L H L H L H X X X

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H

T.Y.E.II. /1 Multiplexers AND Demultiplexer N.Kapoor --5 Therefore if one or both the strobe terminals are at logic 1, all the outputs will be 1, irrespective of the select inputs. Implementing logic:

Demultiplexer Tree:

The Digital Encoder Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, a Digital Encoder more commonly called a Binary Encoder takes ALL its data inputs one at a time and then converts them into a single encoded output. So we can say that a binary encoder, is a multi-input combinational logic circuit that converts the logic level "1" data at its inputs into an equivalent binary code at its output. Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines. An "n-bit" binary encoder has 2n input lines and n-bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations. The output lines of a digital encoder generate the binary equivalent of the input line whose value is equal to "1" and are available to encode either a decimal or hexadecimal input pattern to typically a binary or B.C.D. output code. 4-to-2 Bit Binary Encoder

One of the main disadvantages of standard digital encoders is that they can generate the wrong output code when there is more than one input present at logic level "1". For example, if we make inputs D1 and D2 HIGH at logic "1" at the same time, the resulting output is neither at "01" or at "10" but will be at "11" which is an output binary number that is different to the actual input present. Also, an output code of all logic "0"s can be generated when all of its inputs are at "0" OR when input D0 is equal to one. One simple way to overcome this problem is to "Prioritise" the level of each input pin and if there was more than one input at logic level "1" the actual output code would only correspond to the input with the highest designated priority. Then this type of digital encoder is known commonly as a Priority Encoder or P-encoder for short. Priority Encoders Priority Encoders solve the problem mentioned above by allocating a priority level to each input. The encoder output corresponds to the currently active input with the highest priority. So when an input with a higher priority is present, all other inputs with a lower priority will be ignored. Priority encoders come in many forms with an example of an 8-input priority encoder along with its truth table shown below. 8-to-3 Bit Priority Encoder

Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3 bit priority encoder which has eight active LOW (logic "0") inputs and provides a 3-bit code of the highest ranked input at its output. Priority encoders output the highest order input first for example, if input lines "D2", "D3" and "D5" are applied simultaneously the output code would be for input "D5" ("101") as this has the highest order out of the 3 inputs. Once input "D5" had been removed the next highest output code would be for input "D3" ("011"), and so on.The truth table for a 8-to-3 bit priority encoder is given as: Digital Inputs Binary Output D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 X 0 0 1 0 0 0 0 0 1 X X 0 1 0 0 0 0 0 1 X X X 0 1 1 0 0 0 1 X X X X 1 0 0 0 0 1 X X X X X 1 0 1 0 1 X X X X X X 1 1 0 1 X X X X X X X 1 1 1 T.Y.E.II. /1 Multiplexers AND Decoders/Encoders N.Kapoor --6 From this truth table, the Boolean expression for the encoder above with inputs D0 to D7 and outputs Q0, Q1, Q2 is given as: Output Q0

Output Q1

Output Q2

Then the final Boolean expression for the priority encoder including the zero inputs is defined as:

In practice these zero inputs would be ignored allowing the implementation of the final Boolean expression for the outputs of the 8-to-3 priority encoder above to be constructed using individual OR gates as follows. Digital Encoder using Logic Gates

Binary Decoder A Decoder is the exact opposite to that of an "Encoder" we looked at in the last tutorial. It is basically, a combinational type logic circuit that converts the binary code data at its input into one of a number of different output lines, one at a time producing an equivalent decimal code at its output. Binary Decoders have inputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines, and a n-bit decoder has 2n output lines. Therefore, if it receives n inputs (usually grouped as a binary or Boolean number) it activates one and only one of its 2n outputs based on that input with all other outputs deactivated. A decoders output code normally has more bits than its input code and practical binary decoder circuits include, 2-to-4, 3-to-8 and 4-to-16 line configurations. A binary decoder converts coded inputs into coded outputs, where the input and output codes are different and decoders are available to "decode" either a Binary or BCD (8421 code) input pattern to typically a Decimal output code. Commonly available BCD-to-Decimal decoders include the TTL 7442 or the CMOS 4028. An example of a 2-to-4 line decoder along with its truth table is given below. It consists of an array of four NAND gates, one of which is selected for each combination of the input signals A and B. A 2-to-4 Binary Decoders.

T.Y.E.II. /1

Multiplexers AND Decoders/Encoders

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In this simple example of a 2-to-4 line binary decoder, the binary inputs A and B determine which output line from D0 to D3 is "HIGH" at logic level "1" while the remaining outputs are held "LOW" at logic "0" so only one output can be active (HIGH) at any one time. Therefore, whichever output line is "HIGH" identifies the binary code present at the input, in other words it "de-codes" the binary input and these types of binary decoders are commonly used as Address Decoders in microprocessor memory applications.

74LS138 Binary Decoder Some binary decoders have an additional input labelled "Enable" that controls the outputs from the device. This allows the decoders outputs to be turned "ON" or "OFF" and we can see that the logic diagram of the basic decoder is identical to that of the basic demultiplexer. Therefore, we say that a demultiplexer is a decoder with an additional data line that is used to enable the decoder. An alternative way of looking at the decoder circuit is to regard inputs A, B and C as address signals. Each combination of A, B or C defines a unique address which can access a location having that address. Sometimes it is required to have a Binary Decoder with a number of outputs greater than is available, or if we only have small devices available, we can combine multiple decoders together to form larger decoder networks as shown. Here a much larger 4-to-16 line binary decoder has been implemented using two smaller 3-to-8 decoders. A 4-to-16 Binary Decoder Configuration.

Inputs A, B, C are used to select which output on either decoder will be at logic "1" (HIGH) and input D is used with the enable input to select which encoder either the first or second will output the "1". Memory Address Decoder. Binary Decoders are most often used in more complex digital systems to access a particular memory location based on an "address" produced by a computing device. In modern microprocessor systems the amount of memory required can be quite high and is generally more than one single memory chip alone. One method of overcoming this problem is to connect lots of individual memory chips together and to read the data on a common "Data Bus". In order to prevent the data being "read" from each memory chip at the same time, each memory chip is selected individually one at time and this process is known as Address Decoding. In this application, the address represents the coded data input, and the outputs are the particular memory element select signals. Each memory chip has an input called Chip Select or CS which is used by the MPU to select the appropriate memory chip and a logic "1" on this input selects the device and a logic "0" on the input de-selects it. By selecting or de-selecting each chip, allows us to select the correct memory device for a particular address and when we specify a particular memory address, the corresponding memory location exists ONLY in one of the chips.

T.Y.E.II. /1 Multiplexers AND Decoders/Encoders N.Kapoor --8 For example, Lets assume we have a very simple microprocessor system with only 1Kb of RAM memory and 10 address lines. The memory consists of 128x8-bit (128x8 = 1024 bytes) devices and for 1Kb we will need 8 individual memory devices but in order to select the correct memory chip we will also require a 3-to-8 line binary decoder as shown below. Memory Address Decoding.

The binary decoder requires 3 address lines, (A0 to A2) to select each one of the 8 chips (the lower part of the address), while the remaining 7 address lines (A3 to A9) select the correct memory location on that chip (the upper part of the address). Having selected a memory location using the address bus, the information at the particular internal memory location is sent to the "Data Bus" for use by the microprocessor. This is of course a simple example but the principals remain the same for all types of memory chips or modules. Binary Decoders are very useful devices for converting one digital format to another, such as binary or BCD type data into decimal or octal etc and commonly available decoder IC's are the TTL 74LS138 3-to-8 line binary decoder or the 74ALS154 4-to-16 line decoder. They are also very useful for interfacing to 7-segment displays such as the TTL 74LS47

BCD to 7-Segment Display DecoderAs we saw in the previous tutorial, a Decoder IC, is a device which converts one digital format into another and the most commonly used device for doing this is the Binary Coded Decimal (BCD) to 7-Segment Display Decoder. 7segment LED (Light Emitting Diode) or LCD (Liquid Crystal) displays, provide a very convenient way of displaying information or digital data in the form of numbers, letters or even alpha-numerical characters and they consist of 7 individual LED's (the segments), within one single display package. In order to produce the required numbers or HEX characters from 0 to 9 and A to F respectively, on the display the correct combination of LED segments need to be illuminated and BCD to 7-segment Display Decoders such as the 74LS47 do just that. A standard 7-segment LED display generally has 8 input connections, one for each LED segment and one that acts as a common terminal or connection for all the internal segments. Some single displays have an additional input pin for the decimal point in their lower right or left hand corner. There are two important types of 7-segment LED digital display. The Common Cathode Display (CCD) - In the common cathode display, all the cathode connections of the LED's are joined together to logic "0" and the individual segments are illuminated by application of a "HIGH", logic "1" signal to the individual Anode terminals. The Common Anode Display (CAD) - In the common anode display, all the anode connections of the LED's are joined together to logic "1" and the individual segments are illuminated by connecting the individual Cathode terminals to a "LOW", logic "0" signal.

7-Segment Display Format

Truth Table for a 7-segment displayIndividual Segments Display a b c d e f g 0 1 2 3 4 5 6 7 Individual Segments a b c d e f g Display 8 9 A b C d E F

7-Segment Display Elements for all Numbers. T.Y.E.II. /1 Multiplexers AND Decoders/Encoders

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It can be seen that to display any single digit number from 0 to 9 or letter from A to F, we would need 7 separate segment connections plus one additional connection for the LED's "common" connection. Also as the segments are basically a standard light emitting diode, the driving circuit would need to produce up to 20mA of current to illuminate each individual segment and to display the number 8, all 7 segments would need to be lit resulting a total current of nearly 140mA, (8 x 20mA). Obviously, the use of so many connections and power consumption is impractical for some electronic or microprocessor based circuits and so in order to reduce the number of signal lines required to drive just one single display, display decoders such as the BCD to 7-Segment Display Decoder and Driver IC's are used instead.

Binary Coded DecimalBinary Coded Decimal (BCD or "8421" BCD) numbers are made up using just 4 data bits (a nibble or half a byte) similar to the Hexadecimal numbers we saw in the binary tutorial, but unlike hexadecimal numbers that range in full from 0 through to F, BCD numbers only range from 0 to 9, with the binary number patterns of 1010 through to 1111 (A to F) being invalid inputs for this type of display and so are not used as shown below. Decimal Binary Pattern Decimal BCD BCD Binary 8 4 2 1 Pattern 8 4 2 1 8 1 0 0 0 8 0 0 0 0 0 0 9 1 0 0 1 9 1 0 0 0 1 1 10 1 0 1 0 Invalid 2 0 0 1 0 2 11 1 0 1 1 Invalid 3 0 0 1 1 3 12 1 1 0 0 Invalid 4 0 1 0 0 4 13 1 1 0 1 Invalid 5 0 1 0 1 5 14 1 1 1 0 Invalid 6 0 1 1 0 6 15 1 1 1 1 Invalid 7 0 1 1 1 7 BCD to 7-Segment Display Decoders A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or 74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows a smaller 4-bit binary number (half a byte) to be used to display all the denary numbers from 0 to 9 and by adding two displays together, a full range of numbers from 00 to 99 can be displayed with just a single byte of 8 data bits. BCD to 7-Segment Decoder

The use of packed BCD allows two BCD digits to be stored within a single byte (8-bits) of data, allowing a single data byte to hold a BCD number in the range of 00 to 99. An example of the 4-bit BCD input (0100) representing the number 4 is given below. Example No1

In practice current limiting resistors of about 150 to 220 would be connected in series between the decoder/driver chip and each LED display segment to limit the maximum current flow. Different display decoders or drivers are available for the different types of display available, e.g. 74LS48 for common-cathode LED types, 74LS47 for common-anode LED types, or the CMOS CD4543 for liquid crystal display (LCD) types. Liquid crystal displays (LCDs) have one major advantage over similar LED types in that they consume much less power and nowadays

DECODER / ENCODER Digital computers, microprocessors and other digital systems are binary operated i.e. the data is processed in form of 0s & 1s . However human operators are more familiar with decimal system. Therefore the need arises for interfacing between digital system and human operators. To accomplish this task, numerous binary codes have been developed. The process of generating these binary codes is known as encoding. The reverse process is known as decoding. Therefore an encoder converts an active input signal into a coded output signal. Encoder Circuit is as shown ---Thus if input is 5 , the output becomes ABCD = 0101 74,PRINCE MARKET, 3rd floor,FURNITURE BAZAR,ULHASNAGAR-3. 552365 /540651 T.Y.E.I. /2 / 2 4.MULTIPLEXERS JYOTI CLASSES UNR.-3 Truth Table --In put A B C D 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 DECODER It is same as demultiplexer but without data line. BCD to Decimal Decoder The decoder is as shown in diagram. It is called 1 of 10 decoder. WORKING Let if only Y 5 AND gate has all high inputs, therefore only Y 5 output will be high. Similarly for all Y0 Y10. Therefore here subscript of the high output is equal to the decimal equivalent of the input BCD digit. Therefore it is called as BCD to decimal converter. e.g. TTL IC 7445.

T.Y.E.I. /2 / 2 5. MULTIPLEXERS JYOTI CLASSES UNR.-3 1- OF - 16 DECODER In this case one of the output line is high. Let ABCD is 0000, only the Y 0 AND gate has all inputs high ;therefore only the Y0 output is high. Similarly for all other states. it selects one of many analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. An electronic multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal. On the other end, a demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. A multiplexer is often used with a complementary demultiplexer on the receiving end. An electronic multiplexer can be considered as a multiple-input, single-output switch, and a demultiplexer as a single-input, multiple-output switch. The schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins and the short parallel side containing the output pin