MULTICHIP MODULE TECHNOLOGY HANDBOOK Philip E. Garrou Dow Chemical Company IwonaTurlik Motorola McGRAW-HILL New York San Francisco Washington, D.C. Auckland Bogota Caracas Lisbon London Madrid Mexico City Milan Montreal New Delhi San Juan Singapore Sydney Tokyo Toronto
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MULTICHIP MODULE TECHNOLOGY HANDBOOK
Philip E. Garrou Dow Chemical Company
IwonaTurlik Motorola
McGRAW-HILL New York San Francisco Washington, D.C. Auckland Bogota
Caracas Lisbon London Madrid Mexico City Milan Montreal New Delhi San Juan Singapore
Sydney Tokyo Toronto
CONTENTS
1.1 1.2 1.3 1.4 1.5 1.6
Introduction System Packaging Challenges Packaging Efficiency Miniaturization Reliability Future Challenges
References
Preface xv Acknowledgments xvli Contributors xix
Chapter 1. Technical Drivers 1.1
1.1
1.2
1.3
1.5
1.6
1.7
1.10
Chapter 2. MCM-C Materials, Processes, and Applications 2.1
2.1 Introduction 2.2 2.2 Thick Film Hybrids 2.2
2.2.1 Thick Film Technology 2.3 2.2.2 Photoimageable Thick Film Processing 2.4 2.2.3 Diffusion Patteming 2.4
3.3 Thin Film Processing 3.23 3.3.1 Dielectric Application and Curing 3.23 3.3.2 Via Formation 3.25 3.3.3 Metal Deposition and Definition Techniques 3.32
5.1 Introduction and Definitions 5.1 5.1.1 Convergence of MCM Process Technologies 5.1 5.1.2 State of the Art Circuit Density vs. Processing Area 5.2
5.2 Economic Motivations for LAP Thin Film Processing 5.4 5.3 Leveraging the Fiat Panel Display Infrastructure 5.6 5.4 LAP Construction Materials: Options and Limitations 5.7
5.5 LAP Unit Operations 5.13 5.5.1 Photoresist and Dielectric—Deposition and Curing 5.15 5.5.2 Metal Deposition and Definition 5.18 5.5.3 Photolithography 5.19 5.5.4 Via Generation by Laser Ablation 5.21 5.5.5 Inspection and Electrical Test 5.22
5.6 High-Density LAP Processes 5.22 5.6.1 Sequential (on Laminate) 5.22 5.6.2 Sequential (Nonlaminate) 5.22
5.7 Conclusions and Future Trends 5.25 References 5.26
Chapter 6. 3-D Packaging 6.1
6.1 Introduction 6.1 6.1.1 Surface Mounting Techniques for Packaged Dice 6.2 6.1.2 Multichip Module Techniques for Unpackaged Dice 6.2
X MULTICHIP MODULE TECHNOLOGY HANDBOOK
6.2 Classification 6.4 6.2.1 Bare Die Assembly vs. Packaged Die Assembly 6.4 6.2.2 Multichip Module Assembly 6.7 6.2.3 Stacked Wafer Assembly 6.7 6.2.4 Stacked Heterogeneous Parts—Microsystems 6.7
6.3 Manufacturing Techniques 6.9 6.3.1 Bare Die Assembly 6.10 6.3.2 Packaged Die Assembly 6.16 6.3.3 Multichip Module Assembly 6.21 6.3.4 Stacked Wafer Assembly 6.28 6.3.5 Stacked Heterogeneous Parts—Microsystems 6.30
11.3 Role of Physical Scale and Structure in Transmission Lines 11.6 11.3.1 Transmission Line Properties 11.7 11.3.2 When Is Controlled Impedance Important? 11.8
11.4 Materials Properties and Transmission Lines 11.10 11.4.1 Metal Resistivity and Permeability 11.10 11.4.2 Resistance and Skin Effects 11.11 11.4.3 Dielectric Constant 11.11
11.5 Estimating Delays 11.13 11.5.1 Time-Constant Estimates for Point-to-Point Interconnections 11.13 11.5.2 Time-Constant Estimates for Bus Interconnections 11.16
11.6 Delay Simulations and Examples 11.18 11.7 A System Design Perspective on Delays 11.22
11.7.1 Delay vs. Interconnection Length 11.22 11.7.2 System Size and Delay Budget 11.22
11.8 Conclusions 11.23 References 11.24
Chapter 12. Electronic Packaging for High-Performance Digital ICs 12.1
12.1 Introduction 12.2 12.2 MCMs Operating in Support of High Clock Rate Digital ICs 12.2 12.3 MCMs and High-Speed IC Design 12.9 12.4 Review of the Different MCM Types 12.10
12.5 MCM Features Required for High Clock Rate Digital Systems 12.14 12.6 Transmission Line Effect on MCM Design and Fabrication 12.17 12.7 Achieving Low-Loss Interconnects on MCMs 12.26 12.8 Multiple Power and Ground Planes in High Clock Rate MCMs 12.32 12.9 Electrical Interconnect of Chips to the MCM 12.42 12.10 Thermal Environment of High Clock Rate Digital MCMs 12.47 12.11 Testing of High-Performance MCMs 12.49
12.11.1Test Fixtures for MCMs 12.49 12.11.2Passive Testing of MCMs 12.56 12.11.3External Testing of Active-Circuit MCMs 12.58 12.11.4Built-ln Self-Testof High-Performance MCMs 12.60
12.12 Rework and Repair of High Clock Rate MCMs 12.61 12.13 Packaging of MCMs 12.62 12.14 Additional Requirements for First-Pass Functionality:
Electromagnetic Modeling Tools 12.64 12.14.1 Electromagnetic Parameter Extraction 12.64 12.14.3Modeling Noise Disturbances in Power and Ground Planes 12.72 12.14.2Simulation of Propagating Signal Wavefronts 12.71 12.14.4Has Your EM Modeling Tool Been Validated? 12.75
12.15 The Future: Mixed-Signal Multichip Modules 12.76 Acknowledgments 12.78 References 12.80 Appendix: A Brief Discussion of S-parameters 12.83
Chapter 13. Thermal Management 13.1
13.1
13.2
13.3 13.3
13.16
13.26
13.29
References 13.31
Chapter 14. Known-Good Die 14.1
14.1 Introduction 14.2 14.1.1 ConceptofKGD 14.2 14.1.2 Impact of KGD on Yield 14.3
14.2 Background 14.4 14.2.1 Traditional Integrated Circuit Manufacturing Flow 14.5 14.2.2 Bare Die Supplier Concerns 14.7 14.2.3 Defect Activation 14.8 14.2.4 Reliability Prestress 14.8 14.2.5 Electrical Pretest 14.11
14.3 Recent Progress on KGD 14.16 14.3.1 Industry and Government KGD Initiatives, Evolution, and Accomplishments 14.18 14.3.2 Standards for Unpackaged Chips 14.18 14.3.3 Die Information Exchange Format 14.21 14.3.4 Known-Good Die Technologies 14.23 14.3.5 Levels of Test and Reliability 14.32
14.5 Future Improvements 14.56 14.5.1 Wafer-Level KGD Assurance Technologies 14.56 14.5.2 Singulated Bare Die Testing 14.58 14.5.3 Information Technology: Surfing the Internet for KGD 14.61 14.5.4 KGD from PPM IC Processing 14.62 14.5.5 Füll KGD Availability 14.62
15.3 Test Metrics and Economics 15.5 15.3.1 Fault Coverage 15.5 15.3.2 Yield 15.7 15.3.3 Defect Level and Test Leakage 15.7 15.3.4 Test-Related Cost Issues 15.8
15.4 Test Design and Test Vector Generation 15.10 15.4.1 Test Vectors and Automatic Test Pattern Generation 15.11 15.4.2 Design Modeling and Simulation 15.13 15.4.3 Fault Simulation 15.15