PG-DSO-36-26 Multi-Voltage Processor Power Supply Data Sheet 1 Rev. 2.2, 2006-12-01 TLE 6368 / SONIC 1 Overview 1.1 Features • High efficiency regulator system • Wide input voltage range from 5.5V to 60V • Stand-by mode with low current consumption • Suitable for standard 12V/24V and 42V PowerNets • Step down converter as pre-regulator: 5.5V / 1.5A • Step down slope control for lowest EME • Switching loss minimization • Three high current linear post-regulators with selectable output voltages: 5V / 800mA 3.3V or 2.6V / 500mA 3.3V or 2.6V / 350mA • Six independent voltage trackers (followers): 5V / 17mA each • Stand-by regulator with 1mA current capability • Three independent undervoltage detection circuits (e.g. reset, early warning) for each linear post-regulator • Power on reset functionality • Tracker control and diagnosis by SPI • All outputs protected against short-circuit • Power PG-DSO-36-26 package • Green (RoHS compliant) version of TLE 6368 G1 • AEC qualified SMD = Surface Mounted Device Type Package TLE 6368 G1 / SONIC PG-DSO-36-26 (RoHS compliant)
59
Embed
Multi-Voltage Processor Power Supply TLE 6368 / SONIC Sheets/Infineon PDFs/TLE6368_DS... · TLE 6368 / SONIC Data Sheet 8 Rev. 2.2, 2006-12-01 2 Detailed circuit description In the
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
PG-DSO-36-26
Multi-Voltage Processor Power Supply
Data Sheet 1 Rev. 2.2, 2006-12-01
TLE 6368 / SONIC
1 Overview
1.1 Features• High efficiency regulator system• Wide input voltage range from 5.5V to 60V• Stand-by mode with low current consumption• Suitable for standard 12V/24V and 42V PowerNets• Step down converter as pre-regulator:
5.5V / 1.5A• Step down slope control for lowest EME• Switching loss minimization• Three high current linear post-regulators with
selectable output voltages: 5V / 800mA 3.3V or 2.6V / 500mA 3.3V or 2.6V / 350mA
• Six independent voltage trackers (followers): 5V / 17mA each
• Stand-by regulator with 1mA current capability• Three independent undervoltage detection circuits
(e.g. reset, early warning) for each linear post-regulator• Power on reset functionality• Tracker control and diagnosis by SPI• All outputs protected against short-circuit• Power PG-DSO-36-26 package• Green (RoHS compliant) version of TLE 6368 G1• AEC qualified
SMD = Surface Mounted Device
Type PackageTLE 6368 G1 / SONIC PG-DSO-36-26 (RoHS compliant)
TLE 6368 / SONIC
Data Sheet 2 Rev. 2.2, 2006-12-01
1.2 Short functional description
The TLE 6368 G1 / SONIC is a multi voltage power supply system especially designedfor automotive applications using a standard 12V / 24V battery as well as the new 42Vpowernet. The device is intended to supply 32 bit micro-controller systems which requiredifferent supply voltage rails such as 5V, 3.3V and 2.6V. The regulators for externalsensors are also provided.
The TLE 6368 G1 / SONIC cascades a Buck converter block with a linear regulator andtracker block on a single chip to achieve lowest power dissipation thus being able topower the application even at very high ambient temperatures. The step-down converter delivers a pre-regulated voltage of 5.5V with a minimumcurrent capability of 1.5A. Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V,or 2.6V of output voltages depending on the configuration of the device with currentcapabilities of 800mA, 500mA and 350mA. In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Theiroutputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able todrive a current of 17mA each. The trackers can be turned on and off individually by a 16bit serial peripheral interface (SPI). Through this interface also the status information ofeach tracker (i.e. short circuit) can be read out.
To monitor the output voltage levels of each of the linear regulators three independentundervoltage detection circuits are available which can be used to implement the resetor an early warning function. The supervision of the µC can be managed by the SPI-triggered window watchdog.
For energy saving reasons while the motor is turned off, the TLE 6368 G1 / SONIC offersa stand-by mode, where the quiescent current does not exceed 30µA. In this stand-bymode just the stand-by regulator remains active.
The TLE 6368 G1 / SONIC is based on Infineon Power technology SPT which allowsbipolar , CMOS and Power DMOS circuitry to be integrated on the same monolithiccircuitry.
TLE 6368 / SONIC
Data Sheet 3 Rev. 2.2, 2006-12-01
1.3 Pin configuration
Figure 1 Pin Configuration (Top View), bottom heat slug and GND corner pins are connected
R1
W AKE
Bootstrap
SEL
Q _LDO 2
Q _LDO 1
CLK
G ND
CS
ERR
Q _T2
R3
R2
G ND
Q _T3
Q _T4
Q _T5
Q _T6
G ND
IN
BO O ST
SLEW
SW
FB/L_IN
C+
CCP
C-
G ND
IN
SW
FB/L_IN
DO
DI
Q _STB
Q _T1
Q _LDO 3
6
32
31
4 33
34
35
36
30
5
7
3
2
1
9
8 29
28
27
15
23
22
13 24
25
26
21
14
16
12
11
10
18
17 20
19
TLE 6368
PG-DSO-36-
TLE 6368 / SONIC
Data Sheet 4 Rev. 2.2, 2006-12-01
1.4 Pin definitions and functionsPin No. Symbol Function1,18,19,36
GND Ground; to reduce thermal resistance place cooling areas on PCB close to these pins. The GND pins are connected internally to the heat slug at the bottom.
2 CLK SPI Interface Clock input; clocks the shift register; CLK has an internal active pull down and requires CMOS logic level inputs;see also chapter SPI
3 CS SPI Interface chip select input; CS is an active low input; serial communication is enabled by pulling the CS terminal low; CS input should only be switched when CLK is low; CS has an internal active pull up and requires CMOS logic level inputs ;see also chapter SPI
4 DI SPI Interface Data input; receives serial data from the control device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first; the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see also chapter SPI
5 DO SPI Interface Data output; this tristate output transfers diagnosis data to the controlling device; the output will remain 3-stated unless the device is selected by a low on Chip-Select CS; see also the chapter SPI
6 ERR Error output; push-pull output. Monitors failures in parallel to the SPI diagnosis word, reset via SPI. ERR is an active low, latched output.
7 Q_STB Standby Regulator Output; the output is active even when the buck regulator and all other circuitry is in off mode
8 Q_T1 Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.
9 Q_T2 Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.
10 Q_T3 Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.
TLE 6368 / SONIC
Data Sheet 5 Rev. 2.2, 2006-12-01
11 Q_T4 Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.
12 Q_T5 Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.
13 Q_T6 Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a 1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.
14 Q_LDO3 Voltage Regulator Output 3; 3.3V or 2.6V output; output voltage is selected by pin SEL (see also 2.2.2); For stability a ceramic capacitor of 470nF to GND is sufficient.
15 R3 Reset output 3, undervoltage detection for output Q_LDO3; open drain output; an external pullup resistor of 10kΩ is required
16 R2 Reset output 2, undervoltage detection for output Q_LDO2; open drain output; an external pullup resistor of 10kΩ is required
17 R1 Reset output 1, undervoltage detection for output Q_LDO1 and watchdog failure reset; open drain output ; an external pullup resistor of 10kΩ is required
20 C- Charge pump capacitor connection; Add the fly-capacitor of 100nF between C+ and C-
21 C+ Charge pump capacitor connection; Add the fly-capacitor of 100nF between C+ and C-
22 CCP Charge Pump Storage Capacitor Output; Add the storage capacitor of 220nF between pin CCP and GND.
23 SEL Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3 (see also 2.2.2)
24 Q_LDO2 Voltage Regulator Output 2; 3.3V or 2.6V output; output voltage is selected by pin SEL (see also 2.2.2); For stability a ceramic capacitor of 470nF to GND is sufficient.
25, 26 FB/L_IN Feedback and Linear Regulator Input; input connection for the Buck converter output
1.4 Pin definitions and functions (cont’d)
Pin No. Symbol Function
TLE 6368 / SONIC
Data Sheet 6 Rev. 2.2, 2006-12-01
27 Q_LDO1 Voltage Regulator Output 1; 5V output; acts as the reference for the voltage trackers.The SPI and window watchdog logic is supplied from this voltage. For stability a ceramic capacitor of 470nF to GND is sufficient.
28 Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW and pin Bootstrap, the capcitance value should be 2% of the Buck converter output capacitance
29, 31 SW Switch Output; connect both pins externally through short lines directly to the cathode of the catch diode and the Buck circuit inductance.
30, 32 IN Supply Voltage Input; connect both pins externally through short lines to the input filter/the input capacitors.
33 BOOST Boost Input; for switching loss minimization connect a diode (cathode directly to boost pin) in series with a 100nF ceramic capacitor to the IN pin and from the anode of the diode to the buck converter output a 22Ω resistor. Recommended for 42V applications. In 12/24V applications connect boost directly to IN.
34 WAKE Wake Up Input; a positive voltage applied to this pin turns on the device
35 SLEW Slew control Input; a resistor to GND defines the current slope in the buck switch for reduced EME
1.4 Pin definitions and functions (cont’d)
Pin No. Symbol Function
TLE 6368 / SONIC
Data Sheet 7 Rev. 2.2, 2006-12-01
1.5 Basic block diagram
Figure 2 Block Diagram
R1LinearReg. 1
LinearReg. 2
Tracker5V
ResetLogic
WindowWatchdog
SPI16 bit
µ-controller /memorysupply
Sensorsupplies
(off boardsupplies)
PowerDownLogic
Tracker5V
Tracker5V
Tracker5V
Tracker5V
Tracker5V
TLE 6368
StandbyRegulator
OSZ PWM
Driver
Error-Amplifier
InternalReference
feedback
2*
2*
2*
ref
ref
ref
ref
ref
ref
Protection
4*
BUCKREGULATOR
Boost
IN
Slew
Wake
R2
R3
CLK
CS
DI
DO
ERRGND
Q_STB
SW
Bootstrap
FB/L_IN
C+
C-
CCP
SEL
Q_LDO1
Q_LDO2
Q_LDO3
Q_T1
Q_T2
Q_T3
Q_T4
Q_T5
Q_T6
ChargePump
LinearReg. 3
TLE 6368 / SONIC
Data Sheet 8 Rev. 2.2, 2006-12-01
2 Detailed circuit descriptionIn the following major buck regulator blocks, the linear voltage regulators and trackers,the undervoltage reset function, the watchdog and the SPI are described in more detail.For applications information e.g. choice of external components, please refer to section5.
2.1 Buck RegulatorThe diagram below shows the internal implemented circuit of the Buck converter, i. e. theinternal DMOS devices, the regulation loop and the other major blocks.
Figure 3 Detailed Buck regulator diagram
The 1.5A Buck regulator consists of two internal DMOS power stages including a currentmode regulation scheme to avoid external compensation components plus additionalblocks for low EME and reduced switching loss. Figure 3 indicates also the principle how
Int. voltageregulator
Int. chargepump
Zero crossdetection
Divider
Oscillator1.4MHz
Slope logic
under-voltagelockout
Gate driver
Delay unit
5V 14V
150µA
Vref=6V
Voltagefeedbackamplifier
Currentsense
amplifier+
Currentcomparator
PWM logic
Gate off signalfrom overtemp orsleep command
Trigger forgate on
Trigger forgate off
Slopecompensation
Lowpass
Lowpass
switching frequency 330kHz
Slopecontrol
fromcurrent sensing
tocurrent sense
amplifier
FB/L_IN C+
C-
CCP
SLEW
SWBOOT-STRAP
BOOST
SW
IN
IN
external components
Main switch ON/OFF
Slope switchcharge signal
Slope switchdischarge signal
8 to 10V
MainDMOS
SlopeDMOS
pins
TLE 6368 / SONIC
Data Sheet 9 Rev. 2.2, 2006-12-01
the gate driver supply is managed by the combination of internal charge pump, externalcharge pump and bootstrap capacitor.
2.1.1 Current mode control schemeThe regulation loop is located at the left lower corner in the schematic, there you find thevoltage feedback amplifier which gives the actual information of the actual output voltagelevel and the current sense amplifier for the load current information to form finally theregulation signal. To avoid subharmonic oscillations at duty cycles higher than 50% theslope compensation block is necessary. The control signal formed out of those three blocks is finally the input of the PWMregulator for the DMOS gate turn off command, which means this signal determines theduty cycle. The gate turn on signal is set by the oscillator periodically every 3µs whichleads to a Buck converter switching frequency around 330kHz. With decreasing input voltage the device changes to the so called pulse skipping modewhich means basically that some of the oscillator gate turn off signals are ignored. Whenthe input voltage is still reduced the DMOS is turned on statically (100% duty cycle) andits gate is supplied by the internal charge pump. Below typical 4.5V at the feedback pinthe device is turned off.During normal switching operation the gate driver is supplied bythe bootstrap capacitor.
2.1.2 Start-up procedureTo guarantee a device startup even under full load condition at the linear regulatoroutputs a special start up procedure is implemented. At first the bootstrap capacitor ischarged by the internal charge pump. Afterwards the output capacitor is charged wherethe driver supply in that case is maintained only by the bootstrap capacitor. Once theoutput capacitor of the buck converter is charged the external charge pump is activatedbeing able to supply the linear regulators and finally the linear regulators are released tosupply the loads.
2.1.3 Reduction of electromagnetic emissionIn figure 3 it is recognized that two internal DMOS switches are used, a main switch andan auxiliary switch. The second implemented switch is used to adjust the current slopeof the switching current. The slope adjustment is done by a controlled charge anddischarge of the gate of this DMOS. By choosing the external resistor on the SLEW pinappropriate the current transition time can be adjusted between 20ns and 100ns.
2.1.4 Reducing the switching lossesThe second purpose of the slope DMOS is to minimise the switching losses. Once beingin freewheeling mode of the buck regulator the output voltage level is sufficient to forcethe load current to flow, the input voltage level is not needed in the first moment. By afeedback network consisting of a resistor and a diode to the boost pin (connection see
TLE 6368 / SONIC
Data Sheet 10 Rev. 2.2, 2006-12-01
section 5) the output voltage level is present at the drain of the switch. As soon as thevoltage at the SW pin passes zero volts the handover to the main switch occurs and thetraditional switching behaviour of the Buck switch can be observed.
2.2 Linear Voltage RegulatorsThe Linear regulators offer, depending on the version, voltage rails of 5V, 3.3V and 2.6Vwhich can be determined by a hardware connection (see table at 2.2.2) for proper powerup procedure. Being supplied by the output of the Buck pre-regulator the power losswithin the three linear regulators is minimized. All voltage regulators are short circuit protected which means that each regulatorprovides a maximum current according to its current limit when shorted. Together withthe external charge pump the NPN pass elements of the regulators allow low dropoutvoltage operation. By using this structure the linear regulators work stable even with aminimum of 470nF ceramic capacitors at their output.Q_LDO1 has 5V nominal output voltage, Q_LDO2 has a hardware programmableoutput voltage of 3.3V or 2.6V and Q_LDO3 is also programmable to 3.3V or 2.6V (seesection 2.2.2). All three regulators are on all the time, if one regulator is not needed abase load resistor in parallel to the output capacitance for controlled power down isrecommended.
2.2.1 Startup Sequence Linear RegulatorsWhen acting as a 32 bit µC supply the so-called power sequencing (the dependency ofthe different voltage rails to each other) is important. Within the TLE 6368 G1 / SONIC,the following Startup-Sequence is defined (see also figure 4): VQ_LDO2 ≤ VQ_LDO1; VQ_LDO3 ≤ VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V or 3.3V and VQ_LDO3 = 2.6V or 3.3V The power sequencing refers to the regulator itself, externally voltages applied atQ_LDO2 and Q_LDO3 are not pulled down actively by the device if Q_LDO1 is lowerthan those outputs. That means for the power down sequencing if different output capacitors and differentloads at the three outputs of the linear regulators are used the voltages at Q_LDO2 andQ_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid thisbehaviour three Schottky diodes have to be connected between the three outputs of thelinear regulators in that way that the cathodes of the diodes are always connected to thehigher nominal rail.
TLE 6368 / SONIC
Data Sheet 11 Rev. 2.2, 2006-12-01
Figure 4 Power-up and -down sequencing of the regulators
2.2.2 Q_LDO2 and Q_LDO3 output voltage selection*To determine the output voltage levels of the three linear regulators, the selection pin(SEL, pin 23) has to be connected according to the matrix given in the table below.
* for different output voltages please refer to the multi voltage supply TLE6361
Definition of Output voltage Q_LDO2 and Q_LDO3Select Pin SEL connected to
Q_LDO2 output voltage
Q_LDO3 output voltage
GND 3.3 V 3.3 VQ_LDO1 2.6 V 2.6 VQ_LDO2 2.6 V 3.3 V
VLDO_EN
t
VFB/L_IN
Power Sequencing
0.7V
5V
3.3V2.6V
VRth5
t
2.6VVRth2.6
t0.7V
VQ_LDO1
+/- 50mV
VQ_LDO3 (3.3V Mode)
3.3VVRth3.3
t
+/- 50mV
VQ_LDO2 (2.6V Mode)
5V LDO 5V LDO
5V LDO 5V LDO
TLE 6368 / SONIC
Data Sheet 12 Rev. 2.2, 2006-12-01
2.3 Voltage TrackersFor off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA outputcurrent capability each are available. The output voltages match Q_LDO1 within +5 / -15mV. They can be individually turned on and off by the appropriate SPI commandword sent by the microcontroller. A ceramic capacitor with the value of 1µF at the outputof each tracker is sufficient for stable operation without oscillation. The tracker outputs can be connected in parallel to obtain a higher output currentcapability, no matter if only two or up to all six trackers are tied together. For uniformlydistributed current density in each tracker internal balance resistors at each output areforeseen internally. By connecting two sets of three trackers in parallel two sensors withmore than 50mA each can be supplied, all six in parallel give more than 100mA.The tracker outputs can withstand short circuits to GND or battery in a range from -4 to+40V. A short circuit to GND is detected and indicated individually for each tracker in theSPI status word. Also an open load condition might be recognised and indicated as afailure condition in the SPI status word. A minimum load current of 2mA is required toavoid open load failure indication. In case of connecting several trackers to a commonbranch balancing currents can prevent proper operation of the failure indication.
2.4 Standby RegulatorThe standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA outputcurrent which is on all the time. It is intended to supply the microcontroller in stop modeand requires then only a minimum of quiescent current (<30µA) to extend the batterylifetime.
2.5 Charge PumpThe 1.6 MHz charge pump with the two external capacitors will serve to supply the baseof the NPN linear regulators Q_LDO1 and Q_LDO3 as well as the gate of the BuckDMOS transistor in 100% duty cycle operation at low battery condition. The charge pumpvoltage in the range of 8 to 10V can be measured at pin 22 (CCP) but is not intended tobe used as a supply for additional circuitry.
2.6 Power On ResetA power on reset is available for each linear voltage regulator output. The reset outputlines R1, R2 and R3 are active (low) during start up and turn inactive with a reset delaytime after Q_LDO1, Q_LDO2 and Q_LDO3 have reached their reset threshold. Thereset outputs are open drain, three pull up resistors of 10kΩ each have to be connectedto the I/O rail (e.g. Q_LDO1) of the µC. All three reset outputs can be linked in parallel toobtain a wired-OR.The reset delay time is 8 ms by default and can be set to higher values as 16 ms, 32 msor 64 ms by SPI command. At each power up of the device in case the output voltage at
TLE 6368 / SONIC
Data Sheet 13 Rev. 2.2, 2006-12-01
Q_LDO1 had decreased below 3.3V (max.), the SPI will reset to the default settingsincluding the 8ms delay time. If the voltage on Q_LDO1 during sleep or power off modewas kept above 3.3V the delay time set by the last SPI command is valid.
Figure 5 Undervoltage reset timing
2.7 RAM good flagA RAM good flag will be set within the SPI status word when the Q_LDO1 voltage dropsbelow 2.3V. A second one will be set if Q_LDO2 drops below typical 1.4V. Both RAMgood flags can be read after power up to determine if a cold or warm start needs to beprocessed. Both RAM good flags will be reset after each SPI cycle.
2.8 ERR PinA hardware error pin indicates any fault conditions on the chip. It should be connected toan interrupt input of the microcontroller. A low signal indicates an error condition. Themicrocontroller can read the root cause of the error by reading the SPI register.
2.9 Window WatchdogThe on board window watchdog for supervision of the µC works in combination with theSPI. The window watchdog logic is turned off per default and can be activated by onespecial bit combination in the SPI command word. When operating, the windowwatchdog is triggered when CS is low and Bit WD-Trig in the SPI command word is setto “1”. The watchdog trigger is recognized with the low to high transition of the CS signal.To allow reading the SPI at any time without getting a reset due to misinterpretation theWD-Trig bit has to be set to “0” to avoid false trigger conditions.
VFB/L_IN
tVQ_LDOx
tVRx
t
VRTH,Q_LDOx
tRES
trr
< trr
thermalshutdown
undervoltage
overload
tRES tRES tRES
TLE 6368 / SONIC
Data Sheet 14 Rev. 2.2, 2006-12-01
Figure 6 Window watchdog timing definition
Figure 6 shows some guidelines for designing the watchdog trigger timing taking theoscillator deviation of different devices into account. Of importance (w.c.) is themaximum of the closed window and the minimum of the open window in which thetrigger has to occur.The length of the OW and CW can be modified by SPI command. If a change of thewindow length is desired during the Watchdog function is operating please send the SPIcommand with the new timing with a ’Watchdog trigger Bit’ D15=1.In this case the nextCW will directly start with the new length. A minimum time gap of > 1/48 of the actual OW/CW time between a ’Watchdog disable’and ’Watchdog enable’ SPI-command should be maintained. This allows the internalWatchdog counters to be resetted. Thus after the enable command the Watchdog willstart properly with a full CW of the adjusted length.
t ECW, w.c.= tCW (1+∆)
closed window open window
tCW=tCW
definition
fOSC=fOSCmax
reset start delay time after windowwatchdog timeout
reset delay time without trigger
reset duration time after windowwatchdog time-out
tSR = tOW/2
tOW=tCW
tWDR = tRES
t OWmin
fOSC=fOSCmin
definition
worst cases
t EOW, w.c.= ( tCW+tOW )(1-∆)
Example with:tCW=128ms∆=25% (oscillator deviation)
tECW, w.c. = 128(1.25) = 160ms
tEOW, w.c = (128+128)(0.75) = 192ms
towmin = 32ms
(not the same scale)
t EOW = end of open windowtECW
(not the same scale)
t OWmin= tOW - ∆ * ( tOW + 2* tCW )Minimum open window time:
TLE 6368 / SONIC
Data Sheet 15 Rev. 2.2, 2006-12-01
Figure 7 Window watchdog timing
Figure 7 gives some timing information about the window watchdog. Looking at theupper signals the perfect triggering of the watchdog is shown. When the 5V linearregulator Q_LDO1 reaches its reset threshold, the reset delay time has to run off before
V R th1
tR ESR 1
t
t
V Q _LD O 1
1V
t
W atchdogw indow
t
C S
t
ER R
Perfect triggering after Pow er on R eset
Incorrect triggering
t
W atchdogw indow
C W O W
t
C S
3) 4)
1) W atchdog enable com m and w ith no trigger: D 0D 9D 14D 15=01002) W atchdog trigger: D 15=13) Pretrigger4) M issing trigger
Legend: O W = O pen w indowC W = C losed w indow
w ith W D -trig=1
tSR
C W O W C W O W C W C W O W
tC W
2)2)2)1)
TLE 6368 / SONIC
Data Sheet 16 Rev. 2.2, 2006-12-01
the closed window (CW) starts. Then three valid watchdog triggers are shown, no effecton the reset line and/or error pin is observed. With the missing watchdog trigger signalthe error signal turns low immediately where the reset is asserted after another delay ofhalf the closed window time.Also shown in the figure are two typical failure modes, one pretrigger and one missingsignal. In both cases the error signal will go low immediately the failure is detected withthe reset following after the half closed window time.
2.10 Overtemperature ProtectionAt a chip temperature of more than 150° an error and temperature flag is set and can beread through the SPI. The device is switched off if the device reaches theovertemperature threshold of 170°C. The overtemperature shutdown has a hysteresis toavoid thermal pumping.
2.11 Power Down ModeThe TLE 6368 G1 / SONIC is started by a static high signal at the wake input or a highpulse with a minimum of 50µs duration at the Wake input (pin 34). Voltages in the rangebetween the turn on and turn off thresholds for a few 100µs must be avoided!By SPI command (“Sleep”-bit, D8, equals zero) all voltage regulators including theswitching regulator except the standby regulator can be turned off completely only if thewake input is low. In the case the Wake input is permanently connected to battery thedevice cannot be turned off by SPI command, it will always turn on again.For stable “on” operation of the device the “Sleep”-bit, D8 has to be set to high at eachSPI cycle!When powering the device again after power down the status of the SPI controlleddevices (e.g. trackers, watchdog etc.) depends on the output voltage on Q_LDO1. Didthe voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section)is set otherwise the last SPI command defines the status.
2.12 Serial Peripheral InterfaceA standard 16 bit SPI is available for control and diagnostics. It is capable to operate ina daisy chain. It can be written or read by a 16 bit SPI interface as well as by an 8 bit SPIinterface.The 16-bit control word (write bit assignment, see Figure 8) is read in via the data inputDI, synchronous to the clock input CLK supplied by the µC beginning with the LSB D0.The diagnosis word appears in the same way synchronously at the data output DO (readbit assignment, see figure 9), so with the first bit shifted on the DI line the first bit appearson the DO line.The transmission cycle begins when the TLE 6368 G1 / SONIC is selected by the “notchip select” input CS (H to L). After the CS input returns from L to H, the word that has
TLE 6368 / SONIC
Data Sheet 17 Rev. 2.2, 2006-12-01
been read in at the DI line becomes the new control word. The DO output switches totristate status at this point, thereby releasing the DO bus circuit for other uses. For detailsof the SPI timing please refer to Figures 10 to 13.The SPI will be reset to default values given in the following table “write bit meaning” ifthe RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V).The reset will be active as long as the power on reset is present so during the reset delaytime at power up no SPI commands are accepted.The register content of the SPI - including watchdog timings and reset delay timings - ismaintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did notdecrease below 3.3V).
2.12.1 Write modeThe following tables show the bit assignment to the different control functions, how tochange settings with the right bit combination and also the default status at power up.
2.12.2 Write mode bit assignment
Figure 8 Write Bit assignment
Write Bit meaningFunction Bit Combination DefaultNot assigned D1 X XTracker 1 to 6 - control: turn on/off the individual trackers
2.12.3 Read mode Below the status information word and the bit assignments for diagnosis are shown.
2.12.3.1 Read mode bit assignment
Figure 9 Read Bit assignment
Error bit D0:The error output ERR is low and the error bit indicates fail function if the temperatureprewarning or the watchdog error is active, further if one RAM good indicates a cold startor if a voltage tracker does not settle within 1ms when it is turned on.
Reset timing:Reset delay time tRES valid at warm start
D10D11 00: 64ms10: 32ms01: 16ms 11: 8ms
11
Window watchdog timing:Open window time tOW and closed window time tCW valid at warm start
3.4 Electrical CharacteristicsThe electrical characteristics involve the spread of values guaranteed within thespecified supply voltage and ambient temperature range. Typical values represent themedian values at room temperature, which are related to production processes.
Item Parameter Symbol Limit Values Unit Test Conditionsmin. typ. max.
TLE 6368 / SONIC
Data Sheet 44 Rev. 2.2, 2006-12-01
4 Typical performancecharcteristics
Buck converter switching frequencyvs. junction temperature
Buck converter output voltage at 1.5A loadvs. junction temperature
Buck converter DMOS on-resistancevs. junction temperature
Buck converter current limitvs. junction temperature
-50 -20 10 40 70 100 130 160Tj
°C
fSW
kHz
280
300
420
320
340
360
380
400
-50 -20 10 40 70 100 130 160Tj
°C
VFB/L_IN
V
5.3
5.4
6.0
5.5
5.6
5.7
5.8
5.9
-50 -20 10 40 70 100 130 160Tj
°C
RON
mΩ
50
100
400
150
200
250
300
350
-50 -20 10 40 70 100 130 160Tj
°C
IMAX
A
0.5
1.0
4.0
1.5
2.0
2.5
3.0
3.5
TLE 6368 / SONIC
Data Sheet 45 Rev. 2.2, 2006-12-01
Start-up bootstrap charging currentvs. junction temperature
Device start-up voltage (acc. to spec. 3.2)vs. junction temperature
Bootstrap UV lockout, turn on thresholdvs. junction temperature
Device wake up thresholdsvs. junction temperature
-50 -20 10 40 70 100 130 160Tj
°C
IBTSTR
µA
0
40
280
80
120
160
200
240
-50 -20 10 40 70 100 130 160Tj
°C
VIN
V
2.5
3.0
6.0
3.5
4.0
4.5
5.0
5.5
-50 -20 10 40 70 100 130 160Tj
°C
VBTSTR,
turn on
V
5.0
5.5
8.5
6.0
6.5
7.0
7.5
8.0
-50 -20 10 40 70 100 130 160Tj
°C
Vwake th
V
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Vwake th, on
Vwake th, off
TLE 6368 / SONIC
Data Sheet 46 Rev. 2.2, 2006-12-01
Q_LDO1 output voltage at 800mA loadvs. junction temperature
Reset1 threshold at decreasing V_LDO1vs. junction temperature
Q_LDO1 current limitvs. junction temperature
Q_LDO2 output voltage at 400mA load(2.6V mode) vs. junction temperature
-50 -20 10 40 70 100 130 160Tj
°C
VQ_LDO1
V
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
-50 -20 10 40 70 100 130 160Tj
°C
VRTH
Q_LDO1, de
V
4.45
4.50
4.55
4.60
4.65
4.70
4.75
4.80
-50 -20 10 40 70 100 130 160Tj
°C
IQ_LDO1
V
1400
1300
700
800
900
1000
1100
1200
-50 -20 10 40 70 100 130 160Tj
°C
VQ_LDO2
V
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
TLE 6368 / SONIC
Data Sheet 47 Rev. 2.2, 2006-12-01
Q_LDO2 current limit (2.6V mode)vs. junction temperature
Q_LDO3 output voltage at 300mA load(3.3V mode) vs. junction temperature
Reset2 threshold at decreasing V_LDO2(2.6V mode) vs. junction temperature
Q_LDO3 current limit (3.3V mode)vs. junction temperature
-50 -20 10 40 70 100 130 160Tj
°C
IQ_LDO2
V
850
500
550
600
650
700
750
800
-50 -20 10 40 70 100 130 160Tj
°C
VQ_LDO3
V
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
-50 -20 10 40 70 100 130 160Tj
°C
VRTH
Q_LDO2, de
V
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
-50 -20 10 40 70 100 130 160Tj
°C
IQ_LDO3
V
600
250
300
350
400
450
500
550
TLE 6368 / SONIC
Data Sheet 48 Rev. 2.2, 2006-12-01
Reset3 threshold at decreasing V_LDO3(3.3V mode) vs. junction temperature
Tracker current limitvs. junction temperature
Tracker accuracy with respect to V_LDO1vs. junction temperature
Q_STB output voltage at 500µA loadvs. junction temperature
-50 -20 10 40 70 100 130 160Tj
°C
VRTH
Q_LDO3, de
V
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
-50 -20 10 40 70 100 130 160Tj
°C
IQ_Tx
mA
32
30
18
20
22
24
26
28
-50 -20 10 40 70 100 130 160Tj
°C
dVQ_Tx
mV
4
2
-10
-8
-6
-4
-2
0
-50 -20 10 40 70 100 130 160Tj
°C
VQ_STB
V
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
TLE 6368 / SONIC
Data Sheet 49 Rev. 2.2, 2006-12-01
Q_STB current limitvs. junction temperature
Device current consumption in off modevs. junction temperature
-50 -20 10 40 70 100 130 160Tj
°C
IQ_STB
mA
4.0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
-50 -20 10 40 70 100 130 160Tj
°C
Iq, off
µA
35
30
0
5
10
15
20
25
TLE 6368 / SONIC
Data Sheet 50 Rev. 2.2, 2006-12-01
5 Application Information
5.1 Application Diagram
Figure 14 Application Diagram
TLE 6368
AEA03380ZR.VSD
BuckRegulator
StandbyRegulator
2.5 V
Driver
PWMOSZ
BOOTSTRAP
Q_STB
BuckOutput
IN
BOOST
SLEW
CI310 to100 nF
RSlew0 to20 kΩ
+ CI247 µF
LIUp to47 µH
CI1100 nF
Battery
CBOOST100 nF
DBOOST
FB/L_IN
ChargePump
CFLY100 nF
CCCP220 nF
C+
C-
CCP
Protection
ToIGN
WAKE
Lin. Reg.5 V
Lin. Reg.3.3/2.6 V
Lin. Reg.5/3.3 V
Tracker5 V
Ref
CLDO1,1470 nF
+ CLDO1,24.7 µF
SEL
Q_LDO1
CLDO2,1470 nF
+ CLDO2,24.7 µF
Q_LDO2
CLDO3,1470 nF
+ CLDO3,24.7 µF
Q_LDO3
CT11 µF
Q_T1
Tracker5 V
Ref
CT21 µF
Q_T2
Tracker5 V
Ref
CT31 µF
Q_T3
Tracker5 V
Ref
CT41 µF
Q_T4
Tracker5 V
Ref
CT51 µF
Q_T5
Tracker5 V
Ref
CT61 µF
Q_T6
SPI16 Bit
1 kΩ DO
10 kΩ DI
CS10 kΩ
CLK10 kΩ
PowerDownLogic
ResetLogic
R1
R2
Q_LDO1
R3
WindowWatchdog
4*GND
SensorSupplies(off boardsupplies)
µ-Controller/MemorySupply
2*
CSTB100 nF
RBoost
22 Ω
SW 2*LB
47 µHCBTSTR680 nF
DB3 A,60 V
+CB> 10 µFceramic or> 20 µFlow ESRtantalum
2*
ERR
ToµC
ToµC
10 kΩ10 kΩ
Error-Amplifier Internal
Reference
Feedback
10 kΩ
10 kΩ
TLE 6368 / SONIC
Data Sheet 51 Rev. 2.2, 2006-12-01
5.2 Buck converter circuitA typical choice of external components for the buck converter is given in figure 14. Forbasic operation of the buck converter the input capacitor CI2, the bootstrap capacitorCBTP, the catch diode DB, the inductance LB, the output capacitor CB and the chargepump capacitors CFLY and CCCP are necessary. A Zener Diode at the FB/L_IN input isrecommended as a protection against overvoltage spikes.The additional components shown on top of the circuit lower the electromagneticemission (LI, CI1, CI3, RSlew) and the switching losses (RBoost, CBoost, DBoost). For 12Vbattery systems the switching loss minimization feature might not be used. The Boost pin(33) is connected directly to the IN pins (32, 30) in that case and the components RBoost,CBoost and DBoost are left away.
5.2.1 Buck inductance (LB) selection:The inductance value determines together with the input voltage, the output voltage andthe switching frequency the current ripple which occurs during normal operation of thestep down converter. This current ripple is important for the all over ripple at the outputof the switching converter. As a rule of thumb this current ripple ∆I is chosen between 10% and 50% of the loadcurrent.
For optimum operation of the control loop of the Buck converter the inductance valueshould be in the range indicated in section 3.3, recommended operation range.When picking finally the inductance of a certain supplier (Epcos, Coilcraft etc.) thesaturation current has to be considered. With a maximum current limit of the Buckconverter of 3.2A an inductance with a minimum saturation current of 3.2A has to bechosen.
5.2.2 Buck output capacitor (CB) selection:The choice of the output capacitor effects straight to the minimum achievable ripplewhich is seen at the output of the buck converter. In continuous conduction mode theripple of the output voltage equals:
From the formula it is recognized that the ESR has a big influence in the total ripple atthe output, so ceramic types or low ESR tantalum capacitors are recommended for theapplication.One other important thing to note are the requirements for the resonant frequency of theoutput LC-combination. The choice of the components L and C have to meet also thespecified range given in section 3.3 otherwise instabilities of the regulation loop mightoccur.
5.2.3 Input capacitor (CI2) selection:At high load currents, where the current through the inductance flows continuously, theinput capacitor is exposed to a square wave current with its duty cycle VOUT/VI. Toprevent a high ripple to the battery line a capacitor with low ESR should be used. Themaximum RMS current which the capacitor has to withstand is calculated to:
5.2.4 Freewheeling diode / catch diode (DB)For lowest power loss in the freewheeling path Schottky diodes are recommended. Withthose types the reverse recovery charge is negligible and a fast handover fromfreewheeling to forward conduction mode is possible. Depending on the application (12Vbattery systems) 40V types could be also used instead of the 60V diodes.A fast recovery diode with recovery times in the range of 30ns can be also used if smallerjunction capacitance values (smaller spikes) are desired, the slew resistor should be setin this case between 10 and 20kW.
VRipple ∆I RESRCB1
8 fSW CB⋅ ⋅----------------------------+
⋅=
IRMS ILOADVOUTVIN-------------- 1 1
3--- ∆I
2 ILOAD⋅----------------------- 2⋅+⋅ ⋅=
TLE 6368 / SONIC
Data Sheet 53 Rev. 2.2, 2006-12-01
5.2.5 Bootstrap capacitor (CBTP)The voltage at the Bootstrap capacitor does not exceed 15V, a ceramic type with aminimum of 2% of the buck output capacitance and voltage class 16V would besufficient.
5.2.6 External charge pump capacitors (CFLY, CCCP)Out of the feedback voltage the charge pump generates a voltage between 8 and 10V.The fly capacitor connected between C+ and C- is charged with the feedback voltagelevel and discharged to achieve the (almost) double voltage level at CCP. CFLY is chosento 100nF and CCCP to 220nF, both ceramic types. The connection of CCP to a voltage source of e.g. 7V (take care of the maximumratings!) via a diode improves the start-up behavior at very low battery voltage. The diodewith the cathode on CCP has to be used in order to avoid any influence of the voltagesource to the device’s operation and vice versa.
5.2.7 Input filter components for reduced EME (CI1, CI2, CI3, LI, RSlew)At the input of Buck converters a square wave current is observed causingelectromagnetical interference on the battery line. The emission to the battery lineconsists on one hand of components of the switching frequency (fundamental wave) andits harmonics and on the other hand of the high frequency components derived from thecurrent slope. For proper attenuation of those interferers a π-type input filter structure isrecommended which is built up with inductive (LI) and capacitive components (CI1, CI2,CI3). The inductance can be chosen up to the value of the Buck converter inductance,higher values might not be necessary, CI1 and CI3 should be ceramic types and for CI2 aninput capacitance with very low ESR should be chosen and placed as close to the inputof the Buck converter as possible. Inexpensive input filters show due to their parasitics a notch filter characteristic, whichmeans basically that the lowpass filter acts from a certain frequency as a highpass filterand means further that the high frequency components are not attenuated properly. Forthat reason the TLE 6368 G1 / SONIC offers the possibility of current slope adjustment.The current transition time can be set by the external resistor (located on the SLEW pin)to times between 20ns and 80ns by varying the resistor value between 0Ω (fastesttransition) and 20kΩ (slowest transition).
5.2.8 Feedback circuit for minimum switching loss (RBoost, CBoost, DBoost)To decrease the switching losses to a minimum the external components RBoost, CBoostand DBoost are needed. The current though the feedback resistor RBoost is about a few mAwhere the Diode DBoost and the capacitor CBoost run a part of the load current.If this feature is not needed the three components are not needed and the Boost pin (33)can be connected directly to the IN pins(32, 30).
TLE 6368 / SONIC
Data Sheet 54 Rev. 2.2, 2006-12-01
5.3 Reverse polarity protectionThe Buck converter is due to the parasitic source drain diode of the DMOS not reversepolarity protected. Therefore, as an example, the reverse polarity diode is shown in theapplication circuit, in general the reverse polarity protection can be done in differentways.
5.4 Linear voltage regulators (CLDO1, 2, 3)As indicated before the linear regulators show stable operation with a minimum of 470nFceramic capacitors. To avoid a high ripple at the output due to load steps this output capmight have to be increased to some few µF capacitors.
5.5 Linear voltage trackers (CT1,2,3,4,5,6)The voltage trackers require at their outputs 1µF ceramic capacitors each to avoid someoscillation at the output. If needed the tracker outputs can be connected in parallel, in thatthe output capacitor increases linear according to the number of parallel outputs.
5.6 Reset outputs (R1,2,3)The undervoltage/watchdog reset outputs are open drain structures and require externalpull up resistors in the range of 10kΩ to the µC I/O voltage rail.
TLE 6368 / SONIC
Data Sheet 55 Rev. 2.2, 2006-12-01
5.7 Components recommendation - overview
Device Type Supplier RemarkLI B82479 EPCOS 22µH, 3.5A, 47mΩ
C-caseCLDOx Ceramic various 470nF, 10VCTx Ceramic various 1µF, 60V
TLE 6368 / SONIC
Data Sheet 56 Rev. 2.2, 2006-12-01
5.8 Layout recommendationThe most sensitive points for Buck converters - when considering the layout - are thenodes at the input and the output of the Buck switch, the DMOS transistor. For proper operation the external catch diode and Buck inductance have to beconnected as close as possible to the SW pins (29, 31). Best suitable for the connectionof the cathode of the Schottky diode and one terminal of the inductance would be a smallplain located next to the SW pins. The GND connection of the catch diode must be also as short as possible. In general theGND level should be implemented as surface area over the whole PCB as second layer,if necessary as third layer.The pin FB/L_IN is sensitive to noise. With an appropriate layout the Buck outputcapacitor helps to avoid noise coupling to this pin. Also filtering of steep edges at thesupply voltage pin e.g. as shown in the application diagram is mandatory. CI2 may eitherbe a low ESR Tantalum capacitor or a ceramic capacitor. A minimum capacitance of10µF is recommended for CI2.To obtain the optimum filter capability of the input π-filter it has to be located also asclose as possible to the IN pins, at least the ceramic capacitor CI3 should be next to thosepins.
TLE 6368 / SONIC
Data Sheet 57 Rev. 2.2, 2006-12-01
6 Package Outlines
Green Product (RoHs compliant)To meet the world-wide customer requirements for environmentally friendly productsand to be compliant with government regulations the device is available as a greenproduct. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable forPb-free soldering according to IPC/JEDEC J-STD-020).
Bottom View
1) Does not include plastic or metal protrusion of 0.15 max. per side2) Stand off
1 18
0.25
±0.11.1
36
+0.130.25
36x
19
M
(Heatslug)15.74
0.65
17 x 0.65 = 11.05
±0.1
CA B
19
C3.
25
3.5
MA
X.
+0.1
2)0
0.1±0
.1
36
2.8B
11±0.15 1)
1.3
5˚0.25 ±3
˚
-0.0
2+0
.07
6.3
14.2 ±0.3B
±0.15
0.25
Heatslug
0.95
Heatslug
±0.1
5.9
3.2
±0.1
13.710 1-0.2
Index Marking
15.9 1)±0.1A
1 x 45˚
PG-DSO-36-26SMD = Surface Mounted DeviceDimensions in mm
You can find all of our packages, sorts of packing and others in ourInfineon Internet Page “Products”: http://www.infineon.com/products.
TLE 6368 / SONIC
Data Sheet 58 Rev. 2.2, 2006-12-01
TLE 6368 / SONIC
Revision History: 2006-12-01 Rev. 2.2Previous Version: 2.1Page Subjects (major changes since last revision)general Updated Infineon logo#1 Added “AEC” and “Green” logo#1 Added “Green Product” and “AEC qualified” to the feature list#1 Updated Package Name#57 Added “Green Product” remark#59 Disclaimer Update
Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.
InformationFor further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).
WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.