MULTI-STEP COULOSTATIC IMPULSE GENERATOR AND …...the Generator is to determine the electrochemical constituents of the plant apoplast electrolyte. •The objective of this thesis

MULTI-STEP COULOSTATIC IMPULSE GENERATORAND POTENTIAL MONITORING SYSTEM

Item Type text; Thesis-Reproduction (electronic)

Authors Coenen, Lance Gregory, 1959-

Publisher The University of Arizona.

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Multi-step Coulostatic Impulse Generator and potential monitoring system

Coenen, Lance Gregory, M.S.

The University of Arizona., 1987

U M I 300N. ZeebRd. Ann Arbor, MI 48106

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International

MULTI-STEP COULOSTATIC IMPULSE GENERATOR

AND POTENTIAL MONITORING SYSTEM

by

Lance Gregory Coenen

A Thesis Submitted to the Faculty of the

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

In Partial Fulfillment of the Requirements For the Degree of

MASTER OF SCIENCE WITH A MAJOR IN ELECTRICAL ENGINEERING

In the Graduate College of

THE UNIVERSITY OF ARIZONA

STATEMENT BY AUTHOR

This thesis has been submitted in partial fulfillment of requirements for a Masters degree at the University of Arizona and is deposited in the University Library to be made available to borrowers under the rules of the Library.

Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgement of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his or her judgement the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author.

SIGNED: ,9^^'

APPROVAL BY THESIS DIRECTOR

This thesis has been approved on the date shown below:

Jo < '7 W.G. GENSLER (f Dtfte

Associate Professor of Electrical and Computer Engineering

ACKNOWLEDGEMENTS

The help and assistance of Dr. W.G. Gensler

throughout the length of this project are gratefully

acknowledged. Also acknowledged is the financial assistance

and management support of the Hughes Aircraft Company.

To my family, whose patience and loving support made

this work possible, thank you.

iii

TABLE OF CONTENTS

Page

LIST OF ILLUSTRATIONS Vi

LIST OF TABLES viii

ABSTRACT ix

1. INTRODUCTION 1

Objectives 8

2. SYSTEM LAYOUT 13

Circuit Boards #1 through #5 Description 13

Circuit Board #6 Description 16 Setting Up the Test in the Field 17 The System Block Diagram 17

3. PROGRAMMABLE PULSE TRAIN GENERATOR CIRCUIT BOARD #6 DESIGN 28

Purpose 28 Example #1 30

Design Criteria 36 Theory of Operations 38 Block Diagram Overview 43 Loading the 82C54, the L4508B and

Controlling the A/D Converter 45 The 82C54 Programming Counter 49 Programming the 82C54 51

4. NEC COMPUTER TERMINAL OPERATING INSTRUCTIONS AND UTILITY SOFTWARE 54

UT62 Commands «... 56 D Commands 57 I Commands 57

iv

V

TABLE OF CONTENTS(continued)

Page

P Commands 58 Utility Software Programs 60

Program #1 60 Program #2 62 Program #3 66 Program #4 74 Program #5 75

5. CHECKOUT AND TROUBLE SHOOT PROCEDURES 91

Kim #1 through Kim #5 Circuit Boards ... 91 Coenen Board #6 Checkout 92

6. CONCLUSIONS AND RECOMMENDATIONS 97

REFERENCES 100

1IST DF ILXUSTRATJONS

Figure Page

1. Basic Electrode Arrangement of the Electrophytogram rechnitjue ....... 5

2. Basic Coulostatic Impulse Generator .... 5

3. Basic Response of a Coulostatic M e t h o d . . . . . . . . . . . . 1 2

4. The Potential Acquisition Circuit to Alternate Measurements Between Two Measuring Electrodes ........ 12

5. Basic System Block. Diagram ......... 19

6. Kim #1 Modified Circuit Board S c h e m a t i c . . . . . . . . . . . . . . . 2 0





11. Programmable Pulse Train Generator Circuit Board Schematic ........ 25

12. System Interconnect Schematic ....... 26

13. Front Panel layout ............. 27

14. Constant Sampling late Method ....... 29

15. Example 1 Tine Frame ............ 32

"vi

vii

LIST OF ILLUSTRATIONS (Continued)

Figure Page

16. Basic Response of a Coulostatic Discharge ....... 34

17. Programmable Pulse Train Generator Block Diagram ....... 40

18. Kim #5, U15 Timing Diagram ......... 46

19. Address for Kim #5, U13 Decode ....... 45

20. A/D Converter Timing Diagram ........ 48

21. riming Diagram to Load the 14508B Chips ....... 49

22. riming Diagram to Load the 82C54 Chip 5L

23. 8 2C54 Control Word Formats ......... 53

24. Front Panel Interconnect Diagram ...... 55

25. Future Software Flow Chart ......... 75

LIST OF TABLES

Table Page

L. Kim Circuit Board Control Words 11

2. 114 and U5 Eata vs Output Clock Rates .... 78

viii

ABSTRACT

A Coulostatic Impulse Generator is an electronic

device that transfers electrical charge to and from a pair of

electrodes inserted in plant tissue. Six discrete charge

transfers can be implemented in any desired sequence. The

Generator is also capable of determining the potential of the

electrodes during the charge transfers. The major purpose of

the Generator is to determine the electrochemical

constituents of the plant apoplast electrolyte.

•The objective of this thesis is threefold: 1) to

design, construct and test the supervisory circuitry of the

Coulostatic Impulse Generator, 2) to design, construct and

test the interface between the NEC portable computer and the

Coulostatic Impulse Generator, 3) to generate utility

software to control each circuit board in the system.

Ihe major design problem arises from the extreme

difference in the timing of the charge transfer

(microseconds) and the subsequent plant response

(milliseconds to seconds). A. three step timing sequence is

employed which permits an independent range of sample times

and sample numkers. Data acquired is first stored in RAM in

the computer within the Coulostatic Impulse Generator and

then transferred to the external computer.

ix

CHAPTER 1

INTRODUCTION

Presently, crop water status is assessed by visual

observation of the plant and by evaluating soil samples "vhlch

are taken from the proximity of the plants roots. Both

methods are performed directly in the field and are highly

labor intensive. The analysis and conclusions made are

heavily based on the experience of the person performing the

observation. Furthermore, the analysis of soil samples is

indirect, ie. Measurements of water saturation are talcen

from the soil and then the water content of the plant is

extrapolated from the water content of the soil. Again, fcliis

method is not exact and the results will vary depending on

the experience of the observer.

A plant based method of determining the water content

of a plant was developed by Dr. Gensler in 197•4- This method

uses electronic technology and consists of using an

electrochemical sensor placed directly in the plant stem aa<3

a second electrode which is placed in the soil near the plant

(see Figure 1). The electrochemical sensor, the plant

structure, the soil and the second electrode form a galvanic

1

2

cell. A galvanic cell is a source of electric potential

which is generated by two dissimilar substances when brought

in contact with an electrolyte (plant and soil). The

electric potential generated by this method has been proven

to be coherent, reproducible, and related to the water

content of the plant. Electric potentials of the order of

200 to 400 millivolts D.C. relative to a silver chloride

electrode in the soil are typical. Changes in the potential

from 200 to 400 millivolts D.C. have been directly related to

the variations in the water content of the plant.

These electric potential changes are presently used

as the basis of a protocommercial system using passive

measurements on a repetitive basis. The potentials are

monitored every 15 minutes from up to 56 cotton plants in the

field. The data is converted into a numerical index

indicating the plants water status. The numerical index is

transmitted by radio from the field sight to the farmers

headquarters or a mobile unit. Development of this system is

still under progress. However, it has been found that this

method is affected by other variables other than water

content.

Past research concerning this type of plant/probe

interface has determined that the generated potentials arise

at the interface between the cell electrolyte (plant fluid

and soil) and the surface of the palladium probe. This

3

liquid-so lid juration generates a potential which reflects

-the current status of the plants electrolyte level or water

level.

The characteristics and behavior of this interface

have been studied theoretically and experimentally to

determine the exact cause for the potential. Goldstein did a

-theoretical study of this generated potential and concluded

•that there vere three possible sources listed below:

1) The generated potential is caused by a redox

couple or reduction plus oxidation at the

piobe/'electrolyte interface.

2) The generated potential is caused by a bound

charge in the plant wall surrounding the probe which

causes an image charge of opposite potential to be

induced on the surface of the metallic electrode.

3) The generated potential is caused by free

electrons in the vicinity of the electrode surface.

Goldstein and Rugenstein performed anatomical studies to

determine the tissue structure and healing process of the

plant an the vicinity of the implanted electrode.

SiIva-Diaz performed studies using cyclic volammetry to

determine whether a redox couple exists at the

electrolyte/probe interface. Silva-Diaz determined that

there was no redaction and oxidation potentials occurring at

the voltage levels typically encountered. Furthermore,

4

Silva-Diaz found that the results of cyclic voltammetry was

seriously affected by the solution resistance which was in

the order of 30,000ohms. This high resistance made the

voltammograms very difficult to interpret."^

A new approach to analyzing the water saturation

level in a plant is coulostatics. This method obviates the

problems of solution resistance. The basic method is shown

in Figure 2. A reference electrode is placed in the wet soil

near the plants roots. The two measuring electrodes are

implanted into the stem of the plant and connected to the

circuit shown. The capacitor is charged initially by closing

switch (A) while switch (B) is open. Next, switch (A) opens

and switch (B) closes resulting in a discharge of the

capacitor into the plant stem.

The basic response of a typical coulostatic pulse is

shown in Figure 3. Relative to the reference electrode, the

electrode connected to the positive side of the capacitor

increased in potential and the electrode connected to the

negative side of the capacitor decreased in potential. This

indicates that electron transfer occurs in both directions,

equal in charge density. This also shows that the capacitor

charge is truly isolated from Earth Ground. Because of this

isolation, the coulostatic method can be applied under field

conditions with relatively long lead lengths and normal probe

placements.

5

MEASURING ELECTRODE

REFERENCE ELECTRODE

Figure 1. Basic electrode arrangement of the electrophytogram technique.

Switch B

ex

Reference Electrode

Figure 2. Basic Coulostatic Impulse Generator.

Note that due to the capacitors isolated charge

relative to Earth Ground, the discharge current is from one

electrode through the plant tissue to the other electrode-

No current runs through the plant to the reference probe in

the soil. Furthermore, the length of the current path in the

plant tissue is now about one centimeter or less. This

decreases the solution resistance substantially and hence the

isolation requirements for the circuit in Figure 2 is

decreased. This also results in a potential measurement

which is not affected by the initial capacitor discharge

current.

The magnitude of the charge transferred to the plant

can be calculated at any given instant of time ky subtracting

the two measured potentials at each probe relative to the

reference electrode in the soil and multiplying the results

by the value of the external capacitor. The current level

through the plant can be determined at any giver instant of

tine by taking the time derivative of this value of charge.

For example, if VI and V2 are the two potentials relative to

the reference electrode, then the charge at time T1 is given

by:

Q = (VI(Tl)-V2(Tl)) * C (EXT)

I (Tl) = dQ/dT(Tl)

7

The differential capacitance at each of the liquid-solid

interfaces is given by:

Cdiffl = dQ/dVl

Cdiff2 = dQ/dV2

While a knowledge of the differential capacitance is

useful, there is also physical meaning in the discontinuities

of the charging rate for each probe. The presence of oxide

layers at each metal-liquid interface can be changed in

magnitude at a much higher rate than an oxidation-reduction

process which requires diffusion of reactants to the surface.

Therefore, high speed changes in the potentials at the

electrodes are significant in relating the potential changes

to the plant chemistry.

Ledezma-Razcon investigated the basic feasibility of

the coulostatic pulse technique and found very consistent and

reproducible responses.^ He also performed a second type of

testing called coulometrics. This method is passive in

nature and consists of connecting a resistance across the

measuring and reference electrodes, and recording the

potential across the resistance as the plant gives off

energy. Ledezma used Palladium and Carbon electrodes in his

studies found that the typical input impedence level of the

Probe-Tissue interface is approximately 160 Megaohms. This

8

yields an isolation requirement for the circuit shown in

Figure 2 in the order of 10,000,000,000 ohms.

However, Ledezma-Razcon's investigations revealed

some operational problems with the coulostatic pulse method.

First, the initial charging of the liquid-solid interface

occurred so quickly that conventional analog measurement

equipment operating from portable power sources could not

record the transient rise in potential. Secondly, the

subsequent discharge occurred over a relatively long period,

in the order of 200 to 300 seconds. This wide disparity in

response time during the initial charging and subsequent

discharging was difficult to measure with any degree of

accuracy. A third problem was due to the slow recovery of

the plant potential back to its original potential before the

pulse. This slow recovery was in the order of five to ten

minutes. Therefore, multiple experiments on the same

measuring electrodes was difficult. These operational

difficulties have given rise to the main objectives of this

thesis.

Objectives

A set of circuit boards forming the basic Coulostatic

Impulse Generator were constructed daring the thesis work of

9

Bruce Kim. These boards contained the circuitry for charging

and switching the six capacitors and the analog to digital

5 conversion circuit. The original purpose of this thesis was

to complete the hardware design of the Coulostatic Impulse

Generator and to supply the utility software to control the

movement of charge and the potential acquisition. The major

software problem centered around the use of asynchronous

versus synchronous timing for the potential acquisition.

During the initial design of this software, it became

apparent that not only was software required, but a more

straight forward software approach was possible if additional

timing hardware was added to the original five boards. This

timing hardware would be used to acguire the data

synchronously in three sequential and separable packets. The

objective of the thesis was then modified to implement this

mixed hardware/software approach to the timing supervision

problem. The specific design problems were: hardware

modifications to the Kim circuit boards, design of the

circuit boards backplane and chassis, design of a

Programmable Pulse Train Generator circuit board and design

of the utility software to control this circuit board, and

the five Kim Circuit boards.

The Coulostatic Impulse Generator will be used to

apply multiple coulostatic pulses to cotton plants in the

10

field and to monitor and store the potential changes that

occur during and after the pulses.

The Block Diagram of the system is shown in Figure 5,

Chapter II. There are six individual capacitor circuits.

The switch closures for capacitor charging and discharging is

accomplished by magnetic and solid state relays under control

of the 1806A microprocessor. Potential acquisition circuitry

was included to sample the probe voltage, perform an analog

to digital conversion on the sampled voltage, and store the

results in the microprocessor memory. The circuitry has the

capability to monitor either measuring electrode in the plant

(see Figure 4). All functions are automatically controlled

by the 1806A microprocessor. A Programmable Pulse Train

Generator was designed and implemented for synchronous timing

of the potential acquisition. This circuit is loaded via the

1806A microprocessor with various control words for setting

the sampling rate of the analog to digital converter. Once

the circuit is loaded with the proper information, the

circuit is started by the microprocessor and flags the

microprocessor as to when to obtain a data sample. This

circuit solves one of the most common problems in any

microprocessor system, namely the generation of accurate time

delays under software control. Hence the problem of "real"

time reconstruction of the sampled probe voltage is

11

simpliiiecl as explained In detail in the next Chapters to

follow.

Tlie modified KLm Circuit boards, the Programmable

Pulse Train Generator, and the microprocessor were housed in

a portable chassis. All circuit board connections were done

on the backplane. The front panel has various controls which

were designed to be user friendly under field conditions.

V Transient Region

t A-ae where a andtare constants.

0 30 min. 1 sec.

Figure 3. Basic response of a coulostatic method.

Probe 1

Probe 2

9 =

X Amplifier

Figure 4 .

Reference v Electrode

The potential acquisition circuit to

alternate measurements between the

two measuring electrodes.

CHAPTER II

SYSTEM LAYOUT

The basic design consists of six individual capacitor

circuits, a potential acquisition circuit (A/D converter)

designed to alternate between the two measuring electrodes,

and a Programmable Pulse Train Generator. All of these

circuits are located on six circuit boards and are under the

control of a 180 6A microprocessor. See Figure 5 for the

system layout.

Circuit Boards #1 Through #5 Description

There are five circuit boards that were designed and

constructed by Bruce Kim. These boards are named Kim #L

through Kim 15. The Kim #1 basically consists of regulated

power supplies for the system as well as two parts of the six

capacitor circuits. The Kim #2 consists of two more of the

six capacitor circuits. The Kim #3 has the remaining two

capacitor circuits as well as some digital interface

circuitry <1.6 I/O lines). The Kim #4 contains 16 more I/O

13

14

lines for a total of 32 1/0 lines. These I/O lines control

the six capacitor circuits, the A./D converter and the

programmable pulse train generator by way of the 1806A

microprocessor.

The six capacitor circuits were implemented using two

distinctive relays, mechanical relays with built-in drivers

and solid state relays. Tvo types of relays were used on the

Kim circuit boards for the following reasons. There must be

very high electrical isolation between the system and the

probes in the plant structure up to the moment the tests

begin. Solid state relays have a very large resistance

between the contacts when in the open state. However, this

resistance is not infinite. Solid state relays can be

switched with virtually no contact bounce in microseconds.

By contrast, mechanical relay contacts yield a true open

circuit (infinite resistance). They also require closure

time in the order of a few milliseconds and have contact

bounce. In connecting a capacitor to the probes in the

plant, a mechnical relay contact is in series with a solid

state relay contact. Initially, the two contacts are both

open, thereby achieving an infinite resistance (open) between

the plant probes and the system. The mechanical relay

contact is then closed and allowed to settle down. After a

few milliseconds, the solid state relay contact is closed,

15

thereby permitting a charge transfer fiom the capacitor to

the plant. Every capacitor circuit has two mechnical relays

(MR) and two solid state relays (SS ) .

Contained on the Kim 15 circuit board is the analog

to digital converter used for potential acquisition. Bruce

Kim considered two types of k/D converters; dual slope and

successive approximation. The dual slope A/D converters have

an indirect method of conversion whereiy an analog potential

is sampled then converted into a time period by an integrator

circuit and them concerted to a digital representation by a

clock and a counter. This method is relatively slow but

capable of high acciixacy. On the other hand, the successive

approximation A/D converters employ a method that

sequentially compares the sampled analog' potential with a

series of binary weighted analog values in N steps. Where N

is the resolution in bits. These steps are driver by a clock

which can run at a verry fast rate. The successive

approximation A/D converter topically can do a single

conversion much faster than its dual slope counter part.

Therefore Bruce Kim chose a successive approximation A/D

converter with low power requirements. 5

16

Circuit Board #6 Description

Circuit board #6, named the Programmable Pulse Train

Generator, was designed for this system to solve a major

problem with any microprocessor system, the generation of

accurate time delays. Once programmed by the 1806A

microprocessor, this circuit flags the microprocessor when it

is time to take a data point (potential acquisition). In

other words, the sampling rate is fully programmable and

consists of three intervals. Interval one is programmed with

interval length and sampling rate (frequency). Interval two

and three are also programmed with interval length and

sampling rate. Once thii circuit is loaded with all of this

information, the microprocessor enables the circuit when a

capacitor is connected to the plant. The circuit

automatically runs through interval one then two then three,

sequentially. Interval one, two, and three were designed to

have the capability of being programmed with different clock

speeds ranging from microseconds to seconds and interval

lengths ranging from one data point to 65,536 points. The

only restraint is that any intervals frequency cannot be

faster than the time it takes the A/D converter to make one

17

conversion. This circuitry was designed using state-of-the

arts CMOS circuitry for low power consumption.

Setting Up Tests In The Field

The system was designed to be portable. The physical

size of the enclosure is approximately 19" wide by 9.5" high

by 18" long. The system has an RS232C interface connector on

the front panel to link the 1806A microprocessor to the NEC

8201A portable terminal. To set up the system, two probes

will be inserted into the cotton plant. Subsequently, the

power will be applied to the system from its built-in solar

charged batteries. When the tests are completed, the

potential-time data will be stored in RAM. This cycle may

repeat to obtain multiple data runs if the programmer so

desires. After sufficient data accumulation, one must bring

the equipment back to the Lab to transfer the data into

permanent storage.

The System Block Diagram

Figure 5 depicts the basic system with the RCA CDP

1806A microprocessor. The plant under test is cotton. The

purpose of the system is to stimulate the plant with a

coulostatic pulse and monitor the change in potential versus

time. The Coulostatic Impulse Generator is represented by

18

six capacitors, six variable voltage sources to charge the

capacitors, solid state relays, and mechnical relays. The

monitoring circuit is represented by the A/D converter,

microprocessor, and its peripheral interface circuits, and

the Programmable Pulse Train Generator.

Figure 6 through 10 depicts the modified Kim circuit

boards. The Kim #1 through the Kim #4 boards required minor

modifications to enable the user to adjust the capacitor

voltage via the front panel. The Kim #5 board required

modifications for interfacing to the 1806A microprocessor. A

detailed explanation of the theory and design behind these

circuit boards can be found in Bruce Kim's thesis. Figure 11

depicts Circuit board #6, the Programmable Pulse Train

Generator. A detailed theory and design criteria for this

circuit can be found in Chapter III. Figure 12 shows the

system interconnect schematic. Figure 13 shows the front

panel layout.

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2. Resistance values are In ohms,*lX.W.

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21

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FUNCTION

REF. DESG.

type OP. ARS LMI24 COMfAAATO* ARfc LMIB9 PetKY KlO.Kll 7I2TN-3 RCUAX KI2 . KI3 l3fcC- 5 AtuM KJ4 Ki5,KI&, K17 643-3 «tv»ro« i i|7 HftrxoiH 1 \J £~ MOP i 6 03103 G


1. The parenthesis on K10.K11.K12.IC13.RIO.

and R13 Indicate socket pin numbers.

2 . Resistance values are in ohms.til.*>W.

3. Capacitance values are in microfarads.


1 Circuit Board Schematic

P 3

czi tt.O, 10V

DIO

CO 3 015

D O S

(F*OM c*a&*4> 03 DO?

010 (J 5 on DIZ

MRQ

CU4

K 2 Z

CZ3

HH (5)

!J) 30

\<r F~

301*1/

5fcl IN4I4& K 2 3

kisT :C24

KZO

CLI7 20

K 2 4

+5V (HI

(51 mi SfcL

K 2 5 ;C30

FIGURE

Kim #3 Modified Circuit Board Sc

"~3Ta J. -i

-rir

-NC -uc

K 2 Z

£ = I (C£T) «0 14

• SV rjl'* rr uj L«

l0*LW

' •0>\ L?J .

K 2 3

K24

K25

euto I

e^s3 flu* 4 B'JSS

2 2

LAYOUT Clio cl 20 CL II CL 23

CL 13

CLia CL1* COMfONffMT StOe Cu 30

;> LfcUD-! PluS St 4

FUNCTION!

REF. OES&.

TYPE

e en do PORT U4.U5 CDPI852 Kevts-Toft NETWORK U3 ' MDPI603I03& OP. kMP. ART LMI24 LO»APARMOft *R8 LMI39 Pltl-V* KI8, K13 "712T N - 5

K20.K2I I3&C-5 HELKY K22.K23.KM.KZ5 613-3

VJ X. ,o^ 1«


1. The parenthesis on K18,K]9.K20,K21,R16,

and R19 Indicate socket pin numbers.

2 . Resistance values are in ohms,ill,W.

3. Capacitance values are in microfarads.


.rcuit Board Schematic

P4

-»— +sv J C 32.

CB3

Mo

MRD

FIGURE

CLOCKS

No

CE

UG

VDD

v«

D3

DZ

MODE. Voo DlO US on DIZ CI 3 CI 4 or s 016 on

DOT CS2 V ' CK est CL Vis

QO o 00 I 00 2 00 3 004 oos 00 fr

*dd£ VOO DIO L)7 DII DIZ OI3 D14 CIS D1C. Ot 1 csz CK est CL

Kin M Circuit Board

P4

N P n 5 T U V W

Boso Bust 6u& Z

Bos 3 BUS 4-BusS 0US6 &US1

23

lArour

CLI clz C L 3 CU4 CL3 CL6 CL7 CL0

COfAFONBMT il06

II 12. 13 14 15* 16 n 18

CL9 CLIO CLIl C Lix CLI 3 C LI 4 CU5 tL 16

K

L

M

D3 ( TO ORDfl3)

04 <.TOC*RD*3) 05 CSPAR £ )

FUMC-TIOM

REF. DESG.

TYPE

OEcooen U6 CDP 1853 B-01T I/O PORT Ul, US CDP 18 52.

Boa id Schema "tic

Ay— p Al-P

A2- P

A4- p

Ab -P

T?f\-P

ro nm OF 3 vw-

I S6Z

9US) M 10(h)

c a t X rJnr .1 "PU9

L-^ AH4

Mill

5<»i MIK*)

Mtoi V4)

cut r»5» trsvpc

P<ctcP6I>

®, coy I VRfiFf

38 VWF» AM2.

•irv

-/fVOC FlUTBlfCO •=

*17 *vv r./ftx

Ab«0k

ftr D( ClLT JftfiC V« cmp oho ivs 37

FIGURE 10

Kim #5 Modified Circuit Boarc

24

+5V

VCC Y0 VCC Y0 A0 AI

7i A0 AI Uli Y? A? V3 n Y4 G Yb E3 Yt,

y7 E3

GND

Yt, y7

15.

TP3

TP2 M10! '41

irl i (4

Ull ' )

i: TP4

Ai

P5

19

20

NC-NC-

-f 5v _LrkU-

' un'iil TP5

(7

LAYOUT

TPI TP2 TP3 TP4 TP5 TP6

cH •

1/15

t« HI Ull AM (=2 a

r— At 10 UI3

Mill Kit

U9 Ml «21

—tnD—

COMPONENT JlOff NOTES: UNLESS OTHERWISE SPECIFIED

1. The parenthesis on K26 and K27 indicate

socket pin numbers.

2. Resistance values are 1n oluns,±lX,kW.

3. Capacitance values are 1n microfarads.


FUNCTION

REF! OESGi TfPE

«?F. ««n AR9. ARll LMIZ4 UMIUMI AR10 LMI3? VOlfAtfl ARIZ REF -02AJ 0». ARI3.ARI4.ARlS Of» -01A. •CltlTart U9 MDPIt03IO 3G. covmtia Ull C.D4S 2t N O UIO ICL7JI5 •tour K26.K27 712 TW-5 Imltit UI2 Ht 1- 02GI- 5 •tCOOtft UI3 54HCIJ 8 itfvHtTCfl OI4 54KCI4 l*TC« U l S S4«C.5,7'J

WWR-N

oust Ouib tu' jS 0 V44 Quia BUS 1 Bus l Boio

tvÔ-N

SPARE PARTS

MlOlJfr)

^SJ3

rv>1

t

r-x""1 — 7>^

TPS

fied Circuit Board Schematic

MC<«Ou9U3 AuT o OMtJ 1 lUlMOOi > <? iloc1 id

Pftf^r of KT K 1 <061 0

UI'4A RU N ir*nr

5 CIS MC.145080 TfiTTT i VOD U* »50e

15 OiS QO 1

a oz 7 02 LJ4 9 05 UH 04 ir

qs re 20C6 vVi Oft *l 22Df >? QyHt-

6 04

:???cop,«3

-ma znjftit

'2 06 jto OUT 14 IS 07

C3-C7

x,4st w&mavc0 t3 ^f«cj450ft8 L 5 0>S DO QO

5 01 , ip Q • q2 91 10 C) c s II 6 04 Q 4 1/ S 0> Q^t? 20C6 v„ Q6i' 22C7 if 3H

'Vhckotsd VD0CLK2 *0t VS5

mc4069ub Rt^tT Cl^T VI MCKQMB C0PI863 MC (407 50

U7 52

C040I3A OUT t« q2 CIKI 02

>ii CU2 Qi uti40r3b

»C IKw OUT tDO OUT 217 •*T| V^S SCT

U6 h02c44 KG 22

VC02« ST 1st

'"uciojo 4 00 . 6 Li . ,•? Qi 7 go: 02 >0l3 « " 114 o« n '0 C* M 2006 06

u»m« vod i o?

CATl 0 4CATC I 6 CATE2

IQ AO ? O A I

:< Zl U8 045SS3

CMOl

50 fvs

rrtflr ac 1115 UCK069UQ

ps

FIGURE 11

Programmable Pulse Train Genei Circuit Board Schematic

2 5

tpb u7 cs C3

c?

5, ui'ia rrtS)'i r~L

b.—. ui'ib

<rr

CH lw3

LAYOUT Cioc«ovr

hPD <•' - — wmr (aa o-m-'

J wvl CHSCf/our^} uis

part of

KCATC I 6 C»TC2 J]),,

io *o ? 0 * 1

\ MFCAPAC/rOA i.omf capacitor mci«069ub • • CoMPpwf^r mci4qbib mcmq75b

jjji U15

3 1 1

jmmable Pulse Train Generator Lt Board Schematic

226r0 &riyz 1

226r0 &riyz JLci aoj-i— 21 y nc

ng 20 12v,solar battfx —$1-2 ci aoj-2— 19 w — nc c2 aoj-i— 18 v nc c2 acj -2— 17 cli/u —pa-2

nc is cl2/t hj-3 nc 15 cli/s p4-4 nc 14 r nc— 13 cu/p —m-5

p2-e l^-5v0ut clj/n p4-6 p3-b, p5-v— i i/isvour cu5 im —p4-7

nc io 'cl7/l —p4-8 f5-vv g/+l5v0ur k nc

nc 8 j nc 7/pro0e2 cot h nc strobe 1 out f — nc

nc 5 e —nc p3-s, P1-20— vppooe 2 0 —nc p3-r) p2-17— 3/ppooe 1 c nc

nc 2 b —nc nc -»svdc/a —p2-a,-l

pl-22-c3a0j-I-

Pl-M ;P3-S-c3aoj-2-

nc-pi-3 ;p3-fi-

NC"

nc-C4 AOJ-I-c4 aoj-2-p7-2i,pi-a-

22&RD GRD/Z —PI-2 P2-22 22/GRD GRD/2 —P2-Z

21 Y — N C C6 AOJ-2— 21 BU iS11 —W-u

2O/PPO0E 2 X — CG AOj-t — 20 BUS 4/» —P4-I

19 W — C5 AOJ-2— 0 BUS3/V —M-S

18 V — CSAOJ-1 — 8 BUS2/V —M-l)

(7/PROBE 1 U NC c — I//C13Q BU5I/U PI -P

G C L 8 / T P4-9 —

GfclS SUSO/1 —P4-M

15 C L 9 / S W - l l spare/ ~

£fcl28 RP0BE2;S —P2-2J

14 CUO/R P4 12 spare/ ~ IVC27 BPOBf 1/1 —P2-I7

13 P NC [ -13/026 CLI9/P —P3r6

12 CLII/N —P4-I3 I2/CI.25 cua/N —P3-5

II ai2/w —P4-I4 PHfa— II/C124 CLI7/N —P3"1

IO CU3/U —P4-I5 P5-L— D/CL23 CLIS/L —P4-0

K N c F5-P— 9tl22 CLIS/K —P4-I7

8 J P«,S 8CL2I CLI4/J —P4-I&

7 H P5-T 7fcL20 Q/H —P4<J',P6-I5 S F NC P3P — 6/CII9 MRD/f —PS-IZiP75

5 -5VDC/E —PI-12 P3IM — ycua 7PS/E —P4-F;P7B 4 0 NC P3M VCU7 04 /0 P4-L

3 C — P+W yens 7 03 /C WK 2 B — NC P4-V 2/EUS6 -I5V0C/B —PMI I/+EVOC +5VDC/A R-A/7-Y

P2—1 Id-SWDC 45V0C /A — P2A

p 2 P3

P 5-22—[22£RD GRD/Z —P5-Z P5-22— 22/GRD GRD/Z —P6-Z IC— NC—

21 Y —NC P2-I — 2|/l6VDC +5VDC/V —P2-A IC— NC— 20 X —NC NC — 2Cj/|5vdc EF4/X NC NC— 19 W —NC NC ra/E F3 MRW/W —PS-17 NC—1'8 V —NC *>" c — IB/CF2 A7/V —FS-J

P3-F—|l 7/WBD U —NC PS- 6— 17/EFT AS/U FS-F P5-II— I6CL24- T —NC Pi- 0 — l6yM2 A 5/T —P6-E P5-H*— IE/5" TF3/S —F-7-8 P4- C— I5/NI A4,S —P5-K

NC— 14 Y6/R —F 5-20 P4-0— I4/N2) A3.R —F5-D P5-8 — 13/M *b/P —P5-I9 P5 H 13/CLOCK OUT A2,P —-P5-C P&-3— I2/A0 Y4/N —P5-IB N C — 12 Al/W —PS-8

NC— 11 YJ[M —P5-I2 11 A 0^ —P5-2 P7-L — 1010 7 Y2/L —P5-I0 — •Oyv/Air DB7/L —P5'4,P&10 P7.-K S/0& K —NC ^CLEAR DSS/K —P5-G,P6-9 P7-J — 8/05 J —NC a'sci DBS/J —P&7; P6-8 P7-H — 7/04 H —NC NC 7/SC0 D34/H FS-9; P6-7

P7-F 6JD3 F — NC P4.J— ^CL DB5tF —F5-II, P&-6 P7- £ — 5/02 CL0CKCXJT/E P7-I0 P3-FIP5-5— 5/SIRD DB2/FE —P5-L3;P&-5 P7- 0— 'VOI D —NC ' MC— 4/iNT OBI A) — P5-l4,P6-4 P7— C — 3/00 CLOCK IN/C — P5-H — t?NU DBO/C — FS1^,P6-3

NC— 2 s —NC 2/3MA® TPB/B —PS-SiF3-f P5I — V+5V0C -MVDC/A — P5-A r C — i/CTSSi TPA/A —FU-E,P5-M

p7-22— p7-2 i p7-20— p7-i 9— p7-i8— p7-i7-p7-i 6— p7- 15— p7-m— p 7- i 3— p7- i 2— p7-i p7-io— p7 - 9— PI- 8'

P7- 7 p7- €• p7- 5' p7- 4— p7- 3— p7-2-p7-i—

i—e/-

22/crd 2l/+<*/0C 23/oydc i9/ef3 8/#2

17/EFT o; n2 6/ Ml

s/odck cut 12 ii. icyvgr 3/Ci£Ail 3/sci 7/sco q

visr 3/RNU 2/DSA5 I/DMA l

grd/z -tsvocV* ef4/x

UlSyW a7/v as/ll a5,t aa/s '3/r a2ip a i yt* aoA d37a 086/k ds5/j db4/h 0b3/f CB2£ obi id

OjC tpb/i 7PA/a

P7-Z p7-Y

— P7-X P7-W P7-V

P7-U P7-T

—P7-S —P7-R

P7-P P7-N •P7-M

—P7-L —P7-K

P7-J -P7-H -P7-F P7-E

'-D —P7-C

i6j—P7-B P7-A

p6 p7

PI-19

pi-21 2|pri go '^vwwv-^

ClAQJUST

gkob^tt.(-i

i.

PI-17

Pl.B 2|PT2 GK0

'^vwww C2 adjust

+ 5 6 PT

P2-I9

C3 ADJUST

p2-2

p2r3 2jpr4 crd 't-a/wvw-j c4acuust

~s

•+6V

PT 0 PT

c5 acuust

p3-3d 'u

C6

FIGURE 12

System Intercorirect Scl

GRD/Z BUS5/V

aus4/> bus3/w BUS2/V BUS l/U aiso/T

RPOBE 2/S RPOBf l/fi

CU9/P CLI3/N CLI7/M cli6/l CU5/K CLI4/J

Q/H MRO/F TP8/E DO/O D3/C

-I5VDC/B 46vqc/a

P3

p?-z w-u •P4-T -F4-S

w-r -P4-P •M-N •P2-2C P2-I7

—pj-6 P3-5

—p3"4 •P4-I8 -P4-I7

—P4-I6

—P40-.P6-I5 —P6-IZiP7 5

P4-F.P7-B

-P4-L Pi-K Pl-ll

— P2-A

P3-22— NC— NC-MC-

R3-L-fsk-

P3-J P2-L-p2-m— p2n— P2-R-P2-S—

NC-P2-T— Pl-lr

Pl-M—

Pl-N— Pl-P Pl-S Pl-T—

Pl-U P3-I

22jfeRD 21 20 13 i8£tfc I7,CLI5 IG/tLM I5/CLI3 W/CL'2 13/CLH 12/CUO i1/cl9 o 9/fcL8 8/CL7

7/tl6 6/CL5

5/CL4 4/tL3

3/cl2 2£li i45vpc

GRD/Z V x

BUS7/W BUS 6/V BUS 5/0 8US4/T BUS 3/S BUS2/R BUS I /P 8US0/W SFARE/M

04/L D3/K q/d

MRD/H TP8/F TPA/E

N0/O NL/C N2/B

+5V0C/A

— P3-Z NC

—NC

P3-3/P5"" P32,P5-6

—P3 Yi F6-7 —P3-K) P5-9

P3W.P5-II — p3^p5s —P3U|FS-I4 —P3-T;F5-S —NC

—P3-D —F3-C —P7-6jP3H —P5-5 —P3-E —p?a

P7-I4 —P7-I5 —P7-& —P3A

P4-22-NC-

Pfa-R -Pt>-p_

P6-N _

P7-W— P7+7-

P4-N;P7C-W-PiP7-D-W-aP?E-

pm-P4-S;P7-F-

Pfa-L— R-T,P?-H-

Pb-13 — PH)P7d-

P4-V.P7K-M-HjP7-5— P4W,P7-L-

Pt,-a-P7-M-P4-I—

22FCRD 21 2c/y6 13/ Y5 e/y4 i7/hWR-'g

6/efi I5/BUS0 i4busi 1^bus2 l?/Y3 II/BUS3 I0/Y2 ^bus4 6/ai 7/BUS5 6/8US S 5/Hrd-n 4/8US 7

3/xo 2/AOD 0 IA-5VDC

GRO/Z Y X

+I5VDC/W -I5V0C/V

u CL2 0/r CL2I/S

PROBE |/R CL22/P

PR08E2/N TPA/M

CL23/L

• ADD4 K ADO 7 J

2MHZCL0CK/H

A0D6/F ADD5/E ADD 3/D ADO 2/C

ADD l/Q +5VDC/A

-P4-Z -0 earth gno.

—NC PI-9

—Pl-ll —NC —P3-7 —P3-8

-.PI-6 -P3-9

PI-7 —P7-A —P3-I0

P7-S —P7-V —P7-B.P6-C —P7-U —P7-T —P7-R —P7-P —P7-N

—P4*A

2 6

P4 P5

22/GRD GRO/Z —P7-Z PB-22— 22/GRD GRC^Z — R8-Z P9-22—

2i/+evoc +6VDC/Y —P7-Y P8-2I — 2I/+5VDC +5VDC/V —R8-Y P9-2I— 20/^9/DC EF4/X — P7-X P8-20— 2CflWDC EF4/X —P8-X P9-20—

•I9/EF3 —P7-W PS-19 — IÊF3 NRW/VV —P8-W P9-I9— .ejff2 A7/V —P7-V P8-I0— 1802 A7A/ —FQ-V P9-I8— •17/ER A6/U —P7-U P8-I7— IÊFI A6AJ —pg-u P9-I7— • oNji 'V —P7-T P6-IS — I6/N2 A5/T —FS-T P9-I6— • 6/NI A4/S —P7-S P9-I5 — I^NI A4/S —f£-S P9-I5— • I4/N0 13/R — P7-R P6-I4— 14/NO A3/R —F8-R P9-I4— •O/CLDCKOUT A2,P —P7-P P8-I3— 13/CLCCKOUr A2^ —P0-P F9-I3— •12 Al/k —P7-N P8-I2— 12 Al/N —P0-N P9-I2 •II AOAJI —P7-M P8-II— II AOyU —P8-M P9- I I — - lOfWAIT DB7/L —P7-L P£r 10— icy 0B7A- —P8-L P9- 10 -9/ClEAR DB6/K —P7-K PS- 9— ^CLEAR D86/k —P8-K P9- 9— - a/sci DB5/J —P7-J P8-8— QSCI 085,0 —F8-J P9-8— - 7/SCO DB4/H P7-H P8-7— 7/SCO 034/k —FS-H P9 -7— -c/a 0B3/F P7-F P8-S— W 0B3/F L-fB-F P9 -6— -5/MRD 082^ —P7-E P8- 5— ^355 DB2/E —P8-E P9-5

-4/liTT 081/D P7-D pa-4— 'V/NT OBI/b —P8-D P9 -4—

- 3/RNU 0/C —P7-C P8- 3— 3/RNU DBO/C —P8-C P9 -3— -2/CKMO TPB/B —P7-B P8- 2— 2/CMb TP8/fe —F8-B P9 -2— - 1/OMTTI TPAtt —P7-A P8- 1 — l/OKOT TPA/A R9-A P9 -| —

p8

p3;l9 P3-J8 ,ipT5 r,n

P9

c5 adjust

p3*0 P3-2I

2?PTB GRD

L-a/vww-^

c6ôuusr

si POWfR. * pl-x

m GRD BATTC-J

PT i I +13 VOLT BATT.

22/GRO

21/fSVOC

2c/-i9/0c |9/£f3 6/EF2 I7/£R 6N2 IE/NI l^'no

CLOCK CUT 12 ii iQfmTT ôeart &SCI 7/SCO

4//nt 2/RNU 2/DMTO l/DN(AI

GRC/Z +5VDC/Y

EF4/X mrwyw

A7/V A6/U

a5/t A4/fe A3/t? A2/F A I /fa ao/m

DB7/L D86/K DB5/J DB4/H DSZ/F D82/Z DB/D

DBO/C tpe^fe tra/a

s3

reset

-P9-Z -P9-Y -P9-X -P9-W -fo-v -p9-u _fe-T -f9-s _p9-R -PS-P -f8-n -P9-M —p9-l —f3-k -P9-J _P9—H -f9-f -P9-E -P9-D -P9-C -P9-B -P9-A

pio

:GURE 12

'stem Interconnect Schematic

<D

— OJ ,-o <0- U~) CD o O o <J> O O > > > > > > O O O O O O

O o O O o o Q > > > > Q

lO LO Lf> LD •z. <£> + i + i O

OPROBE I RE ON

OPROBE Z Qsi 052.

O E A R T H R U N O F F GND

O O O O O O CI C2 C3 C4 C5 C6

ADJ ADJ ADJ ADJ ADJ ADJ

FIGURE 13

Front Panel Layout

CHAPTER III

PROGRAMMABLE PULSE TRAIN GENERATOR CIRCUIT BOARD #6 DESIGN

A)Purpose;

During the course of the design it became evident

that inorder to digitize and store the analog signal,

generated on the plant probes, one of two synchronous methods

of sampling would need to be employed. These two methods are

constant sampling rate and variable sampling rate. Both

methods have their advantages and disadvantages when used in

analog to digital conversion circuits.

Constant sampling rate is simple in design. It

employs a single clock frequency which provides a constant

sampling rate of the analog signal. Since the period of the

clock is known, the reconstruction of the analog signal

(digital to analog conversion) is straight forward. See

Figure 14.

2 8

2 9

Vour

CLOCK PULSE

PERIOD - To

T I M VOUT

T I M f c

FIGURE 14

Constant Sampling Rate Method

The tine domain pLot (amplitude vs. time) can easily

be reconstructed as each sampled point amplitude is known by

its digital representation and the time between each point is

the period of -the clock, frequency, T(0).

The minimum clock frequency that can be employed in

this method is twice the highest frequency component of the

analog signal, V(1NI) . Hence, if V (IN) starts out at a very

high frequency f(K) and then slows down to a low frequency

3 0

f (L) , the clock frequency used must be 2f(H). The major

drawback to this method is a clock frequency of 2f(H) will

generate a digital represented point of the analog signal

e~very rl/ 2f (H) of a second, or 2f (H) digital words every

second. If the input signal frequency slows down to f(L) the

clock frequency at this point would only need to be 2f(L) not

2±(H). Hence, as the frequency of the input signal goes from

fast to slow, more digital words are being generated than

necessary. This is a problem since we have limited memory to

work with.

Example #1:

The input analog signal to be converted is a sweeping

sdnewave which starts at 0.1MHz and ends at 10Hz, and sweeps

from 0.1MHz to 10Hz in two seconds. Using the constant

sampling rate method, a sampling rate of .2MHz (twice the

fastest analog frequency) must be used. In two seconds 400

thousand Bytes would be generated and stored.

200,000 cycle/sec.x 2sec. = 400,OOOBytes

The number of Bytes generated could be reduced using

•variable sampling rate. A variable sampling rate can be

hroken into two types: continuously varying rate and step

3 1

varying rate. Both methods basicly adjust the sampling

frequency to the input analog frequency so that the minimum

possible sampling rate is used.

Continuously varying rate would continuously track

the input analog frequency so that the sampling frequency

would always be twice the input analog frequency. Thus, the

minimum number of digital words would be generated. However,

this method would be an extremely complex design as the A/D

circuit would have to track the input signals frequency and

adjust the sampling rate accordingly.

Step varying rate would basicly step change the

sampling rate at predetermined time intervals to

predetermined sampling rates. If one knows the basic

analog-time wave form of the input signal to be digitized,

then this method would be very useful and feasible to design

and implement.

Consider the example #1 problem, and suppose we had

the knowledge that the analog signal was of the form

described. To keep the design simple, we will break up the

two second time interval into four one-half second time

frames shown below in Figure 15:

3 2

nP o o d

fi vp

,0

fa \ 0' .0°

F3

\0'

—f

,0

Fh \0

-h

>^4-

= OS • 5S I.5S 2S

FIGURE 15

Example 1 Time Frame

For interval 1 (0<T<.5s) the sampling rate must be

tvii.ce the highest frequency in that interval. Hence the

sampling frequency in interval 1 is F(l) = .2MHz. The same

is true for interval 2, 3, and 4. Therefore the four

sampling frequencys are the following:

F < 1 ) = - 2 M H z I (2 ) = -0 2MHz F (3 ) = -0 02MHz 1(4) = 200Hz

3 3

From these frequencies we can determine the number of

digital words genera-ted:

(200,000 wordsf sec * .5 sec)+ (20,000 words/' sec * .5 sec) + (2,000 words/sec * .5 sec)+

(200 words/sec * .5 sec)=lll,100 words

In example 1, 400,000 words are generated using fixed

sampling rate. With a step varying sampling rate we

generated 111,100 v/cr&s, almost four times less than fixed

sampling rate. Breaking up the analog signal into more than

four time frames would decrease the number of digital words

generated but increase the complexity of the design.

Since we know from Ledezma-Razcons investigations,

the initial charging of the double layer at the liquid-solid

interface occur so quickly that a fast sampling rate would

need to be used initially. Secondly, the subsequent

relaxation of the double layer charging occurred over a

longer period, in tie order of 200 to 300 seconds. A third

observation was the slow recovery of the plant back to its

original potential condition. This period was in the order

of minutes. See Figure 16 for the basic response of a

coulostatic discharge.

3 4

.5s 3 DOS 30 tAxti.

T I M E

FIGURE 16

Basic Response of a Coulostatic Discharge

From Ledezma—Razcon* s investigations it was evident

-that we have three time intervals. (See Figure 16) . The

first interval I(1) (the transient region) is very fast.

Turing lecleznia's research it was found that this interval

occurred so quickly that conventional analog instrumentation

operating from portable pov/er sources could not record the

signal. This internal will be about 1/2 second. The second

interva 11 1(2) will be about 300 seconds long. After this,

during interval 1(3), the charge device (capacitor) will be

disconnected from the probes and the relaxation of the

3 5

implanted charge will be monitored for approximately 30

minutes if necessary.

It was evident that a three interval, step varying

sampling rate method vould be optimal for this application.

Interval 1(1) waveform is shown as a dotted line as we have

no actual data on this portion of the coulostatic impulse

response. Interval I(1) sampling rate (period) may need to

be in the range of 15 0 microseconds to 500 microseconds.

Interval 1(1) will be 1/2 second in duration giving us 3333

to 16 6 6 Bytes of information to store. However, if this

interval's waveform proves to be continuous, slow in

frequency, and rapid rise time (ie. high amplitude), then we

could reduce our sampling rate drastically to perhaps 1.5

milliseconds giving us only 333 Bytes of information to

store.

Interval I (2) is to some extent expected to follow an

exponential or an error function. If this proves to be the

case than perhaps as little as 300 Bytes of information

daring this interval vil 1 be necessary to reproduce the

waveform. This would dictate that the sampling rate (period)

will be approximately 1 second.

Interval I (3) is again expected to be an exponential

or error function v/ith a very slow time constant. We may

wish to monitor this response for approximately 30 minutes.

3 6

Using 300 points, we derive a sampling rate (period) of 6

seconds.

Since the six important variables to the three

interval, step varying sampling rate was known, [1(1), 1(2)

and 1(3) duration, and 1(1), 1(2) and 1(3) sampling rate,]

the circuit design could be conceived.

B)Design Criteria;

The three interval, step varying, sampling rate clock

circuit will heretofore be referred to as the Programmable

Pulse Train Generator (circuit board #6). The following list

was the design criteria for this circuit:

1. Interval 1(1), 1(2) and 1(3) duration must be

programmable.

2. Interval 1(1), 1(2) and 1(3) sampling rate'

must be programmable.

3. After programming, the circuit must be

automatic and switch from interval 1(1) to 1(2)

to 1(3), sequentially, then turn off.

4. The design would be digital, using state of

the art CMOS chips for a single +5 volt supply.

3 7

5. A frequency range from 4 microseconds to 1

second with 256 possible frequencies between

them.

6. The number of Bytes in each interval range

from approximately 10 to 65 thousand. ie. The

duration of the intervals vary from approximately

1.5 milliseconds to 60 minutes.

7. The circuit must interface with the 1806A on

board computer only. No other circuit boards

will interface with the Programmable Pulse Train

Generator.

The pulse train output of this circuit is the

sampling rate for the A/D conversion. The 1806A

microprocessor controls the A/D converter on the Kim 5 board.

The pulse train would be used as a flag to the microprocessor

telling it when to digitize and store the coulostatic

response. Used in this fashion, the microprocessor does not

have to keep track of real time, nor does it need to make any

decisions on clock speeds or interval durations. In this

configuration, the microprocessor only has to control relay

switching and the A/D converter as well as store data into

memory, making the software simple for the user and the A/D

conversion can run at the fastest sampling rate possible.

3 8

C)Theory of Operations:

In order to achieve an optimal design which would

meet all of the design criteria in Section B, advanced

state-of-the-art CMOS circuitry was investigated. Refer to

Figure 17 for the block diagram of the circuit. The heart of

the Programmable Pulse Train Generator resides in the Harris

82C54 CMOS programmable interval timer. This 24 pin chip

contains three independently programmable and functional 16

bit counters, each capable of handling clock frequencies of

up to 8MHz.

Using the 82C54 timer in the design solved one of the

most common problems in any microcomputer system, the

generation of accurate time delays under software control.

Instead of setting up timing loops in software, the

programmer loads the three counters with the three interval

durations 1(1), 1(2), and 1(3) discussed in Sections A and B.

Hence, design criteria 1 and 6 was met.

To achieve design criteria #2 and #5 which was to

have the sampling rates for interval 1(1), 1(2), and 1(3)

fully programmable from 4 microseconds to approximately 1

second with 256 possible frequencies between them, two CDP

1863 were used in cascade. These 16 pin CMOS chips are 8-bit

programmable frequency dividers capable of handling input

3 9

frequencies greater than 2MHz. In order to program these two

chips during intervals 1(1), 1(2), and 1(3), three MC14508B

CMOS dual 4-bit latches were implemented. Each chip is

loaded via the computer with the sampling rate for one of the

three intervals. These chips have convenient tri-state

outputs allowing the devices to be used in a time sharing bus

line configuration, (ie. the outputs are wired in parallel to

the CDP1863 chips.

The remaining circuitry was implemented to achieve

the remaining design criteria which were: The circuit must

interface with the 1806A microprocessor; the circuit must be

a sequential machine (ie. once programmed the circuit

operates with no control from the 1806A microprocessor),

switching from interval 1(1) to 1(2) then to 1(3) then off.

Logic 1 circuitry provides the appropriate timing

pulses to the three 14508B chips and the 82C54 for loading

operations. This circuits input is the eight multiplexed

address lines, the TPA pulse, and the write (MRD) pulse from

the 1806A microprocessor. Logic 1 output then strobes one of

the three 14508B latches of the 82C54 chip while data is

valid on the bus.

LOGIC 2

CLOCK OUT .

TO EF2

CLOCKi

GATE

GATE

GATE 2

GATE 3

LOGIC 3

OUT GATE 0

GATE

GATE 2 co t/j UJ

i-a: CDq

ao<

STR 2

STR

<8 BIT DATA BUS LOGIC I

CO O CM m n sr =£

CDPI863 CDPI8G3

#2

oo o

44-

LLI a

UJ o

ao s ro

82C54 BUS

MZZ7T* STR 3

CK IN

TPAj r.RD

FIGURE 17

Programmable Pulse Train Generator Block Diagram

4 1

The 82C54 is loaded with three independent 16 bit

counts. Each counter is a count down counter. All three

counters clock inputs are tied together and are driven by

logic circuit #2. Each counter has an enable which allows

the counter to count down. These enables are labeled Gate 0

for counter 0, Gate 1 for counter 1, and Gate 2 for counter

2. When gate is low the count is disabled. Each counter has

an output which are all wired to logic 3. These outputs

pulse low for one clock period when the appropriate counter

reaches a count of zero. Hence, when a count is complete

that counters output pulses low for one clock period.

The three counter outputs are wired into the logic #3

block where they are logically "ANDED" together. The output

of the "AND" gate is wired to a 4013A chip. This chip

consists of two "D" type flip flops which are wired to create

a two bit binary counter. The outputs of this binary counter

are initially (00) when reset. When counter zero completes

its count and output zero pulses low the output of the "AND"

gate pulses low and the binary counter advances one count to

(01). When counter 1 completes its count, the binary counter

advances again in the same fashion to (10). When counter 2

completes its count, again the binary counter advances to

(11) •

4 2

The two bit binary counter is wired to a CD4555B

two-to-four multiplexer chip. The CD4555B has four outputs

labeled Gate 0, Gate 1, Gate 2, and Gate 3. When the 4013

binary counter is at the (00) state, Gate 0 is high. When

the count is at (01) Gate 1 is high. When the count is at

(10) Gate 2 is high. When the count is at (11) Gate 3 is

high. Gate 0 enables the first 14508B chip that holds the

data for the first sampling rate, and enables counter 0 in

the 82C54. Gate 1 enables the second 14508B chip that holds

the data for the second sampling rate, and enables counter 1

in the 82C54. Gate 2 enables the third 14508B chip that

holds the data for the third sampling rate, and enables

counter 2 in the 82C54. Gate 3 stops the input clock and

stops the system.

The outputs of the three 14508B chips are wired to

the two CDP1863 programmable dividers. Each divider is ,

controlled by four of the eight bits. The output of the

CDP1863 #1 is wired to the input of the CDP1863 #2 and to

logic #2. The output of the CDP1863 #2 is wired to logic #2.

Logic #2 block selects CDP1863 #1 or CDP1863 #2 output

depending on Gate 0. If Gate 0 is high, CDP1863 #1 output is

selected. If Gate 0 is low, CDP1863 #2 output is selected.

This way during counter 0 count (interval 1(1)) Gate 0 is

high and the output of logic #2 is the input 2MHz clock

4 3

divided by CDP1863 #1. This enables a higher frequency for

interval 1(1). When Gate 1 and Gate 2 are high the output of

logic 2 is the input 2MHz clock divided by both CDP1863 #1

and CDP1863 #2. This enables lower possible frequencies

during interval 1(2) and 1(3).

Block Diagram Overview

Initially the three 14508B's are programmed with the

appropriate frequencies for sampling Rate 1, sampling Rate 2,

and sampling Rate 3. Counter 0 in the 82C54 is initially

loaded with the number of cycles for interval 1(1). Counter

1 is loaded with the number of cycles for interval 1(2).

Counter 2 is loaded with the number of cycles for interval

1(3). The 4013A is reset by the 1806A microprocessor to a

count of (00). Hence, Gate 0 is high and the first 14508B is

enabled as well as counter 0. The 1806A microprocessor sends

an enable signal (CL24) which enables the 2MHz clock to get

to the input of CDP1863 #1. CDP1863 #1 is programmed with

four bits from the first 14508B. The second and third

14508B's are disabled (Gate 1 and Gate 2 are low). The

output clock from CDP1863 #1 is selected by Logic 2 since

Gate 0 is high. Therefore the output of CDP1863 #1 is the

clock for Counter 0. Counter 0 then counts down to zero.

When the count is complete, Counter 0 output pulses low and

4 4

the 4013 advances to (01), and Gate 0 goes low and Gate 1

goes high. Now the second 14508B is enabled. This chip

holds the data to select the frequency for interval 1(2).

CDP1863 #1 and CDP1863 #2 are both programmed by the 8-Bits.

Logic 2 selects the output of the CDP1863 #2 since Gate 0 is

low. The output of Logic 2 is the 2MHz clock divided by both

CDP1863's. This output is the clock input for counter 1

which is enabled now by Gate 1. Counter 1 counts to zero and

counter 1 output pulses low. The 4013A advances again to

(10). Gate 1 goes low and Gate 2 goes high. The third

14508B is enabled which programs the two CDP1863*s. Logic 2

still- selects the output of CDP1863 #2 since Gate 0 is low.

Gate 2 also enables counter 2. Counter 2 then counts down.

When the count reaches zero, counter 2 output pulses low and

the 4013 advances count to (11). Gate 2 then goes low and

Gate 3 goes high. This stops the counting and the output

clock. The output clock is wired to' EF2 on the 1806A

microprocessor. Refer to Table II for the 14508B Data words

(8-Bits) vs clock out frequencies.

4 5

Loading the 82C54, the 14508B and controlling the A/D Converter

The 82C54 CMOS timer 8-Bit Data Bus input is

connected directly to the 8-Bit,1806A microprocessor Data Bus

for data transfer (loading counters). The three 14508B 8-Bit

Data Bus inputs are also connected directly to the 8-Bit Data

Bus of the 1806A microprocessor for loading frequency data.

The 14508B latches strobe in data during the write

cycle of the microprocessor if the correct address has been

sent out on the address Bus. To accomplish this additional

logic circuitry was required to obtain the proper timing

sequence during a write cycle. The Kim Circuit board #5 was

modified with a 54HC138(U13) decoder which was used to decode

the 8 high order Bits of the 16-Bit multiplex address Bus.

This decoder is used to enable the A/D converter on the Kim

#5 board (U10), the 14508B chips and the 82C54 chip on the

Programmable Pulse Train Generator board. An 8-Bit latch

(U15) was added to the Kim #5 board in order to latch the 8

most significant (high order) Bits of the 16-Bit address.

The TPA signal from the microprocessor was wired to the Kim

#5 board to strobe U15 with the high order address Bits

during the TPA pulse. The timing diagram for U15 latch is

shown in Figure 18.

46

TPA

HIGH BYTE' ADDESS

U 15 LOADED.

>ALID f x LOADED

FIGURE 18

Kim #5, U15 Timing Diagram

U13 then decodes this high order Byte address and enables the

A/D converter for read or write operations or enables one of

the three 14508B chips or the 82C54 chip. The output of the

decoder is eight lines labeled Y(0)-Y(7). These lines go low

if the proper address is latched and decoded. The addresses

used to enable Y(0)-Y(7) are in Figure 19.

ADDRESS

04XX-05XX 06XX-07XX 08XX-09XX OAXX-OBXX OCXX-ODXX OEXX-OFXX

ENABLE

Y (2) Y(3) Y (4) Y (5) Y (6) Y (7)

USED FOR

(U6)82C54 (U6)82C54 (U3)14508B (U2)14508B (Ul)14508B U10 A/D Converter

Note: Y(0) and Y(l) Not Used

FIGURE 19

Address for Kim #5 U13 Decode

47

Reading and writing to the A/D converter is

accomplished using the enable line Y(7) as well as the memory

read pulse (MRD) and the memory write pulse (MWR) from the

microprocessor. The A/D converter starts a conversion with a

read pulse (MRD) only if qualified by Y(7) being in the low

state. The A/D converter sends out the end of conversion

pulse (EOC) when conversion is complete. This EOC pulse is

wired to the Flag 1 (EF1) of the microprocessor. The

microprocessor stores the 12-Bit digital representation of

the analog voltage by performing a memory write operation.

When the memory write pulse (MWR) occurs and the address 8F00

is sent out on the address Bus the high order 6-Bits will be

read by the computer to be stored away in a memory location.

Two mask Bits are added to the high order 6-Bit data to form

an 8-Bit word.

If the address 8E00 is sent out, the low order Bits

will be read by the computer to be stored away in memory.

Again two mask Bits are added to the 6-Bit data to form an

8-Bit word. The two mask Bits are the two most significant

Bits of both 8-Bit words. The timing for TPA, Y(7), the

latched address, the (MRD), and the (MWR) signals are shown

in Figure 20.

48

T PA

ADDRESS-LATCHED.

y?

MRD

W W R

X

Figure 20

A/D Converter Timing Diagram

The three 14508B latches require a high to low

transition on their strobe lines to latch in data. To

accomplish this during a (MRD) pulse (computer reads data

from memory and outputs it), Logic "AND" Gates and inverters

were used on the (MRD) signal, the TPB pulse, and the decoded

enable lines Y(4), Y(5), and Y(6). Refer to the schematic »

for the Coenen Board #6 and Figure 21. When the (MRD) pulse

is generated by the computer during an output command and if

Y(4), Y(5), or Y(6) is decoded the appropriate 14508B chip

will be loaded with the output data. See Table 2 for data vs

output clock frequency.

49

MRD

MRD .

tpb

y 5,g

y4 ,5,6 .

tpb'mrd'Y •4508B"

LOADED "x loaded

FIGURE 21

Timing Diagram to Load the 14508B Chips

The 82C54 Programming Counter

The 82C54 required some additional Logic circuitry to

interface with the 1806A microprocessor. This additional

circuitry solved the timing and addressing problems during

write operations. Like the A/D converter on the Kim #5

Circuit board and the 14508B latches on the programmable

pulse train generator board, it was desirable to address the

82C54 using the high order Byte of the multiplexed address

Bus. In this way, the design would make use of the 8-Bit

50

latch and the decoder (U15 and U13) on the Kim #5 Circuit

board.

Aside from the 8-Bit Data Bus input, the 82C54 has

four inputs that were utilized for loading the chip. The

A(0) and A(1) inputs are the address Bits to select one of

the three counters or the control word register. The control

word register is used to define the counter operation or

mode. The (CS) input is used to enable the chip. A low on

this input enables a write operation. The WR input is used

to load the counters or the control word register depending

on the state of A(0) and A(l) and only if (CS) is low.

To control A(0) and A(l) the two low order Bits were

used from the output of the latch on the Kim #5 Circuit board

(U15, Pins 18 and 19). (CS) was defined by Y(2) or Y(3)

going low from the decoder on the Kim #5 Circuit Board (U13,

Pins 12 and 13). To obtain a low on (WR) at the proper time,

(MRD) from the 1806A microprocessor was inverted then "ANDED"

with (TPB). This output was then inverted to get the desired

(WR) pulse. See the timing diagram in Figure 22.

51

TPA

Aoj Ai

\?3

CS

mrd'

nTrd

TPB

T P B « M R D

T P B * M R D

X Ao,A/ DEFINED I y r ,y3 defined

ILOADED

FIGURE 22

Timing Diagram to Load the 82C54 Chip

Programming the 82C54

The control word register is selected by the write

cycle when A(l), A(0)=(11). When the 1806A microprocessor

completes a write operation to the 82C54, the data is stored

in the control word register and is interpreted as a control

word used to define the counter operation or mode. Counters

are loaded by writing a control word and then an initial

count. All control words (one for each counter) are written

into the control word register, which is selected when A(l),

52

A(0)=(11). The control word specifies which counter is being

programmed.

By contrast, initial counts are written into the

counters after the control word is loaded for that counter.

The A (1) , A(0) inputs are used to select the counter to be

written. The format of the initial count is determined by

the control word used.

The programming procedure for the 82C54 is very

flexible. Only two conventions need to be remembered:

1) For each counter, the control word must be

written before the initial count is written.

2) The initial count must follow the count

format specified in the control word (least

significant Byte only, most significant Byte

only, or least significant Byte and then most

significant Byte).

Since the control word register and the three

counters have separate addresses (selected by the A(l), A(0)

inputs), and each control word specifies the counter it

applies to (SCO, SCI Bits), no special instruction sequence

is required. Any programming sequence that follows the

conventions above is acceptable. However, for simplicity

reasons, the method of loading the least significant Byte and

53

then the most significant Byte was used in the programs found

in Chapter IV. See Fig. 23 for the control word formats.

A1, AO - 11;CS = 0;RD= 1;WR = 0

Dj D6 D5 D4 D3 D2 Do

SC1 SCO RW1 | RWO M2 M1 MO BCD

SC — S«l»ct Counter:

SC1 SCO

0 0 Select Counter 0



1 1 Read-Back Command (See Read Operations)

RW - Rud/WrlU:

RW1 RWO

0 0 Counter Latch Command (see Read Operations)

0 1 Read/Wriie least significant byte only

1 0 Read/Write most significant byte only.

1 1 ReadWrtte least significant byte first, then most significant byte.

NOTE: DON'T CARE BITS(X) SHOULD BE 0 TO INSURE COMPATIBILITY W(TH FUTURE PR00UCTS

M - MODE:

M2 M1 MO

0 0 0 ModeO

0 0 1 Mode 1

X 1 0 Mode 2

X

1

1

t

0

1 Mode 3 X

1

1

t

0 0 Mode 4

X

1

1 0 1 Mode 5

BCD:

0 Binary Counter 16-bits

1 Binary Coded Decimal (BCD) Counter (4 Decades)

FIGURE 23

82C54 Control Word Formats

CHAPTER IV

NEC COMPUTER TERMINAL OPERATING INSTRUCTIONS AND UTILITY SOFTWARE

The interface between the user and the Multi-step

Coulostatic Impulse Generator is the NEC/PC-8201A computer.

This machine is used as a terminal to load, run, and monitor

the programs for the 1806A microprocessor in the Impulse

Generator. The terminal is connected to the Impulse

Generator via a RS232 cable. The terminal is fully portable

and can be powered by the AC adapter or the Ni-cad batteries

located on the bottom side of the key board.

First plug in the RS232 cable to the front receptacle

on the Impulse Generator, then connect the other end of the *

cable to the RS232 receptacle located on the rear of the NEC

terminal (see Figure 24 for the Front Panel Interconnect

Diagram). Turn on the NEC terminal and adjust the contrast

for comfortable viewing. The display will show the menu.

Push the right hand arrow until the reverse field area is

over the word "TELCOM", then push the return key once. Press

the "F.4" key once, and type in "5I72NN" and press the return

key. Press the "F.5" key once. The bottom of the display

54

55

should read: "Prev Full Up Down". If it reads

"Prev Half Up Down", press the "F.2" key once.

NEC PC8201A

FIGURE 24

Front Panel Interconnect Diagram

56

Now the terminal is programmed to talk to the 1806A

microprocessor monitor program. Turn on the Impulse

Generator with switch SI. Push switch S2 down to reset then

back up to run (see Figure 13). Now press the return key on

the terminal once. An astericks should appear on the

display. All programs will be entered, run, and displayed on

the terminal screen via the 1806A microprocessor monitor

program.

The purpose of the monitor program is to provide a

convenient place for the 1806A microprocessor to begin

running. The monitor allows the user to display memory,

insert into memory, and run the program. The monitor program

also has many other functions which are not used for this

application but may be referred to in the user manual for the

Microboard Computer Development System CDP18S693 + CDP18S694.

UT'62 Commands

Following is a description of the three UT62 monitor

program commands used for this application. Note that all

addresses, data, and Byte counts are entered as hexadecimal

numbers (indicated by the letter H following the number).

57

D Commands:

Name: Memory display.

Purpose: To allow, a specified area of memory to be

displayed on the NEC terminal.

Format: D (start ADDR) (space) (# of Bytes) (CR).

Action: The contents of memory, beginning at the

specified (start ADDR) will be transmitted

to the user terminal. (# of Bytes) allows

the transmission of a specific number of

Bytes preceded by a space beginning at the

start address.

Example: D0000 F(CR)

This will display 16 Bytes of memory starting

with address 0000H.

I Commands:

Name: Memory insert.

Purpose: To alter the contents of memory beginning at

the specified address.

Format: I (start ADDR) (space) (data) (CR).

Action: A memory location is accessed at the specified

(start ADDR). The (data) required is one 8-Bit

Byte specified by Two hexidecimal. Any number of

58

Bytes can be entered in a continuous string.

When data entry is complete, a (CR) returns the

user to the monitor program.

Example: 10000 68C30005D3(CR).

This will enter the five data Bytes

(68,C3,00,05,D3) into the five memory locations

starting at location OOOOH and ending at 0004H.

P Commands:

Name: Program Run.

Purpose: To allow a user program to be run beginning at

the specified address.

Format: P (start ADDR) (CR).

Action: The user program will begin execution at the

specified (start ADDR).

Example: POOOO(CR).

This will begin execution of the user program

starting at address OOOOH.

These three monitor commands enable the user to

insert programs and data, display programs and data, and run

user programs which are located in the RAM of the 1806A

microprocessor.

59

Each of the six circuit boards in the Coulostatic

Impulse Generator are controlled by the 1806A microprocessor.

The Kim #1 through the Kim #4 boards contain the six charge

capacitors and the associated circuitry to control the

charging and discharging of the capacitors. The Kim #5 board

contains the circuitry to perform the analog to digital

conversion necessary for data acquisition and storage of the

data into the 1806A microprocessor RAM. The Coenen board #6

contains the circuitry to generate the sampling rate clock

for analog to digital conversion.

Utility software has been generated for these boards.

The following programs serve as a basis for adequate control

of these boards and were useful in the checkout and analysis

of the system. However, no attempt was made to optimize the

software speed or length. These programs will serve the user

as building blocks for future applications. Refer to the

User Manual for Microboard Computer Development System

CDP18S693 + CDP18S694, for the Table of 1806A microprocessor

instructions and OP Codes.

60

Utility Software Programs

Program #1:

Controlling the Kim #1-Kim #4 Circuit boards;

Address 0000

1

2

3

4

6

7

8

9

A

B

C

0050

OP Code/Data 68

C3

00

05

D3

IB

68

C4

00

50

E4

E*

00

Definition Load the next two Bytes into scratch pad register #3.

Load (0005) into register #3.

Set register #3 as the program counter with address (0005) as start point. Set Q high to enable all circuit boards. Q low resets everything. Load the next two Bytes into scratch pad register #4.

Arbitrarily use address (0050) as memory location to send out to the Kim #3 Board, U4 or U5 or the Kim #4 Board, U7 or U8.

Set X=4, R(X) = R(4)

Output, M(R(4))—Out

Stop

Data to be sent.

El = Output to Kim #4, U7, CL8-CL1, 8-Bits

E2 = Output to Kim #4, U8, CL16-CL9, 8-Bits

61

E3 = Output to Kim #3, U4, CL24-CL17, 8-Bits

E4 = Output to Kim #3, u5, CL32-CL25, 8-Bits

See Table I for typical data formats in hexidecimal code.

Using the monitor program for program entry and

program running:

Example:

After reseting the Coulostatic Impulse Generator and

with the reset/run switch back in the run position, press the

return key once then enter the following after the astericks:

*10000 68C30005D37B68C40050E46100(CR)

*10050 01(CR)

*P0000(CR)

CL1 control signals should be high while all other control

signals should be low.

Warning: Refer to schematics on the Kim Circuit boards

when deciding what data to send. If the wrong

relays are switched together a short from the

+5 volt power source to the -5 volt power

source could result. First decide what relays

need to be closed ie. what control signals

(CL1-CL32) then convert the control signals

62

to the proper hexidecimal data word (see

Table 1 for examples). Refer to the User

Manual for Microboard Computer Development

System CDP18S693 + CDP18S694 for additional

OP codes if required.

Program #2:

Self-Test Program to control the Kim #5 Circuit board Analog

to Digital Conversion;

Connect a jumper from Probe 2 tip jack to earth

ground tip jack on the front of the Coulostatic Impulse

Generator. Connect a jumper from the earth ground tip jack

to chassis ground tip jack (see Figure 13). This program

connects Capacitor #1 (C7) on the Kim #1 board to the A/D

circuit on the Kim #5 board. The following control lines are

switched high; CL1, CL3, CL7, CL22, CL21, CL20. With these

relays closed, the Capacitor #1 is charged to a positive

voltage depending on the setting of the CI voltage adjustment

pot of the front panel. Connect A DVM from the tip jack

marked CI voltage and the tip jack marked GND. Adjust the CI

pot to 2 volts. Enter the following program:

2

3

4

5

6

7

8

9

A

B

G

D

E

F

10

11

12

13

14

15

16

OP Code/Data 68

C3

00

05

D3

7B

6 8

C4

00

50

E4

61

68

C4

00

51

E4

63

68

C4

OE

00

E4

63

Definition Set Program Counter to 0005

Set Q high

Get Data for CL1,3,7

0050 is the address for the Data to control CL1-CL8

Set X=4

Output CL1,3,7

Get Data for CL20,21,22

0051 is the address for the Data to control CL17-CL24

Set X=4

Output CL20,21,22

Load dummy address OEOO to write to Kim #5 board to start conversion.

Set X=4

64

Address OP Code/Data Definition 17 67 Dummy output

18 3C Wait for EF1 to go low.

19 18

1A 68 Address 0F00 is the address of the high Byte of data from

IB C4 the Kim #5 board.

1C OF

ID 00

IE E4 Set X=4

IF 6F Input high Byte

20 68 Address 0E00 is the address of the Low Byte of Data from

21 C4 the Kim #5 board.

22 OE

23 00

24 E4 Set X=4

25 6F Input Low Byte

26 30 Jump to(0012)

27 12

28 00 Stop

0050 45 =CL1,3,7

0051 38 =20,21,22

Run the program then reset the system. With the

reset/run switch back in the run position, display the

results by doing the following:

65

*D OEOO 01(CR)

*D 0F00 01 (CR)

The display should show the low and high Bytes

respectively.

Example: Address; 0F00 OEOO

Data; 19 26

19 = 00011001

26 = 00100110

The A/D Converter is a 12-Bit converter and hence the

two most significant Bits must be dropped from both data

words therefore;

Address 0F00 OEOO

Data 011001 100110 = 2 volts

Use the following basic program to correlate the

Binary Data to the 2.0 volt measured potential adjusted on

the front panel. The program is written for the Commadore 64

computer but can be easily modified for any computer which

runs basic. The program will print out a table approximately

30 pages long correlating 12-Bit binary words to voltage

levels ranging from 0 volts to +5 volts DC.

66

10 OPEN4 , 4 20 PRINT#4,"

30 PRINT#4,"DECIMAL BINARY DATA" 40 PRINT#4," 50 DIM J (12) 60 FOR L=0 TO 4095 70 X=L 80 M=L*(5/4095) 90 FOR K=1 TO 12 100 X=X/2 110 IF XOINT(X) THEN: J (K) =1 120 IF X=INT(X) THEN:J(K)=0 130 X=INT(X) 140 NEXT K 150 PRINT#4 fL;" ";J(12);J(11);J(10);J(9);J(8);J(7) ;J(6) ; J(5);J(4);J(3);J(2);J(1);M 160 NEXT L

READY.

Program #3:

Program to load the Coenen board #6 and initialize the pulse train;

Address OP Code/Data Definition 0000 68 Load the Program

Counter with 0005 1 C3

2 00

3 05

4 D3

5 7B Set Q high

6 68 Load the address of 0D00 in the scratch

7 C4 pad register R(4).

Definition 0D00 is the address of U1 on the Coenen board #6.

Set X=4

Output M[R(4)] = Out to U1 Load the address of OBOO in the scratch pad register R(4). OBOO is the address of U2 on the Coenen board # 6 .

Set X=4

Output M[R(4)]=Out to U2 Load the address of 0900 in the scratch pad register R(4). 0900 is the address of U3 on the Coenen board # 6 .

Set X=4

Output M[R(4)]=Out to U3 Load the address of 0151 in the scratch pad register R(4). 0151 is the address of the data to be sent to the control word for Counter #1 in U6 on the Coenen board #6. Set X=4

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

68

OP Code/Data Definition F0 Load D register with data.

68 Load the address 0700 into the scratch pad register R(4). 0700

C4 is the address of the control word for Counter #1 in U6 on the

07 Coenen board #6.

00

54 Load Data=M[R(4)]

E4 Set X=4

67 Output Data M[R(4)]=Out to U6

68 Load the address 0152 in the scratch pad register R(4). 0152

C4 is the address of the Data to be sent to the least significant

01 Byte of Counter #1 in U6 on the Coenen board #6.

52

E4 Set X=4

F0 Load D register with Data


C4 is the address of the Counter #1 ' in U6 on the Coenen board #6.

04

00


E4 Set X=4

67 Output Data M[R(4)]=Out to U6


C4 is the address of the Data to be

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

69

OP Code/Data Definition sent to the most significant

01 Byte of Counter #1 in U6 on the Coenen board #6.

53

E4 Set X=4


68 Load the address 0400 into the scratch pad register R(4).

C4 Address 0400 is the address of Counter #1 in U6 on the Coenen

04 board #6.

00


E4 Set X = 4

67 Output M[R(4)]=Out to U6

68 Load the address 0154 into the scratch pad register R(4). The

C4 Address 0154 is the location of the control word for Counter #2

01 in U6 on the Coenen board #6.

54

E4 Set X=4


68 Load the scratch pad register R(4) with the address 0700.

C4 0700 is the address of the control word for Counter #2 in

07 06 on the Coenen board #6.

00


E4 Set X=4

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

70

OP Code/Data Definition 67 Output M[R(4)]=Out to U6


C4 0155 is the location of the data to be sent to the least

01 significant Byte of Counter #2 in U6 on the Coenen board #6.

55

E4 Set X=4



C4 0500 is the address of Counter #2 in U6 on the Coenen board #6,

05

00


E4 Set X=4



C4 0156 is the address of the data to be sent to the most

01 significant Byte of Counter #2 in U6 on the Coenen board #6,

56

E4 Set X=4



C4 0500 is the address of Counter #2 in U6 on the Coenen board #6.

05

6 2

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

71

OP Code/Data Definition 00


E4 Set X=4



C4 0157 is the address of the data to be sent to the control word

01 for Counter #3 in U6 on the Coenen board #6.

57

E4 Set X=4



C4 0700 is the address of the control word for Counter #3

07 in U6 on the Coenen board #6.

00

54 Load Data=M(R(4))

E4 Set X=4


68 Load scratch pad register R(4) with the address 0158.

C4 0158 is the address of the data to be sent to the least

01 significant Byte of Counter #3 in U6 on the Coenen board #6.

58

E4 Set X=4


79

7A

7B

7C

7D

7E

7F

80

81

8 2

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

72

OP Code/Data Definition 6 8 Load the scratch pad register

R(4) with the address 0600. C4 0600 is the address of Counter

#3 in U6 on the Coenen board #6. 0 6

0 0

E4 Set X=4



C4 0159 is the address of the data to be sent to the high Byte of

01 Counter #3 in U6 on the Coenen board #6.

59

E4 Set X=4



C4 0600 is the address of Counter #3 in U6 on the Coenen board #6.

06 •

00


E4 Set X=4


68 Load the scratch pad register R(4) with 0150. 0150 is the

C4 address of the data to be sent to the Kim #3 board, U4 to set

01 CL24 high this will start up the circuit.

50

73

Address OP Code/Data Definition 90 E4 Set X=4

91 63 Output CL24 high

92 00 Stop

The following example data must be entered into the

indicated addresses before the program can be run:

Address Data Definition of Data

0150 80 CL24 high

0151 34 Control word, Counter #1

0152 EF Least significant Byte #1

0153 4F Most significant Byte #1

0154 74 Control word, Counter #2


0156 01 Most significant Byte #2

0157 B4 Control word, Counter #3


0159 01 Most significant Byte #3

0D00 FF Clock Rate #l(See Table II)

0B00 OF Clock Rate #2(See Table II)

0900 1A Clock Rate #3(See Table II)

Refer to Chapter IV Section C for the detailed theory

of operation on the Coenen board #6. The output of the

7 4

Programmable Pulse Train Generator (Coenen board #6) is

connected to EF2 of the 1806A microprocessor. The program to

perform an analog to digital conversion should loop on EF2

transition. This way the Programmable Pulse Train Generator

tells the 1806A microprocessor when to get a data point.

Program #4:

Loading Ul, U2, or U3 on the Coenen board #6;

Address Data/OP Code Definition 0000 68 Set program counter=R(3)

01 C3

02 00

03 05

04 D3

05 7B Set Q high

06 68 Get address of Data to be sent

07 C4

08 0* Ul, U2, or U3 address

09 00

OA E4 Set X

0B 67 Output Data

0C 30 Jump to address 06

0D 06

0E 00 End

0D00 — Ul Data

Address OP Code/Data Definition 0B00 — U2 Data

0900 — U3 Data

* = D - U1 Data Address *' = B - U2 Data Address * = 9 - U3 Data Address

Program #5:

Loading U6 on the Coenen board #6;

Address OP Code/Data Definition

0000 68 Set program counter=R(3)

01 C3

02 00

03 05

04 D3

05 7B Set Q high

06 68 Set address of Data to be sent, select AO, Al

07 C4

08 0*

09 00

OA E4 Set X

0B 67 Output Data

OC 30 Jump to address 06

0D 06

0E 00 Stop

76

Address OP' Code/Data Definition A1 AO

0400 — U6 Data 0 0 0500 — U6 Data 0 1 0600 — U6 Data 1 0 0700 — U6 Data 1 1

*=4,5,6,7

As a guide line for future software applications the

following flow chart (in Figure 25) may be useful in putting

the various programs, indicated in this chapter together.

START PULSE TRAIN

EF2

START CONVERSION

w

E F I

BOARD N0.6

BOARD N0.5

WAIT FOR FLAG EF2 THEN START ONE A/D CONVERTION

CODE TO LOAD CARD NO. 6 WITH SAMPLING SPECIFICATIONS

CODE TO CHARGE CAPACITOR

CODE TO CONNECT 1 CAPACITOR TO THE PLANT AND THE A/D CONVERTER

CODE TO START THE PULSE TRAIN ON BOARD NO. G

CODE TO STORE DATA

FIGURE 25

Future Software Flow Chart

Table 1

Kim Circuit Board Control Words

Output Statement Control PIA

61 Kim 4, U7

62 Kim 4 / U8

63 Kim 3, U4

64 Kim 3, U5

Output Examples:

Output Data In Binary

61 CL8-CL5 CL4-CL1 62 - CL16-CL13 CL12-CL9 63 CL24-CL CL20-CL17 64 CL32-CL29 CL28-CL25

0000 1111 0001 1110 0010 1101 0011 1100 0100 1011 0101 1010 0110 1001 0111 1000 1000 0111 1001 0110 1010 0101 1011 0100 1100 0011 1101 0010 1110 0001 1111 0000

Control Signals

(8-Bits)

CL8-CL1

CL16-CL9

CL24-CL17

CL32-CL25

Data in

OF IE 2D 3C 4B 5A 69 78 87 96 A5 B4 C3 D2 El FO

TABLE II

U4 and U5 Data vs Output Clock Rates

Interval 1(1):

U4 Data Output (second)

xO 4.00E-06

xl 8.00E-06

x2 3.20E-05

x3 4.00E-05

x4 1.28E-04

x5 1.36E-04

x6 1.60E-04

x7 1.68E-04

x8 5.12E-04

x9 ? 5.20E-04

xA 5.44E-04

xB 5.52E-04

xC 6.40E-04

xD 6.48E-04

xE 6.72E-04

xF 6.80E-04

TABLE II(continued)

Interval 1(2) and 1(3):

[ U5 Data Output (second)

00 3.20E-05

01 6.40E-05

02 2.56E-04

03 3.20E-04

04 1.02E-04

05 1.09E-03

06 1.28E-03

07 1.34E-03

08 4.10E-03

09 4.16E-03

OA 4.35E-03

OB 4.42E-03

OC 5.12E-03

0D 5.18E-03

0E 5.38E-03

OF 5.44E-03

10 6.40E-05

11 1.28E-04

12 5.12E-04

13 6.40E-04

14 2.05E-03

15 2.18E-03

TABLE II (continued)


U4 & U5 Data Output (second)

16 2.56E-03

17 2.69E-03

18 8.19E-03

19 8.32E-03

1A 8.70E-03

IB 8.83E-03

1C 1.02E-02

ID 1.04E-02

IE 1.08E-02

IF 1.09E-02

20 2.56E-04

21 5.12E-04

22 2.05E-03

23 2.56E-03

24 8.19E-03

25 8.70E-03

26 1.02E-02

27 1.08E-02

28 3.28E-02

29 3.33E-02

2A 3.48E-02

2B 3.53E-02

TABLE II(continued)



2C 4.10E-02

2D 4.15E-02

2E 4.30E-02

2F 4.35E-02

30 3.20E-04

31 6.40E-04

32 2.56E-03

33 3.20E-03

34 1.02E-02

35 1.09E-02

36 1.28E-02

37 1.34E-02

38 4.10E-02

39 4.16E-02

3A 4.35E-02

3B 4.42E-02

3C 5.12E-02

3D 5.18E-02

3E 5.38E-02

3F 5.44E-02

40 1.02E-03

41 2.05E-03




42 9.19E-03

43 1.02E-02

44 3.28E-02

45 3.48E-02

46 4.10E-02

47 4.30E-02

48 1.31E-01

49 1.33E-01

4A 1.39E-01

4B 1.41E-01

4C 1.64E-01

4D 1.66E-01

4E 1.72E-01

4F 1.74E-01

50 1.09E-03

51 2.18E-03

52 8.70E-03

53 1.09E-02

54 3.48E-02

55 3.70E-02

56 4.35E-02

57 4.57E-02

TABLE II(continued)



58 1.40E-02

59 1.41E-01

5A 1.48E-01

5B 1.50E-01

5C 1.74E-01

5D 1.76E-01

5E 1.83E-01

5F 1.85E-01

60 1.28E-03

61 2.56E-03

62 1.02E-02

63 1.28E-02

64 4.10E-02

65 4.35E-02

66 5.12E-02

67 5.38E-02

68 1.64E-01

69 1.66E-01

6A 1.74E-01

6B 1.77E-01

6C 2.05E-01

6D 2.07E-01

TABLE II(continued)



6E 2.15E-01

6F 2.17E-01

70 1.34E-03

71 2.69E-03

72 1.08E-02

73 1.34E-02

74 4.30E-02

75 4.57E-02

76 5.38E-02

77 5.64E-02

78 1.72E-01

79 1.75E-01

7A 1.83E-01

7B 1.85E-01

7C 2.15E-01

7D 2.18E-01

7E 2.26E-01

7F 2.28E-01

80 4.10E-03

81 8.20E-03

82 3.28E-02

83 4.10E-02

Interval 1(2) and

U4 & U5 Data

84

' 85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

TABLE iI (continued)

I (3) :

Output (second)

1.31E-02

1.39E-02

1.64E-02

1.72E-02

5.25E-01

5.33E-01

5.58E-01

5.66E-01

6.56E-01

6.64E-01

6.89E-01

6.97E-01

4.16E-03

8.32E-03

3.33E-02

4.16E-02

1.33E-01

1.41E-01

1.66E-01

1.75E-01

5.32E-01

5.41E-01

TABLE II(continued)

Interval 1(2) and 1(3)


9A 5.66E-01

9B 5.74E-01

9C 6.66E-01

9D 6.74E-01

9E 6.99E-01

9F 7.07E-01

AO 4.35E-03

1A 8.70E-03

A2 3.48E-02

A3 4.35E-02

A4 1.39E-01

A5 1.48E-01

A6 1.74E-01

A7 1.83E-01

A8 5.57E-01

A9 5.65E-01

AA 5.92E-01

AB 6.00E-01

AC 6.96E-01

AD 7.05E-01

AE 7.31E-01

AF 7.40E-01

TABLE II(continued)


U4 & U5 Data

BO

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

CO

C I

C2

C3

C4

C5

Output (second)

4.42E-03

8.83E-03

3.54E-02

4.42E-02

1.41E-01

1.51E-01

1.77E-01

1.86E-01

5.66E-01

5.75E-01

6.01E-01

6.10E-01

7.07E-01

7.16E-01

7.43E-01

7.51E-01

5.12E-03

1.02E-02

4.10E-02

5.12E-02

1.64E-01

1.74E-01

TABLE II(continued)


U4 & U5 Data

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

DO

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

Output (second)

2.05E-01

2.15E-01

6.55E-01

6.66E-01

6.96E-01

7.06E-01

8.19E-01

8.29E-01

8.60E-01

8.70E-01

5.18E-03

1.04E-02

4.14E-02

5.18E-02

1.66E-01

1.76E-01

2.07E-01

2.18E-01

6.63E-01

6.73E-01

7.04E-01

7.15E-01

TABLE II(continued)


U4 & U5 Data

DC

DD

DE

DF

EO

El

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

FO

F1

Output (second)

8.29E-01

8.39E-01

8.70E-01

8.81E-01

5.38E-03

1.07E-02

4.30E-02

5.38E-02

1.72E-01

1.83E-01

2.15E-01

2.26E-01

6.89E-01

6.99E-01

7.32E-01

7.42E-01

8.60E-01

8.72E-01

9.04E-01

9.15E-01

5.44E-03

1.09E-02




F2 4.35E-02

F3 5.44E-02

F4 1.74E-01

F5 1.85E-01

F6 2.18E-01

F7 2.28E-01

F8 6.96E-01

F9 7.07E-01

FA 7.40E-01

FB 7.51E-01

FC 8.70E-01

FD 8.81E-01

FE 9.14E-01

FF 9.25E-01

CHAPTER V

CHECKOUT AND TROUBLE SHOOT PROCEDURES

Kim #1 through Kim #5 Circuit Boards

Checkout and trouble shooting procedures for the Kim

#1 through the Kim #5 Circuit boards can be found in Bruce

Kim's thesis titled the Multi-Step Electro Chemical Impulse

Generator and Potential Monitoring System, dated 1985.

However, Bruce Kim performed his checkout procedures by means

of plugging each board into a test fixture and wiring up

power and stimulus via jumper wires. Since my research

included designing the interface between the Kim Circuit

boards, the Coenen board #6 and the 1806A microprocessor

boards, a much simpler approach is now available.

Each of the Kim boards is controlled by the 1806A

microprocessor. By placing any one of the circuit boards on

A 44 pin extender board gives the trouble shooter the

capability to perform unlimited tests using the programs

outlined in Chapter IV. All of the necessary information for

fault isolation can be found within this text and Bruce Kim's

thesis. To discuss every possible fault and its trouble

shooting procedure would not be feasible within this text.

91

92

One should take a logical approach when fault isolation is

necessary. Great care must be taken with all circuit boards

as they all contain CMOS circuitry which is very susceptible

to electro-static damage. The trouble shooter should wear a

grounding wrist strap at all times when working on the

circuit boards. Power should always be turned off before

circuit boards are removed or replaced within the chassis.

The front panel must be removed from the chassis to

gain access to the circuit boards. Once the front panel is

removed, it should be placed on top of the chassie with the

potenteometers, switches, test points, and the RS232

connection facing up. In this way, the system can be fully

operated and checked out simultaneously.

Coenen Board #6 Checkout

To verify proper operation and/or to trouble shoot

the Programmable Pulse Train Generator (Coenen board #6),

follow the procedures outlined below:

1) Turn off power to the system via the front panel

switch and remove the front panel from the chassis.

Lay the front panel on top of the chassis so that

the interconnecting wires (from the front panel to

the chassis) are out of the way from pulling the

93

Coenen board #6 out. Remove the Coenen board #6

carefully and replace it with the 44 pin extender

board. Insert the Coenen board #6 into the

extender with the components facing to the left.

Connect the NEC/PC-8201A Computer to the front

panel via the RS232 cable as described in Chapter

IV. Turn power on to the system and reset the

microprocessor via the front panel reset switch as

outlined in Chapter IV.

2) Obtain a single trace, 5MHz scope. Connect the

ground pin of the probe to pin (22) or (Z) on the

Coenen board #6. Connect the probe tip to pin (E)

of the Coenen board #6. Set up the scope to

measure a 5V square wave which will vary from

.5ms to 15ms.

3) Load the computer program #3 for the Programmable

Pulse Train Generator outlined in Chapter IV. Run

the program. The scope display should show a .6ms

square wave for 14.5 seconds, then a 5.0ms square

wave for 3 seconds, and a 12ms square wave for

6.5 seconds, then it should shut off.

This checkout procedure verifies the following:

A) Proper loading of the MC14508B chips (U1,U2,

U 3 ) .

94

B) Proper loading of the H82C54 chip (U6).

C) Proper counting within the H82C54 and proper

sequencing between the three counters.

D) Proper frequency division by the two CDP1863

(U4,U5).

E) Proper operation of all associated logic

circuitry.

If the Coenen board #6 should fail this test, the Engineer

should refer to Chapter III on the theory of operation for

this complex circuitry. Again, for the Author to explain the

trouble shooting procedures for every possible fault

condition possible on this board would be unrealistic.

However, the trouble shooter should follow some basic steps

outlined below when attempting to isolate a fault condition:

1) Turn power off.

2) Disconnect the wires from pins 4,5, and 7 on U8.

Tie the wires that were on pins 5+7 "Low" (ground).

Tie the wire that was on pin 4 "High" (+5 Volts).

Remove the wire from pin 6 on U8 and tie the wire

"Low" (ground).

3) Turn power on, and reset the system.

4) Load U1 with 8-Bits of data by running the short

program #4 which loads U1 and sets (CL24) "High".

(Refer to Chapter IV for programming information.)

9 5

This procedure will enable the trouble shooter to verify

proper operation of Ul, U4, Ull, and U12. Step 2 above

enables U1 and disables U2 and U3. By loading different

8-Bit data words in Ul, the trouble shooter can verify proper

frequency division of the 2MHz clock in vs the clock out.

By tying the wire from pin 4 of U8 "Low" (ground) and

the wire from pin 5 of U8 "High" (+5 Volts), the trouble

shooter has enabled U2 and disabled Ul and U3. The trouble

shooter can then run a short program to load U2 with 8-Bits

of data and set (CL24) "High". This procedure will verify

proper operation of U2, U4, U5, U9, Ull, and U12. By

programming different 8-Bit data words into U2, the trouble

shooter can verify proper frequency division of the input

2MHz clock vs the output clock.

Again, the trouble shooter can verify the proper

operation of U3 by tying the wire from pin 7 of U8 "High" (+5

Volts) and the wire from pin 5 of U8 "Low" (ground), thus

enabling U3. Running a short program which loads U3 with

8-Bits of data and setting (CL24) "High" will enable the

trouble shooter to verify the proper operation of U3, U4, U5,

U9, Ull, and U12.

If the trouble shooter discovers a fault by the

procedures outlined above for the checkout of Ul, U2, or U3

then he must verify proper loading of Ul, U2, and U3. This

96

would be done by running the short program #4 which loops

indefinitely and sends out the same 8-Bit data word to Ul,

U2, or U3. While the program is running, the trouble shooter

may check all timing as shown in Figure 21 for loading Ul,

U2, and U3.

The trouble shooter may enable Ul, U2, or U3 by tying

one of the wires from U8 pins 4, 5, or 7 respectively "High".

Note: Only one of the three chips Ul, U2, or U3 may be

enabled at one time or a burn out may occur! This enabling

of Ul, U2, or U3 lets the trouble shooter verify the loaded

data within the chip.

If the trouble shooter does not find any faults with

the above procedures then the fault may reside in U6, Ull,

U7, or U8. It is suggested that the trouble shooter connect

the wires back up to U8 pins 4, 5, and 7 as shown on the

schematic Figure 11 and run the short program #5 to load U6

and loop indefinitely. See Chapter IV on programming. The

trouble shooter should verify proper timing as shown in

Figure 22 while the program is running. If the timing

appears to be correct, the trouble shooter should verify

proper operation of U7 and U8. U7 is wired to form a modular

II counter and U8 is a 2 to 4 decoder.

CHAPTER VI

CONCLUSIONS AND RECOMMENDATIONS

The complete testing of the portable system could

not be performed since the application software would be

developed on another thesis. The application software will

be very complex and lengthy depending on the type of tests

Dr. Gensler wishes to be performed. The entire system is

under complete control of the software and was designed to be

very flexible. Thousands of software versions could be

written to perform a specific test. The intent of my

research was to complete the hardware design to the extent

that from a system point of view the Coulostatic Impulse

Generator would perform as required with the maximum

flexibility possible. Utility software was written and

checked out for each of the circuit boards. This utility

software can be used as the building blocks for the

application software and/or self testing the individual

circuit boards. The Programmable Pulse Train Generator was

designed to generate accurate time delays for the sampling

rate of the A/D Converter. Hence, the 1806A microprocessor

need not keep track of "real" time. This simplifies the

9 7

98

application software extremely. However to load the

Programmable Pulse Train Generator requires about one hundred

lines of code. The utility software found in Chapter IV is

only the beginning. I manually entered the code via the NEC

terminal and ran it for checkout. In the future, the large

application software for the field would be burned in a PROM

or EPROM. The application software should be first tested on

a resistive circuit between the probes in the lab before

taking it out to the field.

Using the utility software I developed during

checkout indicated that the following design criteria were

met:

1) The system was able to generate a positive or

negative Coulostatic Impulse to the probes.

2) The system was capable of performing an analog to

digital conversion and storing the data in memory.

3) The Programmable Pulse Train Generator was proven

to be functional and was successfully programmed

by the 1806A microprocessor.

In the interest of future study, Dr. Shier had

suggested a possible alternate design to the Programmable

Pulse Train Generator (Circuit board #6). Referring to

9 9

Figure 17, Dr. Shier indicated that the two CDP1863

programmable divide down chips, used in cascade, gives us

only 128 possible output frequencies not 256 as previously

expected. This is calculated by the following method:

8-Bits of Resolution = 2® = 256

However, for example, clock out will be the same frequency

for the two 8-Bit combinations = 2F or F2 (Hex). This is

true for 128 combinations, hence;

256/2 = 128 possible output frequencies

If 256 different frequencies were required, an

alternate design would need to be developed. Dr. Shier

suggested using an 8-Bit BCD Up counter whos output would be

compared to either Interval 1(1) data word, or Interval 1(2)

data word, or Interval 1(3) data word depending on which

Interval was running. When the counter runs from (OOHex) to

say Interval 1(1) data word, clock out would be toggled. The

counter would be reset to (OOHex) again and the cycle re-run.

This technique would still utilize the 82C54 for counting

Interval lengths, however, much of the remaining circuitry

would need to be replaced.

Dr Gensler indicated that a range of 128 possible

frequencies would be more than adequate at this point in

time. However, this new approach would be considered if the

128 frequencies proved to be inadequate.

REFERENCES

1. W. Gensler, "An Electrochemical Instrumentation System for Agriculture and the Plant Science." Journal of the Electrochemical Society, Vol. 127, No. 11 November 1980.

2. A. Goldstein and W. Gensler, "Bioelectrochemistry and Bioenergergetics," Journal of the Electrochemical Society.

3. F. Silva-Diaz and W. Gensler, "In Vivo Cyclic Voltammetry in Cotton Under Field Conditions," Journal of the Electrochemical Society, Vol. 130 NO. 7 July 1983.

4. E. Ledezma-Razcon, "Modeling of the Bioelectric System Formed by Palladium and Carbon Electrodes Inserter in Cotton Plants," M.S. Thesis, 1984.

5. B. Kim, "Multi-Step Electrochemical Impulse Generator and Potential Monitoring System," M.S. Thesis, 1985.

6. W. Gensler, Personal Communique, Associate Professor, Department of Electrical and Computer Engineering, University of Arizona, Tucson, Arizona, 1984.

7. RCA, CMOS-LSI DATA BOOK, (USA, RCA, 1982) Thom Luke Sales, Inc. Scottsdale, Arizona, pp. 271-276.

8. RCA, RCA Microboard Computer CDP18S601A Handbook, (USA, RCA, 1980) pp. 1-15.

9. RCA, COS/MOS Integrated Circuits, (USA, RCA, 1980) pp. 82-85, pp. 344-348.

10. Motorola, CMOS Data Book, (USA, Motorola, 1978) Chap. 7, p. 159, pp. 371-375.

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REFERENCES(continued)

11. Harris, CMOS Data Book, (USA, 1984) Chap. 3, pp. 27-42.

12. Bruce Kim, Personal Communique, Electrical Engineering Graduate Student, University of Arizona, Tucson, Arizona, 1985.

MULTI-STEP COULOSTATIC IMPULSE GENERATOR AND …...the Generator is to determine the electrochemical constituents of the plant apoplast electrolyte. •The objective of this thesis

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