Mukherjee Part1

7/29/2019 Mukherjee Part1

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Janusz Rajski

Nilanjan Mukherjee

Mentor Graphics Corporation


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Presenters: Janusz RajskiNilanjan MukherjeeMentor Graphics [email protected]

Co-author:Jerzy Tyszer Poznan Univ. of Technology

Presenters and authors


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Tutorial ground rules

Definition: Embedded Test refers to design-for-

testability techniques where testing isaccomplished entirely or partially through on-chiphardware.

Disclaimer:

This tutorial is not intended to endorse ordiscredit any commercial technology or product.


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Audience

Designers of complex integrated circuits

IP core providers and integrators Test engineers

EDA tools developers

EDA tools users Researchers

Project managers

Everybody interested in state-of-the-art embedded test

technology, to reduce the cost of manufacturing test

In particular:


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Tutorial objectives

To present:

Compelling reasons for ET adoption Common barriers for ET adoption

State-of-the-art ET fundamentals and practice

Architectures for logic and memory BIST Embedded deterministic techniques

At-speed ET

multiple-clock domain designs

multi-frequency designs

Tools for BIST synthesis automation

Application examples and case studies


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Outline

Introduction

Embedded stimuli generators

Compactors of test responses

Logic BIST

Deterministic forms of embedded test Embedded at-speed test

Comparison of scan/ATPG, logic BIST andembedded forms of deterministic test

BIST schemes for embedded memory arrays

Summary of embedded test


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Design characteristics

CPU core

Memory

ASIC

ASIC

ASIC

PLL

IP core

DSP core

Memory

IP core

Memory

Memory

Memory

ASIC

AnalogI / 0


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System on Chip characteristics

CPU core

Memory

ASIC

ASIC

ASIC

PLL

IP core

DSP core

Memory

IP core

Memory

Memory

Memory

ASIC

AnalogI / 0

System architecture

Microprocessors, DSP cores Buses, peripherals, memory

ASIC portion

Structures: Logic, memory, analog

Multiple embedded memories:

DRAM, Flash, CAM

Analog and mixed signal: PLLs,clock recovery

Field programmable logic

RF cores: wireless receivers IP cores and reusable blocks

available from multiple vendors

Design efficiency achieved byhierarchical core-based design style


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New defects

Geometries shrink at 30% every three years

Defect sizes do not shrink in proportion

Increase of wiring levels from 6 to 9

Interconnect delays dominate

Gate delays reduced Bridging faults


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[Sematech, 1998]

Sematech S-121

Test Method Evaluation Key Findings &

Conclusions

Objective:

Evaluate various test methodologies Large sample size

Extensive data collection & analysis


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Sematech S-121

Device 116K equivalent gates

0.45 m L effective (0.8 m drawn) 50 MHz operating speed

249 signal I/Os

3 metal levels

Full LSSD Scan plus JTAG boundary scan 8 Chains, 5,280 master/slave LSSD latches (10,560

total latches)

Sample size 20,000 units

Test methods: Stuck-at faults, Functional tests, Transition delay

faults & IDDQ


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Sematech S-121

SAF - 99.5% co verage

(8300 patt erns )

FUNC - 52% SAF coverage

(532K cy cles)

IDDQ - >96% pseudo SAF coverage(195 patterns )

Delay - 90% Trans it ion co verage

(15232 patt erns )

IDDQ1463

FUNC6

78

1 1251

13

SAF6

0 52

Delay 14

34

36

FUNC

IDDQ

1

Package test results(pre Burn-in)


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S-121 Conclusions

All test methods detected unique defects

Near 100% SAF coverage missed many defects

Large defect coverage overlap between SAF & Delay

SAF are a subset of Transition faults

IDDQ threshold setting significantly affects yield 98% of the IDDQ fails survived burn-in

Many (bridging) defects detected only by IDDQ

But diminishing IDDQ effectiveness in DSM

Some Functional tests are still required

Opportunity to optimize test coverage levels & capital


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BridgeM1-2

Bridge M2

Bridge M4

Break trans

Bridge Poly M2

Bridge M3

Bridge M1-3

Bridge poly M1

Bridge M3-4

Open Poly

Open Contact

Bridge M1

Unknown Br

Break M3Bridge Poly M2

Break M2

Bridge M3-4

Break M1

Bridge Poly M4

Bridge Poly

Unknown

Via break

Defect Pareto 350 nm

Al4-5 Levels

Oxide

Dielectric

W Plugs

350 nm Process 5 million Transistors

A Transistor

Process Shrinks vs. Defect Types


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Defect distribution changewith process

100 nm Process -- 250 million transistors

A Transistor

Cu

(8 Levels)

Low-K

Dielectric

CuPlugs

Unknown

Defect Pareto 100 nm

?

Process Shrinks vs. Defect Types


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Defects vs. Fault Coverage

[M. Rodgers , et. al. DAC 2000]

1 10 100 1000 K-Ohms

.18 um

.25 um

Test chip FA results

Increasing defect populations causingmore VDD, Temp, & freq sensitive device fails

Bridge Defect Observed Resistance

Wired AND & OR models

are not sufficientSpeed limiting defects

Frequency of bridging defectsis increasing

Need to drive ATE & modelingrequirements from the defectsto be detected

Will drive need for more scan

vectors


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Quality requirements

Y 1 - Y

p

1 - p

Faultsdetected

Escapes


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Quality requirements

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

0.01

0.990 0.991 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000

p

Yield = 0.1

Yield = 0.9

Escapes = (1 - Y)(1 - p)


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Fault models

Stuck-at-0 and stuck-at-1

Transitions

Path delay

Multiple detectsVDD


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Very high test quality

Very high fault coverage

Wide range of fault models

stuck-at

transition

path delay at-speed testing

multiple detects

bridging

defect based cross-talk effects

... fading IDDQ

Coverage

Escapes


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High-performance MPU/ASIC gate count

0

50

100

150

200

250

300

2001 2002 2003 2004 2005 2006 2007

ITRS Roadmap 2001

Gate count


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Scan chains

The pattern count for transition faults may reach 20,000


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Scan test

ATE

Sca

n

input

channels

Primary outputs

Scan

output

cha

nnels

Primary inputs


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ATE cost

Tester cost = b + S m p

b - base cost (zero pins)

m - incremental cost per pin

p - number of pins

High performanceASIC / MPU

DFT tester

Low performanceMicrocontroller

250 - 400

100 - 350

200 - 350

2700 - 6000

150 - 650

1200 - 2500

512

512 - 2500

256 - 1024

b [ K$ ] m [ $ ] p

Test cost can be

$0.05/second


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Volume of scan test data

Test cycles = PatternsScan cellsScan chains

...


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Scan test time

Test time = Scan cellsScan chains

...

FrequencyPatterns


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Scan test cost

Shift frequency 20 MHz

Gate count 10M

Scan chains 32

Padding ratio 1.4

Scan patterns 20K

Vector memory 64MV

Reload penalty 2s

Insertions 4

Tester rate 0.05$

Scan cells500,000

Cells per scan15,625

Longest scan chain21,875

Cycles437.5M

Scan test time21.9s

Passes6

Reload time12.0s

Time pre device87.5s

Cost per device4.4$

More
http://localhost/var/www/apps/conversion/ITC2002_tut/Scan%20test%20cost.xlshttp://localhost/var/www/apps/conversion/ITC2002_tut/Scan%20test%20cost.xlshttp://localhost/var/www/apps/conversion/ITC2002_tut/Scan%20test%20cost.xls


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High-performance MPU/ASIC

0

2

4

6

8

10

12

2001 2002 2003 2004 2005 2006 2007

32 channels

20,000 patterns

Required ATE memory

Gigabits/channel


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High-performance MPU/ASIC

0

20

40

60

80

100

120

2001 2002 2003 2004 2005 2006 2007

100 MHz scan shift

Scan test time

seconds


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ATE accuracy vs. device speed

Tester accuracy will improve from 200 ps to 175 ps by 2012

Clock period will decrease to 330 ps Margin of error for ATE approaches 50% clock period

0

100

200

300

400

500

600

2001 2002 2003 2004 2005 2006 2007

Device period

ATE accuracy

Accuracyrequired


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Requirements for Embedded Test

Increasing device complexity, operating speed,

and new fault models stress conventional scanbased test:

Exploding volume of test data

Increasing scan test time, and

Escalating scan test cost

Embedded Test is required to:

Generate most of the test data on-chip

Compacting test responses on-chip, and Providing on-chip control for at-speed test


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Very low cost

Dramatically reduced volume of test data (10-100X)

Dramatically reduced scan test time (10-400X)

ATE Memory

[Mvectors]

0

5

10

15

20

25

30

35

0 1 2 3 4 5 6 7

10X

10X

Scan test time[s]

2M gatesScan/ATPG

16 scan chains

5k vectors

2s handler/index time

1 test

10MHz scan shift


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Long term scalability

0.1

1

10

10 0

0 1.5 3 4.5 6 7.5 9 10.5

100X increasein 10 years!

Volume inconventional DFT

years


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0.1

1

10

10 0

0 1.5 3 4.5 6 7.5 9 10.5

Radical compression is required!

Immediate 5-10Xcompression

Compressionahead of volume

for 10 yearsVolume in

conventional DFT

Compression factor

years


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0.1

1

10

10 0

0 1.5 3 4.5 6 7.5 9 10.5

Radical compression is required

Compressionshould beahead ofMoores law for

10 years!Volume in

conventional DFT

Compression factor

Compressedvolume

years

Mukherjee Part1

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