M.Tech. (VLSI Design) Curriculum & Syllabi (AY 2009-10 onwards).doc

M.Tech. VLSI Design Curriculum

(2009 - 10 onwards)

University Core Course Code Course Title L T P C

EEE 609 Computational Techniques 3 1 0 4ENG

-601 -

Professional and Communication Skills (or)Foreign Language

0 2

0 0

4 0

22

EEE 698 Seminar ‐ ‐ ‐ 1

Total credits 07

University ElectiveCourse Code Course Title L T P C

University Elective 3 0 0 3

Total credits 03

Programme Core Course Code Course Title L T P CEEE 587 Physics and Modeling of Semiconductor Devices 3 0 0 3EEE 588 Digital IC Design 3 0 0 3EEE 589 Analog IC Design 3 0 0 3EEE 591 VLSI Digital Signal Processing 3 0 0 3EEE 596 ASIC Design 3 0 0 3EEE 600 VLSI Design Verification and Testing 3 0 0 3EEE 540 Embedded System Design 3 0 0 3EEE 598 Computer Aided Design for VLSI 3 0 0 3EEE 610 Custom IC Design Lab 0 0 2 1EEE 611 ASIC Design Lab 0 0 2 1EEE 612 VLSI Digital Signal Processing Lab 0 0 2 1EEE 613 Embedded System Design Lab 0 0 2 1EEE 699 Student Project ‐ ‐ ‐ 20

Total credits 48

Programme Elective Credits to be taken: 15

Course Code Course Title L T P C

EEE 597 Low Power IC Design 3 0 0 3EEE 599 Mixed Signal IC Design 3 0 0 3EEE 601 Memory Design and Testing 3 0 0 3EEE 602 Hardware / Software Co Design‐ 3 0 0 3EEE 603 Advanced Computer Architecture 3 0 0 3EEE 604 Scripting Languages for VLSI Design Automation 3 0 0 3EEE 605 Fault Tolerant‐ and Dependable Systems 3 0 0 3EEE 590 IC Technology 3 0 0 3

Packaging and Interconnect Analysis 3 0 0 3 RFIC Design 3 0 0 3 Reconfigurable Computing 3 0 0 3 DSP Architectures 3 0 0 3

Electromagnetic Interference and Compatibility in Electronic System Design 3 0 0 3 Nanoelectronics 3 0 0 3 Image Processing and Compression Techniques 3 0 0 3 Micro Electro Mechanical System 3 0 0 3 Single Electronics Device Applications and Modeling 3 0 0 3

System-On Chip Design 3 0 0 3

Programme Elective instead of University Elective can be taken

Credit Summary Minimum Qualifying credits 73

Total credits Offered (UC+PC+PE) 73

University Core 7

University Elective 3

Programme Core Offered 48

Programme E lective 15

UC – University Core PC – Programme Core PE – Programme Elective UE – University Elective

M.Tech. VLSI Design – Courses Offered – 200809 onwards

No. Course Code Course Title L T P C Course Offered by

SyllabusVersion

AC approval Date

Course Type

397 EEE 609 Computational Techniques 3 1 0 4 SSH 1.00 18AC UC 368 EEE 587 Physics and Modeling of Semiconductor Devices 3 0 0 3 SES 1.10 18AC PC 369 EEE 588 Digital IC Design 3 0 0 3 SES 1.10 18AC PC 370 EEE 589 Analog IC Design 3 0 0 3 SES 1.00 16AC PC 371 EEE 590 IC Technology 3 0 0 3 SES 1.00 16AC PE372 EEE 591 VLSI Digital Signal Processing 3 0 0 3 SES 1.10 18AC PC 398 EEE 610 Custom IC Design Lab 0 0 2 1 SES 1.00 18AC PC 399 EEE 611 ASIC Design Lab 0 0 2 1 SES 1.00 18AC PC 400 EEE 612 VLSI Digital Signal Processing Lab 0 0 2 1 SES 1.00 18AC PC 401 EEE 613 Embedded System Design Lab 0 0 2 1 SES 1.00 18AC PC 46 ENG 601 Professional and Communication Skills 0 0 4 2 SSH 1.00 15AC UC

232 EEE 698 Seminar ‐ ‐ ‐ 1 SES 1.00 16AC UC 233 EEE 699 Student Project - - - 20 SES 1.00 16AC UC 383 EEE 596 ASIC Design 3 0 0 3 SES 1.10 18AC PC384 EEE 597 Low Power IC Design 3 0 0 3 SES 1.00 16AC PE 385 EEE 598 Computer Aided Design for VLSI 3 0 0 3 SES 1.10 18AC PC386 EEE 599 Mixed Signal IC Design 3 0 0 3 SES 1.00 16AC PE 387 EEE 600 VLSI Design Verification and Testing 3 0 0 3 SES 1.10 18AC PC388 EEE 601 Memory Design and Testing 3 0 0 3 SES 1.00 16AC PE 389 EEE 602 Hardware / Software Co Design‐ 3 0 0 3 SES 1.00 16AC PE 390 EEE 603 Advanced Computer Architecture 3 0 0 3 SES 1.00 16AC PE 391 EEE 604 Scripting Languages for VLSI Design Automation 3 0 0 3 SES 1.10 18AC PE 392 EEE 605 Fault Tolerant‐ and Dependable Systems 3 0 0 3 SES 1.00 16AC PE 261 EEE 540 Embedded System Design 3 0 0 3 SES 1.00 16AC PE Packaging and Interconnect Analysis 3 0 0 3 SES 1.00 16AC PE RFIC Design 3 0 0 3 SES 1.00 16AC PE Reconfigurable Computing 3 0 0 3 SES 1.00 16AC PE DSP Architectures 3 0 0 3 SES 1.10 18AC PE

Electromagnetic Interference and Compatibility in Electronic System Design

3 0 0 3 SES 1.00 16AC PE

Nanoelectronics 3 0 0 3 SES 1.00 16AC PE Image Processing and Compression Techniques 3 0 0 3 SES 1.00 16AC PE Micro Electro Mechanical System 3 0 0 3 SES 1.00 16AC PE Single Electronics Device Applications and Model

ing 3 0 0 3 SES 1.00 16AC PE

System-On-Chip Design 3 0 0 3 SES 1.00 PE

Credit Summary

Minimum Qualifying credits 73

Total credits Offered (UC+PC+PE+UE) 73

UC 07

PC Offered 48

PE Needed 15

UE 3

UC – University Core PC – Programme Core PE – Programme Elective UE –University Elective

Students admitted during 2009-2010

PHYSICS AND MODELING OF SEMICONDUCTOR DEVICESL T P C3 0 0 3

Course Objectives: This course will help the students acquire a deep understanding of modeling FET devices which plays an important role in fabrication of integrated circuits. This is likely the most advanced course on this topic that students will encounter. It should prepare students for research or development of device technology or digital or analog circuits for many years to come. Course Outcomes: A student completing this course will be able to

Explain and apply the semiconductor concepts of drift, diffusion, donors and acceptors, majority and minority carriers, excess carriers, low level injection, minority carrier lifetime, quasi-neutrality, and quasi-statics;

Explain the underlying physics and principles of operation of p-n junction diodes, metal-oxide-semiconductor (MOS) capacitors, bipolar junction transistors (BJTs), and MOS field effect transistors (MOSFETs), and describe and apply simple large signal circuit models for these devices which include charge storage elements.

Semiconductor Physics:Metals, insulator, semiconductors, intrinsic and extrinsic semiconductors, direct and indirect band gap, free carrier densities, Fermi distribution, density of states, Boltzmann statistics, thermal equilibrium, current flow mechanisms, drift current, diffusion current, mobility, band gap narrowing, resistance, generation and recombination, lifetime, internal electro-static fields and potentials, Poisson’s equation, continuity equations, drift-diffusion equations.PN-Junction Diodes: Thermal equilibrium physics, energy band diagrams, space charge layers, internal electro-static fields and potentials, reverse biased diode physics, junction capacitance, wide and narrow diodes, transient behavior, transit time, diffusion capacitance, small signal model.Bipolar Transistors: Basic theory and operation, heavy doping effects, double diffused transistors, Ebers-Moll model, low forward bias, junction and diffusion capacitance, transit times, parasitic, small-signal models, Early effect, saturation and inverse operation, breakdown mechanisms, punch-through.MOS Transistors MOS capacitor, accumulation, depletion, strong inversion, threshold voltage, contact potential, oxide and interface charges, body effect, drain current, saturation voltage, gate work function, channel mobility, sub-threshold conduction, short channel effects, effective channel length, effects of channel length and width on threshold voltage, Compact models for MOSFET and their implementation in SPICE. Level 1, 2 and 3, MOS model parameters in SPICE. UDSM Transistor Design Issues Short channel and ultra short channel effects; Effect tox , effect of high k and low k dielectrics on the gate leakage and Source –drain leakage; tunneling effects; different gate structures in UDSM - impact and reliability challenges in UDSM.Text Books:

1.Y.P. Tsividis, The MOS Transistor, McGraw-Hill, international edition ed., 1988.2.S.M.Sze, Semiconductor Devices Physics and Technology, John Wiley & Sons Inc, (2/e).

References:1.Getreu, Modeling the bipolar transistor, New York, NY: Elselvier, 1978.2.D. Roulston, Bipolar Semiconductor Devices, McGraw Hill, 1990.3.N. Arora, MOSFET Models for VLSI Circuit Simulation, Springer-Verlag, 1993.4.P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE, McGraw-Hill, 1988.5. D.W. Greve, Field Effect Devices and Applications, Prentice Hall Series in Electronics and VLSI, 1998


DIGITAL IC DESIGNL T P C3 0 0 3

Course Objective: This course is preparatory for study in the field of Very Large Scale Integrated (VLSI) digital circuits and engineering practice. The course focuses upon the systematic analysis and design of basic digital integrated circuits in CMOS technology. Problem solving and creative circuit design techniques are emphasized throughout. This course provides the foundation for subsequent courses in the design of digital integrated circuits and systems. Basic principles, methodologies, and ad-hoc analysis and design techniques are emphasized.Course Outcomes: After completion of this course the students will be familiar with modern VLSI circuits and will be able to design most of them.

Introduction Issues in Digital IC Design. Quality Metrics of a Digital Design. MOS Transistor. Manufacturing CMOS Integrated Circuits. Design Rules. Layouts. The CMOS inverterStatic CMOS Inverter: Static and Dynamic Behavior Practices of CMOS Inverter. Components of Energy and Power: Switching, Short-Circuit and Leakage Components. Technology scaling and its impact on the inverter metrics. CMOS Combinational Logic Circuit DesignStatic CMOS Design: Complementary CMOS, Ratioed Logic, Pass Transistor Logic. Dynamic CMOS Design: Dynamic Logic Design Considerations. Speed and Power Dissipation of Dynamic logic, Signal integrity issues, Cascading Dynamic gates. CMOS Sequential Logic Circuit DesignIntroduction. Static Latches and Registers. Dynamic Latches and Registers. Pulse Based Registers. Sense Amplifier based registers. Latch vs. Register- based pipelines structures.Interconnect and Timing Issues Interconnects: Resistive, Capacitive and Inductive Parasitics. Computation of R, L and C for given inter-connects. Buffer Chains. Timing Issues: Timing classification of digital systems. Synchronous Design - Origins of Clock Skew/Jitter and Impact on Performance. Clock Distribution Techniques. Latch based clocking. Synchronizers and Arbiters. Clock Synthesis and Synchronization using a Phase-Locked Loop.

Text Books: 1. Jan M.Rabaey, Anantha Chadrakasan, Borivoje Nikolic, “Digital Integrated Circuits: A

Design Perspective”, (2/e), PHI.20052. Neil.H.E.Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design: A Circuit and Systems

Perspective”, (3/e). Pearson Education. 2006.References:1. David A Hodges, Horace G Jackson and Resve A Saleh, “Analysis and Design of Digital

Integrated Circuits in Deep Submicron Technology” TMH.20052. Sung-Mo Kang, Yusuf Leblebicii, “ CMOS Digital Integrated Circuits- Analysis and Design”

McGraw-Hill International Edition.


ANALOG IC DESIGNL T P C3 0 0 3

Objective:To design analog IC components and building blocks in CMOS technology. To understand the relationships between devices, circuits and systems. Emphasize the design of practical amplifiers, small systems and their design parameter trade-offs.Course outcomes:A student who successfully fulfills the course requirements will have demonstrated:

an ability to analyze bias circuit using CMOS current mirror. an ability to design feedback and differential operational amplifier. an ability to analyze stability of operational amplifiers an ability to apply frequency compensation techniques for Amplifiers an ability to analyze basic operation of PLL.

Current source and Amplifier design:MOS Device models, MOS Current Sources and Sinks, Current Mirror: Basic Current Mirrors, Cascode current Mirrors. Current and Voltage Reference circuits. Single stage Amplifies: Basic concepts, Common source stage, Common gate stage, Cascode stage. Differential stage: Single ended and differential operation. Basic Differential Pair.Feedback AmplifiersIdeal feedback equation, Gain sensitivity, Effect of Negative Feedback on Distortion, Types of Amplifiers. Feedback configurations: voltage-voltage, current-voltage, current-current, voltage-current feedback. Practical configurations and Effect of loading.Frequency response of AmplifiersMiller effect, Frequency response of Common source stage, Common gate stage, Cascode stage and Differential pair. Noise in single stage Amplifiers: Common source stage, Common gate stage, Cascode stage. Differential pair, Noise Bandwidth.Operational AmplifierDifferential and common mode circuits, Op Amp CMRR requirements, Need for single and multistage amplifiers, Effect of loading in differential stage. Performance Analysis: dc gain, frequency response, noise, mismatch, slew rate of cascode and two stage OP Amps, Fully Differential Op Amps- Common-Mode feedback, loop stability.Stability analysis and Frequency compensationStability of Feedback: Basic Concepts, Instability and the Nyquist Criterion, Stability Study for a Frequency-Selective Feedback Network, Root Locus: Effect of Pole Locations on Stability, multipole systems.Frequency Compensation: Concepts and Techniques for Frequency Compensation – Dominant pole, Miller Compensation, Compensation of Miller RHP Zero, Nested Miller, Compensation of two stage OP Amps.Phase Locked LoopsProblem of Lock acquisition, Phase Detector, Basic PLL and its dynamics, Charge-pump PLL, Non-ideal effects in PLL: PFD/CL non idealities, Jitter, Delay Locked Loop, Applications.Text Books:

1. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill, 2000.2. Gray, Hurst, Lewis, and Meyer: “Analysis and design of Analog Integrated Circuits”, (4/e), John

Wiley and SonsReferences:

1. Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design”, (Second Edition) Oxford University Press, February 2002.

2. David Johns and Ken Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, Inc., 1997


ASIC DESIGNL T P C3 0 0 3

Objective of the Course: To study the issues relating to the design of application-specific integrated circuits (ASICS) for digital systems.Course OutcomesAfter completion of this course

Students will be able to design and synthesize a complex digital functional block using Verilog HDL.

Students will demonstrate an understanding of how to optimize the performance, area, and power of a complex digital functional block, and the tradeoffs between these.

Students will demonstrate an understanding of issues involved in ASIC design, including technology choice, Timing analysis, tool-flow, testability.

IntroductionImplementation Strategies for Digital ICs: Custom IC Design, Cell-based Design Methodology. Array based implementation approaches. Traditional and Physical Compiler based ASIC Flow. Digital ASIC Design using Verilog HDLVerilog HDL: Levels of Abstraction, Hierarchical modeling and Delay modeling, Verilog constructs, FSM, Memory modeling. Complex Digital System Design Examples. RTL Simulation and SynthesisFunctional Simulation: Testbench Wrappers. Event-based Simulation: Event-based Simulation. Cycle-based Simulation. RTL Synthesis: An overview of the synthesis based ASIC design flow. Synthesis Environment. technology library: technology libraries, logic library basics, delay calculations. Partitioning and Coding Styles: Partitioning for synthesis, Coding guideline for synthesis. Logic Inference: Order dependence. Optimization and mapping constraints (clock, delay, area, design). Instantiating special operators and black boxes. FSM synthesis, Performance-driven synthesis.Static Timing Analysis Overview of timing verification and static timing analysis. Critical path. Timing exceptions. Multicycle paths, false paths, and timing constraints (such as setup, hold, recovery, and pulse width). Practical usage of timing analysis. Design for TestabilityTypes of DFT. Scan Insertion. Design Rules, DFT guidelines. Built-in-Self-Test(BIST):Test pattern Generation – Exhaustive , Pseudo Random , Pseudo Exhaustive , Output Response Analysis , Logic BIST architectures – With and without scan chains , Register Reconfiguration , Boundary Scan and core testing.Text Books:

1. T.R.Padmanabhan, B.Bala Tripura Sundari, “Design through Verilog HDL” Wiley Interscience, 2004.2. Himanshu. Bhatnagar, “Advanced ASIC Chip Synthesis” (2/e).KAP.20023. Farzad Nekoogar, “Timing Verification of Application-Specific Integrated Circuits” Farzad

Nekoogar, Prentice-Hall. 19994. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing for Digital, Memory and Mixed-

Signal VLSI Circuits", KAP, 2000References:

1. Donald E. Thomas, Philip R. Moorby, “The Verilog® Hardware Description Language” (5/e) KAP. 2002

2. Maheshwari, Naresh, Sapatnekar, S “Timing Analysis and Optimization of Sequential Circuits”. 1998, Springer. ISBN: 978-0-7923-8321-5

3. Prime Time user guide


VLSI DIGITAL SIGNAL PROCESSINGL T P C3 0 0 3

Objective of the Course: The objective of this course is to provide students, reviews of various DSP algorithms and addresses their representation, and high-level architectural transformations and design of algorithm structures for various DSP algorithms based on algorithm transformations.Course Ourcomes: Students understand the issues and methods associated with the sampling of continuous time

signals Students can able to understand the finite world length effects and design redundant arithmatic

structures. Students can able to understand the the algoithmic-architecture transoformation at higher level. Able to understand the pipelines techniques and programable DSP Processors.

Introduction TO Digital Signal ProcessingIntroduction, A Digital signal-processing system, The sampling process, Discrete time sequences. Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear time-invariant systems, Digital filters : Realization of FIR and IIR systems, finite word length effects Scaling and Round off noise.

Implementation of Arithmetic architecturesBit Level Arithmetic Architectures: Parallel Multipliers, Interleaved Floor-plan and Bit-plan based Digital Filters, Bit-Serial Multipliers, Bit Serial Filter Design and Implementation, Canonic Signed Digit Arithmetic, Distributed Arithmetic.

Redundant Arithmetic: Redundant Number Representations, Carry-Free Radix-2 Addition and Subtraction. Hybrid Radix-4 Addition, Radix-2 Hybrid Redundant Multiplication Architectures, Data Format Conversion-Redundant to Non-Redundant Converter

Numerical Strength Reduction : Sub-Expression Elimination, Multiple Constant Multiplication, Sub-Expression Sharing in Digital Filters, Additive and Multiplicative Number Splitting.

Architecture and Algorithm Transformations Data flow graph representation, Iteration bounds Algorithms for computing Iteration bound, Retiming. Unfolding. Folding. Algorithmic strength reduction in filters and transforms. Fast convolution.

Reference Books:1. Emmanuel C. Ifeachor, Barrie W. Jervis, “Digital signal processing-A practical approach”,

Second edition, Pearson education, Asia 2001.2. Keshab K.Parhi, “VLSI Digital Signal Processing Systems: Design and

Implementation”,Wiley, Inter Science, 1999. 3. J. Proakis and D. Manolakis, “Digital Signal Processing” PHI4. Gary Yeap, “Practical Low Power Digital VLSI Design”, Kluwer Academic Publishers, 1998.5. Mohammed Ismail and Terri Fiez, “Analog VLSI Signal and Information Processing” Mc

Graw-Hill, 1994.6. S.Y. Kung, H.J. White House, T. Kailath, “VLSI and Modern Signal Processing”, PHI


COMPUTER AIDED DESIGN FOR VLSIL T P C3 0 0 3

Course Objectives: This course reviews the major components of the modern computer-aided circuit design flow. An important motivation for the course is to explore the directions in which computer-aided circuit design evolves as it copes with the challenges brought about by the increased complexity of deep submicron silicon technology. Course Outcomes:After the completion this course the students shall be able to

Understand the techniques and algorithms for physical and logic-level design automation. Explain the optimization methods contemplate various performances such as silicon area, timing,

power consumption, and crosstalk.Prerequisite to study the course:Digital Design, Basic graph theory concepts, Data structure.Introduction Y Chart, Physical design top-down flow. Design styles: Full Custom, Standard Cell, Gate Arrays, Field Programmable Gate Arrays, Sea of Gates.Logic Synthesis and Technology MappingComputer-aided synthesis and optimization, Introduction to Combinational logic synthesis – Binary decision diagrams (BDD): Principles, Implementations and Construction, Manipulation, Variable ordering. Two-level and multi-level logic optimizations. Sequential logic optimization.Algorithms for Physical Design AutomationPartitioning: Problem formulation, Group Migration Algorithms – Kernighan-Lin, Fiduccia-Mattheyses algorithm, Performance driven Partitioning. Floor Planning: Problem Formulation, Integer Programming, Rectangular dualization, Simulated Annealing based floorplanning. Placement: Breuer’s algorithm, Cluster Growth approach, Sequence pair technique.Pin Assignment: General pin assignment, Channel pin assignment. Routing: Global routing: Problem formulation, Maze routing, Line Probe algorithms, Weighted Steiner tree approach.Detailed routing: Problem formulation, Two layer channel routing – Left Edge algorithm, Dogleg router, Net Merge channel router, Three-layer channel routing – HVH, VHV router. Introduction to switch box routing.Over the Cell Routing: Two layer Over-the-cell routers.Clock routing: Clocking schemes, Exact Zero skew algorithm. Power and Ground routingCompaction: Problem formulation, One dimensional Compaction – Constraint graph based, Virtual Grid based compaction, Two dimensional compaction, Hierarchical compaction.Timing AnalysisStatic and Dynamic timing analysis for single and multiple path data flows. Compensation techniques. Critical path delays. Back annotation.Text Books:

1. Naveed Sherwani , “Algorithms for VLSI Physical design automation”, 3e, Springer International edition, 2005.

2. Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, 1st edition, McGraw-Hill, 19943. H. Yosuff and S.M. Sait, “VLSI Physical Design Automation – Theory and Practice”, McGraw Hill

publication, 1995. Reference Books:

1. Sung Kyu Lim, “Practical Problems in VLSI Physical Design Automation” Springer. 20082. Michael John Sebastian Smith, “Application Specific Integrated Circuits”, Pearson Education Asia,

2001.3. Sabih. H. Gerez , “ Algorithms for VLSI design Automation”, John Wiley & sons Ltd.,2004. 4. M.Sarrafzadeh, C.K.Wong, “An introduction to VLSI physical design ”,McGraw-Hill international

editions,1996.


EMBEDDED SYSTEM DESIGN

L T P C3 0 0 3

Introduction to Embedded System: An embedded system, processor, hardware unit, soft ware embedded into a system, Example of an embedded system, OS services, Embedded Design life cycle; Modeling embedded systems

Processor and Memory Organization: Structural unit in as processor, processor selection for an embedded systems. Memory devices, memory selection for an embedded system, allocation of memory to program statements and blocks and memory map of a system. Direct memory accesses.

Devices and Buses for Device Networks: I/O devices, serial communication using FC, CAN devices, device drivers, parallel port device driver in a system, serial port device driver in a system, device driver for internal programmable timing devices, interrupt servicing mechanism, V context and periods for switching networked I/O devices using ISA, PCI deadline and interrupt latency and advanced buses.

Programming Concepts and embedded programming in C: Languages, Firmware development environment, Start up code or Boot loader, Abstraction Layers, Application Layer, build download debug process of firmware.

Program Modeling Concepts in Single and Multiprocessor Systems: software development process, modeling process for software analysis before software implementation, programming model for the event controlled or response time constrained real time programs, modeling of multiprocessor system.

Inter-Process Communication and Synchronization of Processors: Tasks and threads; multiple process in an application, problems of sharing data by multiple tasks and routines, inter process communications. RTOS task scheduling models interrupt literacy and response times, performance metric in scheduling models, standardization of RTOS, list of basic functions, synchronization.

Reference Books:

1. Frank Vahid and Tony Givargis,”Embedded System Design: A Unified Hardware/ Software Approach, John Wiley ,2002.

2. Steve Heath , “Embedded Systems Design”, EDN Series ,2003.

3. David E simon,” An Embedded Software Primer”, 1st edition, Addison Wesley 1999.

4. Wayne Wolf “Computers as components: Principles of Embedded Computing System Design The Morgan Kaufmann Series in Computer Architecture and Design, 2008

5. Jane W. S., Liu, “Real time systems”, Pearson Education, 2000.

6. Raj Kamal, “Embedded systems Architecture, Programming and design”, Second Edition, 2008.


VLSI DESIGN VERIFICATION AND TESTINGL T P C3 0 0 3

Course Objective: The objective of this course is to involve the students in the theory and practice of VLSI test and verifications.Course Outcome :

After the course the students will be familiar with the testing and verification methodology of VLSI circuits.

Prerequisite: Undergraduate level Digital Logic Design Course Digital IC Design

Introduction Scope of testing and verification in VLSI design process. Issues in test and verification of complex chips, embedded cores and SOCs.Design Verification TechniquesDesign verification techniques based on simulation, analytical and formal approaches. Functional verification: Timing verification. Formal verification. Physical Verification and Analysis. Basics of equivalence checking and model checking. Hardware emulation.Fault modeling and Test GenerationDefects, Errors, and Faults. Functional Versus Structural Testing. Levels of Fault Models. Single Stuck-at Fault. Testability measures: Controllability and Observability. Fault Simulation: Serial, Parallel, deductive, Concurrent, Differential Simulation. Combinational Test Generations: Random Test generation, Redundancy Identification (RID). ATPG for Combinational Circuits: D-Algorithm, PODEM. Sequential Circuit Test Generations: ATPG for single-clock synchronous circuits, Time-frame expansion model, Designing a Sequential ATPG.Advanced TestingAnalog and Mixed-Signal Circuit Trends. Functional DSP-Based Testing. Static ADC and DAC Testing Methods. Analog Fault Models. Types of Analog Testing. Analog Fault Simulation. IDDQ Test.

Text Books: 1. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing for Digital, Memory and

Mixed-Signal VLSI Circuits", Kluwer Academic Publishers, 20002. Masahiro Fujita, Indradeep Ghosh, Mukul Prasad “Verification Techniques for System-Level

Design” Elsevier.3. Prakash Rashinkar, Peter Paterson, Leena Singh, “System-On-a-ChipVerification

Methodology and Techniques” KLUWER ACADEMIC PUBLISHERS. 2002.References

1. M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable Design", IEEE Press.

2. Michael Keating and Pierre Bricaud, “Reusable Methodology Manual for System-on-a-chip Designs”, 2nd Edition, Kluwer Academic Publishers, 1999.

3. Parag K.Lala, “Fault Tolerant and Fault Testable Hardware Design” BS Publications, 2002


4. Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen , VLSI Test Principles and Architectures: Design for Testability, Elsevier's Science & Technology publishing.

CUSTOM IC DESIGN LABL T P C0 0 2 1

Study of VLSI CAD Tools (Working environment, Introduction to Linux and vi editor, Cadence Virtuoso ADE with Spectre simuulator/Mentor graphics Design Architect with Eldo simulator)

Applying MOS I-V equations and small-signal models to MOS circuits Analyzing switching characteristics and power consumption of the inverter Analyzing and designing complex CMOS gates for speed Designing an inverter chain to drive off-chip loads Design and characterization of various digital blocks (combinational and sequential elements) Physical Design of Analog and Digital cells (layout, DRC,LVS, RCX, Post-layout

simulation) Designing current sources and analyzing differential amplifiers Analysis and design of the CMOS 2-stage and folded-cascode op-amps

Mini-project:Standard cell design

Working on a team to implement a small analog and digital VLSI project Presenting the team project in front of peers

CAD Tools : Cadence, Mentor Graphics.


ASIC DESIGN LABL T P C0 0 2 1

Working with VLSI CAD Tools(like Cadence IUC, RTL Compiler, SoC Encounter, ModelSim etc.)

EDA tools and design kit configuration Design project organization HDL examples Text editing Design flow steps Verilog simulation

Digital System Design using Verilog HDL RTL synthesis

Starting the Design Vision graphical environment RTL model analysis Design elaboration Design environment definition Design constraint definitions Design mapping and optimization Analyze and resolve design problems Report generation VHDL/Verilog gate-level netlist generation and post-synthesis timing data (SDF)

extraction Design constraints generation for placement and routing Design optimization with tighter constraints using scripts

Standard cell placement and routing Starting the Encounter graphical environment Design import Global net connections Operating conditions definition Floorplan Specification Power ring/stripe creation and routing Core cell placement Timing analysis Clock tree synthesis (optional) Design routing Timing analysis Design checks Report generation Post-route timing data extraction Post-route netlist generation GDS2 file generation

Proto-typing of a design using FPGA Design Kit Working on a team to implement a Digital System design project


VLSI DIGITAL SIGNAL PROCESSING LABL T P C0 0 2 1

Simulation Experiments using Matlab.(3 sessions)

1) Generation of Periodic signals using Fourier synthesis Equation.2) Implementation of Fourier Transform for basic finite interval pulses.3) Spectrum analysis of multi tone sinusoidal signal using Discrete Fourier Transform.4) Implementation of FFT radix-2 Algorithms.5) Realization of various structure of FIR and IIR systems using Matlab functions.

Real time experiments using TMS6713 Processor. (3 sessions)

1) Implementation of Digital filters in TMS6713 Processor using C programming in cc-studio for real time processing of audio signals

2) Study of parallel processing and pipeline processing features of TMS6713 Processor.

Simulation Experiment using VHDL/ Verilog.(3 sessions)

1) Behavioral and Dataflow models for adders and multipliers for 8 bit signed 2’s compliment arithmetic.

2) Structural models for FIR filters using direct form realization and Data Broadcast realization.

Mini Projects: Titles on focus:1) Implementation of Optimum multipliers.2) Implementation of redundant Arithmetic units.3) Implementation of FFT processor.4) Implementation of 2D-DCT Processor.5) Implementation Algorithm for retiming for clock minimization.6) Implementation of Optimum Digital filters using sub expression sharing and Canonic signed

digit arithmetic.7) Development of optimum assembly level coding exploiting the parallel processing features of

TMS6713 Processor for signal processing application.8) Study and implementation of CORDIC algorithm for trigonometry functions.9) Study and implementation of Systolic Architectures for Bit serial systems.10) Audio interfacing and basic filtering operation using FPGA.

Note: The student should do a compulsory mini project on above titles. Other related topics can also be selected. The duration for mini project is 3 months from the first day of the laboratory. As a part of the mini project a detailed project report has to be submitted after ompletion

of the project.

EMBEDDED SYSTEM DESIGN LAB


L T P C0 0 2 1

1. Software development tools - Introduction to cross assembler, Linker, Locator and

conversion utility

2. Assembly Language Programming

3. Interface to Switches, LEDs, and 7-segment displays

4. Interface to a Hexadecimal Keypad

5. Writing programs to perform user output to the LCD

6. Interfacing EEPROM/NVRAM to a typical microcontroller

7. Testing EEPROM/NVRAM access and performing user I/O

8. Writing Interrupt Service Routines

9. RS-232, RS-485, I2C Communication

LOW POWER IC DESIGNL T P C


3 0 0 3Course Objectives:To gain a sound knowledge of the sources of power consumption in UDSM CMOS designs and to develop a broad insight into the methods used to confront the low power issue from lower level (circuit level) to higher levels (system level) of abstraction.Course Learning Outcomes:

Design a power efficient system in reasonable trade off. Estimate and Analyze the power consumed in the circuit level Construct a system with multiple supply and multiple threshold voltages. Optimizing the code to reduce the power in the software level.

Pre-Requisite Courses: i) Digital IC Design, ii) Computational Techniques

Low Power Design Methods Motivation, Context and Objectives, Sources of Power dissipation in Ultra Deep Submicron CMOS Circuits – Static, Dynamic and Short circuit components. Effects of scaling on power consumption, Low power design flow, Normalized Figure of Merit (PDP, EDP), Power optimization at Algorithmic level, Architectural level, Register Transfer level, Logic level and Circuit level. Power Estimation using Static and Dynamic techniques, Hierarchical sequence compaction for reducing power simulation time. Algorithmic and Architecture Level Optimization Hardware/Software co-design, Pipelining and Parallel Processing approaches for low power in DSP filter structures, Multiple supply voltage and Multiple threshold voltage designs for low power, Optimal drivers of high speed low power ICs, Computer arithmetic techniques for low power.Sleep Transistor DesignDesign metrics, switch efficiency, area efficiency, IR drop, normal Vs reverse body bias. Layout design of Area efficiency, Single row Vs double row, Inrush current and current latency.Register Transfer Level Optimization Low power clock, Interconnect and layout designs, Reducing power consumption in memory cells, Clock gating, Deglitching for low power, Bus Encoding techniques. Logic Level and Circuit Level Optimization Theoretical background – Calculation of Steady state probability, Transition probability, Conditional probability, Transition density; Estimation and optimization of Switching activity, Power cost computation model, Transistor variable re-ordering for power reduction, Low power library cell design (GDI). Low Power Design of Sub-Modules Circuit techniques for reducing power consumption in Adders, Multipliers. Synthesis of FSM for low power, Retiming sequential circuits for low power. IP Design for Low PowerArchitecture and partitioning for power gating, power controller design for the USB OTG, Issues in designing portable power controllers, clocks and resets, Packaging IP for reuse with power intent. Software Level Power Optimization Power analysis of embedded software, OS issues, Power management techniques.Text Books:1. Kaushik Roy, Sharat Prasad, “Low Power CMOS VLSI circuit design”, John Wiley and Sons Inc., 2000. 2. Soudris, Dimitrios, Christrian Pignet, Goutis, Costas, “Designing CMOS circuits for low power”,

Springer International, 2004. Reference Books:1. G.K.Yeap, Farid N.Najm, “Low Power VLSI design and technology”, World Scientific Publishing, 1996. 2. A.P.Chandrakasan, R.W.Broderson, “Low Power Digital VLSI Design”, IEEE Press, 1998. 3. Gary K.Yeap, “Practical Low Power Digital VLSI Design”, Kluwer Academic Press, 1998.4. Jan M.Rabaey, Massoud Pedram, “Low power Design methodologies”, Kluwer Academic Press, 19965. Michael Keating, David Flynn “ Low Power Methodology Manual for System-On-Chip Design”

Springer Publication 2007MIXED SIGNAL IC DESIGN

L T P C3 0 0 3


Objective: This course covers many aspects of the design of dynamic analog circuits and analog-digital interface electronics in CMOS technology. It covers the specification and design of analog-to-digital and digital-analog converters and several sample converter implementations in detail.Course outcomes:A student who successfully fulfills the course requirements will have:

i. an ability to design Sample and Hold circuits.ii. an ability to design Switched Capacitor Amplifiers and analysis its non idealities. iii. an ability to design various types of ADC/DAC for a given specificationiv. an ability to design a oversampling converter considering all the practical issues for the given

specification.Prerequisite: Analog IC Design.SamplingIntroduction, sampling, Spectral properties of sampled signals, Oversampling – Anti-alias filter design. Time Interleaved Sampling, Ping-pong Sampling System, Analysis of offset and gain errors in Time Interleaved Sample and Hold. Sampling circuits- Distortion due to switch, Charge injection, Thermal noise in sample and holds, Bottom plate sampling, Gate bootstrapped switch, Nakagome charge pump. Characterizing Sample and hold, Choice of input frequency.Switched Capacitor AmplifiersSwitched Capacitor (SC) circuits– Parasitic Insensitive Switched Capacitor amplifiers, Non idealities in SC Amplifiers – Finite gain, DC offset, Gain- Bandwidth Product. Fully differential SC circuits, DC negative feedback in SC circuits.Analog to Digital ConverterData converter fundamentals: Offset and gain Error, Linearity errors, Dynamic Characteristics, SQNR, Quantization noise spectrum. Flash ADC, Regenerative latch, Preamp offset correction, Preamp Design, necessity of up-front sample and hold for good dynamic performance. Folding ADC, Multiple-Bit Pipeline ADCs.Digital to Analog Converter Linearity errors, DAC spectra and pulse shapes. NRZ vs RZ DACs. DAC Architectures: Binary weighted, Thermometer DAC, Current steering DAC – Current cell design in current steering DAC, Charge Scaling DAC, Pipeline DAC.Oversampling Converter Benefits of Oversampling, Oversampling with Noise Shaping, Signal and Noise Transfer Functions, First and Second Order Delta-Sigma Converters. Signal Dependent Stability of Describing Function Method. Introduction to Continuous-time Delta Sigma Modulators, time-scaling, inherent anti-aliasing property, Excess Loop Delay, Time-constant changes, Influence of Op amp nonidealities. Effect of OP Amp nonidealities - finite gain bandwidth, Effect of ADC and DAC nonidealities. Dynamic Element Matching - Dynamic Element Matching by Data Weighted Averaging, Effect of Clock jitter.Text Books:

1. M. Gustavsson, J. Wikner, and N. Tan, “CMOS Data Converters for Communication” Kluwer Academic Publishers, 2000.

2. Behzad Razavi, “Principles of Data Conversion System Design” Wiley-IEEE Press, 1994.3. David A.Johns, Ken Martin, “Analog Integrated Circuit Design” John Wiley & Sons Inc. 1997

Reference Books: 1. R.Jacob Baker, “CMOS Mixed Signal Circuit Design”, IEEE Press Series on Microelectronic

Systems, 2002.2. Andrzej Handkiewicz, “Mixed Signal Systems – A Guide to CMOS Circuit Design”, IEEE Press

Series on Microelectronic Systems, 2003.3. Van de Plsddvhr, Rudy J, “CMOS Integrated A/D and D/A Converters” BS Publications,2005

IC TECHNOLOGYL T P C3 0 0 3


Course Objectives: This course introduces students to the fundamentals of VLSI manufacturing processes and technology.Course Outcomes:After the completion of this course, Students will be able to

Understand physics of the Crystal growth, wafer fabrication and basic properties of silicon wafers.

Learning lithography techniques and concepts of wafer exposure system, types of resists etc. Understand Concepts of thermal oxidation and Si/SiO2 interface and its quality

measurements. Learn concepts of thin film deposition including chemical Vapor Deposition and Physical

vapor deposition. Understand back-end technology to define contacts, interconnect, gates, source and drain, and

measurements techniques to insure quality of designs. Understand MOS and Bipolar Process Integration.

IntroductionIntroduction to Semiconductor Manufacturing and fabrication. Physics of the Crystal growth, wafer fabrication and basic properties of silicon wafers.Lithography, Thermal Oxidation of SiliconThe Photolithographic Process, Etching Techniques, Photomask Fabrication, Exposure Systems, Exposure sources, The Oxidation Process, Modeling Oxidation, Masking Properties of Silicon Dioxide, Technology of Oxidation, Si-SiO2 Interface.Diffusion, Ion Implantation, Film DepositionThe Diffusion Process , Mathematical Model for Diffusion, Constant- ,The Diffusion Coefficient , Successive Diffusions, Diffusion Systems, Implantation Technology, Mathematical Model for Ion Implantation, Selective Implantation, Channeling, Lattice Damage and Annealing, Shallow Implantations, Chemical Vapor Deposition, Physical Vapor Deposition, Epitaxy.Interconnections and Contacts, Packaging and YieldMetal Interconnections and Contact Technology, Diffused Interconnections, Polysilicon Interconnections and Buried Contacts, Silicides and Multilayer-Contact Technology, Copper Interconnects and Damascene Processes, Wafer Thinning and Die Separation, Die Attachment, Wire Bonding, Packages, Yield.MOS Process Integration, Bipolar Process IntegrationBasic MOS Device Considerations, MOS Transistor Layout and Design Rules, Complementary MOS (CMOS) Technology, The Junction-Isolated Structure, Current Gain, Transit Time, Basewidth, Breakdown Voltages, Other Elements In SBC Technology, Advanced Bipolar Structures, Other Bipolar Isolation Techniques. Deep Submicron Processes, Low-Voltage/Low-Power CMOS/BiCMOS Processes. Future Trends and Directions of CMOS/BiCMOS Processes.Text Books:

1. J. Plummer, Michael D. Deal and Peter B. Griffin, “Silicon VLSI Technology, fundamentals, practice and modeling” Pearson Education, 2009.

2. Richard C. Jaeger , “Introduction to Microelectronic Fabrication”, Second EditionReference Books:

1. C.Y. Chang and S. M. Sze, ULSI Technology, McGraw Hill 19962. S.K. Ghandhi, VLSI Fabrication Principles, Wiley. 2nd edition 19943. Stanley wolf , “Silicon Processing for VLSI era, volume 4, Deep sub-micron process

technology” Lattice Press.1990PACKAGING AND INTERCONNECT ANALYSIS

Objective of the Course: L T P C3 0 0 3


To have the students develop a fundamental understanding of the basic principles used in the packaging of modern electronics so that when faced with a packaging issue they can recognize the various methods available and perform the tradeoffs necessary to select the appropriate/optimum packaging solution for the applications. Prerequisite to study the course: An undergraduate degree in a scientific or engineering area, including familiarity with computer-aided design and engineering analysis methods for electronic circuits and systems.Course Outcomes Students master fundamental knowledge of electronic packaging including package styles, hierarchy, and

methods of package necessary for various environments. Basic understanding and application of electronic packaging models and electrical performance concepts

such as impedance, loss, time delay, rise time, etc. The ability to analyze the interconnect and signal interconnect issues.IntroductionIntroduction. Electronic Packaging, Interconnection Implementation. Wire Bonding Interconnection, Tape-Automated Bonding, Solder Bump Bonding, Packaging technology updates-BGA, Conventional Packages. PLCC, PQFP, CQFP, and TSOP. Flip Chip and MCM Packaging TechnologiesBond pad, wire bonding, substrate, WPI Ace, Integrated Circuit, heat sink, electroplating, eutectic, photo resist, Conductive Polymer, epoxy, Semiconductor Device, ball grid array, fault coverage, solder paste, polyimide, Kirkendall voids, Surface Mount Technology, solder ball. MCM Packaging Technology, MCM Architecture, MCM Technologies.3D VLSI Packaging TechnologyAdvantages of 3D Packaging Technology Over Conventional Technologies: Size and Weight, Silicon Efficiency, Interconnect Usability and Accessibility, Delay, Noise, Power Consumption, Speed, Interconnect Capacity, Interconnection Capacity Between Packaging Levels. Vertical Interconnections in 3D Electronics: Periphery Interconnection between Stacked ICs - Stacked Tape Carrier - Solder Edge Conductors - Thin Film Conductors on Face-of-a-Cube - An Interconnection Substrate Soldered to the Cube Face Folded Flex Circuits - Wire Bonded Stacked Chips. Area Interconnection between Stacked ICs: Flip-chip Bonded Stacked Chips without Spacers - Flip-chip Bonded Stacked Chips with Spacers - Microbridge Springs and Thermo-migration Vias. Periphery Interconnection between Stacked MCMs: Solder Edge Conductors. Thin Film Conductors on Face-of-a-Cube - A flip-chip bonded to faces of the stack - Blind Castellation Interconnection. Area Interconnection between Stacked MCMs: Arrays of Contacts between MCMs with through hole vias. Limitations of 3D Packaging Technology.Signal Integrity Problems in On-Chip InterconnectsInterconnect Figures of Merit. Interconnect Parasitics Extraction. Signal Integrity Analysis. Design Solutions for Signal Integrity. IC Interconnect SynthesisOverview & static topology optimization- Global routing Topology: finding high quality sink permutation, tree construction for a given permutation- optimization of multisource nets: linear time computation of ARD(T) under Elmore delay, repeater insertion algorithm- timing driven Maze routing. Noise in interconnect modeling- crosstalk effects in digital circuits- noise detection in logic circuits.- techniques for avoiding interconnect noise.Reference Books:

1. John H. Lau,Ball Grid Array Technology.2. John H. Lau, Flip Chip Technologies3. Said F. Al-Sarawi and Derek Abbott, “3D VLSI Packaging Technology”

(http://www.eleceng.adelaide.edu.au/personal/alsarawi/packaging_www.html)4. Chung-KuanCheng, John Lillis, Shen Lin, “Interconnect Analysis and Synthesis”, Norman Chang,

John Wiley & sons, 2000.5. Jeffrey.A.Davis, James D.Meindl. “Interconnect techniques and design for Giga scale integration”,

Kluwer academic publishers, 2003.6. Ban P. Wong, “Nano-CMOS circuit and physical design” John Wiley. 2005.

RFIC DESIGNL T P C


3 0 0 3

Objective of the Course: This course is for IC designers who would like to become familiar with the design of integrated radio front-end circuits.

Prerequisite: Analog Integrated Circuit Design and knowledge on Electromagnetic theory.

Introduction to RF & Wireless TechnologyComplexity, design and applications. Choice of Technology. Basic concepts in RF Design: Nonlinearly and Time Variance, intersymbol Interference, random processes and Noise. Definitions of sensitivity and dynamic range, conversion Gains and Distortion. Passive and Active DevicesPassive devices: monolithic capacitors, resistors, inductors, RLC networks, transmission lines, lumped and distributed resonators, impedance matching networks, transformers, and baluns. Active devices: MOSFET operations (in both long channel and deep submicron regimes), practical limitations, and other various silicon transistors and technologies (Si/SiGe Bipolar, SOI, etc.).Analog & Digital Modulation for RF CircuitsComparison of various techniques for power efficiency. Coherent and Non coherent defection. Mobile RF Communication systems and basics of Multiple Access techniques. Receiver and Transmitter Architectures and Testing heterodyne, Homodyne, Image-reject, Direct-IF and sub-sampled receivers. Direct Conversion and two steps transmitters. BJT and MOSFET behavior at RF frequencies. Modeling of the transistors and SPICE models. Noise performance and limitation of devices. Integrated Parasitic elements at high frequencies and their monolithic implementation. Basic Blocks in RF Systems & their VLSI Implementation Low Noise Amplifiers design in various technologies, Design of Mixers at GHz frequency range. Various Mixers, their working and implementations, Oscillators: Basic topologies VCO and definition of phase noise. Noise-Power trade-off. Resonatorless VCO design. Quadrature and single-sideband generators, Radio Frequency Synthesizes: PLLS, Various RF synthesizer architectures and frequency dividers, Power Amplifiers design. Linearisation techniques, Design issues in integrated RF filters.

Text Books1. T.H.Lee, The Design of CMOS Radio-Frequency Integrated Circuits", Cambridge University

Press, 1998.2. B.Razavi, RF Microelectronics, Prentice-Hall PTR,1998

Reference Books1. R.Jacob Baker,H.W.Li, and D.E. Boyce, CMOS Circuit Design ,Layout and Simulation,

Prentice-Hall of India,1998.2. Y.P. Tsividis Mixed Analog and Digital VLSI Devices and Technology, McGraw Hill,1996

MEMORY DESIGN AND TESTINGL T P C


3 0 0 3Objective of the Course: This course will cover various aspects of semiconductor memories, including basic operation principles, device design considerations, device scaling, device fabrication, addressing, and readout circuits and testing memories.

Course OutcomeAfter completion of this course the students will

Understand the functionality of various memory devices - SRAM, DRAM, NVRAM (non-volatile memory) and can able to design them.

Understand the testing strategy of Memory circuits. Prerequisite to study the course: IC Technology, Physics of Semiconductors and Modeling, Digital IC design. Volatile and Non Volatile Memories Masked Read-Only Memories (ROMs)-Programmable Read - Only Memories (PROMs)-Erasable (UV) Programmable Road-Only Memories (EPROMs)-Floating-Gate EPROM Cell-One Time Programmable (OTP) EPROMS-Electrically Erasable PROMs (EEPROMs)- EEPROM Technology and Architecture.

Static Random Access Memories (SRAMs): SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation - Silicon On Insulator (SOl) Technology.

Dynamic Random Access MemoryDynamic Random Access Memories (DRAMs): DRAM Technology Development - CMOS DRAMs -DRAMs Cell Theory and Advanced Cell Structures: M-Bit Cell, Sense Amplifier, Row Decoder Elements. Array Architecture. Peripheral Circuitry. Global Circuitry and Considerations: Data Path elements, Address path elements, Synchronization in DRAMs BiCMOS DRAMs - Soft Error Failures in DRAMs-CAM topology – Masking – CAM Features - Future of Memories - NVRAM - FeRAM – MRAM.

Memory Testing and PatternsGeneral Fault Modeling – Read Disturb Fault Model – Precharge Faults – False Write Through Data Retention Faults – Decoder Faults. Zero/one Pattern – Exhaustive Test Patterns – Walking, Matching and Galloping – Pseudo Random Pattern – CAM pattern.Design For Test and BISTWeak Write Test mode – Bit Line Contact Resistance – PFET Test – Shadow Write and Shadow Read.

Text Books1. R.Dean Adams, “High Performance Memory Testing : Design Principles, Fault Modeling and

Self Test” , Springer, 2002.2. Brent Keeth, R. Jacob Baker, Brian Johnson, Feng Lin, “DRAM Circuit Design:

Fundamental and High-Speed Topics”, 2E, Wiley - IEEE press December 2007.References

1. M.Bushnell, V.Agrawal, “Essentials of Electronic Testing for Digital, Memory & Mixed-Synal VLSI Citcuits”, Springer, 1st edition 2nd printing 2005

http://www.wiley.com/WileyCDA/WileyTitle/productCd-0470184752.html

http://www.wiley.com/WileyCDA/WileyTitle/productCd-0470184752.html

http://as.wiley.com/WileyCDA/Section/id-302477.html?query=Feng+Lin

http://as.wiley.com/WileyCDA/Section/id-302477.html?query=Brian+Johnson

http://as.wiley.com/WileyCDA/Section/id-302477.html?query=R.+Jacob+Baker

http://as.wiley.com/WileyCDA/Section/id-302477.html?query=Brent+Keeth


RECONFIGURABLE ARCHITECTURESL T P C3 0 0 3

Objective of the Course: The objective is to deal with topics, starting from a historical perspective on early reconfigurable systems, ranging across a wide variety of results and techniques for reconfigurable models, examining more recent developments such as optical models and run-time reconfiguration (RTR), and finally touching on an approach to implementing a dynamically reconfigurable model.Prerequisite to study the course: Knowledge in Graph Algorithms and basics of Computer Architecture.Introduction to reconfigurable architectures:Principles and issues, examples, R-Mesh at a glance, Important Issues.Reconfigurable Mesh:Reconfigurable Mesh-Two Dimensional R-Mesh, Expressing R-Mesh Algorithms, Fundamental Algorithmic Techniques-Data movement, Efficiency Acceleration, Neighbor Localization, Sub-R Mesh Generation, Distance Embedding, Connectivity Embedding, Function Decomposition.Models of Reconfiguration:Restricted bus structure, word size, accessing buses, higher dimensions, one-way streets, More ways of reconfiguration-Reconfigurable Network, Reconfigurable Multiple Bus Machine, Optical Models, Reconfiguration in FPGAs, How powerful is Reconfiguration?Algorithmic Scalability and Complexity:Scalability of Algorithms - for HVR,LR, FR, meshes and Matrix Manipulations, Concepts on dis-joints, Bus structures including Multiple bus machines, Degrees of scalability, Trade-offs. Mapping of Higher order meshes, What are the salient difference between PRAMs, E-RMBMs, F-RMBM, S-RMBM, B-RMBM and Randomized PRAMS. Arithmetic on the Mesh:Conversion among number formats, floating point numbers, maximum / minimum, Foundation-addition, Multiplication, Division, Multiplying Matrices-Matrix-vector Multiplication, Matrix multiplication, Sparse Matrix Multiplication.Run-Time ReconfigurationRun-Time Reconfiguration, Run-time reconfiguration techniques for Field Programmable Gate Arrays (FPGAs), PLDs and EFTAs - Relationships between FPGA-type and R-Mesh-type platforms - Implementing R-Mesh algorithms on an FPGA-type environment.

Text Books: .

Ramanathan Vaidhyanathan, Jerry Trahan, “Dynamic Reconfiguration: Architectures and Algorithm”, KA,P 2003.


ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN ELECTRONIC SYSTEM DESIGN

L T P C3 0 0 3

Prerequisite:Electromagnetic Theory and IC Design TechnologyCourse Objectives: To cover the practical aspects of noise and interference suppression and control in electronic circuits for the engineer who is or will be involved in hardware design. Expected Outcomes: After the completion of this course the students can be able to:

Understand terminologies for EMI and EMC Analyze, understand, explain and quantify an EMC problem Design hardware to achieve the necessary isolation between RF stages Understand and reduce crosstalk coupling mechanisms Design a digital power bus to achieve the required noise budget Learn and understand ESD (electrostatic discharge) Aware of the different EMC regulations worldwide

EMI ENVIRONMENTSources of EMI, conducted and radiated EMI, Transient EMI, EMI-EMC Definitions and units of parameters.EMI COUPLING PRINCIPLESConducted, Radiated and Transient Coupling, Common Impedance Ground Coupling, Radiated Common Mode and Ground Loop Coupling, Radiated Differential Mode Coupling, Near Field Cable to Cable Coupling, Power Mains and Power Supply Coupling.EMI MEASUREMENTSEMI SPECIFICATION / STANDARDS / LIMITS: Units of specifications, Civilian standards Military standards. EMI Test Instruments/Systems, EMI Test, EMI Shielded Chamber, Open Area Test Site, TEM Cell Antennas, Conductors Sensors/Injectors/Couplers, Military Test Method and Procedures, Calibration Procedures.EMI CONTROL TECHNIQUESShielding, Filtering, Grounding, Bonding, Isolation Transformer, Transient Suppressors, Cable Routing, Signal Control, Component Selection and Mounting.EMC DESIGN OF PCBSPCB Traces Cross Talk, Impedance Control, Power Distribution Decoupling, Zoning, Motherboard Designs and Propagation Delay Performance Models.

Text Books: 1. Bernhard Keiser, " Principles of Electromagnetic Compatibility ", Artech house, 3rd Ed, 1986.2. Henry W.Ott, " Noise Reduction Techniques in Electronic Systems ", John Wiley and Sons,

1988.3. V.P.Kodali, " Engineering EMC Principles, Measurements and Technologies ", IEEE Press,

1996.


ADVANCED COMPUTER ARCHITECTUREL T P C3 0 0 3

Objective of the Course: To familiarize students with architecture of the newest processors exploiting the instruction-level parallelism and its impact on a compiler design. To make them understand features of parallel systems which make use of functional parallelism at a process- or thread-level and also data parallelism.Prerequisite to study the course: Students must have graduate standing and have successfully completed an undergraduate-level computer architecture course and be well-versed in how a basic computer works, assembly language programming, pipelining, caching, and virtual memory.Parallel computer models: The state of computing, Classification of parallel computers, Multiprocessors and multicomputers, Multivector and SIMD computers.Program and network properties: Conditions of parallelism, Data and resource Dependences, Hardware and software parallelism, Program partitioning and scheduling, Grain Size and latency, Program flow mechanisms, Control flow versus data flow, Data flow Architecture, Demand driven mechanisms, Comparisons of flow mechanismsSystem Interconnect Architectures: Network properties and routing, Static interconnection Networks, Dynamic interconnection Networks, Multiprocessor system Interconnects, Hierarchical bus systems, Crossbar switch and multiport memory, Multistage and combining network.Advanced processors: Advanced processor technology, Instruction-set Architectures, CISC Scalar Processors, RISC Scalar Processors, Superscalar Processors, VLIW Architectures, Vector and Symbolic processorsPipelining: Linear pipeline processor, nonlinear pipeline processor, Instruction pipeline Design, Mechanisms for instruction pipelining, Dynamic instruction scheduling, Branch Handling techniques, branch prediction, Arithmetic Pipeline Design, Computer arithmetic principles, Static Arithmetic pipeline, Multifunctional arithmetic pipelinesMemory Hierarchy Design: Cache basics & cache performance, reducing miss rate and miss penalty, multilevel cache hierarchies, main memory organizations, design of memory hierarchies. Multiprocessor architectures: Symmetric shared memory architectures, distributed shared memory architectures, models of memory consistency, cache coherence protocols (MSI, MESI, MOESI), scalable cache coherence, overview of directory based approaches, design challenges of directory protocols, memory based directory protocols, cache based directory protocols, protocol design tradeoffs, synchronization, Scalable point –point interfaces: Alpha364 and HT protocols, high performance signaling layer.Enterprise Memory subsystem Architecture: Enterprise RAS Feature set: Machine check, hot add/remove, domain partitioning, memory mirroring/migration, patrol scrubbing, fault tolerant system.References:

1. Kai Hwang, “Advanced Computer Architecture: Parallelism, Scalability and Programmability”, McGraw-Hill Inc, 1993

2. Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. Morgan Kaufman Publishers, Inc., 2003, 1136 p., ISBN 1-55860-596-7.

3. D. E. Culler, J. Pal Singh, and A. Gupta, “Parallel Computer Architecture: A Hardware/Software Approach”, HarcourtAsia Pte Ltd., 1999.

4. Kai Hwang, " Advanced Computer Architecture ", McGraw Hill International5. Harvey G.Cragon,”Memory System and Pipelined processors”; Narosa Publication


SCRIPTING LANGUAGES FOR VLSI DESIGN AUTOMATIONL T P C3 0 0 3

Course Objectives: VLSI Engineers who wish to become skilled in the practical use of UNIX/PERL/Tcl for tasks related to programmable logic or ASIC design. Prerequisite:Some experience with at least one software programming language like C is highly advantageous. No previous knowledge of Tcl/Tk is required. Students are expected to be computer literate and to have an understanding of the digital hardware design.UNIXIntroduction to Unix, Overview of commands, Unix Shell scripting , Overview of scripting language –PERL , TCL , PythonPERLHistory and Concepts of PERL, Scalar Data ,Arrays and List Data, Control structures, Hashes, Basics I/O, Regular Expressions ,Functions, Miscellaneous control structures, Formats , Directory access , File and Directory manipulation , process management ,System database access , User data manipulation.Tool Command LanguageAn Overview of TCL and Tk , Tcl Language syntax ,Variables ,Expressions, Lists , Control flow , procedures, Errors and exceptions ,String manipulation , Accessing files , Processes , Managing Tcl Internals ,HistoryApplicationsAutomatic code generation , Report Filtering , Netlist patching , Test Vector Generation , Controlling Tools

Text Books: 1. Larry Wall, Tom Christiansen, John Orwant, “Programming PERL”, Oreilly Publications, 3rd

Edn., 20002. Eric Foster-Johnson, John C. Welch, and Micah Anderson Beginning Shell

scripting, ,Wiley Publication,20053. John K. Ousterhout, Tcl and the Tk Toolkit, Addison-Wesley Publishing Company, Inc.,1993

References:1. Randal L, Schwartz Tom Phoenix, “Learning PERL”, Oreilly Publications, 3rd Edn., 20002. Brent B. Welch and Ken Jones, “Practical Programming in Tcl and TK”


HARDWARE/SOFTWARE CO-DESIGNL T P C3 0 0 3

Objective of the Course: To understand the methodologies related to High level synthesis and Compiler optimization.

Prerequisite to study the course: Digital design and Programming and Hardware description languages.Specification of embedded systems Why Co-design? - Comparison of co-design approaches – MoCs: State oriented, Activity oriented, Structure oriented, Data oriented and Heterogeneous – Software CFSMs – Processor Characterization.HW/SW Partitioning methodologiesPrinciple of hardware/software mapping - Real time scheduling - design specification & constraints on Embedded systems - Tradeoffs - Partitioning granularity - Kernigan-Lin Algorithm - Extended Partitioning - Binary Partitioning: GCLP AlgorithmCo-synthesis & EstimationSoftware synthesis – Hardware Synthesis - Interface Synthesis – Co-synthesis Approaches: Vulcan, Cosyma, Cosmos, Polis and COOL – Estimation: Hardware area, execution timing and power; Software memory and execution timing.Co-simulation & Co-verificationPrinciples of Co-simulation – Abstract Level; Detailed Level – Co-simulation as Partitioning support – Co-simulation using Ptolemy approach.Text Books: Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Claudio Passerone, Alberto Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki, Bassam Tabbara. “Hardware-Software Co-Design of Embedded Systems: The POLIS Approach”, 2004. Ralf Niemann, “Hardware/Software Co-Design for Data Flow Dominated Embedded Systems”, Springer, 1998, ISBN:0792382994.References:Peter Marwedel, “Embedded System Design”, Springer, 2006, ISBN:1402076908.Russell John Rickford, Bernd Kleinjohann, “Design and Analysis of Distributed Embedded Systems”, Springer, 2002, ISBN:1402071566. Achim Rettberg, Mauro C Zanella, Franz J Rammig, “From Specification to Embedded Systems Application”, Springer, 2005, ISBN:0387275576http://embedded.eecs.berkeley.edu/research/hsc/class.F04/index.htmlhttp://www.tik.ee.ethz.ch/tik/education/lectures/ES/http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/http://courses.cs.tamu.edu/rabi/cpsc489/resources.shtml

http://courses.cs.tamu.edu/rabi/cpsc489/resources.shtml

http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/

http://www.tik.ee.ethz.ch/tik/education/lectures/ES/

http://embedded.eecs.berkeley.edu/research/hsc/class.F04/index.html


DSP ARCHITECTURESL T P C3 0 0 3

Objective of the Course: This course on digital signal processing architectures which focuses on the implementation and design of families of DSP architectures with in-depth analysis of the relevant algorithms. Students learn the essential advanced topics in digital signal processing, Internal DSP architectural requirements for a DSP device, system level hardware design of DSP Architectures and interfacing peripherals to programmable DSPs.Prerequisite to study the course: Familiarity with digital filters, matrix algebra, and random signal analysis.

ARCHITECTURES FOR PROGRAMMABLE DSP DEVICESBasic Architectural features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Speed Issues, Features for External interfacing.EXECUTION CONTROL & PIPELININGHardware looping, Interrupts, Stacks, Relative Branch support, Pipelining and Performance, Pipeline Depth, Interlocking, Branching effects, Interrupt effects, Pipeline Programming models.ADSP ARCHITECTURES AND SYNTHESIS Top Down approach to DSP LSI, Circuit Synthesis, High Performance Data conversion Techniques, LSI Algorithms and Architectures, Hierarchical Design of Processor Arrays, Systolic Arrays, Stack Filters, Wave-front Array Processors, Floating Point DSP processors, Systolic Processors for Image Processing; Standard digital signal processors, Application Specific IC’s for DSP, ADSP system architectures, Standard DSP architecture, Ideal DSP architectures, Equalizers, Adaptive Equalizers, Multiprocessors and multi-computers, Systolic and Wave front arrays, Shared memory architectures. Mapping of DSP algorithms onto hardware, Implementation based on complex PEs, Shared memory architecture with Bit – serial PEs.INTERFACING MEMORY & I/O PERIPHERALS TO PROGRAMMABLE DSP DEVICESMemory space organization, External bus interfacing signals, Memory interface, Parallel I/O interface, Programmed I/O, Interrupts and I/O, Direct memory access (DMA). A Multichannel buffered serial port (McBSP), McBSP Programming, a CODEC interface circuit, CODEC programming, A CODEC-DSP interface example.

Text Books: 1. Avtar Singh and S. Srinivasan , “Digital Signal Processing”, Thomson Publications, 2004.2. Lars Wanhammer, “DSP Integrated Circuits”, Academic press, New York 1999.3. Lapsley et al., “DSP Processor Fundamentals, Architectures & Features , S. Chand & Co, 2000.References:1. B.VenkataRamani and M. Bhaskar, “Digital Signal Processors, Architecture, Programming and

Applications”, TMH, 2004.2. Jonatham Stein, “Digital Signal Processing”, John Wiley, 2005.3. Bayoumi, MA, VLSI Design Methodology for DSP Architectures, Klumer, 1994. 4. Sung-Yuan Kung, Robert E.Owen, J.Gerg Nash, “VLSI Signal Processing” Vol.1, Vol.II. IEEE

Press. 1986


FAULT TOLERANT AND DEPENDABLE SYSTEMSL T P C3 0 0 3

Course objectives:With the VLSI, Field Programmable Gate Array (FPGA), and System On a Chip(SOC) technologies, transistors are getting smaller and smaller thus today's digital systems are more complex than ever before. This increased complexity leads to more cross-talk noise and other sources of transient errors ( like single event upset) during normal operation. Traditional off-line testing strategies cannot guarantee detection of these transient faults. The critical applications that are relying on faster operations need built-in fault-tolerant and self-checking mechanisms to assure reliable and dependable operation.

This course focuses on the state-of-the-art approaches to designing dependable systems, covering the following topics:

• Dependability attributes: availability, reliability, and safety • Fault models and prediction of hardware failure rates.

• Hardware fault-tolerance, physical and temporal redundancy. • Software safety, software fault tolerance. • Safety-critical embedded systems • Case studies of dependable-system design.

Prerequisite: Design of digital systems.

Course topics: 1. Introduction to fault tolerance and failsafe design techniques. Goals & applications of fault

tolerance. Classification of faults. Reconfiguration Techniques using SRAM based Field Programmable Gate Arrays (FPGAS).

2. Modeling of the faults in hardware and software. Test vector generation, and Built In Self Test (BIST) concepts. Test data compression techniques: Signature analysis, ONE’s counting, and Transition counting.

3. Fault detection and fault location techniques 4. Fundamentals of Reliability - Basic definitions (Ch.1)5. Error detecting and correcting codes (Ch.2)6. Self checking logic design(ch.3)7. Self checking checkers (ch.4)8. Fault-Tolerant Design- Hardware, Information,Time, and software redundancy. System level

fault tolerance (Ch. 6). 9. Evaluation techniques : Quantitative evaluation and Reliability modeling. 10. Case studies- Applications of Fault tolerance to control Systems and computers.

Term paper presentations by students.

Text book:Parag K. Lala, "Self checking and Fault Tolerant Digital Design", Morgan Kaufmann Publishers, 2001. Reference:B.W. Johnson, "Design and analysis of Fault Book Tolerant Digital Systems ", Addison-Wesley Publishing Company, 1989.


IMAGE PROCESSING AND COMPRESSION TECHNIQUESL T P C3 0 0 3

Aims and Objectives: To develop theoretical and algorithmic principles behind the acquisition, display, manipulation and processing of digital images. To explore the methods used to digitize, transfer, display, organize, process and compare digital images and image sequences. To analyze technique in image compression

Prerequisites: Design and Analysis of Algorithms, C or C++ programming languages and object oriented design, Matrix Algebra, Fourier Transforms

Course Outcome: Will get knowledge on Image Transform, Image Enhancement and Image segmentation techniques, color image processing and image compression.

Image Formation and Display: Digital Image Structure, cameras and eyes, Television video signals, other image acquisition and display, brightness and contrast adjustments, grayscale transforms. Warping.

Linear Image processing: Convolution, 3x3 edge modification Analysis, FFT Convolution.

Special Imaging Techniques: Spatial Resolution, sample spacing and sampling aperture, signal to noise ratio, morphological image processing, computed tomography.

Data compression: Data Compression Strategies, Run length Coding, Huffman Encoding, Delta Encoding, LZW Compression, JPEG (Transform Compression), MPEG.

Applications and Techniques of Image processing in Remote Sensing, Bio medical, Forensic and Security,

Text Books:Reference Books:

1. Steven W. Smith , “ Digital Signal Processing: A Practical Guide for Engineers and Scientists” , Elsevier, 2003

2. Anil.K.Jain, “Fundamentals of Digital Image Processing” PHI, 1995. 3. R.C.Gonzalez and R.E. Woods, “Digital Image Processing”, PHI, 2002.


SINGLE ELECTRONICS DEVICE APPLICATIONS AND MODELINGL T P C

3 0 0 3Course Prerequisites: Semiconductor device physics, Quantum Physics, NanoelectronicsAim: Single Electronics and the devices are emerging as the futuristic devices for ultra-dense digital IC designs and their understanding and modeling techniques are required to be learnt. Students will be exposed to this emerging field.Expected Outcome: The students exposed this area of Single Electron and a few electron devices, their characteristics and advanced concepts of such devices for futuristic Integrated devices will enable students to get opportunities in the advanced technology R & D groups in India and Abroad. Unique opportunity exist for such students.Basic Single Electron devices Single Electron Box, Single Electron transistor, Single-Electron Traps, Single-Electron Turnstile and Pumps, SET Oscillators, Comparison Between FET and SET Circuit DesignsAnalog and Digital Applications- Voltage State Logics, Charge State Logics, Logic Circuit Applications of SETs- Merged SET and MOSFET Logic, CMOS- Type Logic Circuit, Pass- Transistor Logic, Multigate SET, Background-Charge-Insensitive Memory, Crested Tunnel Barriers, Single-Electron Transistors and Memories- Introduction to Memory Devices, Floating Gate Scheme, Single-electron MOS memory (SEMM)- Structure, Fabrication Procedure, Experimental Observations, Analysis, Effect of Trap States Effect of Thicker Tunnel Diode Experimental Behavior of Memories- Percolation Effects, Limitations in Use of Field Effect, Confinement and Random Effects in Semiconductors, Variances due to Dimensions, Limits Due to Tunneling, Tunneling in Silicon; Nonvolatile Random-Access Memory (NOVORAM), Other Single-Electron and Few-Electron Devices and Memories, Electrostatic Data Storage (ESTOR) SESO Transistor- History, Single-electron devices to SESO, Fabricated SESO Transistor, SESO Memory, Memory-Technology ComparisonIntroduction Simulation Methods and Numerical Algorithms – Monte Carlo Method, Solution of the Master Equation, Coupling with SPICE, Free Energy, Tunnel Transmission Coefficient, Energy Levels, Evaluation Schemes for Co tunneling, Rate Calculation Including Electromagnetic Environment, Numerical Integration of Tunnel Rates, Time Dependent Node Voltages and Node Charges, Stability Diagram and Stable States, Capacitance Calculations, SIMON single-electron software package.Text Books:1. Shunri Oda and David Ferry, “Silicon Nanoelectronics”,CRC Press, Taylor & Francis Group, 2006. 2. D. V. Averin, Y. V. Nazarov, “Macroscopic quantum tunneling of charge and co-tunneling”, in H.

Grabert, M. H. Devoret (eds.), Single charge tunneling: Coulomb blockade phenomena in nanostructures, Plenum Press and NATO Scientific Affairs Division, New York and London, 1992, pp. 217-247.

3. Christoph Wasshuber, “Computational Single-Electronics", 2001, Springer-Verlag, Reference Books:1. K. Goser, P. Glosekotter, “Nanoelectronics and Nanosystems” Springer, 2005. 2. R. Tsu, “Superlattice to Nanoelectronics” Elsevier, 2005. 3. A. N. Korotkov, D. V. Averin, K. K. Likharev, S. A. Vasenko, “Single-electron transistors as

ultrasensitive electrometers”, Single-electron tunneling and mesoscopicg devices, Springer, 1992.Journal paper:

1. “Single Electron Devices and their Applications, Konstantin K. Likharev, PROCEEDINGS OF THE IEEE, VOL. 87, NO. 4, APRIL 1999.p 606- 632.


MICRO ELECTRO MECHANICAL SYSTEML T P C3 0 0 3

Aims: To teach different methods of micromachining and how these methods can be used to

produce a variety of MEMS, including microstructures, microsensors, and microactuators Expose the students to design, simulation and analysis softwares. In addition to this the course covers the various applications of MEMS in different field.

Learning Outcomes: Design of MEMS based systems

Introduction To MEMS:

Historical background of Micro Electro Mechanical Systems, role of MEMS in improved efficiency, Smart materials and structures, materials-processing, synthesis, Multifunctional polymers.

Material Processing and Device Fabrication: Lithography, Ion Implantation, Etching, Wafer bonding, Integrated processes, Bulk silicon micro machining, surface micro machining, CVD oxide process.

Micro Sensors and Micro actuators:

Micromechanical components – springs, bearings, gears and connectors, High temperature sensors, Capacitive pressure sensor, bulk micro-machined accelerometer, Surface micro machined micro spectrometer.

Applications of MEMS:

Blood Pressure Monitoring Transducers, Disposable Blood Pressure Monitoring Transducers. MEMS devices – Infusion pumps, Kidney dialysis, Respirators, Active noise and vibration control, Intelligent structures, micro –robots, Smart structures for aircraft, automotive requirements, automobile, Satellite, Buildings and Manufacturing systems.

Text book:

1. Tai-Ran Hsu, ‘MEMS & Microsystem, Design and Manufacture’, McGraw Hill, 2002

References:

1. Julian W.Gardner, Vijay. K.Varadhan, Osama O.Awadelkahn (2001), “MicroSensors, MEMS and Smart Devices”, Wiley Publishers

2. Gregory T.A.Kovacs (1995), “Micromachined Transducers – Source Book”, McGraw Hill Publishers – ISBN : 0-07-116462-6

NANOELECTRONICS


L T P C3 0 0 3

Course Prerequisites: Physics and modeling of Semiconductor DeviceAim: Nanoelectronics is the next transition in the device and integrated circuit technologies which are necessitated due to the need for several 10s to 100s of THz device requirements for various demands for speeds and drastic reduction of power requirements.Expected Outcome/ Objectives: Is to introduce students to the complexities of the emerging technologies and introduce them to the issues related to the operation of such devices and understand the functionality of such devices. This will enable the students to take up their jobs in R & D and new process technologies.Introduction to Nanoelectronics Limitations of the conventional MOSFETs at Nanoscales, introductory concepts of Ballistic transport and Quantum confinement, Differences in Few Electron Devices (as analog version) and Single Electron Devices (as digital version) of Nanoelectronic devices.Current Nanoelectronic Devices. Conventional MOS-FET, Gate Leakage due to Gate oxide, High K dielectrics and improvements in performance. Scaling effect, Quantum Effects in MOSFETs, Strained Silicon, Fully Depleted SOI, MOSFET, Double Gate MOSFET, Multi-gate MOSFETs, FIN-FET, Electrically Induced Junctions for EJ-MOSFETs, Ballistic Transport, Conductance Quantization, Quantum Point Contact Devices, New inter-connect strategies. Nanostructures and Quantum Devices: Low-dimensional structures: Quantum wells, Quantum wires, and Quantum dots; Density of states in low-dimensional structures; Resonant tunneling phenomena and applications in diodes and transistorsIntroduction to Single Electronics Principle of the Single-Electron Transistor- The Coulomb Blockade Phenomenon, Theoretical Quantum Dot Transistor; - Energy of Quantum Dot system, Single-Electron Quantum-Dot Transistor, Single-Hole Quantum-Dot Transistor, Single-Electron Transistor, Coulomb Blockade Devices, Conductance Oscillation and Potential Fluctuation, Transport under Finite temperature and Finite Bias, Single-Electron Effect, Modeling of Transport: Tunneling- Quantum kinetic Equation, Carrier Statistics and Charge Fluctuations.Quantum electronics: Upcoming Electronic Devices (QED), Electrons in Mesoscopic structures, Examples of Quantum Electronic Devices: Quantum Interference Devices, SQUIDs, Split –Gate Transistor, Electron –Wave Transistor, Electron –Spin Transistor, , Resonant Tunnelling Devices, Quantum Oscillators, Quantum Cellular Automata (QCA), Quantum –dot Array, Introduction Quantum Computing. Carbon Nantubes and CNT Based devices Carbon Nanotube theory: structure and phonon dispersion relations, nomenclature, acoustic and optical phonons, Nanotube theory: electronic structure, optical properties. Electronic structure of graphene, SW and MWCNTs, 1D quantization in nanotubes, van Hove singularities, CNT-FET, CNT-TUBFET, CNT-SET, CNT memories, CNT based switches, Logic Gates, CNT based RF devices, CNT based RTDs,Molecular Electronics: Overview, Characterization of switches and complex molecular devices, polyphenylene based Molecular rectifying diode switches. Polymer Electronics, Self-Assembling Circuits, Optical Molecular Memories Technologies, Quantum Mechanical Tunnel Devices, Quantum Dots & Quantum wires Spintronics: Introduction to Spintronics. Principles and concepts, Spintronic devices and applications, spin filters, spin diodes, spin transistors.Text Books:1. “Silicon Nanoelectronics” By Shunri Oda, David Ferry, CRC Press, Taylor & Francis Group, 2006. 2. C.N.R. Rao and A. Govindaraj “Nanotubes and nanowires”, RSC Publishing, 2005.3. “Nanoelectronics and Nanosystems” By K. Goser, P. Glosekotter, Springer, 2005. 4. Karl Goser, Peter Glosekotter, Jan Dienstuhl , “ Nanoelectronics and Nanosystems- From Transistors to

Molecular and Quantum Devices”, Springer-Verlag 20045. M. Ziese and M. J. Thornton (Eds.), “Spin Electronics”, Springer-Verlag 2001Reference Paper:1. “Single Electron Devices and their Applications, Konstantin K. Likharev, PROCEEDINGS OF THE

IEEE, VOL. 87, NO. 4, APRIL 1999.p 606- 632.

SYSTEM-ON- CHIP DESIGN


L T P C3 0 0 3

Aim:To provide an overview on the present state design technology for System-On-Chip

INTRODUCTION

Architecture of the present-day SoC - Design issues of SoC- Hardwar-Software Codesign – Core

Libraries – EDA Tools

DESIGN METHODOLOGY FOR LOGIC CORES

SoC Design Flow – guidelines for design reuse – Design process for soft and firm cores – Design

process for hard cores – System Integration

DESIGN METHODOLOGY FOR MEMORY AND ANALOG CORES

Embedded memories – design methodology for embedded memories – Specification of analog

circuits – High speed circuits

DESIGN VALIDATION

Core-Level validation – Core Interface verification - SoC design validation

CORE AND SoC DESIGN EXAMPLES

Microprocessor Cores – Core Integration and On-chip bus – Examples of SoC

Text Book:Rochit Rajsuman, ‘System-on-a-Chip: Design and Test’, Artech House, 2000

Reference Books:1. Steve Furber, ARM System-on-Chip Architecture, 2 nd ed, Addison-Wesley Professional, 2000

2. Ricardo Reis & Jochen A.G. Jess, ‘Design of System on a Chip : Devices & Components’, Kluwer, 2004

3. Laung-Terng Wang, Charles E. Stroud, Nur A. Touba, ‘System-on-Chip Test Architectures’, Morgan Kaufmann, 2007

COMPUTATIONAL TECHNIQUES L T P C3 0 0 3

http://www.ebookee.com.cn/ARM-System-on-Chip-Architecture-2nd-Edition-by-Steve-Furber_137858.html


Course Objective: This course aims to cover mathematical techniques and models used in the solution of computer engineering problems in microelectronics. Course Outcomes:By the end of the course, students will have a broad understanding of the various notions used in computational complexity theory to classify computational problems as hard or easy to solve. They will become familiar with the important complexity classes, how they are related to each other, typical problems in those classes. They will be familiar with Finite difference methods and probability theory and random process.Set TheoryBasics of Set theory: Subsets, Set Operators, Sets of Numbers – Functions: Product Sets and Graphs of Functions – Relations – Operations - Cardinal- Partially and Totally Ordered Sets - Algebra of Propositions – Quantifiers - Boolean Algebra - Logical Reasoning. Graph TheoryBasic concepts of GT: Paths, Reachability and Connectedness; Matrix representations - Trees - Connectivity - Euler tours and Hamilton Cycles - Matchings - Edge Colouring - Directed Graphs - Random Graphs.Complexity of AlgorithmsComparing algorithms - Machine independence - Example of finding the maximum- θ(theta) notation - O(big oh) notation - Properties of θ and O - θ as an equivalence relation - Sufficiently large, Eventually positive, Asymptotic - o (little oh) notation - using θ to compare polynomial evaluation algorithms, average running time, tractable, intractable, graph coloring problem. Probability, Stochastic and Random ProcessesDeterministic and probabilistic function, Probabilistic space, Joint probability, conditional probability, Bernoulli Trails, Bayes’ Theorem, Entropy, M.S.E., Normal Random variables, Central Limit Theorem, Stochastic Processes, Markovian Processes, Stationary and Non-stationary processes, Time variant and Time invariant signals, Ergodic processes, Covariance, Correlation, Auto & cross correlations, Power Spectrum. Finite Difference MethodsOrdinary differential equations of second order – finite difference methods, Finite difference methods. Forelliptic equations, Diffusion equation – explicit method – Von-Neumann stability condition, Crank–Nikolson Implicit method. Wave equation–explicit method, CFL stability condition. Text Books:

1. J.P. Trembley and R. Manohar, “Discrete Mathematical Structures with Applications to Computer Science”, Tata McGraw Hill – 13th reprint (2001).

2. Edward A. Bender & S. Gill Williamson “Mathematics for Algorithm and Systems Analysis”, Dover (2005) ISBN 0-486-44250-0

3. S. Lipschutz and M. Lipson, “Discrete Mathematics”, TMH, 2nd Edition (2000).4. Murray R. Spiegal, “Theory and problems of Statistics” Schaum’s series,TMH,.1999

References:1. J A Bondy and U S R Murthy, “Graph Theory with Applications”, Elsevier Publishing Co., Inc., New

York, 1976.2. Lipschutz, Seymour, “Schaum's Outline of Theory and Problems of Set Theory and Related Topics”,

McGraw-Hill Companies, July 19983. Liu "Elements of Discrete Mathematics" McGraw Hill.4. Richard Johnsonbaugh, “Discrete Mathematics”, 5th Edition, Pearson Education (2001).

M.Tech. (VLSI Design) Curriculum & Syllabi (AY 2009-10 onwards).doc

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