VLSI A RCHITECTURE FOR D ISCRETE F RACTIONAL F OURIER T RANSFORM A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF TECHNOLOGY IN INFORMATION TECHNOLOGY (MICRO ELECTRONICS) INDIAN INSTITUTE OF INFORMATION TECHNOLOGY, ALLAHABAD, U.P. 211012, INDIA JUNE, 2010 Submitted By V. Naga Vara Prasad M. M. Tech. IT (MI) IIIT-Allahabad IMI2008007 Under the Supervision of Dr. K. C. Ray IIIT-Allahabad
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VLSI ARCHITECTURE FOR DISCRETE FRACTIONAL FOURIER TRANSFORM
A THESIS
SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
MASTER OF TECHNOLOGY IN INFORMATION TECHNOLOGY
(MICRO ELECTRONICS)
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY, ALLAHABAD, U.P. 211012, INDIA
JUNE, 2010
Submitted By V. Naga Vara Prasad M.
M. Tech. IT (MI) IIIT-Allahabad
IMI2008007
Under the Supervision of Dr. K. C. Ray IIIT-Allahabad
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY
ALLAHABAD
(Deemed University) (A Centre of Excellence in Information Technology, Established by Govt. of India)
Date: ______________
WE DO HEREBY RECOMMEND THAT THE THESIS WORK
PREPARED UNDER OUR SUPERVISION BY V. NAGA VARA PRASAD M.
ENTITLED VLSI ARCHITECTURE FOR DISCRETE FRACTIONAL
FOURIER TRANSFORM BE ACCEPTED IN PARTIAL FULFILMENT OF
THE REQUIREMENTS FOR THE DEGREE OF MASTER OF
TECHNOLOGY IN INFORMATION TECHNOLOGY (MICRO
ELECTRONICS) FOR EXAMINATION.
COUNTERSIGNED
Prof. S. Sanyal,
DEAN (ACADEMICS)
Dr. K. C. Ray THESIS ADVISOR
INDIAN INSTITUTE OF INFORMATION TECHNOLOGY
ALLAHABAD
(Deemed University) (A Centre of Excellence in Information Technology, Established by Govt. of India)
CERTIFICATE OF APPROVAL*
The foregoing thesis is hereby approved as a creditable study in the area of
information technology carried out and presented in a manner satisfactory to
warrant its acceptance as a pre-requisite to the degree for which it has been
submitted. It is understood that by this approval the undersigned do not
necessarily endorse or approve any statement made, opinion expressed or
conclusion drawn therein but approve the thesis only for the purpose for
which it is submitted.
COMMITTEE ON
FINAL EXAMINATION
FOR EVALUATION
OF THE THESIS
* Only in case the recommendation is concurred in
CANDIDATE DECLARATION
This is to certify that Report entitled “VLSI Architecture for Discrete
Fractional Fourier Transform” which is submitted by me in partial
fulfillment of the requirement for the completion of M.Tech. In Information
Technology (specialization in Microelectronics) to Indian Institute of
Information Technology, Allahabad comprises only my original work and
due acknowledgements has been made in the text to all other materials
used.
Date: V. Naga Vara Prasad M.
M.Tech. IT: Microelectronics
Enrollment No: IMI2008007
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad v | P a g e
Abstract The conventional Fourier transform is recognized as a significant tool in wide
areas of signal, image processing and communication. Its discrete version turned as an
essential module in many applications with the advent of its hundreds of fast
computation algorithms and DSP processors. This thesis has been adding an
additional value to this integral transform with a novel architecture of its generalized
form. This generalized Fourier transform attracted the attention of signal, image and
optical processing communities. Researchers identified its benefits by finding wide
range of applications such as orthogonal frequency division multiplexing, optimum
filters, Image registration, Image encryption, Image water marking, modulation and
demodulation, human emotion detection, Optimal receivers, biomedical signal
detection etc. This thesis enables the real time implementation of their proposals for
different applications. Unlike the ordinary Fourier transform, the fractional Fourier
transform have multiple definitions. Among these definitions, many researches are
recommended a definition which is defined based on Eigen Vector Decomposition
(EVD) as a legitimate definition. With the study of its properties using MATLAB
simulations, we ensured the usability of this definition based on EVD. In this thesis,
we proposed architecture for discrete fractional Fourier transform, which consumes
hardware complexity of O(4N). Where N is transform order. This proposed
architecture has been simulated and synthesized using verilogHDL, targeting a FPGA
device (XLV5LX110T). Hardware simulations are compared with the MATLAB
simulations which show that the results are very close with some quantization error.
The synthesized results have been represented in terms of hardware utilization and
timing, which shows that the proposed architecture can be operated at maximum
frequency of 217MHz. The proposed architecture is also compared with the existing
architecture which shows that the proposed architecture in this thesis is better in terms
of timing and area complexity.
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad vi | P a g e
Acknowledgement
I would like to express my deep gratitude to Dr. K. C. Ray for the numerous inspiring discussions and constant support throughout this study.
I am highly thankful to him that in spite of his demanding professional
preoccupation he always made himself available for guidance to me in my thesis work.
I am very thankful to Prof. M. Radhakrishna, H.O.D, Department of Microelectronics, IIIT-A. For his vision, motivation and whole-hearted
support throughout my academics.
I am deeply indebted to Prof. B.R Signh and Mr. Manish goswami for their feedback and valuable comments during our regular presentations
which helped me a lot in this thesis work.
VLSI Architecture for Discrete Fractional Fourier Transform
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And we simulated the DFrFT for the rotation angles (fractional values) 00(0.00), 300(0.33), 600(0.67), 900(1.00), 1200(1.33), 1500(1.67), 1800(2.00), 2100(2.33), 2400(2.67), 2700(3.00), 3000(3.33), 3300(3.67) and 3600(4.00).
Fig.5.2: Input Samples for MATLAB Simulation of DFrFT
Fig.5.3: MATLAB Simulation Result of DFrFT for α=00
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Fig.5.4: MATLAB Simulation Result of DFrFT for α=300
Fig.5.5: MATLAB Simulation Result of DFrFT for α=600
Fig.5.6: MATLAB Simulation Result of DFrFT for α=900
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Fig.5.7: MATLAB Simulation Result of DFrFT for α=1200
Fig.5.8: MATLAB Simulation Result of DFrFT for α=1500
Fig.5.9: MATLAB Simulation Result of DFrFT for α=1800
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Fig.5.10: MATLAB Simulation Result of DFrFT for α=2100
Fig.5.11: MATLAB Simulation Result of DFrFT for α=2400
Fig.5.12: MATLAB Simulation Result of DFrFT for α=2700
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Fig.5.13: MATLAB Simulation Result of DFrFT for α=3000
Fig.5.14: MATLAB Simulation Result of DFrFT for α=3300
Fig.5.15: MATLAB Simulation Result of DFrFT for α=3600
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TABLE-5.2
COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULT FOR ROTATION ANGLE OF 00
Sample No.
Input Samples for both Matlab and Xilinx-ISE
Simulator
MATLAB Simulation Results for α = 00
Xilinx-ISE Simulation
Results of Proposed Architecture for α = 00
01 0000 + 0000 i 0000 + 0000 i 0000 + 0000 i
02 0271 + 0000 i 0271 + 0000 i 0270 + 0000 i
03 0475 + 0000 i 0475 + 0000 i 0474 + 0000 i
04 05b5 + 0000 i 05b5 + 0000 i 05b4 + 0000 i
05 05f7 + 0000 i 05f7 + 0000 i 05f7 + 0000 i
06 0532 + 0000 i 0532 + 0000 i 0531 + 0000 i
07 0387 + 0000 i 0387 + 0000 i 0387 + 0000 i
08 013f + 0000 i 013f + 0000 i 013f + 0000 i
09 fec1 + 0000 i fec1 + 0000 i fec1 + 0000 i
10 fc79 + 0000 i fc79 + 0000 i fc78 + 0000 i
11 face + 0000 i face + 0000 i facd + 0000 i
12 fa09 + 0000 i fa09 + 0000 i fa09 + 0000 i
13 fa4b + 0000 i fa4b + 0000 i fa4b + 0000 i
14 fb8b + 0000 i fb8b + 0000 i fb8a + 0000 i
15 fd90 + 0000 i fd90 + 0000 i fd90 + 0000 i
16 0000 + 0000 i 0000 + 0000 i ffff + 0000 i
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TABLE-5.3
COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULTS FOR ROTATION ANGLE OF 300 AND 600
Sample No.
MATLAB Simulation Results for α = 300
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 300
MATLAB Simulation Results for α = 600
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 600
01 009d + 00e7 i 009c + 00e6 i 006b + 0005 i 006b + 00004 i
02 000e + 015e i 000e + 015d i ff4d + 00a4 i ff4c + 00a3 i
03 fe1f + 026d i fe1f + 026c i ffc0 + febd i ffbf + febc i
04 fad1 + febe i fad0 + febd i 01ac + 0003 i 01ab + 0002 i
05 ff06 + f991 i ff06 + f991 i ff4d + 032f i ff4c + 032e i
06 03c5 + fbc3 i 03c4 + fbc2 i fa9c + fd58 i fa9b + fd58 i
07 03c5 + fe6d i 03c5 + fe6d i 0318 + f88b i 0318 + f88b i
08 01b8 + ffeb i 01b8 + ffeb i 0458 + ff9f i 0457 + ff9e i
09 fea2 + ffc3 i fea1 + ffc3 i fe35 + ff58 i fe35 + ff57 i
10 fc08 + 0035 i fc07 + 0034 i f96e + 018d i f96d + 018c i
11 faa1 + 01ac i faa0+ 01ac i fca3 + 0692 i fca4 + 0692 i
12 fbdb + 04f4 i fbda + 04f3 i 0392 + 0310 i 0391 + 0310 i
13 0107 + 0543 i 0107 + 0543 i 015f + fdf6 i 015f + fdf5 i
14 0327 + 0145 i 0327 + 0144 i fefd + ff9a i fefc + ff9a i
15 016f + ff41 i 016f + ff40 i ffb6 + 0050 i ffb6 + 004f i
16 002d + ff23 i 002d + ff23 i 0021 + 0073 i 0022 + 0072 i
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TABLE-5.4
COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULTS FOR ROTATION ANGLE OF 900 AND 1200
Sample No.
MATLAB Simulation Results for α = 900
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 900
MATLAB Simulation Results for α = 1200
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 1200
01 ffae + 0000 i ffae + ffff i 006b + fffb i 006b + fffb i
02 0052 + 0010 i 0051 + 0010 i 0021 + ff8d i 0021 + ff8d i
03 ffae + ffde i ffae + ffde i ffb6 + ffb0 i ffb6 + ffb0 i
04 0054 + 0037 i 0053 + 0037 i fefd + 0066 i fefc + 0065 i
05 ffaa + ffaa i ffaa + ffaa i 015f + 020a i 015f + 0209 i
06 005b + 0088 i 005a + 0087 i 0392 + fcf0 i 0391 + fcef i
07 ff91 + fef4 i ff91 + fef4 i fca3 + f96e i fca3 + f96d i
08 fdc1 + f4b5 i fdc1 + f4b4 i f96e + fe73 i f96d + fe73 i
09 0000 + 0000 i 0000 + 0000 i fe35 + 00a8 i fe34 + 00a7 i
10 fdc1 + 0b4b i fdc0 + 0b4b i 0458 + 0061 i 0458 + 0061 i
11 ff91 + 010c i ff91 + 010b i 0318 + 0775 i 0318 + 0774 i
12 005b + ff78 i 005a + ff78 i fa9c + 02a8 i fa9b + 02a7 i
13 ffaa + 0056 i ffaa + 0055 i ff4d + fcd1 i ff4c + fcd1 i
14 0054 + ffc9 i 0053 + ffc8 i 01ac + fffd i 01ab + fffc i
15 ffae + 0022 i ffae + 0021 i ffc0 + 0143 i ffbf + 0143 i
16 0052 + fff0 i 0051 + ffef i ff4d + ff5c i ff4c + fff5c i
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TABLE-5.5
COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULTS FOR ROTATION ANGLE OF 1500 AND 1800
Sample No.
MATLAB Simulation Results for α = 1500
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 1500
MATLAB Simulation Results for α = 1800
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 1800
01 009d + ff19 i 009d + ff18 i 0000 + 0000 i 0000 + 0000 i
02 002d + 00dd i 002d + 00dd i 0000 + 0000 i ffff + 0000 i
03 016f + 00bf i 016e + 00bf i fd90 + 0000 i fd90 + ffff i
04 0327 + febb i 0327 + febb i fb8b + 0000 i fb8a + 0000 i
05 0107 + fabd i 0107 + fabc i fa4b + 0000 i fa4a + 0000 i
06 fbdb + fb0c i fbdb + fb0c i fa09 + 0000 i fa08 + ffff i
07 faa1 + fe54 i faa1 + fe53 i face + 0000 i facd + 0000 i
08 fc08 + ffcb i fc07 + ffcb i fc79 + 0000 i fc78 + 0000 i
09 fea2 + 003d i fea1 + 003c i fec1 + 0000 i fec1 + 0000 i
10 01b8 + 0015 i 01b8 + 0015 i 013f + 0000 i 013f + ffff i
11 03c5 + 0193 i 03c5 + 0192 i 0387 + 0000 i 0387 + ffff i
12 03c5 + 043d i 03c4 + 043d i 0532 + 0000 i 0532 + 0000 i
13 ff06 + 066f i ff06 + 066e i 05f7 + 0000 i 05f7 + ffff i
14 fad1 + 0142 i fad0 + 0141 i 05b5 + 0000 i 05b5 + ffff i
15 fe1f + fd93 i fe1f + fd93 i 0475 + 0000 i 0475 + 0000 i
16 000e + fea2 i 000e + fea2 i 0271 + 0000 i 0271 + ffff i
VLSI Architecture for Discrete Fractional Fourier Transform
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TABLE-5.6
COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULTS FOR ROTATION ANGLE OF 2100 AND 2400
Sample No.
MATLAB Simulation Results for α = 2100
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 2100
MATLAB Simulation Results for α = 2400
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 2400
01 009d + 00e7 i 009c +00e6 i 006b + 0005 i 006b + 0004 i
02 002d + ff23 i 002d + ff22 i 0021 + 0073 i 0021 + 0072 i
03 016f + ff41 i 016e + ff40 i ffb6 + 0050 i ffb5 + 004f i
04 0327 + 0145 i 0327 + 0144 i fefd + ff9a i fefc + ff9a i
05 0107 + 0543 i 0107 + 0543 i 015f + fdf6 i 015f + fdf5 i
06 fbdb + 04f4 i fbda + 04f3 i 0392 + 0310 i 0391 + 0310 i
07 faa1 + 01ac i faa0 + 01ac i fca3 + 0692 i fca3 + 0692 i
08 fc08 + 0035 i fc08 + 0034 i f96e + 018d i f96e + 018c i
09 fea2 + ffc3 i fea1 + ffc3 i fe35 + ff58 i fe35 + ff57 i
10 01b8 + ffeb i 01b7 + ffea i 0458 + ff9f i 0457 + ff9e i
11 03c5 + fe6d i 03c5 + fe6d i 0318 + f88b i 0318 + f88b i
12 03c5 + fbc3 i 03c5 + fbc2 i fa9c + fd58 i fa9b + fd59 i
13 ff06 + f991 i ff06 + f991 i ff4d + 032f i ff4c + 032e i
14 fad1 + febe i fad0 + febd i 01ac + 0003 i 01ab + 0002 i
15 fe1f + 026d i fe1f + 026d i ffc0 + febd i ffc0 + febc i
16 000e + 015e i 000e + 015e i ff4d + 00a4 i ff4d + 00a3 i
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Indian Institute of Information Technology, Allahabad 51 | P a g e
TABLE-5.7
COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULTS FOR ROTATION ANGLE OF 2700 AND 3000
Sample No.
MATLAB Simulation Results for α = 2700
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 2700
MATLAB Simulation Results for α = 3000
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 3000
01 ffae + 0000 i ffae + ffff i 006b + fffb i 006b + fffb i
02 0052 + fff0 i 0052 + ffef i ff4d + ff5c i ff4c + ff5c i
03 ffae + 0022 i ffae + 0021 i ffc0 + 0143 i ffbf + 0143 i
04 0054 + ffc9 i 0053 + ffc8 i 01ac + fffd i 01ab + fffc i
05 ffaa + 0056 i ffaa + 0055 i ff4d + fcd1 i ff4c + fcd1 i
06 005b + ff78 i 005a + ff78 i fa9c + 02a8 i fa9b + 02a7 i
07 ff91 + 010c i ff91 + 010b i 0318 + 0775 i 0318 + 0074 i
08 fdc1 + 0b4b i fdc0 + 0b4b i 0458 + 0061 i 0458 + 0061 i
09 0000 + 0000 i 0000 + 0000 i fe35 + 00a8 i fe34 + 00a7 i
10 fdc1 + f4b5 i fdc0 + f4b4 i f96e + fe73 i f96d + fe73 i
11 ff91 + fef4 i ff91 + fef4 i fca3 + f96e i fca3 + f96d i
12 005b + 0088 i 005a + 0087 i 0392 + fcf0 i 0392 + fcf0 i
13 ffaa + ffaa i ffaa + ffaa i 015f + 020a i 015f + 020a i
14 0054 + 0037 i 0053 + 0036 i fefd + 0066 i fefc + 0065 i
15 ffae + ffde i ffae + ffde i ffb6 + ffb0 i ffb6 + ffb0 i
16 0052 + 0010 i 0051 + 0010 i 0021 + ff8d i 0021 + ff8d i
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TABLE-5.8
COMPARISON OF MATLAB AND XILINX-ISE SIMULATION RESULTS FOR ROTATION ANGLE OF 3300 AND 3600
Sample No.
MATLAB Simulation Results for α = 3300
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 3300
MATLAB Simulation Results for α = 3600
Xilinx-ISE Simulation Results of Proposed
Architecture for α = 3600
01 009d + ff19 i 009d + ff18 i 0000 + 0000 i 0000 + 0000 i
02 000e + fea2 i 000e + fea1 i 0271 + 0000 i 0270 + 0000 i
03 fe1f + fd93 i fe1f + fd93 i 0475 + 0000 i 0474 + 0000 i
04 fad1 + 0142 i fad0 + 0141 i 05b5 + 0000 i 05b4 + 0000 i
05 ff06 + 066f i ff06 + 006e i 05f7 + 0000 i 05f7 + 0000 i
06 03c5 + 043d i 03c4 + 043d i 0532 + 0000 i 0531 + 0000 i
07 03c5 + 0193 i 03c5 + 0192 i 0387 + 0000 i 0387 + 0000 i
08 01b8 + 0015 i 01b8 + 0015 i 013f + 0000 i 013f + 0000 i
09 fea2 + 003d i fea1 + 003c i fec1 + 0000 i fec1 + 0000 i
10 fc08 + ffcb i fc07 + ffcb i fc79 + 0000 i fc78 + 0000 i
11 faa1 + fe54 i faa1 + fe53 i face + 0000 i facd + 0000 i
12 fbdb + fb0c i fbdb + fb0c i fa09 + 0000 i fa09 + 0000 i
13 0107 + fabd i 0107 + fabc i fa4b + 0000 i fa4b + 0000 i
14 0327 + febb i 0327 + febb i fb8b + 0000 i fb8a + 0000 i
15 016f + 00bf i 016f + 00bf i fd90 + 0000 i fd90 + 0000 i
16 002d + 00dd i 002d + 00dd i 0000 + 0000 i ffff + 0000 i
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The MATLAB simulation results are presented in Fig.5.2 to fig 5.15.The
simulated output with timing has been shown in Appendix-A. This shows that the
proposed architecture takes latencies of 19 clock cycles (14 clock cycles for Level-I
and 5 clock cycles for both Level-II and Level-III discussed in previous section). The
Results shows that the signal is rotating in time frequency plane. When the rotation
angle is zero the output results is same as input means it acts as a identity operator.
When the rotation angle is 900, the output result is same as the Fourier transform of
the given input signal. When the rotation angle is 1800, the signal is time inverted.
For the final rotation angle 3600, the output result is same as the input means the
fractional Fourier transform acted as an identity operator.
Implementation results:
Finally the proposed design has been synthesized using Xilinx XST tool,
targeting a FPGA device (XLV5LX110T) [40]. The synthesis results obtained for
hardware has been presented in Table-5.9. And the device utilization summary report
is presented in Table-5.10.
TABLE-5.9
HDL SYNTHESIS REPORT- MACRO STATISTICS
Component Name Number of Components
16×64bitROM 2
Multipliers 69
Adders/Subtractors 104
16 to 1 Multiplexers 2
Counters 2
Registers 217
Accumulators 33
The synthesis report in this table-5.9 shows that the synthesis results for hardware
requirement are approximately same as the theoretical results. Timing report of this
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad 54 | P a g e
implementation shows that the proposed design can be operated at maximum
frequency of 217MHz.
The proposed architecture in this paper has been compared with the architecture
presented in [27] for N=1024. The comparison for hardware and timing has been
highlighted in Table-5.11.
TABLE-5.10
DEVICE UTILIZATION-SUMMARY REPORT
Selected Device : 5vlx110tff1136-3
Slice Logic Utilization:
Number of Slice Registers: 5661 out of 69120 8%
Number of Slice LUTs: 3635 out of 69120 5%
Number used as Logic: 3417 out of 69120 4%
Number used as Memory: 218 out of 17920 1%
Number used as SRL: 218
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 7283
Number with an unused Flip Flop: 1622 out of 7283 22%
Number with an unused LUT: 3648 out of 7283 50%
Number of fully used LUT-FF pairs: 2013 out of 7283 27%
Number of unique control sets: 19
IO Utilization:
Number of IOs: 82
Number of bonded IOBs: 82 out of 640 12%
IOB Flip Flops/Latches: 16
Specific Feature Utilization:
Number of Block RAM/FIFO: 4 out of 148 2%
Number using Block RAM only: 4
Number of BUFG/BUFGCTRLs: 4 out of 32 12%
Number of DSP48Es: 36 out of 64 56%
VLSI Architecture for Discrete Fractional Fourier Transform
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TABLE-5.11
COMPARISON OF PROPOSED ARCHITECTURE WITH [27]
FOR 1024-POINT DFRFT
Hardware requirement
Component Name Number of Components
Architecture in [27] Proposed Architecture
Multipliers 1048576 4101
Adders/ Subtactors 1048576 4144
Registers 5242880 12280
Multiplexers 3072 (2:1 Mux)
3072 (4:1 Mux) 2 (1024:1 Mux)
Counters Not Mentioned 2
Timing details
Maximum speed 99.58 MHz 217.39 MHz
Sampling frequency 33.00 MHz 217.39MHz
This shows that the proposed design in this paper is better in terms of hardware
complexity and timing compared to architecture presented in [27].
VLSI Architecture for Discrete Fractional Fourier Transform
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Chapter 6
Conclusion and Future work
his thesis added an additional value to the conventional Fourier transform with a novel architecture of its generalized form which widens its applications range. The architecture achieves a better tradeoff between the area and timing
constraints that suitable for many applications. In signal, image processing applications like optimal filtering, optimal receivers, multiplexing, modulation and demodulation, image encryption, image compression and image restoration applications it is necessary to have flexibility to change the rotation angle along with fixed input vector length, which is achieved with this thesis. The closeness of the Xilinx ISE simulation results with the MATLAB simulations have been ensures its accuracy. This work achieved better results in terms of both hardware optimization and timing issues without compromising the accuracy of the results.
Future scope:
• The variable length fractional Fourier transform that is suitable for most of the applications.
• ASIC implementation of this proposed architecture for improvement of timing performance.
T
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Chapter 6
Conclusion and Future work
his thesis added an additional value to the conventional Fourier transform with a novel architecture of its generalized form which widens its applications range. The architecture achieves a better tradeoff between the area and timing
constraints that suitable for many applications. In signal, image processing applications like optimal filtering, optimal receivers, multiplexing, modulation and demodulation, image encryption, image compression and image restoration applications it is necessary to have flexibility to change the rotation angle along with fixed input vector length, which is achieved with this thesis. The closeness of the Xilinx ISE simulation results with the MATLAB simulations have been ensures its accuracy. This work achieved better results in terms of both hardware optimization and timing issues without compromising the accuracy of the results.
To make this novel architecture most beneficial we recommend addition of flexibility to this tool in terms of its input vector length. By making the vector length flexible this architecture has been a singular for many applications. We conclude this chapter with the recommendation of variable length discrete fractional Fourier transform as future scope of work.
T
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VLSI Architecture for Discrete Fractional Fourier Transform
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VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad 62 | P a g e
Appendix-A
Xilinx-ISE Simulation Results of Proposed DFrFT Architecture
ilinx 10.1i – ISE Simulation results of the 16-point DFrFT with the sinusoidal input for the rotation angles (fractional values) of 00(0.00), 300(0.33), 600(0.67), 900(1.00), 1200(1.33), 1500(1.67), 1800(2.00),
2100(2.33), 2400(2.67), 2700(3.00), 3000(3.33), 3300(3.67) and 3600(4.00). The first and final inputs are sampled at 740ns and 1035ns. The simulation results are started to give from 1950ns to 2250ns as sown in fallowing figures fig.a.1 to fig.a.14. In the each figure the first and final samples are labeled.
X
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad 63 | P a g e
Fig.
a.1:
The
Inpu
t Sam
ples
for t
he S
imul
atio
n of
pro
pose
d D
FrFT
arc
hite
ctur
e us
ing
‘Xili
nx IS
E’ S
imul
ator
Fig.
a.2:
The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘0
0 ’ usi
ng ‘X
ilinx
ISE’
Sim
ulat
or
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad 64 | P a g e
Fig.
a.3:
The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘3
00 ’ usi
ng ‘X
ilinx
ISE’
Sim
ulat
or
Fig.
a.4:
The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘6
00 ’ usi
ng ‘X
ilinx
ISE’
Sim
ulat
or
Fig.
a.5:
The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘9
00 ’ usi
ng ‘X
ilinx
ISE’
Sim
ulat
or
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad 65 | P a g e
Fig.
a.8:
The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘1
800 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
Fig.
a.7:
The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘1
500 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
Fig.
a.6:
The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘1
200 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad 66 | P a g e
Fig.
a.11
: The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘2
700 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
Fig.
a.10
: The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘2
400 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
Fig.
a.9:
The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘2
100 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad 67 | P a g e
Fig.
a.14
: The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘3
600 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
Fig.
a.13
: The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘3
300 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
Fig.
a.12
: The
Sim
ulat
ion
Res
ult o
f pro
pose
d D
FrFT
arc
hite
ctur
e fo
r Rot
atio
n an
gle
of ‘3
000 ’ u
sing
‘Xili
nx IS
E’ S
imul
ator
VLSI Architecture for Discrete Fractional Fourier Transform
Indian Institute of Information Technology, Allahabad 68 | P a g e
Publications M.V.N.V.Prasad, K.C.Ray and A.S.Dhar, “FPGA Implementation of Discrete
Fractional Fourier Transform” International Conference on Signal Processing and
Communications, IISc, Bangalore, India, July 17-21, 2010. Accepted.