Mtech Seminar Rprt

1.INTRODUCTION

With the scalingof semiconductor process technology, theperformanceofmodern VLSIchipsimproves significantly.Wehaveseen operatingfrequenciesof integratedcircuits reachmulti-gigahertz,resultinginmorerigorous timingrequirements. Timing related defects originated from manufacturing process-related problems, such as resistive opens and shorts, metal mousebites, viavoids, etc.,willbecomemorecommon. Consequently,delayfaultscausedby thesephysical defects,which preventthe circuit from meeting the timing requirements, are of growing concern in nanometer technologies.Moreover,itshouldbenoted thatthemanufacturingprocessisbecoming moredifficulttobecontrolledwith theincreasingcomplexity ofmodernVLSIchips. Therefore,electrical parameters,such assaturation current,gatecapacitance,threshold voltage,etc.,mayvaryfromonedevicetoanother.Asaresult,thedelayof gatesand timing-critical pathswillhavelargevariationsandcanhardlybepredictedduring the designstagedueto the imprecisionofverification models. Furthermore, thecircuit timingwouldalsobeby theapplicationenvironmentconditionssuchastemperature, impactedsupplyvoltagenoise,etc.Hence thereisan urgentneed toconducteffective delaytestingforascertainingthecorrectoperationofchips atthe ratedfrequency.Delay faults are a category of faults which cause functional chip to fail at specifiedclockspeedandtheobjectiveofdelayfaulttestinganddebugis todetecttiming defects andensurethatthedesignmeets thedesiredperformancespecifications.Although timingverification andfunctionalsimulation during thedesign cycle ensurethatachip meetsitsperformancespecifications,itshouldbenotedthatthesetechniquesareapplied toamodelof anIntegratedCircuit(IC)andnottoactualsiliconandhencecannotdetect delayfaultswhich arecausedbyfactorslikecrosstalkinduceddelay,excessivevoltage drop andswing on thesupplynets,etc.Additionally,processvariationscanhavea significantinfluenceonachipsfailuretomeetspecifiedperformance.Process parameter variations canresultindistributeddelayfaultsinthechip, whichcauseminordelayfaults onmultiplegatesin agiven path toaccumulateandresultin thepathfailing tomeet performance specifications. Adding moredetails tomodels ofanICtoincorporate thesefactors willcausecomputational

costsoftimingverificationmethods tobecome prohibitive.Diminishingfeaturesizeslimittheobservabilityofchips,makingtestand debugmoredifficultespeciallyfortimingviolations.Theuseof on-chiptestingcircuitry allowsforat-speedtestingessentialforaccuratedetectionoftimingviolations.

CMOS Digital Intergrated Circuits-TermworkHighPrecisionOCDM ArchitectureThe on-chip path delay measurement techniques have been gained many attentionsforresearchersinrecentyears,foritcanprovideacost-effectivealternative waytoperformdelaydefectdetectionandsilicondebuginmodernVLSI chips.Valuable information,which pointstheperformancelimiterandcircuitfailure,canbe obtainedby theon-chippathdelaymeasurementtechniquewithamuchhigherconfidence.

Amrita School of Engineering, CoimbatoreDept.ofECE4

2.COMPARISON WITHRELATED WORKS

Severalarchitectureshavealreadybeenproposedfordelaytestingand silicon debug.Oneofthosewhicharecloselyrelatedtothisworkis themodifiedVernierDelay Line(VDL)techniqueforpath delaymeasurement.However;theVDLbased techniques havesomedisadvantages [1].AtypicalVDLis showninFig2.1.

Fig.2.1TypicalVernier Delay Line

Herethemaximumdelaythatcanbemeasuredislimitedton (td1-td2).

Fig.2.2ModifiedVDL

Theauthorsaremotivatedby thefactthatalthough VDL-basedtechniquescan providehighdelaymeasurementresolution,it,however,needslots ofstages toachievea largemeasurementrange [2].Asaresult,thehardwareoverheadsof thesetechniquesare considerable.Also,due tothemanystages,readingoutthemeasurementresultsstoredin theVDLneedsalotof scanclockcycles,thusthewholedelaymeasurementprocessis time-consuming.Moreover,thedelaysoftheimportlines,whichareusedforfeedingthe PUMintothepathdelaymeasurementunit,shouldbetakenintoaccounttoavoidtheloss of precisionfordelaymeasurementof circuitpaths.Inthispaper,itispresentedanon- chippathdelaymeasurement(OCDM)circuit,inwhichthedelayrangesof delaystages areincreasedbyafactor oftwograduallyfrom thelasttothefirstdelaystage.Thetime differenceof twoinputsignalsinthenextdelaystagereliesonthestoredvalueof the currentdelay stage.Further,itisproposedadelay calibration techniquetocalibratethe delaydifferenceoftheimportlinesforfeedingthePUMintotheOCDMcircuit.The maincontributions ofthis workcanbelistedinthefollowing:1)Without decreasingthedelaymeasurement resolution,theproposedapproachcan expanddelay measurementrangemuch easierwith significantlylesshardwareoverhead comparedtoprevious VDL-baseddelaymeasurementapproaches.Bykeepingasmall quantity ofthedelaystages,theproposedapproachcanalsoachieveshortdelay measurementtime.2) A calibration circuit and a signal transition converter are incorporated into the proposed on-chippath delaymeasurementarchitecture,thereby providingamoreprecise andeffectivewayforpathdelaymeasurement.3)Foreachoftheflip-flopsexistedattheendpoints ofthePUMs,a2-to-1multiplexeris added.Thedatainputs ofthe2-to-1multiplexerareconnectedtothedata-inputanddata- outputoftheflip-flop,respectively.Bythisway,thedelaydifferenceoftheimportlines, whichareusedforconnecting thePUMintothepath delaymeasurementunit,canbe calibrated.Henceahighprecisionofpathdelaymeasurementis guaranteed.

3.OCDMCIRCUIT

ThepurposeoftheproposedOCDMcircuitistoreducethenumberofdelay stagesintheVDL,thustoachieveasignificantlylesshardwareoverheadaswellaslessdelaymeasurementtime [3].TheproposedOCDM circuitis shownbelow.

Fig.3.1.ProposedOCDM circuit

3.1 Structureandoperation

ThebasicstructureoftheproposedOCDM circuitisshowninFig.3.1,whichcan convertthepath delay ofthePUMintoaseriesofdigitalvaluesthatcanbestoredin the flip-flopsof theVDL chain.EachdelaystageconsistedintheVDL chainisconstructed byapositiveedgetriggeredD-typeflip-flop,fourmultiplexers,andseveralbuffers.In theproposedOCDMcircuit,itisassumedthattheinputxisfedbytheoutputofthe PUM,whiletheinputyisfedbytheinputofthePUM.Soalwaysyswitchesearlierthan xdoesduringthedelaymeasurementperiod.Inordertoexplaintheoperationof the OCDM circuit,lets considerthecasethatboththeinputandoutputsignalsofthePUM

are risingtransitions.

Theupperdelayunit(UDU)refers tothebuffer chainthatstarts attheinputofthe delaystageatwhichthetransitionsignalispropagatedfromnodey,andendsatthe inputofthemultiplexerwhoseoutputisconnectedtothedatainputoftheflip-flopin eachdelaystageof theOCDMcircuit.Thelowerdelayunit(LDU)issimilartoUDU, exceptthat it startsatthe input ofthedelaystageat whichthetransitionsignalis propagatedfromnodex andendsattheinputof anothermultiplexerwhoseoutputis connectedtotheclockinputoftheflip-flopineachdelaystage.Thedelayrangeis definedasthedelaydifferencebetweenthetwodelayunitsineachdelaystageof the OCDM circuit.FromthelaststagetothefirststageoftheOCDM circuit,thedelayrange ofeachstageisincreasedbyafactoroftwo.Supposetheinputandoutputsignalsof theupperdelaychaininthefirstdelay stage arey1 andy2,respectively,accordingly,x1andx2areassumedforthelowerdelay chain. All flip-flops ofthe OCDM circuit are initialized to logic ZERO values by assertingtheresetsignal.Thedelaymeasurementmodeisactivatedbyassertingthe mode signal.Asx1andy1 signals propagatethroughtheirrespectivedelayunits,thetime differencebetweenthetwo signals willbereduced.

Fig.3.2.Relationshipbetweentimedifferenceoftwoinputsignals andthatoftwo outputsignals inthefirstdelaystage.(a)LogicONE intheflip-710flop. (b) Logic ZEROinthe flip-flop.

As showninFig.3.2(a),assumingthatx1 signallagsthey1signalbyenoughtime (i.e.,y1switchesmuchearlier),andhencealogic-highvalue willbeholdintheflip-flop. Asaresult,y2willbethesignalthatpassesthroughtheUDUandthebufferBUFBin theupperdelay chainfromy1,whilex2willbethesignal thatpassesthrough theLDU andthebufferBUFBinthelowerdelay chainfromx1.Thedelay ofBUFBislarge enoughtoensurethatastablelogichighvaluecanbestoredintheflip-flopbeforethe twotransitionsignalsarriveattheinputs ofthemultiplexers whoseoutputs areconnected totheinputsofthenextdelaystage.Clearly,thetimedifferencebetweenandisreduced byanamountwhichequals thedelayrangeofthis delaystage.ThebuffernamedBUFAineachdelay stagehasadelayvaluethatislargerthan thecumulativedelayof thepaththatcontainsLDUandBUFBof thesamedelaystage. Likewise,ifthetimedifferenceofy1andx1issmallerthan thedelayrange,theflip-flop willholdlogicZEROvalue.Therefore,thesignalspropagatingthroughBUFA are then selectedby themultiplexers.Asaresult,thetimedifferencebetweeny2andx2willbe equaltothatofy1andx1,as showninFig.3.2(b).Consequently,theprincipleof theOCDMcircuitis thatifthetimedifference betweenthetwoinputsofeachdelaystageislargerthanthedelayrangeofthesame stage,alogicONEvaluewillbestoredintheflip-flopof thedelaystage.Thetime differencebetweenthetwooutputsignals willbeupdatedbysimply subtractingthedelay rangefromthatbetweentheinputsignalsofthedelaystage.Otherwise,theflip-flopof thedelaystage willholdalogicZEROvalue,andthetimedifferencebetween theoutput signals willkeepthesameas thatbetweentheinputsignals ofthedelaystage.Notethatthereexistsasetuptimeinthestoreblockof eachdelaystageasshown inFig.3.1,whichconsistsof aDflip-flopandtwomultiplexers.If thetimedifference betweenthetwoinputsof thestoreblockissmallerthanthesetuptime,anerrorlogic value may be hold in the flip-flop. Therefore, inorder to provide better delay measurementprecision,the DCUnitcellconstructedby twobufferlinesisproposedfor delaycompensation,whichmeansthattheupperandlowerdelayunitsof DCUnitare designedsuch thatthedelay differencebetween themisapproximatelyequalto thesetup time.

Thevaluesstoredinthedelaylinecanbeshiftedoutseriallyusingtheclock signalshiftclkintheshiftmodebyde-assertingthemodesignal.Thedelay ofthePUM canthenbeobtained.

3.2DelayRangeCalibration

Thedelayrangeof eachdelaystageintheOCDMcircuitwouldbevarieddueto theprominentprocessvariations.Itisthusnecessarytocalibratethedelayrangesto assuretheprecisionofpathdelaymeasurementresultbeforeusingtheOCDMcircuit. Fig.3.3shows thebasicstructureof thecalibrationcircuit,whichcanbeembeddedinto theOCDMcircuit fordelayrangecalibration.Theoutputsofthecalibrationcircuit, denotedasy andx,aredirectlyconnectedtotheinputswiththesamenotationsofthe OCDMcircuit,respectively.Twoinputs ofthecalibrationcircuit,denotedaspinandpout, arefedbytheinputandoutputof thePUM,respectively.Clearly,whentheCSsignalis setto1,thegeneratedtransitionsatthey andxcanbesentintotheOCDMcircuitfor delaymeasurement.When theCSsignalissetto0,thedelay range calibration processis conducted.

Fig.3.3. Calibrationcircuit

Fig.3.4.Timingwaveformfor calibrationcircuit

Thesimplifiedtimingwaveformforthedelay rangecalibrationisshownin the Fig.3.4.TheFF1andFF2arerisingandfallingedgetriggeredflip-flops respectively. First,theflip-flopsof FF1andFF2areinitiatedwithlogicZERObytheresetsignal. Then,logicONEwillbeloadedintotheFF1andFF2bytherisingandfallingedgesof theclocksignal respectively.Clearly,thetimedifferencebetween thegeneratedrising transitionsatyandxisequaltothewidthofthepositivehalfcycleoftheclocksignal. Thetimeperiodofthe clocksignalcanbe programmeddeterministicallywith high resolutionusingtheon-chipclockgenerator.Assumingthenumberof delaystagesintheOCDMcircuitism.Thefollowing presentsthecalculationmethodforobtainingthedelayrangeofeachdelaystage,which is describedby Eq.3.1:a11x1+a12x2++a1mxm =b1

a21x1+a22x2++a2mxm =b2

..

am1x1+am2x2+..+ammxm =bm ..(3.1)

Let

Wehave

AX=B(3.2)

wherexj(1