MSP430_B3

MSP430

August 18, 2013

MSP430 1

Outline

Ultra low power features and Introduction Architecture Functions, Interrupts, low power modes Digital input output On chip Peripherals Interfacing

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Factors contributing to power consumption

Power= Vcc Icc Clock frequency Dynamic power Current leakage Peripherals

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Ultra low power features

Flexible clock system

ACLK auxillary clock > crystal (32khz) , VLO (12khz) MCLK >main clock (100khz to 25Mhz) SMCLK > sub main clock ( DCO, external clk source)

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Ultra low power features

Multiple operating modes

Need for different modes:1 Processor not running2 Peripherals might be idle

Ultra low power stand by mode Minimum active duty cycle

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Ultra low power features

Instant wake up

Ultra fast wake up of DCO

Ultra low power features

Zero power BOR

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Ultra low power features

Other features

Intelligent peripherals1 SMCLK2 Generate PWM signals, takes ADC samples

Low pin leakage

Pin out

More than 1 function Same function on more than 1 pin TCLK,TMS,TDI,TDO,TEST pins JTAG interface SBWTDIO,SBWTCK Spy Bi wire interface A0-,A0+,...A4+,A4- ADC SCLK,SD0,SCL universal serial interface

Figure: Pin-out of the MSP430F2003 and F2013

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Functional Block diagram

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Memory map

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Nomenclature

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Architecture

Central Processing Unit

16 bit RISC CPU Von Neumann architecture 3 stage instruction pipeline 16 bit ALU, 16 registers

1 R0: Program Counter2 R1: Stack Pointer3 R2: Status Register4 R2/R3: Constant

Generator Registers5 R4 - R15: General

Purpose Registers

Figure: MSP430 CPU block diagram

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Architecture

Addressing modes

7 addressing modes for source 4 for destination

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Architecture

Instruction set

Orthogonal instruction set 27 core instructions

1 Double operand2 Single operand3 Program flow control

24 emulated instructions Byte, word and address instructions

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Functions and subroutines

Functions and Subroutines are lines of code that you use morethan once

Functions are used in C ,subroutines used in ALP Local variables are used only when a function is called

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What happens when a subroutine is called?

The return address to be pushed on to the stack The address of the subroutine is then loaded into the PC and

execution continues from there

At the end of the subroutine the ret instruction pops thereturn address off the stack into the PC

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Storage of local variables

CPU registers are simple and fast To use a fixed location in RAM Disadvantages:

The space in RAM is reserved permanently, even when thefunction is not being called, which is wasteful.

The function is not reentrant. To allocate variables on the stack and is generally used when

a program has run out of CPU registers

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Program- example

%Subroutine from substk 0.s43, which now saves and restores R4 correctly

; Subroutine to give delay of R12 *0.1s

; Parameter is passed in R12 and destroyed

; R4 used for loop counter, stacked and restored

-----------------------------------------------------------------------

DelayTenths:

push.w R4 ; Stack R4: will be overwritten

jmp LoopTest ; Start with test in case R12 = 0

OuterLoop:

mov.w #DELAYLOOPS ,R4 ; Initialize loop counter

DelayLoop: ; [clock cycles in brackets]

dec.w R4 ; Decrement loop counter [1]

jnz DelayLoop ; Repeat loop if not zero [2]

dec.w R12 ; Decrement number of 0.1s delays

LoopTest:

cmp.w #0,R12 ; Finished number of 0.1s delays?

jnz OuterLoop ; No: go around delay loop again

pop.w R4 ; Yes: restore R4 before returning

Ret ; Return to caller

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Stack Operation

Figure: Stack operation

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Low power Operation

Very low power leakage, and it operates from a single supply rail Low current drain in standby mode Useful because it shuts down certain areas of the CPU in order to save power As the LPM mode rises power consumption decreases, the time needed to wake

up increases

The MSP430 is switched into a low power mode by altering bits in the statusregister

Processing within an interrupt routine will determine when the processor needsto change from a low power mode to normal operation, and alters those samestatus register bits to achieve that

It does this by directly modifying the memory location where the processorsstatus register was pushed onto the stack at the start of the interrupt

When the interrupt routine returns, using the RETI instruction, the alteredstatus register value is loaded into the processor status register, and theprocessor continues operation in the newly selected mode

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MSP430 modes of operation

LPM0 - The CPU is disabled. LPM1 - The loop control for the fast clock (MCLK) is also disabled. LPM2 - The fast clock (MCLK) is also disabled. LPM3 - The DCO oscillator and its DC generator are also disabled. LPM4 - The crystal oscillator is also disabled. The most popular 3 are the

following

1 Active mode (AM), I = 300 uA

All clocks are active2 Low-power mode 0 (LPM0), I = 85uA

CPU is disabled ACLK and SMCLK remain active, MCLK is disabled

3 Low-power mode 3 (LPM3), I = 1uA

CPU is disabled MCLK and SMCLK disabled ACLK remains active DCOs dc-generator is disabled

As the number of the LPM mode number rises, the number of things disabledon the chip also rises

But interrupts can wake up the device from any low power mode, process, anddecide whether to restore the low power or active mode.

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Interrupts in MSP430

The MSP430 processor responds to an interrupt in 9 steps:

Completing the currently executing instruction Pushing the PC, program counter which points to the next instruction, onto the

stack

Pushing the SR, status register, onto the stack Selects the highest priority interrupt, if more than one is waiting execution The interrupt request flag resets automatically on single-source flags; multiple

source flags remain set for servicing by software

The SR is cleared; This terminates any low-power mode; because the GIE(interrupt enable) bit is cleared, further interrupts are disabled

The content of the interrupt vector is loaded into the PC; the programcontinues with the interrupt service routine (ISR) at that address

On executing a return from an ISR, the SR and PC are popped from the stack;returning to execute the instruction at the point of the interrupt

When the SR is restored, interrupts are re-enabled

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Interrupt Stack

Figure: Interrupt stack

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Interrupt vector table

The interrupt vector table is mappedat the very highest end of memoryspace (upper 16 words ofFlash/ROM), in locations 0FFE0hthrough to 0FFFEh

The MSP430 uses vectoredinterrupts where each ISR has itsown vector stored in a vector tablelocated at the end of programmemory

MSP430 requires 6 clock cyclesbefore the ISR begins executing

When interrupt occurs, thecorresponding flag (bit) is set to 1.

An interrupt handler should normallydisable the interrupt by setting flagto 0, allowing another interrupt tooccur

Figure: Interrupt vector table

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Digital I/O

8 bit digital I/O port Multifunctional capabilities Digital I/O features:

Independently programmable individual I/Os Individually configurable P1 and P2 interrupts Independent input and output data registers Individually configurable pullup or pulldown resistors

Pins P2.6 and P2.7 - not digital inputs by default Avoiding floating pins Parallel port

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P1 Digital I/O control

Digital I/O is user configurable

Input Register P1IN Output Register P1OUT Direction Register P1DIR Pullup/Pulldown Resistor Enable Register P1REN Function Select Register P1SEL Interrupt enable, P1IE Interrupt edge select, P1IES Interrupt flag, P1IFG

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On-chip peripherals: Outline

Mode of communication with outside world

MSP430 On-chip peripherals

1 Basic Timer1

2 Watchdog Timer

3 Real-time clock

4 Timer A, Timer B

5 Comparator A

6 ADC: ADC10, SD16 A

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Timers

Essential to almost every embedded application

Functions

1 Generate fixed-period events

2 Periodic wakeup

3 Count edges

4 Timer calls allow CPU to sleep, consuming much less power

MSP430 Timer modules

1 Basic Timer1

2 Watchdog Timer (WDT)

3 RTC

4 Timer A/B

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Basic Timer1

Present in all MSP430xF4xx devices BTCTL, counters not initialized by reset Provides clock for LCD module

Figure: Simplified block diagram of Basic Timer1

Figure: Basic Timer1 control register BTCTL

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Watchdog timer

Features

Up-counter Counts up and resets the MSP430 when it reaches its limit Always active after the MSP430 has been reset Protects the system against failure of software

Figure: Watchdog timer concept

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Watchdog timer

Figure: Watchdog timer circuitryMSP430 32

WDT operation

Controlled by 16-bit register WDTCTL Password WDTPW = 0x5A in the upper byte Software reset

Figure: The lower byte of the watchdog timer control register WDTCTL

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Watchdog Timer

Important facts

Always active after the MSP430 has been reset Default period: 32,768 counts (32 ms) Counter (WDTCNTCL bit) must be repeatedly cleared:

petting, feeding, or kicking the dog

Interval Timer

Used when protective function is not desired Set the WDTTMSEL bit

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Real-Time Clock

Features

Added to recent devices in the MSP430xFxx family 32-bit counter mode with selectable clock sources Calendar and clock mode Automatic counting of seconds, minutes, hours, day of week,

month, year in calendar mode

Selectable BCD format Not an alarm clock

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Timer A Module

Features

Most versatile, general-purpose timer Async 16-bit timer/counter Selectable count mode Extensive interrupt capability Extensive connections to other modules

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Timer A Module

Figure: Simplified block diagram of Timer A

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Timer A: Capture mode

Measure time before a signal event occurs

Input signal sources

External pin Internal signal (i.e., Comp A) Vcc/GND

Applications

Analog signal rising to Comp A threshold Slope ADC Frequency measurement Vcc threshold detect (via voltage divider)

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Timer A: Compare Mode

Cause an event after a defined period (exact opposite of capturemode)

Event kinds

CPU interrupt Modules tied internally to timer output (DMA, start

ADC/DAC conversion)

External components

Applications

PWM generation RTC Timer A UART

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Timer A: Count Modes

Modes

Continuous: Up to FFFF, rolls over to 0000, back up to FFFF Up: Up to value specified by CCR0, rolls over to 0000, back

up to CCR0 value

Up/down: Up to value specified by CCR0, count down to0000, back up to CCR0 value

Figure: Count modes of Timer A

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Timer B

Event kinds

Provided on larger devices in all MSP430 families Differences with Timer A

1 Registers are double buffered2 Range of periods can be selected for the Continuous mode3 Sampling mode is not possible (not suitable for receiving

asynchronous signals)4 All outputs can be put into a high-impedance state (TBOUTH

pin)

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Timer usages

Scenarios

PWM: Use Timer B if available, otherwise Timer A Less regular outputs: Connect directly to an output of

Timer A or B.

Inputs to be sampled at regular intervals: Connect to Timer A(Sampling mode)

Inputs to be timed: Timer A or B Periodic software interrupts

1 Watchdog timer (if it is not needed as a watchdog)2 Basic Timer13 Timer A or B

The last resort: Software loops

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Comparator A

Features

Supports precision slope analog-to-digital conversion Supply voltage supervision Monitoring of external analog signals Output provided to Timer A capture input Interrupt capability

Figure: Comparator A circuitry

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ADC10 Introduction

ADC10 module supports

1 Fast, 10-bit analog-to-digital conversions

2 Implements a 10-bit SAR core

3 Sample select control

4 Reference generator

5 Data transfer controller (DTC)

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Features of ADC10

Greater than 200-ksps maximum conversion rate

Monotonic 10-bit converter

Sample-and-hold with programmable sample periods

Conversion initiation by software or Timer A

Software selectable on-chip reference voltage generation(1.5 V or 2.5 V)

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Features of ADC10..2

Up to eight external input channels

Conversion channels for internal temperature sensor, VCC

Monotonic 10-bit converter

Separates programs into self contained tasks

Selectable conversion clock source

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10-Bit ADC Core What it does..

Converts an analog input to its 10-bit digitalrepresentation

Stores the result in the ADC10MEM register Configured by two control registers,

ADC10CTL0 and ADC10CTL1 Enabled with the ADC10ON bit.

ADC10CLK What the clk does..

Used both as the conversion clock and togenerate the sampling period

Selection using ADC10SSELx bits and divisionfrom 1 to 8 using the ADC10DIVx

ADC10OSC, generated internally, is in the5-MHz range

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Conversion Modes

CONSEQx Mode Operation

00 Single channel single-conversion single channel is converted once.01 Sequence-of-channels sequence of channels is converted once.10 Repeat single channel single channel is converted repeatedly.11 Repeat sequence-of-channels sequence of channels is converted repeatedly.

NADC = 1023 Vin VminV max Vmin

Stopping Conversions

Depends on the mode of operation Resetting ENC Or by default set CONSEQx = 0

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Different Registers of the ADC10

Figure: ADC10 Registers

Among the various registers, the control register comprises of thefollowing bits,

Figure: ADC10 Control Register

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SD16

Sigma Delta Convertors

1 Consists of up to three independent sigma-deltaanalog-to-digital converters

2 Each channel has up to 8 fully differential multiplexedanalog input pairs including a built-in temperature sensor

3 Built-in temperature sensor accessible by all channels

4 Selectable low-power conversion mode

5 Software selectable on-chip reference voltage generation(1.2 V)

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Interfacing

Hardware Demonstration

1 Blinking LEDs

2 Random Light Display- John Davies

3 ADC for thresholding using the 2 inbuilt LEDs

4 LCD shield - a note on energia

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References

1 MSP430 Microcontroller Basics, John Davies

2 www.ti.com/msp430

3 http://www.uniti.in/teaching-material/79

4 en.wikipedia.org/wiki/TI_MSP430

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