MPPT

Chapter 1 Introduction

Water resources are essential for satisfying human needs, protecting health, and ensuring food

production, energy and the restoration of ecosystems, as well as for social and economic

development and for sustainable development. However, according to the World Water

Development Report in 2003, it has been estimated that two billion people are affected by water

shortages in over forty countries, and 1.1 billion do not have sufficient drinking water. There

is a great and urgent need to supply environmentally sound technology for the provision of

drinking water. Remote water pumping systems are a key component in meeting this need. It

will also be the first stage of the purification and desalination plants to produce potable water. In

our project, a simple but efficient photovoltaic water pumping system is presented. It investigates

in detail the maximum power point tracker (MPPT), a power electronic device that significantly

increases the system efficiency.

1.1 Water Pumping Systems and Photovoltaic Power

A water pumping system needs a source of power to operate. In general, AC powered

system is economic and takes minimum maintenance when AC power is available from the

nearby power grid. However, in many rural areas, water sources are spread over many miles of

land and power lines are scarce. Installation of a new transmission line and a transformer to the

location is often prohibitively expensive. Windmills have been installed traditionally in such areas;

many of them are, however, inoperative now due to lack of proper maintenance and age. Today,

many stand-alone type water pumping systems use internal combustion engines. These systems

are portable and easy to install. However, they have some major disadvantages, such as: they

require frequent site visits for refueling and maintenance, and furthermore diesel fuel is often

expensive and not readily available in rural areas of many developing countries. The consumption

of fossil fuels also has an environmental impact, in particular the release of carbon dioxide (CO2)

into the atmosphere. CO2 emissions can be greatly reduced through the application of renewable

energy technologies, which are already cost competitive with fossil fuels in many situations. Good

examples include large-scale grid-connected wind turbines, solar water heating, and off-grid

stand-alone PV systems. The use of renewable energy for water pumping systems is, therefore, a

very attractive proposition. Windmills are a long-established method of using renewable energy;

however they are quickly phasing out from the scene despite success of large-scale grid-tied wind

turbines.

PV systems are highly reliable and are often chosen because they offer the lowest life-

cycle cost, especially for applications requiring less than 10KW, where grid electricity is not

available and where internal-combustion engines are expensive to operate.

1.2 Energy Storage Alternatives

Needless to say, photovoltaics are able to produce electricity only when the sunlight is available,

therefore stand-alone systems obviously need some sort of backup energy storage which

makes them available through the night or bad weather conditions. Among many possible storage

technologies, the lead-acid battery continues to be the workhorse of many PV systems because it is

relatively inexpensive and widely available. In addition to energy storage, the battery also has

ability to provide surges of current that are much higher than the instantaneous current available

from the array, as well as the inherent and automatic property controlling the output voltage of

the array so that loads receive voltages within their own range of acceptability. While batteries

may seem like a good idea, they have a number of disadvantages. The type of lead-acid

battery suitable for PV systems is a deep-cycle battery, which is different from one used for

automobiles, and it is more expensive and not widely available. Battery lifetime in PV systems is

typically three to eight years, but this reduces to typically two to six years in hot climate since

high ambient temperature dramatically increases the rate of internal corrosion. Batteries also

require regular maintenance and will degrade very rapidly if the electrolyte is not topped up and

the charge is not maintained. They reduce the efficiency of the overall system due to power

loss during charge and discharge. Typical battery efficiency is around 85% but could go below

75% in hot climate. From all those reasons, experienced PV system designers avoid batteries

whenever possible.

For water pumping systems, appropriately sized water reservoirs can meet the

requirement of energy storage during the downtime of PV generation. The additional cost of

reservoir is considerably lower than that incurred by the battery equipped system. As a

matter of fact, only about five percent of solar pumping systems employ a battery bank.

1.3 The Proposed System

The experimental water pumping system proposed in this thesis is a stand-alone type without

backup batteries. As shown in Figure 1-1, the system is very simple and consists of a single PV

module, a maximum power point tracker (MPPT), and a DC water pump. The size of the system

is intended to be small; therefore it could be built in the lab in the future. The system including

the subsystems will be simulated to verify the functionalities.

Figure 1-1: Block diagram of the proposed PV water pumping system

1.3.1 PV Module

There are different sizes of PV module commercially available (typically sized from 60W

to 170W). Usually, a number of PV modules are combined as an array to meet different

energy demands. For example, a typical small-scale desalination plant requires a few thousand

watts of power.

1.3.2 Maximum Power Point Tracker

The maximum power point tracker (MPPT) is now prevalent in grid-tied PV power

systems and is becoming more popular in stand-alone systems. It should not be confused

with sun trackers, mechanical devices that rotate and/or tilt PV modules in the direction of

sun. MPPT is a power electronic device interconnecting a PV power source and a load,

maximizes the power output from a PV module or array with varying operating conditions,

and therefore maximizes the system efficiency. MPPT is made up with a switch-mode DC-

DC converter and a controller. For grid-tied systems, a switch-mode inverter sometimes fills

the role of MPPT. Otherwise, it is combined with a DC-DC converter that performs the

MPPT function. In addition to MPPT, the system could also employ a sun tracker. According to

the data in reference, the single-axis sun tracker can collect about 40% more energy than a

seasonally optimized fixed-axis collector in summer in a dry climate. In winter, however, it can

gain only 20% more energy. The effect of sun tracker is smaller because a larger fraction of

solar irradiation is diffuse. It collects 30% more energy in summer, but the gain is less than

10% in winter. The two-axis tracker is only a few percent better than the single-axis version.

Sun tracking enables the system to meet energy demand with smaller PV modules, but it

increases the cost and complexity of system. Since it is made of moving parts, there is also a

higher chance of failure. Therefore, in this simple system, the sun tracker is not implemented.

Chapter 2 Photovoltaic Modules

2.1 Introduction

The history of PV dates back to 1839 when a French physicist, Edmund Becquerel,

discovered the first photovoltaic effect when he illuminated a metal electrode in an

electrolytic solution. Thirty-seven years later British physicist, William Adams, with his student,

Richard Day, discovered a photovoltaic material, selenium, and made solid cells with 1~2%

efficiency which were soon widely adopted in the exposure meters of camera. In 1954 the first

generation of semiconductor silicon-based PV cells was born, with efficiency of 6%, and

adopted in space applications. Today, the production of PV cells is following an exponential

growth curve since technological advancement of late ‘80s that has started to rapidly improve

efficiency and reduce cost. This chapter discusses the fundamentals of PV cells and modeling of a

PV cell using an equivalent electrical circuit. The models are implemented using MATLAB to

study PV characteristics and simulate a real PV module.

2.2 Photovoltaic Cell

Photons of light with energy higher than the band-gap energy of PV material can

make electrons in the material break free from atoms that hold them and create hole-electron

pairs, as shown in Figure 2-1. These electrons, however, will soon fall back into holes

causing charge carriers to disappear. If a nearby electric field is provided, those in the

conduction band can be continuously swept away from holes toward a metallic contact where they

will emerge as an electric current. The electric field within the semiconductor itself at the junction

between two regions of crystals of different type, called a p-n junction.

The PV cell has electrical contacts on its top and bottom to capture the electrons, as

shown in Figure 2-2. When the PV cell delivers power to the load, the electrons flow out of

the n-side into the connecting wire, through the load, and back to the p-side where they

recombine with holes. Note that conventional current flows in the opposite direction from

electrons.

2.3 Modeling a PV Cell

The use of equivalent electric circuits makes it possible to model characteristics of a PV

cell. The method used here is implemented in MATLAB programs for simulations. The same

modeling technique is also applicable for modeling a PV module.

Figure 2-1: Illustration of the p-n junction of PV cell Showing hole-electron pairs created by photons

Figure 2-2: Illustrated side view of solar cell and the conducting current

2.3.1 The Simplest Model

The simplest model of a PV cell is shown as an equivalent circuit below that consists of an ideal current source in parallel with an ideal diode. The current source represents the current generated by photons (often denoted as Iph or IL), and its output is constant under constant temperature and constant incident radiation of light.

There are two key parameters frequently used to characterize a PV cell. Shorting together the terminals of the cell, as shown in Figure 2-4 (a), the photon generated current will

Accumulated positive charge

Figure 2-3: PV cell with a load and its simple equivalent circuit

follow out of the cell as a short-circuit current (Isc). Thus, Iph = Isc. As shown in

Figure 2-4 (b), when there is no connection to the PV cell (open-circuit), the

photon generated current is shunted internally by the intrinsic p-n junction diode.

This gives the open circuit voltage (Voc). The PV module or cell manufacturers

usually provide the values of these parameters in their datasheets.

Figure 2-4: Diagrams showing a short-circuit and an open-circuit condition

The output current (I) from the PV cell is found by applying the Kirchoff’s current law (KCL) on the equivalent circuit shown in Figure 2-3.

IIsc Id (2.1)

where: Isc is the short-circuit current that is equal to the photon generated current, and Id is the current shunted through the intrinsic diode.

The diode current Id is given by the Shockley’s diode equation:

I d Io (eqV d / kT1) (2.2)

where: Io is the reverse saturation current of diode (A), q is the electron charge (1.602×10-19 C), Vd is

the voltage across the diode (V), k is the Boltzmann’s constant (1.381×10-23 J/K), T is the junction

temperature in Kelvin (K). Replacing Id of the equation (2.1) by the equation (2.2) gives the

current-voltage relationship of the PV cell.

I I sc Io(eqV / kT1) (2.3)

where: V is the voltage across the PV cell, and I is the output current from the cell.

The reverse saturation current of diode (Io) is constant under the constant temperature and found by setting the open-circuit condition as shown in Figure 2-4 (b). Using the equation (2.3), let I = 0 (no output current) and solve for Io.

To a very good approximation, the photon generated current, which is equal to Isc, is directly proportional to the irradiance, the intensity of illumination, to PV cell [15]. Thus, if the value, Isc, is known from the datasheet, under the standard test condition, Go=1000W/m2 at the air mass (AM) = 1.5, then the photon generated current at any other irradiance, G (W/m2), is given by:

I sc G|G G oI|sc Go

A detailed block diagram of the proposed system is shownin Figure 4. A DC to DC boost converter is used to interfacethe PV array output to DC motor driven centrifugal pump.The control unit consists of a microchip PIC16F877A-I/Pmicrocontroller and interface circuits required to lead thePV array’s voltage and current signals to the microcontroller.A turbine flow rate sensor (Type DF-HN, 120 l/min H2O,KOBOLD) is used to provide an indirect measurement of theflow rate velocity in l/min with a square wave signal as anoutput signal whose frequency varies linearly with flow rate.The latter output waveform is shaped by hex Schmitt-triggerinverter chip (74LS14N) and applied to microcontroller 16-bit timer/counter pin (T1CKI).The controller on chip 10-bit Pulse Width Modulation(PWM) generator output drives the DC to DC boost converteraccording to MPPTs algorithms. The boost convertercomprises: MOSFET switch IRF730, diode BYT 71 andcoil (L = 1mH) [4]. The switching frequency (6,125 KHz)is designed to obtain low output ripple. To implement theserial communication with the PC which has a display

3. MICROCONTROLLER

3.1. Introduction

The PIC micro was originally designed around 1980 by General

Instrument as a small, fast, inexpensive embedded microcontroller with

strong I/O capabilities.  PIC stands for "Peripheral Interface Controller". 

The PIC micro has some advantages in many applications over

the older chips such as the Intel 8048/8051/8052 and its derivatives, the

Motorola MC6805/6hHC11, and many others.   Its unusual architecture

is ideally suited for embedded control.  Nearly all instructions execute in

the same number of clock cycles, which makes timing control much

easier.  The PIC micro is a RISC design, with only thirty-odd

instructions to remember; its code is extremely efficient, allowing the

PIC to run with typically less program memory than its larger

competitors.

Very important, though, is the low cost, high available clock

speeds, small size, and incredible ease of use of the tiny PIC.  For

timing-insensitive designs, the oscillator can consist of a cheap RC

network.  Clock speeds can range from low speed to 20MHz. Versions

of the various PIC micro families are available that are equipped with

various combinations ROM, EPROM, OTP, EPROM, EEPROM, and

FLASH program and data memory. 

3.2. Features

High-Performance RISC CPU:

Only 35 single-word instructions to learn.

All single-cycle instructions except for program branches, which

are two-cycle.

Operating speed: DC – 20 MHz clock input, DC – 200 ns

instruction cycle.

Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8

bytes of Data Memory (RAM), Up to 256 x 8 bytes of EEPROM

Data Memory.

Analog Features:

10-bit, up to 8-channel Analog-to-Digital Converter (A/D).

Brown-out Reset (BOR).

Analog Comparator module with:

Two analog comparators.

Programmable on-chip voltage reference (VREF) module.

Programmable input multiplexing from device inputs and

internal voltage reference.

Comparator outputs are externally accessible.

Peripheral Features:

Timer0: 8-bit timer/counter with 8-bit prescaler.

Timer1: 16-bit timer/counter with prescaler, can be incremented

during Sleep via external crystal/clock.

Timer2: 8-bit timer/counter with 8-bit period register, prescaler

and post scalar.

Two Capture, Compare, PWM modules

Capture is 16-bit, max. resolution is 12.5 ns.

Compare is 16-bit, max. resolution is 200 ns.

PWM max. resolution is 10-bit.

Synchronous Serial Port (SSP) with SPI™ (Master mode) and

I2C™ (Master/Slave).

Universal Synchronous Asynchronous Receiver Transmitter

(USART/SCI) with 9-bit address detection.

Parallel Slave Port (PSP) – 8 bits wide with external RD, WR and

CS controls (40/44-pin only).

Brown-out detection circuitry for Brown-out Reset (BOR).

CMOS Technology:

Low-power, high-speed Flash/EEPROM technology.

Fully static design.

Wide operating voltage range (2.0V to 5.5V).

Commercial and Industrial temperature ranges.

Low-power consumption.

Special Microcontroller Features:

100,000 erase/write cycle Enhanced Flash program memory

typical.

1,000,000 erase/write cycle Data EEPROM memory typical.

Data EEPROM Retention > 40 years.

Self-reprogrammable under software control.

In-Circuit Serial Programming™ (ICSP™) via two pins.

Single-supply 5V In-Circuit Serial Programming.

Watchdog Timer (WDT) with its own on-chip RC oscillator for

reliable operation.

Programmable code protection.

Power saving Sleep mode.

Selectable oscillator options.

In-Circuit Debug (ICD) via two pins.

3. PIN DIAGRAM

Pin diagram of 16F877A 40-pin PDIP.

TABLE3-1:PIC16F874A/877A PINOUT DESCRIPTION

TABLE 3-1: PIC16F874A/877A PINOUT DESCRIPTION

(CONTINUED)

TABLE 3-1: PIC16F874A/877A PINOUT DESCRIPTION

(CONTINUED)

TABLE 3-1: PIC16F874A/877A PINOUT DESCRIPTION

(CONTINUED)

3.4 ARCHITECTURE DIAGRAM

3.5. Architecture Overview

The PIC uses Harvard architecture, unlike the von Neumann

architecture used in most general-purpose processors you may be

familiar with.  The von Neumann architecture uses the same bus for

program memory, data memory, I/O, registers, etc.  This makes it easy

to bring the common bus out to device I/O pins for adding memory, but

it limits the bus bandwidth that can be used for any one function since

the bus is shared.  Von Neumann processors are generally micro coded,

CISC (Complex Instruction Set Computer) designs (though there are, of

course, exceptions).

The Harvard architecture uses separate program memory and data

memory busses.  This makes it easy to design the processor for very

efficient use of program memory, since the program memory bus can be

of a much different width than the data memory.   Instructions usually

(always in the case of the PIC) take up only one program memory

location, compared to one, two or even three in a typical von Neumann

design.   Harvard-architecture machines are generally non-micro coded,

RISC (Reduced Instruction Set Computer) designs (again, exceptions

are to be found).  One drawback to the Harvard architecture is that it is

very difficult to bring the memory address and data busses out to device

pins, so adding external program memory is difficult at best.  For this

reason, most Harvard machines have only internal program memory.

For example, the popular PIC16F84 contains 1K words of FLASH

program memory, 68 bytes of data RAM, and 64 bytes of data EPROM. 

While this seems like an extremely limited amount of code and data

space, the PIC's incredibly compact code makes the most of it.

   1024 instruction word memory actually means 1024 instructions,

no less.  Even immediate-mode instructions, where an operand is part of

the instruction itself, takes only one memory location, as do CALL and

GOTO instructions.  There even exists a single-chip implementation of a

TCP/IP stack and HTTP server written for a 16F84.

The PIC is also a non-micro coded design.  In larger processors,

each binary machine language instruction often is "executed" by a series

of microcode steps.   While this is a great approach for building large,

complex processors with a wide range of instructions, it also leads to

great complexity and takes up a lot of real estate.  The PIC uses the

instruction word itself, decoded by logic gates as it is read from program

memory, to control the flow of data through the chip.

The seemingly odd 14-bit instruction word length is a direct result

of the internal architecture of the processor itself.  In the case of the

16F84 or 16C711, we need 13 bits just to address all of program

memory.  In the case of the smaller 16C54 with only 512 words of

program memory and 25 bytes of RAM, we can get by with a 12-bit

instruction word -- which is exactly what the 16C54 uses.  Conversely,

with more memory we would use a longer instruction word, like the 16

bits in the 18Cxxx family.

The ALU

Now let's look at the real workhorse, the Arithmetic and Logic

Unit, or ALU section.  Notice we have a MUX that controls what data is

gated into the right side of the ALU.  The left side of the ALU gets its

data from the W register.  The W register, or WREG, is going to be

where a lot of work takes place. 

Nearly any instruction result can be placed in the W reg and later

used for another operation.  We can also leave the W reg alone and put

the results of subsequent operations directly into RAM locations or send

them to an I/O port or control register.  This kind of flexibility is where a

lot of the power and versatility of the PIC comes from, as we'll see in a

little bit.

The ALU can perform several operations on the data that is gated

into it.  The exact function to be performed is determined by several bits

in the opcode.  They include CLEAR, ADD, SUB, INC, DEC, AND,

OR, XOR, COM, Rotate Right, Rotate Left, SWAP nibbles, NOP, and a

couple of special cases.

Data Memory

Data memory consists of a relatively small block of static RAM.

This can range from 25 bytes on up.  The lower twelve data memory

locations are not really RAM; they are special registers that are

addressed the same way data memory is addressed.

Data memory is divided into two areas: Special Function Registers

(SFRs) and General Purpose Registers (GPRs).  Special function

registers control the operation of various parts of the device. 

Depending on the processor, there may be other SFRs present, or

there may be SFR addresses that are unused.  You'll need to examine the

data sheet for your particular processor for the exact details, but some

things are relatively constant among most or all PICs.

The General Purpose register area is just that - non-dedicated RAM

registers you can use for any function.

Data memory is bank switched.  The bank selected is determined

by the setting of two bits in the STATUS register.  Some processors

have up to four banks of data memory, some have less than four.  If you

need to access locations in more than one bank, you can either use the

RP0/RP1 bits in the STATUS register or use the FSR register for

indirect addressing.  By using the FSR register you can address any

location in any bank.  The data contained in the register pointed to by the

FSR shows up in the INDF register at location 0.

Oscillators

Every PIC needs a clock.  The PIC uses four clock cycles to

complete one instruction cycle.  Since the PIC is fully static, the clock

rate can vary from DC (nothing) to the maximum rated speed, which is

currently around 20MHz for some parts.

What do we mean by "fully static"?  Some microprocessors use

some dynamic circuitry internally, which operate similar to dynamic

RAM.  These processors have a certain specified minimum clock

frequency which must be maintained, just like a minimum power supply

voltage.  The PIC has no such limitation; the processor clock can be

completely stopped.  In fact, the SLEEP instruction does just that - shuts

down the clock oscillator!  This leads to enormous power savings.  A

PIC in sleep mode will draw just a few microamperes.

There are several methods of clocking a PIC.  These are:

LP - Low power crystal

XT - Crystal or ceramic resonator

HS - High Speed crystal or resonator

RC - Resistance/capacitance

The first three methods use either a parallel-cut crystal or a

ceramic resonator.   LP mode is generally used for low-power

applications using watch-type crystals or ceramic resonators in the

32kHz to 200kHz range.  XT mode is used from typically 455kHz to

4MHz, and HS mode is usually used above 4MHz.  The modes are very

similar except for the amount of drive supplied to the crystal.  In these

three modes, an external clock source can also be used instead of a

crystal or resonator.  If you have an existing clock signal of the desired

frequency in your circuit, you can connect this signal to the OSC1 pin

and leave the OSC2 pin open.

When using a crystal or resonator, it is good practice to connect a

small capacitor from each OSC lead to ground.  This helps assure stable

oscillator operation and reliable start-up.  Consult the Microchip data

sheet for your processor and the specs for your crystal for the

recommended values, but 15pF to 33pF seems to be adequate for most

clock frequencies over 400kHz or so.

The last mode is RC mode.  If your application is not at all timing

sensitive, RC mode is simple and inexpensive.  To use this mode, you

simply connect and external resistor ranging from 5K to 100K Ohms

from Vdd to OCS1, and an external capacitor from OSC1 to Vss.  The

external capacitor can be eliminated, but Microchip warns that the

frequency can vary widely and change often.  They recommend at least

20pF of external capacitance for anything resembling stable operation. 

Of course, RC mode will be affected much more than any of the crystal

or resonator modes by temperature, part to part variations, etc.

3.6. I/O Ports

The typical mid-range PIC processor has two I/O ports, PORTA

and PORTB.  PORTA is five bits and PORTB is eight bits.  Each pin

can be used for input or output, depending on the state of the

corresponding bit in the TRIS register for that port.   For example, if the

TRISA register contains binary 00001111, then PORTA bits 0, 1, 2, and

3 are input and bit 4 is output.  The other bits in the TRISA register are

"don't care", since the corresponding data latches and pins don't exist. 

For now, let's look at some of the special features we have on the ports:

RA4 is a special pin.  It has a Schmitt trigger input which can be

used as a timer/counter input to TMR0 if you want to use it for

that. 

RA4 also has an open-drain output configuration.  This means that

if you want to use it for output like the other pins, you will need to

use an external pull-up resistor or some other circuit.  You can pull

the pin LOW under program control, or you can let it float, but to

make it assume a HIGH level you will need an external pull-up

resistor.

PORTB pins 4 through 7 can cause an interrupt on change, if you

have enabled the RBIE bit in the OPTION register.  This interrupt

can also wake the processor from SLEEP mode.  This, along with

the weak pull-ups, make it ideal for keypad interfacing with wake-

on-key press.

These I/O port pins are extremely flexible.  For example, let's say

you want to design a remote combination keypad lock for controlling

access to a room.  It needs to be battery powered, so low power is a

primary consideration.  You also want to sound an alarm if the lock is

tampered with or opened.  You don't want to store combinations in the

box, you want to manage them from a central computer, so you want to

send the combination to a remote computer to authenticate the person

and log access.   Quite a tall order for one chip.  Let's see how this could

be done with a low-cost 16C84:

You could use RB7-1 for a 3x4 keypad.  Using RB7-4's weak

pullups and interrupt-on-change capability, you can put the CPU in

ultra-low-power SLEEP mode when it's not in use for longer

battery life.

Use RB0 for a tamper switch to wake up the PIC , sound an alarm,

and send a message to the central computer.

Use RA4 for a multi-drop, shared serial bus along with any number

of other units to send a serial data stream back to the central

computer on one signal wire (plus ground, of course).

Use RA2 & 3 for status LED's and/or a piezo beeper to give the

user feedback when keys are pressed, blink red or green to indicate

whether he or she has used a valid password, etc.

All that and we have a pin left over!  And the code will easily fit

into the 'C56's 1K word program memory with room to spare.  All

keypad debounce and serial communication functions are handled in

software, with no external devices required.   And you can run the whole

thing on a few AA batteries without so much as a voltage regulator - the

CPU is happy with anything from 2 to 6 Volts!

Of course, you could replace the 16C56 with a 16F84 and store

passwords locally in EEPROM, where they would be safe from power

failures.

3.7. MEMORY ORGANIZATION

There are three memory blocks in the PIC16F877A devices. They

are Flash program memory, RAM data memory and EEPROM data

memory. The program memory and data memory have separate buses so

that concurrent access can occur.

3.7.1. Program Memory Organization

The PIC16F87XA devices have a 13-bit program counter capable

of addressing an 8K word x 14 bit program memory space. The

PIC16F876A/877A devices have 8K words x 14 bits of Flash program

Memory, while PIC16F873A/874A devices have 4K words x 14 bits.

Accessing a location above the physically implemented address will

cause a wraparound. The Reset vector is at 0000h and the interrupt

vector is at 0004h.

3.7.2. Data Memory Organization

The data memory is partitioned into multiple banks which contain

the General Purpose Registers and the Special Function Registers. Bits

RP1 (Status<6>) and RP0 (Status<5>) are the bank select bits. Each

bank extends up to 7Fh (128 bytes). The lower locations of each bank

are reserved for the Special Function Registers. Above the Special

Function Registers are General Purpose Registers, implemented as static

RAM. All implemented banks contain Special Function Registers. Some

frequently used Special Function Registers from one bank may be

mirrored in another bank for code reduction and quicker access.

3.7.3. GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indirectly,

through the File Select Register (FSR).

FIGURE 3-3: PIC16F877A REGISTER FILE MAP

3.7.4. SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and

peripheral modules for controlling the desired operation of the device.

These registers are implemented as static RAM. The Special Function

Registers can be classified into two sets: core (CPU) and peripheral.

For example those registers associated with the core functions are

STATUS, OPTION_REG, INTCON, PIE1, PIR1, PIE2, PIR2, PCON,

PORTA, TRISA etc; and registers associated with peripheral functions

are PCL, PCLATH etc;

3.8. PERIFERALS

Different PICs have different on-board peripherals

Some common peripherals are:

Tri-state (“floatable”) digital I/O pins

Analog to Digital Converters (ADC) (8, 10 and 12bit, 50ksps)

Serial communications: UART (RS-232C), SPI, I2C, CAN

Pulse Width Modulation (PWM) (10bit)

Timers and counters (8 and 16bit)

Watchdog timers, Brown out detect, LCD drivers

DIGITAL I/O PINS

All PICs have digital I/O pins, called ‘Ports’

Ports have 2 control registers

– TRISx sets whether each pin is an input or output

– PORTx sets their output bit levels

Most pins have 25mA source/sink (directly drives LEDs)

ADCs

Only available in 14bit and 16bit cores

Fs (sample rate) < 54KHz

Most 8bits, newer PICs have 10 or 12bits

All are +/- 1LSB and are monotonic

Theoretically higher accuracy when PIC is in sleep mode (less

digital noise)

Can generate an interrupt on ADC conversion done

USART: UART

Serial Communications Peripheral : Universal Synchronous /

Asynchronous Receiver/Transmitter

Only available in 14bit and 16bit cores

Interrupt on TX buffer empty and RX buffer full

Asynchronous communication: UART (RS-232C serial)

–Can do 300bps - 115kbps

–8 or 9 bits, parity, start and stop bits, etc.

–Outputs 5V so you need a RS232 level converter (e.g.,

MAX232)

USART: USRT

Synchronous communication: i.e., with clock signal

SPI = Serial Peripheral Interface

– 3 wire: Data in, Data out, Clock

– Master/Slave (can have multiple masters)

– Very high speed (1.6Mbps)

– Full speed simultaneous send and receive (Full duplex)

I2C = Inter IC

– 2 wire: Data and Clock

– Master/Slave (Single master only; multiple masters clumsy)

CCP Modules

Capture/Compare/PWM (CCP).

10bit PWM width within 8bit PWM period (frequency)

– Enhanced 16bit cores have better bit widths.

Can use PWM to do DAC.

Capture counts external pin changes.

Compare will interrupt on when the timer equals the value in a

compare register.

Timers

Available in all PICs.

14+bit cores may generate interrupts on timer overflow.

Some 8bits, some 16bits, some have prescalers.

Can use external pins as clock in/clock out.

Missionaries

Sleep Mode: PIC shuts down until external interrupt (or internal

timer) wakes it up.

Interrupt on pin change: Generate an interrupt when a digital input

pin changes state (for example, interrupt on key press).

Watchdog timer: Resets chip if not cleared before overflow

Brown out detect: Resets chip at a known voltage level

LCD drivers: Drives simple LCD displays

Future: CAN bus, 12bit ADC, better analog functions

VIRTUAL PERIPHERALS:

– Peripherals programmed in software. UARTS, timers, and

more can be done in software (but it takes most of the

resources of the machine)

3.9. INSTRUCTION SET SUMMARY

The PIC16 instruction set is highly orthogonal and is comprised of three

basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each PIC16 instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. The format for each of the categories is presented in Figure 15-1, while the various opcode fields are summarized in Table 15-1. Table 15-2 lists the instructions recognized by the MPASM™ Assembler.

TABLE 3-2: OPCODE FIELD DESCRIPTIONS

For byte-oriented instructions, ‘f’ represents a file register

designator and‘d’ represents a destination designator. The file register

designator specifies which file register is to be used by the instruction.

The destination designator specifies where the result of the operation is

to be placed. If‘d’ is zero, the result is placed in the W register. If‘d’ is

one, the result is placed in the file register specified in the instruction.

FIGURE 3-4: GENERAL FORMAT FOR INSTRUCTIONS

For bit-oriented instructions, ‘b’ represents a bit field designator

which selects the bit affected by the operation, while ‘f’ represents the

address of the file in which the bit is located.

For literal and control operations, ‘k’ represents an eight or

eleven-bit constant or literal value.

One instruction cycle consists of four oscillator periods; for an

oscillator frequency of 4 MHz, this gives a normal instruction execution

time of 1 μs. All instructions are executed within a single instruction

cycle, unless a conditional test is true, or the program counter is changed

as a result of an instruction. When this occurs, the execution takes two

instruction cycles with the second cycle executed as a NOP.

All instruction examples use the format ‘0xhh’ to represent a

hexadecimal number, where ‘h’ signifies a hexadecimal digit.

TABLE 3-3: PIC16F877A INSTRUCTION SET

4 Maximum Power Point Tracking Algorithms

4.1 An overview of Maximum Power Point Tracking

A typical solar panel converts only 30 to 40 percent of the incident solar irradiation into electrical energy. Maximum power point tracking technique is used to improve the efficiency of the solar panel.According to Maximum Power Transfer theorem, the power output of a circuit is maximum when the Thevenin impedance of the circuit (source impedance) matches with the load impedance. Hence our problem of tracking the maximum power point reduces to an impedance matching problem. In the source side we are using a boost convertor connected to a solar panel in order to enhance the output voltage so that it can be used for different applications like motor load. By changing the duty cycle of the boost converter appropriately we can match the source impedance with that of the load impedance.

4.2 Different MPPT techniquesThere are different techniques used to track the maximum power

point. Few of the most populartechniques are:1) Perturb and Observe (hill climbing method)2) Incremental Conductance method3) Fractional short circuit current4) Fractional open circuit voltage5) Neural networks6) Fuzzy logic

The choice of the algorithm depends on the time complexity the algorithm takes to track theMPP, implementation cost and the ease of implementation.

4.2.1 Perturb & ObservePerturb & Observe (P&O) is the simplest method. In this we use

only one sensor, that is the voltage sensor, to sense the PV array voltage and so the cost of implementation is less and hence easy to implement. The time complexity of this algorithm is very less but on reaching very close to the MPP it doesn’t stop at the MPP and keeps on perturbing on both the directions. When this happens the algorithm has reached very close to the MPP and we can set an appropriate error limit or can use a wait function which ends up increasing the time complexity of the algorithm. However the method does not take account of the rapid change of irradiation level (due to which MPPT changes) and considers it as a change in MPP due to perturbation and ends up calculating the wrong MPP. To avoid this problem we can use incremental conductance method.

4.2.2 Incremental ConductanceIncremental conductance method uses two voltage and current

sensors to sense the output voltage and current of the PV array. At MPP the slope of the PV curve is 0.

(dP/dV)MPP=d(VI)/dV (4.1)0=I+VdI/dVMPP (4.2)dI/dVMPP = - I/V (4.3)

The left hand side is the instantaneous conductance of the solar panel. When this instantaneous conductance equals the conductance of the solar then MPP is reached. Here we are sensing both the voltage and current simultaneously. Hence the error due to change in irradiance is eliminated. However the complexity and the cost of implementation increases.As we go down the list of algorithms the complexity and the cost of implementation goes on increasing which may be suitable for a highly complicated system. This is the reason that Perturb and Observe and Incremental Conductance method are the most widely used algorithms.

Owing to its simplicity of implementation we have chosen the Perturb & Observe algorithm for our study among the two.

4.2.3 Fractional open circuit voltageThe near linear relationship between VMPP and VOC of the PV

array, under varying irradiance and temperature levels, has given rise to the fractional VOC method.VMPP = k1 Voc (4.4)where k1 is a constant of proportionality. Since k1 is dependent on the characteristics of the PV array being used, it usually has to be computed beforehand by empirically determining VMPP and VOC for the specific PV array at different irradiance and temperature levels. The factor k1 has been reported to be between 0.71 and 0.78. Once k1 is known, VMPP can be computed with VOC measured periodically by momentarily shutting down the power converter. However, this incurssome disadvantages, including temporary loss of power.

4.2.4 Fractional short circuit currentFractional ISC results from the fact that, under varying tmospheric

conditions, IMPP is approximately linearly related to the ISC of the PV array.IMPP =k2 Isc (4.5)where k2 is a proportionality constant. Just like in the fractional VOC technique, k2 has to be determined according to the PV array in use. The constant k2 is generally found to be between 0.78 and 0.92. Measuring ISC during operation is problematic. An additional switch usually hasto be added to the power converter to periodically short the PV array so that ISC can be measured using a current sensor.

4.2.5 Fuzzy Logic ControlMicrocontrollers have made using fuzzy logic control popular for

MPPT over last decade. Fuzzy logic controllers have the advantages of working with imprecise inputs, not needing an accurate mathematical model, and handling nonlinearity.

4.2.6 Neural NetworkAnother technique of implementing MPPT which are also well

adapted for microcontrollers is neural networks. Neural networks commonly have three layers: input, hidden, and output layers. The number nodes in each layer vary and are user-dependent. The input variables can be PV array parameters like VOC and ISC, atmospheric data like irradiance and temperature, or any combination of these. The output is usually one or several reference signals like a duty cycle signal used to drive the power converter to operate at or close to the MPP.

MPPT technique

Convergencespeed

Implementationcomplexity

Periodictuning

Sensed parameters

Perturb & observe

Varies Low No Voltage

Incrementalconductance

Varies Medium No Voltage, current

Fractional Voc Medium Low Yes Voltage

Fractional Isc Medium Medium Yes current

Fuzzy logic control

Fast High Yes Varies

Neural network

Fast High Yes Varies

4.3 Perturb & Observe AlgorithmThe Perturb & Observe algorithm states that when the operating voltage of the PV panel isperturbed by a small increment, if the resulting change in power _P is positive, then we are

going in the direction of MPP and we keep on perturbing in the same direction. If _P is negative,we are going away from the direction of MPP and the sign of perturbation supplied has to bechanged.

Figure 4.1 : Solar panel characteristics showing MPP and operating points A and B [16]Figure 4.1 shows the plot of module output power versus module voltage for a solar panel at a given irradiation. The point marked as MPP is the Maximum Power Point, the theoretical maximum output obtainable from the PV panel. Consider A and B as two operating points. As 31 shown in the figure above, the point A is on the left hand side of the MPP. Therefore, we can move towards the MPP by providing a positive perturbation to the voltage. On the other hand, point B is on the right hand side of the MPP. When we give a positive perturbation, the value of _P becomes negative, thus it is imperative to change the direction of perturbation to achieve MPP. The flowchart for the P&O algorithm is shown in Figure 4.2.

Figure 4.2 : Flowchart of Perturb & Observe algorithm

Flow chart of the proposed method

4.4 Limitations of Perturb & Observe algorithm

Figure 4.3 : Curve showing wrong tracking of MPP by P&O algorithm under rapidly varying irradiance

In a situation where the irradiance changes rapidly, the MPP also moves on the right hand side of the curve. The algorithm takes it as a change due to perturbation and in the next iteration it changes the direction of perturbation and hence goes away from the MPP as shown in the figure. However, in this algorithm we use only one sensor, that is the voltage sensor, to sense the PV array voltage and so the cost of implementation is less and hence easy to implement. The time complexity of this algorithm is very less but on reaching very close to the MPP it doesn’t stop at the MPP and keeps on perturbing in both the directions. When this happens the algorithm has reached very close to the MPP and we can set an appropriate error limit or can use a wait function which ends up increasing the time complexity of the algorithm.

4.5 Implementation of MPPT using a boost converterThe system uses a boost converter to obtain more practical uses out of the solar panel. The initially low voltage output is stepped up to a higher level using the boost converter, though the use of the converter does tend to

introduce switching losses. The block diagram shown in Figure 4.4 gives an overview of the required implementation.

References

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[4] Analysis of Wind Energy in the EU-25 - European Wind Energy Association - 2007[5] Solar Power (Book) - T Harko[6] Harnessing Solar Power (Book) - K Zweibel – 1990[7] REN21 Renewables 2010 Global Status Report[8] “How biomass energy works” - Union of Concerned Scientists[9] Geothermal Energy: Renewable Energy and the Environment - William E. Glassley - CRCPress - 2010[10] Impact of Enhanced Geothermal Systems (Egs) on the United States in the 21st Century: AnAssessment - Tester, Jefferson W. et. al. - 2006[11] Advanced Algorithm for control of Photovoltaic systems - C. Liu, B. Wu and R. Cheung[12] A new Analog MPPT Technique: TEODI - N. Femia, G. Petrone, G. Spagnuolo, M. Vitelli[13] Comprehensive approach to modeling and simulation of Photovoltaic arrays - MarceloGradella Villavla, Jones Rafael Gazoli, Ernesto Ruppert Filho[14] Power Electronics: Circuits, Devices and Operations (Book) - Muhammad H. Rashid