Microprocessor Microcontroller Unit III (16 Marks) Page Om Sakthi ADHIPARASAKTHIENGINEERINGCOLLEGE DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING EC2304-MICROPROCESSORS AND MICROCONTROLLERS UNIT- III MICROPROCESSOR PERIPHERAL INTERFACING 1. With neat block diagram explain the 8255 Programmable Peripheral Interface.(OR)Parallel communication Interface • 8255 has three registers of 8 bits each and are called as Port A, Port B and Port C. • The port A and upper 4 bits of Port C are grouped and called as Group A. • Similarly, Port B and lower 4 bits of Port C are grouped as Group B. • In addition to three registers A, B and C, there is another register called control register. • The contents written into the control register decides the operating modes of the three parallel ports. • In order to identify the four registers, 8255 uses two address lines A0 and A1. Click to buy NOW! P D F - X C H A N G E w w w . d o c u - t r a c k . c o m Click to buy NOW! P D F - X C H A N G E w w w . d o c u - t r a c k . c o m
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Microprocessor Microcontroller Unit III (16 Marks) Page
Om Sakthi
ADHIPARASAKTHIENGINEERINGCOLLEGE
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
EC2304-MICROPROCESSORS AND MICROCONTROLLERS
UNIT- III
MICROPROCESSOR PERIPHERAL INTERFACING
1. With neat block diagram explain the 8255 Programmable Peripheral Interface.(OR)Parallel communication Interface
• 8255 has three registers of 8 bits each and are called as Port A, Port B and Port C. • The port A and upper 4 bits of Port C are grouped and called as Group A. • Similarly, Port B and lower 4 bits of Port C are grouped as Group B. • In addition to three registers A, B and C, there is another register called control register. • The contents written into the control register decides the operating modes of the three
parallel ports. • In order to identify the four registers, 8255 uses two address lines A0 and A1.
Microprocessor Microcontroller Unit III (16 Marks) Page
Pin diagram of 8255
• PA0 – PA7, PB0 – PB7, PC0 – PC7 - These three ports of 8255 needs 8 lines each and so 24 pins are allotted for ports and connected to external Input or output devices.
• A0 and A1 – These pins are allotted for selecting one of the 4 registers available in 8255. • D0-D7 - Data lines are connected to the data bus of the processor. • RD and WR - Active low control signals for reading and writing to the registers, • CS – It is made to low for chip select CS , This signal is obtained from the decoder which
decodes the address lines and identifies the 8255 addressing. • RESET - Reset 8255 • VCC - +5 v power supply • GND – connected to Ground
Microprocessor Microcontroller Unit III (16 Marks) Page
Input control and opération (mode 1 ): Step 1
The input device places data in the data lines i.e., the Port A or Port B lines. This is communicated to 8255 by making STB (Strobe Input) low.
Step 2 8255 acknowledges the receipt of the data to the input by making IBF
(Input Buffer Full) high. This also indicates that the data has been latched into the input port.
Step 3 8255 then makes INTR line (Interrupt Request) high and applies an
interrupt to the processor. This signal is applied with a condition that INTE (Interrupt Enable) must be high. INTE for Port A is controlled by bit set/reset of PC4 and INTE for port B is controlled by bit set/reset of PC2. PC2 and PC4 can be controlled using BSR mode.
Step 4 The processor in the interrupt service routine reads the data from the corresponding input port. Reading from the port is done by selecting the 8255 port and applying RD active low signal.
Step 5 During Read operation the RD signal low. When RD signal goes low, INTR signal is reset. IBF is reset by the rising edge of the RD input.
Microprocessor Microcontroller Unit III (16 Marks) Page
Output control signal and operation (mode 1) : The control signals or handshake signals used for the output in mode 1 of 8255 are OBF,
ACK and INTR.
Step 1 The processor will initiate the data transmission by writing the data to be
transmitted to the output device to the corresponding port of 8255. Step 2
To transfer the data to the output device, 8255 will make OBF (Output Buffer Full- active low signal) “low” to indicate that the CPU has written data to be given to the specified port.
The OBF flip flop will be set by the rising edge of the WR input. Step 3
The data available on the output port pins are then read by the output device.
After receiving data from the port pins, ACK is an active low input signal to 8255 from the peripheral device indicating that it is accepting data.
OBF output signal of 8255 is reset by ACK input being low. Step 4
8255 will now inform to the processor that data has been transferred to the output device by making INTR (Interrupt Request) line high.
A “high” on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU.
INTR is set when ACK is a “one”, OBF is a “one” and INTE is a “one”. Step 5
In the interrupt Service routine, the processor writes the next data to be transmitted to the output device to the output port of 8255.
INTR signal is reset by the falling edge of WR. Mode 2 (Strobed bidirectional I/O):
In mode 2, data is transmitted and received via port A pins (bi-directional bus I/O) with handshaking capability.
Only Port A can be configured in Mode 2 and is used as a bi-directional port while port C is used for handshaking signals.
Meanwhile, Port B can be configured to be in Mode 0 or 1 and Port B cannot be configured for mode2.
Microprocessor Microcontroller Unit III (16 Marks) Page
Control signals and operations:
The input and output operation of 8255 in mode is similar to the operation in mode 1 except that the Port A is bidirectional port.
The data is transmitted and received through the Port A lines. For the output operation, as in mode 1, the data transfer is initiated by the processor by
making the active low signal OBF low. This indicates that the processor has written data to output port. The output device after reading the data will give an acknowledgement by making ACK
(Acknowledge signal – Active low signal) low. The processor will then be interrupted by 8255 to indicate that the output data port is
ready for next data output or transmission. Here, the interrupt can be applied to processor only if INTE 1 flip flop associated with
OBF and controlled by PC4 is set by the processor earlier The input operation is also similar to mode 1 operation. Here the data transfer is
initiated by the input device by placing the data on the port pins. Then an active low control signal STB is given to 8255 by the input device for taking
data. 8255 will now latch up the data to its port and then give an active high signal IBF to the
input device. 8255 will then issue an interrupt signal to the processor to indicate that a data is readily
available for read operation. Here, the interrupt can be applied to processor only if INTE2 flip flop associated with IBF
and controlled by PC4 is set by the processor earlier.
Microprocessor Microcontroller Unit III (16 Marks) Page
3. Show how two 8255 chip can be connected in an connected in an 8086-based system to form a 16-bit port.
• Interfacing of 8255 with 8086 requires two 8255 chips for 16 bit input and output • M/IO will be inverted before connecting to the decoder • RD and WR are directly connected to 8086
4. Explain serial communication Interface USART (8251) with neat diagram 8251 is Universal Synchronous Asynchronous Receiver Transmitter (USART) is used for
serial data communication.
8251 receives parallel data from the CPU and transmits the same in serial form. This device also receives serial data from the outside and converts them into parallel data and sends it to the CPU.
8251 can support both synchronous and asynchronous transmission formats and is programmable. It supports full duplex serial transmission and reception and variable baud rates.
Basically it consists of a parallel to serial shift register for the transmitting over TXD line from buffer and a serial to parallel converter for data received on the RXD line.
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• D0 to D7- Data bus: A group of Bidirectional data bus that is used for data and control word transfer between CPU and 8251.
• RESET: A logic High applied on this pin pits 8251 into “"reset status." The time duration required for reset signal is six clock pulses.
• CLK: Clock signal is used to generate internal device timing. CLK signal is independent of RXC (receive clock) or TXC (Transmit clock). In general, the CLK frequency must be much higher than the RXC and TXC frequencies.
• WR - Write Data/Command: It is an active low input signal for writing data and control words from the CPU into the 8251.
• RD- Read Data: It is an active low input signal for reading data and status words from the 8251.
• C/D - Control/Data: It is an input signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed.
• CS - Chip Select: It is an "Active low" input signal which selects the 8251 for CPU accesses.
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• TXD - Transmit Data line: It is an output signal for transmitting serial converted data from 8251.
• TXRDY - Transmitter Ready: It is an output signal which indicates 8251is ready to accept a transmitted data character. But the terminal is always at low level if CTS = high
• TXEMPTY - Transmitter Empty: It is an output signal that indicates that the 8251 has transmitted all the characters and had no data character to be transmission.
• TXC - Transmitter Clock: This is a clock input signal that determines the transfer speed of transmitted data or in other words, the baud rate for transmission.
• In "synchronous mode," the baud rate will be the same as the frequency of TXC.
• In "asynchronous mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC.
• RXD- Receive Data: A signal line that receives serial data.
• RXRDY - Receiver Ready: It is a signal that indicates that the 8251 contains a character that is ready to READ and CPU can read the data.
• RXC - Receiver Clock: This is a clock input signal that determines the transfer speed of received data or the baud rate of reception.
• In "synchronous mode," the baud rate is the same as the frequency of RXC.
• In "asynchronous mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.
• SYNDET/BD - Sync detect/break detect
• DSR - Data Set Ready: This is an input port for MODEM interface.
• DTR - Data Terminal Ready: This is an output port for MODEM interface.
• CTS - Clear to Send data: This is an input signal for MODEM interface which is used for controlling a transmit circuit.
• RTS - Request to Send: This is an output port for MODEM interface.
5. Explain the 8279 keyboard and display controller with neat sketch. The major features of 8279 are listed below.
Supports up to a maximum of 64 key matrix with 2-key lockout or N-key rollover options
Supports up to 16 digit display interface with many options Simultaneous keyboard and display operations
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8 character FIFO memory to store codes of keys pressed 16 byte display-RAM to store display data to 16 digits
IC8279 basically has three sections. The first section is the display section with its own display RAM. The next section is keyboard scan section with FIFO registers. The last one is the control logic with signals for interfacing to the processor.
The control section basically consists of data bus buffer for interfacing to the processor.
The I/O section uses the control signals such as A0, CS, RD and WR. CS is used to select the IC and this is an active low signal. Similarly RD and WR are the active low control signals for indication of
direction of data transfer on the data bus, DB0-DB7. A logic 1 on A0 line means the data bus content is a command or status. A
logic 0 means the data bus content is the data for the IC8279.
Keyboard section
• 8279 has four scan lines SL0 – SL3and eight return lines RL0 – RL7, a shift line and a control line. Scan lines are connected to rows of the keyboard. Return lines are connected to column of the keyboard. Shift line and control lines are connected to shift
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and control keys. IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.
• The scan counter has two modes to scan the key matrix Encoded scan Decoded scan
• In keyboard encoded scan, row is output on the low order three lines and it is decoded by 3 to 8 decoder to provide 8 x 8 keyboard
• In keyboard decoded scan, four lines are connected to four rows of keyboard to provide 4x8 keyboard
• Data format generated for each key pressed is
• This information is stored in FIFO (First In First Out) RAM. The status logic generates an
interrupt after each FIFO read operation till the FIFO is empty. Modes of Keyboard section • Encoded scan keyboard – 2 key lock out • Encoded scan keyboard - N key roll over • Decoded scan keyboard – 2 key lock out • Decoded scan keyboard - N key roll over • Encoded scan sensor Matrix • Decoded scan sensor Matrix • Strobed input Two types of Debouncing
• 2 key Lock out In this mode of operation, If two keys are pressed within a debounce cycle
(simultaneously), no key is recognized till one of them remains closed and the other is released. The last key that remains depressed is considered as single valid key depression.
• N-Key Rollover : In this mode, each key depression is treated independently. When a key is
pressed, the debounce circuit waits for 2 keyboards scans and then checks whether the key is still depressed. If it is still depressed, the code is entered in FIFO RAM.
• Scanned Sensor Matrix : In this mode, a sensor array can be interfaced with 8279 using either encoded or
decoded scans. With encoded scan 8*8 sensor matrix or with decoded scan 4*8 sensor matrix can be interfaced. The sensor codes are stored in the CPU addressable sensor RAM.
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In this mode, if the control line goes low, the data on return lines is stored in the FIFO byte by byte.
FIFO Status FIFO status is used in keyboard and strobed input modes to indicate the number
of characters in the FIFO and to indicate error. Overrun error occurs when the entry of another character into a full FIFO is
attempted. Underrun error occurs when the CPU tries to read an empty FIFO.
Display Section
• It consist of four scan lines SL0 – SL3, two 4 bit output ports(A0 – A3 and B0 – B3), 16 x 8 display RAM and Blank display line for display operation.
• For BCD type seven segment LED display, only 4 bit codes are needed. Both right and left entry display formats are possible.
• Display RAM can be loaded or read by the CPU after the correct mode and address is set. When the keyboard is in the decoded scan, display will automatically be in decoded mode, i.e 4 characters will be displayed.
• BD is used to blank display during digit switching • OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant
nibble of display. Display Mode
• Left Entry Mode : In the left entry mode, the data is entered from left side of the display unit. The first entry is displayed on the leftmost display and the sixteenth entry on the rightmost display. The seventeenth entry is again displayed at the leftmost display position.
• Right Entry Mode : In the right entry mode, the first entry to be displayed is entered on the rightmost display. The next entry is also placed in the right most display but after the previous display is shifted left by one display position.
6. Explain the command words of 8279 Keyboard Display Mode – The format of the command word to select different modes of operation are
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b) Programmable clock: The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler.
c) Read FIFO / Sensor RAM: In sensor matrix mode, the bits AAA select one of the 8rows of RAM. If AI flag is set, each successive read will be from the subsequent RAM location.
d) Read Display RAM: This command enables a programmer to read the display RAM data. AI is the auto increment flag for display RAM and AAAA is the address of the character to be read.
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e) Write Display RAM: This command enables a programmer to write the display RAM data. AI is the auto increment flag for display RAM and AAAA is the address of the character to be write.
f) Display Write Inhibit/Blanking :
The IW (inhibit write flag) bits are used to mask the individual A or B nibble. The blank display bit flags (BL) are used for blanking A and B nibbles.
g) Clear Display RAM:
The CD2, CD1, CD0 is a selectable blanking code to clear all the rows of the display RAM CD – Clear display RAM CF – Clear FIFO status CA – Clear All
h) End Interrupt / Error mode Set:
For the sensor matrix mode, this command lowers the IRQ line and enables further writing into the RAM.
For N-Key roll over mode, if the E bit is programmed to be ‘1’, the 8279 operates in special Error mode.
7. Explain the block diagram of 8253 Programmable Interval timer with neat sketch. 8254 can be operated at frequency of up to 8MHz whereas 8253 can be
operated only up to a maximum frequency of 2.6MHz.
Features of IC 8253.
Generation of accurate time delay
Three independent 16-bit down counters called as channels