MPI_UNIT_5

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UNIT 5 MPI CSE DEPARTMENT

UNIT 5

UNIT 5 CONTENTS AT A GLANCE: SERIAL DATA TRANSFER SCHEMES: Asynchronous and synchronous data transfer schemes, 8251 USART architecture and interfacing, RS - 232C Serial data standard, RS- 423A and RS - 422A, sample program of serial data transfer.

ADVANCED MICROPROCESSORS:

Introduction to 80286,

salient features of 80386, real and protected mode segmentation and paging.

Data Transmission:

Most digital messages are longer than just a few bits.

The message is broken into smaller parts and transmitted sequentially.

Bit-serial transmission conveys a message one bit at a time through a channel.

Each bit represents a part of the message.

The individual bits are then reassembled at the destination to compose the message.

Data transfer in microcomputer can be done in two ways:

1. Parallel data transfer

2. Serial data transfer

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Serial Transmission:

one bit is sent at a time

It may seem that anyone would choose parallel transmission for high speeds

However, most communication systems use serial mode

There are two main reasons

First, serial networks can be extended over long distances at much less cost

Second, using only one physical wire means that there is never a timing problem caused

by one wire being slightly longer than another

Sender and receiver must contain a hardware that converts data from the parallel form used in

the device to the serial form used on the wire

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parallel transmission:

multiple bits are sent at the same time

Parallel transmission allows transfers of multiple data bits at the same time over separate media

In general, parallel transmission is used with a wired medium that uses multiple, independent

wires

Furthermore, the signals on all wires are synchronized so that a bit travels across each of the

wires at precisely the same time

Figure 9.2 illustrates the concept, and shows why engineers use the term parallel to characterize

the wiring

A parallel mode of transmission has two main advantages:

High speed: it can send N bits at the same time

a parallel interface can operate N times faster than an equivalent serial interface

Match to underlying hardware: Internally, computer and communication hardware uses

parallel circuitry

a parallel interface matches the internal hardware of computer as well

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Serial transmission types:

Asynchronous Each byte is encoded for transmission

Start and stop bits No need for sender and receiver synchronization

Synchronous Sender and receiver must synchronize

Done in hardware using phase locked loops (PLLs) Block of data can be sent More efficient

Less overhead than asynchronous transmission Expensive

Asynchronous serial transmission:

1. The sender and receiver are not Synchronised.

2. The sender sends only one character at a time.

3. Each character needs a start bit and a stop bit, parity bit.

4. Start is denoted by low signal(0V) and end is denoted by high signal (5v)

5. There can be idle time between each character.

6. It is a slow and inefficient method of data transmission.

7. It is an inexpensive method for low speed transmission.

Parity

8. Parity is used in Asynchronous transmission.

9. Detects any errors in each character being sent.

10. A bit in each byte is set aside as the parity bit.

11. In even parity, the bit is set to 1 or 0 to ensure an even number of 1s.

12. In odd parity, the bit is set to 1 or 0 to ensure and odd number of 1s.

13. The receiving system checks the system being used and the number of 1s

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Synchronous transmission:

1. The senders and the receivers clocks are synchronised.

2. The sender sends a packet of data at a time.

3. Synchronisation is achieved by sending a start frame and a stop frame.

4. It is a more efficient method of transmission as only a start and stop frame are required with up

to 8Kb of data in the packet of data.

5. Asynchronous has a much higher overhead.

Data

bit1

Data

bit2

Data

bit3

Data

bit4

Data

bit5

Data

bit6

Data

bit7

Data

bit8

Sync1 Sync2

Fig: synchronous bit format

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A communications channel is classified as one of three types:

(depending on the direction of transfer)

Simplex

Full-Duplex

Half-Duplex

Simplex: a simplex mechanism can only transfer data in a single direction

It is analogous to broadcast radio or television

Figure 9.8a illustrates simplex communication

Full-Duplex: allows transmission in two directions simultaneously

It is analogous to a voice telephone conversation

in which a participant can speak even if they are able to hear background music

at the other end

Half-Duplex: A half-duplex mechanism involves a shared transmission medium

The shared medium can be used for communication in each direction

But the communication cannot proceed simultaneously

It is analogous to using walkie-talkies where only one side can transmit at a time

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To Interface microcomputer with serial data lines, the data must be converted to and from serial form.

To do this, two registers are used.

1. Serial in parallel out shift register

2. Parallel in serial out shift register.

Digital data transmission using modems and standard phone lines:

Fig: Digital data transmission using modems showing sequence of signals exchanged between sender device and

receiver device

When transmitter is communicating with receiver , the following sequence of signals will be exchanged:

1. DTE asserts DTR(data terminal ready signal) to tell modem that DTE device is ready.

2. When modem is powered up and ready to transmit or receive data, modem will asserts DSR (data set ready)

3. when terminal ready to send, it will send RTS(Request to send) signal to modem.

4. the modem will asserts its Carrier Detect (CD) signal to terminal to indicate the establishment of connection

with computer.

5. then modem sends CTS (clear to send) signal back to the terminal

6. Now the terminal transmitter sends character to modem

7. When terminal sends all characters, it makes RTS signal high

8. This causes modem to unassert its CTS signal and stops transmitting.

Note: The above signals exchange occurs on the receivers side also.

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8251 USART ARCHITECTURE AND INTERFACING

The hardware needed to convert data between an internal parallel form and a serial form can

be straightforward or complex

depending on the type of serial communication mechanism

A related chip, Universal Synchronous-Asynchronous Receiver and Transmitter (USART) handles

conversion for synchronous networks

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data

communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from

the CPU and transmits serial data after conversion. This device also receives serial data from the outside

and transmits parallel data to the CPU after conversion.

Block diagram of the 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter)

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The 8251 Universal Synchronous/Asynchronous Receiver/Transmitter packaged in a 28-pin

DIP made by Intel. It is typically used for serial communication

It includes 5 sections

1. read/write control logic

2. transmitter

3. receiver

4. data bus system

5. modem control

The 8251 functional configuration is programed by software. Operation between the 8251 and a CPU is

executed by program control.

Control Words

There are two types of control word.

1. Mode instruction (setting of function)

2. Command (setting of operation)

3.STATUS word

1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait for write"

at either internal reset or external reset. That is, the writing of a control word after resetting will be

recognized as a "mode instruction."

Items set by mode instruction are as follows:

Synchronous/asynchronous mode

Stop bit length (asynchronous mode)

Character length

Parity bit

Baud rate factor (asynchronous mode)

Internal/external synchronization (synchronous mode)

Number of synchronous characters (Synchronous mode)

The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous mode,

it is necessary to write one-or two byte sync characters. If sync characters were written, a function will

be set because the writing of sync characters constitutes part of mode instruction.

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11


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2) Command word

Command is used for setting the operation of the 8251. It is possible to write a command whenever

necessary after writing a mode instruction and sync characters.

Items to be set by command are as follows:

Transmit Enable/Disable

Receive Enable/Disable

DTR, RTS Output of data.

Resetting of error flag.

Sending to break characters

Internal resetting

Hunt mode (synchronous mode)

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Status Word

It is possible to see the internal status of the 8251 by reading a status word. The bit configuration of

status word is shown in Fig. 5.

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Pin Description

D 0 to D 7 (l/O terminal)

This is bidirectional data bus which receive control words and transmits data from the CPU and sends

status words and received data to CPU.

RESET (Input terminal)

A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode

instruction." The min. reset width is six clock inputs during the operating status of CLK.

CLK (Input terminal)

CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC. However,

the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and

Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode.

WR (Input terminal)

This is the "active low" input terminal which receives a signal for writing transmit data and control words

from the CPU into the 8251.

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RD (Input terminal)

This is the "active low" input terminal which receives a signal for reading receive data and status words

from the 8251.

C/D (Input terminal)

This is an input terminal which receives a signal for selecting data or command words and status words

when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word

or status word will be accessed.

CS (Input terminal)

This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. Note:

The device wont be in "standby status"; only setting CS = High.

TXD (output terminal)

This is an output terminal for transmitting data from which serial-converted data is sent out. The device

is in "mark status" (high level) after resetting or during a status when transmit is disabled. It is also

possible to set the device in "break status" (low level) by a command.

TXRDY (output terminal)

This is an output terminal which indicates that the 8251is ready to accept a transmitted data character.

But the terminal is always at low level if CTS = high or the device was set in "TX disable status" by a

command. Note: TXRDY status word indicates that transmit data character is receivable, regardless of

CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge or WR

signal.

TXEMPTY (Output terminal)

This is an output terminal which indicates that the 8251 has transmitted all the characters and had no

data character. In "synchronous mode," the terminal is at high level, if transmit data characters are no

longer remaining and sync characters are automatically transmitted. If the CPU writes a data character,

TXEMPTY will be reset by the leading edge of WR signal. Note : As the transmitter is disabled by setting

CTS "High" or command, data written before disable will be sent out. Then TXD and TXEMPTY will be

"High". Even if a data is written after disable, that data is not sent out and TXE will be "High".After the

transmitter is enabled, it sent out. (Refer to Timing Chart of Transmitter Control and Flag Timing)

TXC (Input terminal)

This is a clock input signal which determines the transfer speed of transmitted data. In "synchronous

mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode", it is possible to

select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of

TXC sifts the serial data out of the 8251.

RXD (input terminal)

This is a terminal which receives serial data.

RXRDY (Output terminal)

This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the CPU

reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data

character before the next one is received completely, the preceding data will be lost. In such a case, an

overrun error flag status word will be set.

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RXC (Input terminal)

This is a clock input signal which determines the transfer speed of received data. In "synchronous

mode," the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is possible to

select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In "internal synchronous mode." this

terminal is at high level, if sync characters are received and synchronized. If a status word is read, the

terminal will be reset. In "external synchronous mode, "this is an input terminal. A "High" on this input

forces the 8251 to start receiving data characters.

In "asynchronous mode," this is an output terminal which generates "high level"output upon the

detection of a "break" character if receiver data contains a "low-level" space between the stop bits of

two continuous characters. The terminal will be reset, if RXD is at high level. After Reset is active, the

terminal will be output at low level.

DSR (Input terminal)

This is an input port for MODEM interface. The input status of the terminal can be recognized by the

CPU reading status words.

DTR (Output terminal)

This is an output port for MODEM interface. It is possible to set the status of DTR by a command.

CTS (Input terminal)

This is an input terminal for MODEM interface which is used for controlling a transmit circuit. The

terminal controls data transmission if the device is set in "TX Enable" status by a command. Data is

transmitable if the terminal is at low level.

RTS (Output terminal)

This is an output port for MODEM interface. It is possible to set the status RTS by a command.

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PROCEDURE FOR SENDING AND RECEIVING CHARACTERS using USART:

Data characters can be sent to and read from the 8251 on:

1. Interrupt basis

2. Polled basis

To send data on interrupt basis:

1. TxRDY pin of the 8251A is connected to an interrupt input of 8259A

2. The transmitter should be enabled

3. When CTS pin is low and 8251A buffer is ready for a character, TxRDY pin will go high

4. 8259A, interrupt path should be enabled .

5. The processor goes to interrupt service procedure which writes data character to 8251A .

6. TxRDY should reset until buffer is ready for receiving another character.

7. Counter should be maintained for keeping track of how many characters have been sent.

To receive data on interrupt basis:

1. RxRDY pin of the 8251A is connected to an interrupt input of 8259A

2. The receiver should be enabled

3. When 8251A buffer is ready to read a character, RxRDY pin will go high

4. 8259A, interrupt path should be enabled .

5. The processor goes to interrupt service procedure which reads data character.

6. RxRDY should reset until buffer is ready for another character to be read.

7. Counter should be maintained for keeping track of how many characters have been received.

To send and receive data on polled basis:

Program instructions should be written. The following are sequence of instructions to be written for

sending and receiving data on polled method basis:

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Serial communication data transmission standards:

The 3 standards we refer here are:

1. RS 232C[recommended standard 232 C version]

2. RS 423A[recommended standard 423 A version]

3. RS 422A[recommended standard 422 B version]

RS 232C :

Typically used to connect a modem to a computer

Standard for transfer of characters across copper wire

Produced by EIA (Electronics Industry Association)

Full name is RS-232-C

RS-232 defines serial, asynchronous communication

Serial - bits are encoded and transmitted one at a time (as opposed to parallel

transmission)

Asynchronous - characters can be sent at any time and bits are not individually

synchronized

SPECIFICATIONS

Connection must be less than 50 feet

Data represented by voltages between +15v and -15v

25-pin connector, with specific signals such as data, ground and control assigned to

designated pins

Specifies transmission of characters between, e.g., a terminal and a modem

Transmitter never leaves wire at 0v; when idle, transmitter puts negative voltage (a 1)

on the wire

RS 232C are of 2 types:

1. 9 pin

2. 25 pin

RS-232 DB25 Pin Out

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9 pin RS 232C:

Comparison of 3 standards:

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RS 232C TTL conversions:

Connecting 2 - RS 232 compatible equipment:

Also called as NULL modem connection

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ADVANCED MICROPROCESSORS:

Introduction to 80286:

Features of 80286:

80286 is high performance processor ( 6 times better than 8086)

Address bus size is 24bit

Data bus size is 16bit

80286 has large address space

16Megabytes physical

1 Giga byte virtual space per one task

80286 has integrated memory management, four levels of memory protection, support for

Virtual memory and OS

80286 has high bandwidth bus interface( 12.5 megabytes/sec)

80286 has facility of having optional Processor extension(80287)

80286 SUPPORTS 2 upward compatible operating modes

8086 real address mode

Protected virtual address mode

Available in 12.5Mhz, 10MHz & 8Mhz & 6 Mhz clock frequencies

80286 is the first member of the family of advanced microprocessors with memory

management and protection abilities

The 80286 CPU, with its 24-bit address bus is able to address 16Mb of physical memory.

Available in 68 pin ceramic LCC , PGA, PLCC packages

Memory management , virtual memory management & protection abilities.

Operating Modes:

Intel 80286 has 2 operating modes.

1. Real address mode.

2. Protected Virtual address mode.

Real Address Mode :

80286 just as a fast 8086

All memory management and protection mechanisms are disabled

Protected Virtual Address Mode

80286 works with all of its memory management and protection capabilities

with the advanced instruction set.

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Pins of 80286:

68 pins are available

Fig: pin diagram of 80286

Register organization of 80286:

The 80286 CPU contains almost the same set of registers, as in 8086.

1. Eight 16-bit general purpose registers.

2. Four 16 bit segment registers.

3. Status(FLAG register) and control register

4. Instruction pointer.

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80286 Flag Register:

80286 block diagram:

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80286 block diagram has 4 parts: 1. Address unit 2. Bus unit 3. Instruction unit 4. Execution unit

1. Address Unit

Calculate the physical addresses of the instruction and data that the CPU want to access

Address lines derived by this unit may be used to address different peripherals.

Physical address computed by the address unit is handed over to the BUS unit.

2. Bus Unit Transmit the physical address over address bus A0 A23. Instruction Pipelining. Prefetcher module in the bus unit performs this task of prefetching. Bus controller controls the prefetcher module. Fetched instructions are arranged in a 6 byte prefetch queue. Processor Extension Interface Module Take care of communication

b/w CPU and a coprocessor. 3. Instruction Unit

Receive arranged instructions from 6 byte prefetch queue. Instruction decoder decodes the instruction one by one and are latched

onto a decoded instruction queue. O/p of the decoding circuit drives a control circuit in the Execution unit.

4. Execution unit Control unit is responsible for executing the instructions received from

the decoded instruction queue. Contains Register Bank. ALU is the heart of execution unit. After execution ALU sends the result either over data bus or back to the

register bank.

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80386: Two versions of 80386 are commonly available: 1) 80386DX 2)80386SX

80386DX 80386SX

32 bit address bus 24 bit address bus

32bit data bus 16 bit data bus

Packaged in 132 pin ceramic pin grid array(PGA)

100 pin flat package

Address 4GB of memory

Addresses 16 MB memory

Sailent features of 80386:

First 32-bit processor in the IA-32 architecture family

32-bit registers used both for holding operands and addressing

32-bit address bus that supports up to 4 Gbytes of physical memory

32 bit data bus

Segmented-memory model and flat memory model

Paging (fixed 4-Kbyte page) for virtual memory management

386CX, 386DX(with FPU inside)

The 80386 cpu supports 16k number of segments and thus total virtual memory space is

4GB *16 k=64 tera bytes

Memory management section supports

Virtual memory

Paging

4 levels of protection

20-33 MHz frequency

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Architecture of 80386 The Internal Architecture of 80386 is divided into 3 sections.

Central processing unit(CPU) Memory management unit(MMU) Bus interface unit(BIU)

Central processing unit is further divided into Execution unit(EU) and Instruction unit(IU) Execution unit has 8 General purpose and 8 Special purpose registers which are either used for handling data or calculating offset addresses.

Fig: 80386 architecture

The Instruction unit decodes the opcode bytes received from the 16-byte instruction code queue and arranges

them in a 3- instruction decoded instruction queue.

After decoding them pass it to the control section for deriving the necessary control signals. The barrel shifter

increases the speed of all shift and rotate operations.

The multiply / divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum

time.

Even 32- bit multiplications can be executed within one microsecond by the multiply / divide logic

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The Memory management unit consists of

Segmentation unit and

Paging unit.

Segmentation unit allows the use of two address components, viz. segment and offset for relocability and

sharing of code and data.

Segmentation unit allows segments of size 4Gbytes at max.

The Paging unit organizes the physical memory in terms of pages of 4kbytes size each.

Paging unit works under the control of the segmentation unit, i.e. each segment is further divided into pages.

The virtual memory is also organizes in terms of segments and pages by the memory management unit.

The Segmentation unit provides a 4 level protection mechanism for protecting and isolating the system code

and data from those of the application program.

Paging unit converts linear addresses into physical addresses.

The control and attribute PLA checks the privileges at the page level. Each of the pages maintains the paging

information of the task. The limit and attribute PLA checks segment limits and attributes at segment level to

avoid invalid accesses to code and data in the memory segments.

The Bus control unit has a prioritizer to resolve the priority of the various bus requests.This controls the access

of the bus. The address driver drives the bus enable and address signal A0 A31. The pipeline and dynamic bus

sizing unit handle the related control signals.

Register Organization:

80386 will have the following types of registers:

1. General purpose registers( EAX, EBX, ECX, EDX)

2. Segment registers(CS,DS,ES,SS,FS,GS)

3. Pointer and index registers(SP,BP,SI,DI)

4. Instruction pointer(IP)

5. Flag register

6. Segment debug registers(DR0,DR1,DR2,DR3,DR4,DR5,DR6,DR7)

7. Control Registers( CR0, CR1, CR2, CR3)

8. Test registers

Flag Register of 80386: The Flag register of 80386 is a 32 bit register. Out of the 32 bits, Intel has reserved bits

D18 to D31, D5 and D3, while D1 is always set at 1.Two extra new flags are added to the 80286 flag to derive

the flag register of 80386. They are VM and RF flags.

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Control Registers: The 80386 has three 32 bit control registers CR0, CR2 and CR3 to hold global machine status

independent of the executed task. Load and store instructions are available to access these registers.

Debug and Test Registers: Intel has provide a set of 8 debug registers for hardware debugging. Out of these

eight registers DR0 to DR7, two registers DR4 and DR5 are Intel reserved.

The initial four registers DR0 to DR3 store four program controllable breakpoint addresses, while DR6 and DR7

respectively hold breakpoint status and breakpoint control information.

Two more test register are provided by 80386 for page caching namely test control and test status register.

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Real Address Mode of 80386

After reset, the 80386 starts from memory location FFFFFFF0H under the real address mode. In the real mode,

80386 works as a fast 8086 with 32-bit registers and data types.

In real mode, the default operand size is 16 bit but 32- bit operands and addressing modes may be used with

the help of override prefixes.

The segment size in real mode is 64k, hence the 32-bit effective addressing must be less than 0000FFFFFH. The

real mode initializes the 80386 and prepares it for protected mode.

Memory Addressing in Real Mode: In the real mode, the 80386 can address at the most1Mbytes of physical

memory using address lines A0-A19.

Paging unit is disabled in real addressing mode, and hence the real addresses are the same as the physical

addresses.

To form a physical memory address, appropriate segment registers contents (16-bits) are shifted left by four

positions and then added to the 16-bit offset address formed using one of the addressing modes, in the same

way as in the 80386 real address mode.

The segment in 80386 real mode can be read, write or executed, i.e. no protection is available.

Any fetch or access past the end of the segment limit generate exception 13 in real address mode.

The segments in 80386 real mode may be overlapped or non-overlapped.

The interrupt vector table of 80386 has been allocated 1Kbyte space starting from 00000H to 003FFH.

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Protected Mode of 80386:

All the capabilities of 80386 are available for utilization in its protected mode of operation.

The 80386 in protected mode support all the software written for 80286 and 8086 to be executed under the

control of memory management and protection abilities of 80386.

The protected mode allows the use of additional instruction, addressing modes and capabilities of 80386.

ADDRESSING IN PROTECTED MODE: In this mode, the contents of segment registers are used as selectors to

address descriptors which contain the segment limit, base address and access rights byte of the segment.

The effective address (offset) is added with segment base address to calculate linear address. This linear

address is further used as physical address, if the paging unit is disabled, otherwise the paging unit converts the

linear address into physical address.

The paging unit is a memory management unit enabled only in protected mode. The paging mechanism allows

handling of large segments of memory in terms of pages of 4Kbyte size.

The paging unit operates under the control of segmentation unit. The paging unit if enabled converts linear

addresses into physical address, in protected mode.

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SEGMENTATION:

Descriptor tables: These descriptor tables and registers are manipulated by the operating system to ensure

the correct operation of the processor, and hence the correct execution of the program.

Three types of the 80386 descriptor tables are listed as follows:

GLOBAL DESCRIPTOR TABLE ( GDT )

LOCAL DESCRIPTOR TABLE ( LDT )

INTERRUPT DESCRIPTOR TABLE ( IDT )

Descriptors: The 80386 descriptors have a 20-bit segment limit and 32-bit segment address. The descriptor of

80386 are 8-byte quantities access right or attribute bits along with the base and limit of the segments.

The 80386 has five types of descriptors listed as follows:

1.Code or Data Segment Descriptors.

2.System Descriptors.

3.Local descriptors.

4.TSS (Task State Segment) Descriptors.

5.GATE Descriptors.

The 80386 provides a four level protection mechanism exactly in the same way as the 80286 does.

Descriptor Attribute Bits for above figure: The A (accessed) attributed bit indicates whether the segment has

been accessed by the CPU or not.

The TYPE field decides the descriptor type and hence the segment type.

The S bit decides whether it is a system descriptor (S=0) or code/data segment descriptor ( S=1).

The DPL field specifies the descriptor privilege level.

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The D bit specifies the code segment operation size. If D=1, the segment is a 32-bit operand segment, else, it is

a 16-bit operand segment.

The P bit (present) signifies whether the segment is present in the physical memory or not. If P=1, the segment

is present in the physical memory.

The G (granularity) bit indicates whether the segment is page addressable. The zero bit must remain zero for

compatibility with future process.

The AVL (available) field specifies whether the descriptor is for user or for operating system.

PAGING:

Paging Operation: Paging is one of the memory management techniques used for virtual memory multitasking operating system. The segmentation scheme may divide the physical memory into a variable size segments but the paging divides the memory into a fixed size pages. The segments are supposed to be the logical segments of the program, but the pages do not have any logical relation with the program. The pages are just fixed size portions of the program module or data. The advantage of paging scheme is that the complete segment of a task need not be in the physical memory at any time. Only a few pages of the segments, which are required currently for the execution need to be available in the physical memory. Thus the memory requirement of the task is substantially reduced, relinquishing the available memory for other tasks. Whenever the other pages of task are required for execution, they may be fetched from the secondary storage. The previous page which are executed, need not be available in the memory, and hence the space occupied by them may be relinquished for other tasks. Thus paging mechanism provides an effective technique to manage the physical memory for multitasking systems. Paging Unit: The paging unit of 80386 uses a two level table mechanism to convert a linear address provided by segmentation unit into physical addresses. The paging unit converts the complete map of a task into pages, each of size 4K. The task is further handled in terms of its page, rather than segments. The paging unit handles every task in terms of three components namely page directory, page tables and page itself. Paging Descriptor Base Register: The control register CR2 is used to store the 32-bit linear address at which the previous page fault was detected. The CR3 is used as page directory physical base address register, to store the physical starting address of the page directory. The lower 12 bit of the CR3 are always zero to ensure the page size aligned directory. A move operation to CR3 automatically loads the page table entry caches and a task switch operation, to load CR0 suitably. Page Directory : This is at the most 4Kbytes in size. Each directory entry is of 4 bytes,thus a total of 1024 entries are allowed in a directory.The upper 10 bits of the linear address are used as an index to the corresponding page directory entry. The page directory entries point to page tables. Page Tables: Each page table is of 4Kbytes in size and many contain a maximum of 1024 entries. The page table entries contain the starting address of the page and the statistical information about the page. The upper 20 bit page frame address is combined with the lower 12 bit of the linear address. The address bits A12- A21 are used to select the 1024 page table entries. The page table can be shared between the tasks.

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Virtual 8086 Mode of 80386:

In its protected mode of operation, 80386DX provides a virtual 8086 operating environment to execute the 8086 programs.

The real mode can also used to execute the 8086 programs along with the capabilities of 80386, like protection and a few additional instructions.

Once the 80386 enters the protected mode from the real mode, it cannot return back to the real mode without a reset operation.

Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086 programs while in protected mode.

The address forming mechanism in virtual 8086 mode is exactly identical with that of 8086 real mode.

In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in the 4Gbytes address space of the protected mode of 80386.

Like 80386 real mode, the addresses in virtual 8086 mode lie within 1Mbytes of memory.

In virtual mode, the paging mechanism and protection capabilities are available at the service of the programmers.

The 80386 supports multiprogramming, hence more than one programmer may be use the CPU at a time.

MPI_UNIT_5

Documents

time parallel transmission

parallel mode of transmission

parallel data transfer

serial data transfer

serial mode

parallel interface

serial form

serial networks