MPC8560 PowerQUICC III Torridon User's Guide - NXP

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MPC8560 PowerQUICC III™ Torridon User’s Guide

MPC8560UGRev. 0.112/2004

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MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1

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ContentsParagraph Number Title

Page Number

Chapter 1 References

1.1 Glossary ...............................................................................................................................11.2 References............................................................................................................................3

Chapter 2 Introduction

2.1 Background..........................................................................................................................12.2 Scope....................................................................................................................................12.3 System Overview.................................................................................................................1

Chapter 3 Motherboard

3.1 Motherboard Overview........................................................................................................13.2 Motherboard Features ..........................................................................................................2

Chapter 4 Processor

4.1 Overview..............................................................................................................................14.2 MPC8560 Processor Configuration .....................................................................................24.3 COP Interface ......................................................................................................................4

Chapter 5 Flash

5.1 Overview..............................................................................................................................15.2 Flash.....................................................................................................................................1

Chapter 6 DDR

6.1 Overview..............................................................................................................................16.1.1 DDR Memory ..................................................................................................................16.1.2 The MPC8560’s DDR Memory Controller .....................................................................16.1.2.1 Available Signals .........................................................................................................16.2 Design Considerations .........................................................................................................26.2.1 Signal Termination...........................................................................................................26.2.2 Signal Connections ..........................................................................................................36.2.2.1 Address and Control Signals .......................................................................................36.2.2.2 Data..............................................................................................................................36.2.2.3 Clock............................................................................................................................4


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6.2.2.4 Serial Presence Detect .................................................................................................46.2.2.5 DDR SDRAM Power ..................................................................................................46.2.2.6 Voltage Generation ......................................................................................................56.3 Physical Implementation......................................................................................................56.3.1 Schematics .......................................................................................................................76.4 Layout ................................................................................................................................126.4.1 Address and Control ......................................................................................................126.4.2 Data................................................................................................................................146.4.3 Clocks ............................................................................................................................176.4.4 DDR Power....................................................................................................................19

Chapter 7 RapidIO

7.1 Overview..............................................................................................................................17.1.1 RapidIO Interconnect.......................................................................................................17.1.2 The MPC8560’s RapidIO Controller...............................................................................17.1.3 Signals Descriptions ........................................................................................................17.2 Design Considerations .........................................................................................................27.2.1 Signal Termination...........................................................................................................27.2.2 Signal Connections ..........................................................................................................37.3 Logic Analyser Connection .................................................................................................57.4 Physical Connections ...........................................................................................................77.5 Layout Considerations .......................................................................................................11

Chapter 8 GBit Ethernet

8.1 Overview..............................................................................................................................18.2 GBit Ethernet Connection....................................................................................................18.3 GMII Interface .....................................................................................................................28.4 PHY Device .........................................................................................................................38.5 Magnetics & RJ45 ...............................................................................................................58.6 Layout Considerations .........................................................................................................6

Chapter 9 UART

9.1 Overview..............................................................................................................................1

Chapter 10 PCI

10.1 Overview..............................................................................................................................110.2 PCI Clocks ...........................................................................................................................2


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10.3 Bus Connectivity..................................................................................................................210.4 PCI Configuration................................................................................................................210.5 Schematics ...........................................................................................................................2

Chapter 11 Peripheral Support

11.1 Overview..............................................................................................................................111.2 IDE Interface........................................................................................................................111.2.1 Compact Flash Support....................................................................................................411.2.1.1 Overview......................................................................................................................411.2.1.2 Implementation on Torridon ........................................................................................411.3 USB......................................................................................................................................611.4 PS2 .......................................................................................................................................7

Chapter 12 Communications

12.1 Overview..............................................................................................................................112.2 Test .......................................................................................................................................112.3 QUADS Compatible Headers ..............................................................................................112.4 UTOPIA Interface..............................................................................................................13

Chapter 13 Reset

13.1 Overview..............................................................................................................................113.2 Reset Sources .......................................................................................................................113.3 Reset Scheme.......................................................................................................................2

Chapter 14 Clocking

14.1 Overview..............................................................................................................................114.2 System Clocks......................................................................................................................114.3 RapidIO Clocks....................................................................................................................414.3.1 Overview..........................................................................................................................414.3.2 Torridon’s RapidIO Sub-System......................................................................................514.3.3 Processor Clocks..............................................................................................................714.3.4 TSI500 Clocks .................................................................................................................714.3.5 Clock Distribution on Torridon........................................................................................914.4 Processor Real Time Clock................................................................................................1414.5 GBit Ethernet Clocks .........................................................................................................1614.6 Southbridge Real Time Clock............................................................................................16


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Chapter 15 Voltage Regulation

15.1 Overview..............................................................................................................................115.2 Power Available ...................................................................................................................115.3 Power Required....................................................................................................................215.4 Power Distribution ...............................................................................................................215.5 Voltage Generation...............................................................................................................415.5.1 CPLD Power ....................................................................................................................415.5.2 5V/3.3V Switching ..........................................................................................................615.5.3 MPC8560.........................................................................................................................815.5.3.1 MPC8560 Power Requirements ..................................................................................815.5.3.2 Core & PLL Voltage ....................................................................................................815.5.3.3 DDR DRAM I/O Voltage ..........................................................................................1415.5.3.4 I/O Voltage.................................................................................................................1615.5.4 DDR SDRAM................................................................................................................1615.5.5 GBit Ethernet .................................................................................................................1815.5.6 TSI500 ...........................................................................................................................2115.6 Power Sequencing..............................................................................................................25

Chapter 16 Processor Sockets

16.1 Overview..............................................................................................................................116.2 The Need For Sockets..........................................................................................................116.3 Socket Criteria .....................................................................................................................116.4 The Choice of a Socket ........................................................................................................216.5 Socket Mechanics ................................................................................................................216.6 The Base Package Emulator (BPE) .....................................................................................416.7 The Flat Pin Array (FPA).....................................................................................................616.8 Alternative Parts ..................................................................................................................816.9 Sockets on Torridon .............................................................................................................8

Chapter 17 Heat Sinks

17.1 Overview..............................................................................................................................117.2 Processor Thermal Characteristics.......................................................................................117.3 Thermal Management Information ......................................................................................217.4 Adhesives and Thermal Interface Materials ........................................................................217.5 Heat Sink Selection..............................................................................................................317.6 Fans......................................................................................................................................517.7 Heat Sinks On Torridon .......................................................................................................6


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Appendix A Schematics

Appendix B Revision History


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TablesTable Number Title

Page Number

1-1 Glossary of Terms .......................................................................................................................14-1 MPC8560 Configuration.............................................................................................................34-2 COP/JTAG Connector.................................................................................................................56-1 DDR SDRAM Interface Signals .................................................................................................26-2 Data Byte Lanes ........................................................................................................................147-1 RapidIO Interface Signals ...........................................................................................................27-2 RapidIO Probe - P30 ...................................................................................................................77-3 RapidIO Probe - P31 ...................................................................................................................87-4 RapidIO Probe - P32 ...................................................................................................................97-5 RapidIO Probe - P33 .................................................................................................................108-1 TSEC GMII Interface Signals.....................................................................................................28-2 PHY Configuration Pins .............................................................................................................48-3 Setting PHY Configuration Pins .................................................................................................48-4 PHY Configuration Pins on Torridon .........................................................................................58-5 Ethernet Connections ..................................................................................................................69-1 Specific MPC8560 - UART Signals ...........................................................................................19-2 RS232 Connector ........................................................................................................................211-1 CompactFlash Interconnect.........................................................................................................412-1 ADS Compatible Expansion Connector - P28 - Row A .............................................................512-2 ADS Compatible Expansion Connector - P28 - Row B .............................................................612-3 ADS Compatible Expansion Connector - P28 - Row C .............................................................712-4 ADS Compatible Expansion Connector - P28 - Row B .............................................................812-5 ADS Compatible Expansion Connector - P29 - Row A .............................................................912-6 ADS Compatible Expansion Connector - P29 - Row B ...........................................................1012-7 ADS Compatible Expansion Connector - P29 - Row C ...........................................................1112-8 ADS Compatible Expansion Connector - P29 - Row D ...........................................................1212-9 16 Bit UTOPIA Connector - P7 - Row A .................................................................................1312-10 16 Bit UTOPIA Connector - P7 - Row B .................................................................................1412-11 16 Bit UTOPIA Connector - P7 - Row C .................................................................................1412-12 16 Bit UTOPIA Connector - P7- Row D ..................................................................................1512-13 16 Bit UTOPIA Connector - P7 - Row E..................................................................................1612-14 16 Bit UTOPIA Connector - P7 - Row F..................................................................................1613-1 Reset Signals ...............................................................................................................................315-1 Power Supplied from an ATX Power Supply .............................................................................115-2 Power Required...........................................................................................................................215-3 MPC8560 Power Requirements..................................................................................................816-1 Alternative Socket Vendors.........................................................................................................817-1 Package Thermal Characteristics ................................................................................................1


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TablesTable Number Title

Page Number

B-1 Revision History .........................................................................................................................1


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FiguresFigure Number Title

Page Number

2-1 Typical Torridon Platform Configuration ...................................................................................23-1 Torridon Motherboard.................................................................................................................13-2 Torridon Block Diagram .............................................................................................................34-1 MPC8560 POR Configuration ....................................................................................................24-2 COP/JTAG Connections .............................................................................................................65-1 Flash ROM..................................................................................................................................25-2 Flash ROM Schematics - Local Bus Controller..........................................................................35-3 Flash ROM Schematics - Address/Data Demuxing....................................................................45-4 Flash ROM Schematics - Flash...................................................................................................56-1 DDR Termination........................................................................................................................36-2 DDR SDRAM Voltage Levels ....................................................................................................46-3 DDR SDRAM Voltage Generation .............................................................................................56-4 64 Bit DDR SDRAM ..................................................................................................................66-5 MPC8560 DDR Controller .........................................................................................................86-6 SODIMM Connection...............................................................................................................106-7 VTT Voltage Generation ...........................................................................................................116-8 Address and Control..................................................................................................................126-9 Address and Control Layout .....................................................................................................136-10 Data ...........................................................................................................................................156-11 Data Layout...............................................................................................................................166-12 DLL Configuration ...................................................................................................................176-13 DDR Clock Signals ...................................................................................................................186-14 Clock Layout.............................................................................................................................196-15 LP2995 Layout..........................................................................................................................206-16 VREF Layout ............................................................................................................................216-17 VTT Island ................................................................................................................................226-18 VTT Voltage Monitoring...........................................................................................................227-1 RapidIO Termination ..................................................................................................................27-2 RapidIO Signal Connections.......................................................................................................47-3 Tektronix TLA700 System..........................................................................................................57-4 P6880 Probes...............................................................................................................................57-5 Mother Board Connection...........................................................................................................67-6 Probe Layout ...............................................................................................................................67-7 RapidIO Receive Path Layout...................................................................................................117-8 RapidIO Receive Path Layout (With Logic Probes).................................................................128-1 GBit Ethernet Connection...........................................................................................................18-2 GMII Interface ............................................................................................................................38-3 RJ45 with Integrated Magnetics .................................................................................................6


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8-4 MDI Bus Layout .........................................................................................................................79-1 RS232 Interface...........................................................................................................................19-2 MPC8560 CPM...........................................................................................................................39-3 RS232 Transceiver ......................................................................................................................410-1 Boot Processor’s PCI Bus ...........................................................................................................110-2 MPC8560’s PCI Interface - Schematics......................................................................................310-3 PCI Slot - Schematics .................................................................................................................511-1 Primary IDE Interface - Schematics ...........................................................................................211-2 Secondary IDE Interface - Schematics .......................................................................................311-3 CompactFlash Connection ..........................................................................................................611-4 USB - Schematics .......................................................................................................................711-5 PS2 - Schematics.........................................................................................................................812-1 E1/T1 Card..................................................................................................................................212-2 QUADS Compatible Headers .....................................................................................................312-3 Connectivity to the QUADS Headers .........................................................................................413-1 Reset Scheme ..............................................................................................................................213-2 Resets ..........................................................................................................................................614-1 System Clocks.............................................................................................................................214-2 System Clocks - Schematics .......................................................................................................314-3 RapidIO Clocking .......................................................................................................................514-4 RapidIO Sub-System...................................................................................................................614-5 RapidIO Clock Options...............................................................................................................714-6 TSI500 RapidIO Clock Options..................................................................................................814-7 RapidIO Clock Distribution on Torridon ..................................................................................1014-8 High Speed Clock Generation...................................................................................................1114-9 Slow Speed Clock Generation ..................................................................................................1314-10 Processor Real Time Clocks .....................................................................................................1414-11 Processor Real Time Clocks - Schematics................................................................................1514-12 GBit Ethernet Clocks ................................................................................................................1614-13 Real Time Clock Schematics ....................................................................................................1815-1 Power Distribution ......................................................................................................................315-2 CPLD Power - Schematics..........................................................................................................515-3 3.3V/5V Isolator - Schematics ....................................................................................................715-4 NXI100 Power Module ...............................................................................................................815-5 Vdd Power - Schematics ...........................................................................................................1015-6 Vdd Power - Feedback- Schematics .........................................................................................1115-7 PLL Power - Schematics...........................................................................................................1315-8 DDR12 Module.........................................................................................................................1415-9 2.5V Voltage Generation...........................................................................................................1515-10 1.25V Signal Generation...........................................................................................................17


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15-11 GBit Ethernet - 2.5V Generation ..............................................................................................1915-12 GBit Ethernet - 1.5V Generation ..............................................................................................2015-13 TSI500 - 2.5V Generation.........................................................................................................2215-14 TSI500 - 1.3V Generation.........................................................................................................2315-15 TSI500 - 1.2V Generation.........................................................................................................2415-16 Power-Up Sequence ..................................................................................................................2616-1 Socket Mechanics .......................................................................................................................316-2 Processor - Socket Swapping......................................................................................................416-3 The BPE ......................................................................................................................................516-4 The FPA ......................................................................................................................................716-5 BPE .............................................................................................................................................816-6 PowerQUICCIII in FPA..............................................................................................................916-7 PowerQUICCIII in FPA - Side View ..........................................................................................916-8 PowerQUICCIII + FPA + BPE .................................................................................................1016-9 Heat Sink Attached ...................................................................................................................1017-1 Heat Sink Attachment .................................................................................................................217-2 Thermal Performance of Interface Material................................................................................317-3 Aavid Thermalloy 10-THMA-01 Thermal Characteristics ........................................................417-4 Aavid Thermalloy 10-THMA-01 Dimensions............................................................................517-5 Heat Sink on Torridon.................................................................................................................6A-1 Top Level ....................................................................................................................................2A-2 Boot Processor—Top Level ........................................................................................................3A-3 Boot Processor—Local Bus—Flash ...........................................................................................4A-4 Boot Processor—DDR SDRAM.................................................................................................5A-5 Boot Processor—PCI Interface ...................................................................................................6A-6 Boot Processor—RapidIO Interface ...........................................................................................7A-7 Boot Processor—GigaByte Ethernet Interface—Top .................................................................8A-8 Boot Processor—GigaByte Ethernet Interface ...........................................................................9A-9 Boot Processor—GigaByte Ethernet Interface—PHY1 ...........................................................10A-10 Boot Processor—GigaByte Ethernet Interface—PHY2 ...........................................................11A-11 Boot Processor—Communications Processor Module .............................................................12A-12 Boot Processor—Auxiliary Functions ......................................................................................13A-13 Boot Processor—Power On Configuration...............................................................................14A-14 Boot Processor—PCI Expansion ..............................................................................................15A-15 Southbridge—Top Level...........................................................................................................16A-16 Southbridge—PCI, PIDE, AC97 ..............................................................................................17A-17 Southbridge—Side, ISA, Peripheral .........................................................................................18A-18 Southbridge—IO.......................................................................................................................19A-19 Boot Processor—PCI Slot.........................................................................................................20A-20 Boot Processor—Power ............................................................................................................21


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A-21 Work Processor 1—Top Level ..................................................................................................22A-22 Work Processor 1—Local Bus ..................................................................................................23A-23 Work Processor 1—DDR SDRAM...........................................................................................24A-24 Work Processor 1—RapidIO Interface .....................................................................................25A-25 Work Processor 1—PCI Interface .............................................................................................26A-26 Work Processor 1—GigaByte Ethernet Interface—Top ...........................................................27A-27 Work Processor 1—GigaByte Ethernet Interface .....................................................................28A-28 Work Processor 1—GigaByte Ethernet Interface—PHY .........................................................29A-29 Work Processor 1—Communications Processor Module .........................................................30A-30 Work Processor 1—Auxiliary Functions ..................................................................................31A-31 Work Processor 1—Power On Configuration...........................................................................32A-32 Work Processor 1—Power ........................................................................................................33A-33 Work Processor 2—Top Level ..................................................................................................34A-34 Work Processor 2—Local Bus ..................................................................................................35A-35 Work Processor 2—DDR SDRAM...........................................................................................36A-36 Work Processor 2—RapidIO Interface .....................................................................................37A-37 Work Processor 2—PCI Interface .............................................................................................38A-38 Work Processor 2—GigaByte Ethernet Interface—Top ...........................................................39A-39 Work Processor 2—GigaByte Ethernet Interface .....................................................................40A-40 GigaByte Ethernet Interface—PHY..........................................................................................41A-41 Work Processor 2—Communications Processor Module .........................................................42A-42 Work Processor 2—Auxiliary Functions ..................................................................................43A-43 Work Processor 2—Power On Configuration...........................................................................44A-44 Work Processor 2—Power ........................................................................................................45A-45 Work Processor 3—Top Level ..................................................................................................46A-46 Work Processor 3—Local Bus ..................................................................................................47A-47 Work Processor 3—DDR SDRAM...........................................................................................48A-48 Work Processor 3—RapidIO Interface .....................................................................................49A-49 Work Processor 3—PCI Interface .............................................................................................50A-50 Work Processor 3—GigaByte Ethernet Interface—Top ...........................................................51A-51 Work Processor 3—GigaByte Ethernet Interface .....................................................................52A-52 Work Processor 3—GigaByte Ethernet Interface—PHY .........................................................53A-53 Work Processor 3—Communications Processor Module .........................................................54A-54 Work Processor 3—Auxiliary Functions ..................................................................................55A-55 Work Processor 3—Power On Configuration...........................................................................56A-56 Work Processor 3—Power ........................................................................................................57A-57 RapidIO Switch—Top Level.....................................................................................................58A-58 RapidIO Switch—Ports 0 and 1................................................................................................59A-59 RapidIO Switch—Ports 2 and 3................................................................................................60A-60 RapidIO Switch—Misc.............................................................................................................61


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A-61 RapidIO Switch—Power...........................................................................................................62A-62 Clocking—Top Level................................................................................................................63A-63 Clocking—Processor ................................................................................................................64A-64 Clocking—RapidIO ..................................................................................................................65A-65 Reset Control.............................................................................................................................66A-66 Power Supply—Top Level........................................................................................................67A-67 Power Supply—Core Voltage ...................................................................................................68A-68 Power Supply—IO Voltages .....................................................................................................69A-69 Power Supply—Supplied Power...............................................................................................70A-70 WP—Debug Ports.....................................................................................................................71


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Chapter 1 ReferencesThis section contains references used throughout this design guide.

1.1 GlossaryTable 1-1 shows acronyms and terms used throughout this design guide.

Table 1-1. Glossary of Terms

Term Description

ATA AT Attachment

ATM Asynchronous Transfer Mode

Boot Processor MPC8560 Networking and Communications Processor

CD Carrier Detect

COP Common On-Board Processor

CPM Communication Processor Module

CTS Clear To Send

DDR SDRAM Double Data Rate SDRAM

DIMM Dual Inline Memory Module

DIP Dual Inline Package

DLL Delay Locked Loop

DMA Direct Memory Access

DSR Data Send Ready

DTR Data Terminal Ready

EEPROM Electrically Erasable Programmable Read Only Memory

FCC Fast Communications Controller

FIFO First In First Out

FPGA Field Programmable Gate Array

GMII GBit Media Independent Interface

GPCM General Purpose Chip Select Machine

I2C Inter-Integrated Circuit Controller

IDE Integrated Device Electronics

I/O Input/Output


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References

LP-LVDS Link Protocol - Low Voltage Differential Signalling

JTAG Joint Test Access Group

MAC Media Access Controller

MCC Multi-Channel Communications Controller

MII Media Independent Interface

PCB Printed Circuit Board

PCI Peripheral Component Interconnect

PCMCIA Personal Computer Memory Card International Association

PLL Phase Locked Loop

PHY Physical Interface

POR Power on Reset

PowerQUICC MPC8xx Networking and Communications Processor

PowerQUICCII MPC82xx Networking and Communications Processor

PowerQUICCIII MPC85xx Networking and Communications Processor

RI Ring Indicator

RIO RapidIO

ROM Read Only Memory

RTS Ready to Send

Rxd Received Data

SCC Serial Communications Controller

SDRAM Synchronous Dynamic Random Access Memory

SPD Serial Presence Detect

SSTL_2 Stub Series Terminated Logic for 2.5 Volts

TDM Time Division Multiplex

TSEC Triple Speed Ethernet Controller

Txd Transmitted Data

USB Universal Serial Bus

UTOPIA Universal Test Operational Physical Interface for ATM

Work Processor MPC8560 Networking and Communications Processor

Table 1-1. Glossary of Terms (continued)

Term Description

References



1.2 ReferencesPlease refer to the following for more information.

1. MPC8560 Integrated Processor Reference Manual2. MPC8540 Integrated Processor Reference Manual3. TSI500 RapidIO Multi-port Switch User Manual4. M88E1011 Data Sheet5. Via VT82C686B “Super South” South Bridge Data Sheet6. Torridon System Specification - Ver 1.37. Torridon User Manual - Ver 2.0



References



Chapter 2 IntroductionThis section provides a brief introduction to the Torridon Platform.

2.1 BackgroundTorridon has been developed as a demonstration vehicle for Motorola’s new generation of integrated communication processors, the PowerQUICCIII in a multi processor RapidIO environment. As well as a demonstration system, it is also a hardware and software reference platform and code development platform.

2.2 ScopeThis design guide details the key design features of the platform and describes the specific implementation. This document is intended as a guide for hardware designers who are involved in the development of PowerQUICCIII based products.

It is not intended as a system specification nor a user manual for Torridon. Both these exist as separate documents.

2.3 System OverviewAlthough Torridon is designed such that it can plug into a larger system (e.g. through connectivity to a backplane), typically the platform will operate as a stand alone system. System configurations can change depending, for example, on the peripherals which are attached. The diagram in Figure 2-1 shows one possible system configuration.



Introduction

Figure 2-1. Typical Torridon Platform Configuration

The system consists of various parts• The Torridon motherboard• PCI expansion cards (e.g. graphics, additional peripherals)• USB Peripherals (e.g. keyboard, mouse)• Non-volatile storage (e.g. hard disk drive, Compact Flash)• Communications (e.g. Gbit Ethernet, RS232)• Linux Software Operating System• Software Development Environment

ID E 0 /1

U S B

P C I

R S 2 3 2R S 2 3 2G B i t

S o f t w a r eS o f t w a r e

T o r r i d o n B o a r d



Chapter 3 MotherboardThis section provides a brief introduction to the Torridon Motherboard.

3.1 Motherboard OverviewFigure 3-1below shows a picture of the Torridon Motherboard.

Figure 3-1. Torridon Motherboard



Motherboard

The board supports four MPC8560 processors. The main processor, which is responsible for booting the others and controlling the main peripherals, is referred to as the Boot Processor. The other three processors are referred to as Work Processor 1, 2 and 3.

The Boot Processor is responsible for peripheral support (e.g. USB, PS2 keyboard/mouse, hard disk, audio) via a “Southbridge chip”. It also provides support for a 64 bit PCI plug in card. It utilizes DDR memory as its local storage. Off board communications are made via a UART connection and a dual GBit ethernet connection.

In addition to the boot processor, there are the three additional PowerQUICCIII processors, Work Processor 1, 2 and 3. Each one of these processors support their own local DDR memory, UART and GBit Ethernet connections.

All of the processors communicate with each other via parallel RapidIO. A Tundra TSI500 RapidIO switch provides the switch fabric.

The board is powered from a 12V/5V/3.3V supply. All the other required voltages being generated on-board.

3.2 Motherboard FeaturesThe motherboard consists of various subsystems

• Processor - The board has four MPC8560 processors.• Flash - The main processor boots from its own local Flash ROM.• DDR - Each processor has its own local bank of DDR memory.• RapidIO - The processors communicate with each over RapidIO. This communication is

via a RapidIO switch.• GBit Ethernet - Each processor provides an interface to GBit Ethernet.• UART - Each processor provides connectively to a UART port.• PCI Expansion - Provided by a 64 bit PCI slot.• Peripheral Support - Provided by a South Bridge Chip.• Communications - Additional communications are handled via a “QUICC Application

Development System” (QUADS) Compatible Header and a UTOPIA connection to the backplane

• Reset - The system reset is handled by an on-board CPLD.• System Clocking - All the required clock signals are generated locally on board.• Voltage Regulation - All the required voltage levels are generated locally on board.

Motherboard Features



Figure 3-2 below shows a block diagram of the system.

Figure 3-2. Torridon Block Diagram

MPC8560

J3 16 Bit UTOPIA

DDR

MPC8560

MPC8560

TSI500RapidIO

Switch

DDR

DDR

DDR

D-Type

RJ45 PHY

UART

Gbit EthernetReset

GBit1GBit2GBit3GBit4

GBit1

GBit3

GBit4

MPC8560

GBit2

RJ45 PHYRJ45 PHYRJ45 PHY

RJ11RJ11RJ11

PHY UART1UART2UART3UART4

PHYPHYPHY

UART1

UART2

UART3

UART4

GBit5

GBit5RJ45 PHY

Flash+ Latch

ClockGeneration

VoltageRegulation

QUADS Compatible

Header

QUADS Compatible

Header

64 Bit PCI

RIO Access

South Bridge

IDE

USB

IDE

J5 Power

Work Processor 2

Work Processor 1

Work Processor 3

Boot Processor



Motherboard



Chapter 4 ProcessorThis section describes the processor sub-section on the Torridon Motherboard.

4.1 OverviewThe processors on Torridon are all MPC8560s. The MPC8560 PowerQUICCIII is the next generation PowerQUICCII integrated communications processor. The MPC8560 provides integration of processing power for networking and communications peripherals resulting in higher device performance. The MPC8560 has four main system blocks.

The first block is a high-performance embedded e500 core processor with 256 kbyte of level-2 cache, implementing the enhanced Book E instruction set architecture.

The second block is the communications processor module (CPM). The CPM of the MPC8560 supports three high-performance fast communications channels (FCCs) for 155Mbps ATM and Fast Ethernet, and up to 256 full-duplex, time-division-multiplexed (TDM) channels using two multi-channel controllers (MCCs). Other communications (for example UART) are supported by the serial communication controllers (SCCs).

The third block is a bus controller which provides a DDR SDRAM memory controller, a local bus controller, I2C interconnect as well as an interrupt controller.

The fourth block provides additional interfaces for system integration. These include two integrated 10/100/1000 Triple Speed Ethernet controllers (TSECs), a 64-bit PCI/PCI-X controller and a RapidIO interconnect. This high level of integration simplifies board design and offers significant bandwidth and performance for high-end control-plane and data-plane applications.

Each MPC8560 provides the following main functionality on board:• A DDR memory controller• A Flash ROM memory controller (On the Boot Processor only)• An RS232 interface• Two GBit Ethernet interfaces (Only one is supported on each of the Work Processors)• A PCI interface (provides a connection to the Southbridge) (On the Boot Processor only)• A RapidIO interface



Processor

4.2 MPC8560 Processor ConfigurationUnlike the PowerQUICCII family which uses a hard reset configuration word for initial configuration of the processor, the MPC8560 uses dedicated input pins. These pins are sampled during the assertion of reset and are used to configure variables such as the internal clock frequency, boot ROM location and so on.

These pins are sampled during the assertion of reset. This reset signal is generated locally on-board from the reset circuitry. The configuration signals are passed through a ‘244 buffer with its output enable signal controlled by the reset. This is shown in Figure 4-1 below.

Figure 4-1. MPC8560 POR Configuration

Note: For the sake of clarity, only six configuration signals are shown in the diagram above.

Some of the signals are changeable via a set of DIP switches, whereas others are hard wired on the board.

Some of these signals have an internal pull-up which selects a default state.

‘244 Buffer

OEReset*

MPC85x0

ConfigurationPins

+3.3V

+3.3V

0V

0V

MPC8560 Processor Configuration



Table 4-1 below summarizes these configuration pins and their specific usage on Torridon.

Table 4-1. MPC8560 Configuration

Functional Pin Usage ChipDefault

TorridonSetting Torridon Setup Description Controlled By Note

LA[28:31] Internal PLL Ratio None 1010 Internal clock set to 10:1 Ratio DIP Switches 1

1 Based on a 33.3MHz input clock, the platform clock will run at 333MHz.

LALE, LGPL2 e500 Core PLL Ratio None 01 e500 core set to 5:2 Ratio DIP Switches 2

TSEC1_TxD[6:4] Boot ROM Location 111 111 Processor boots from 32bit ROM DIP Switches 3

LWE[2:3] Host/Agent Config. 11 11 Processor acts as a host processor

DIP Switches 4

LA[27] CPU Boot Hold off 1 1 Processor is released from reset without waiting for external

configuration

DIP Switches 5

LGPL3,LGPL5 Boot Sequence Config. 11 11 Boot sequencer is disabled Default Assumed

—

EC_MDC Adjust TSEC Width 1 1 TSEC Port Width set to GMII Default Assumed

—

TSEC1_TxD[7] Configure TSEC 1 I/F 1 0 TSEC1 set to GMII mode DIP Switches —

TSEC2_TxD[7] Configure TSEC 2 I/F 1 0 TSEC2 set to GMII mode DIP Switches 6

LGPL0, LPGL1 RapidIO Clock Source 11 01 The source of the RapidIO Transmit Clock is the RapidIO

Receive Clock

DIP Switches —

TSEC2_TxD[4:2] RapidIO Device ID None 001 Select RapidIO Device ID DIP Switches 7

PCI_REQ64 PCI Width (32 or 64) 1 1 PCI Bus set to 32 Bit Default Assumed

8

PCI_GNT[1] PCI I/O Impedance 1 0 PCI I/O Impedance set to 25 ohms

DIP Switches 8

PCI_GNT[2] PCI Arbiter Enable 1 1 Internal PCI Arbitrator is Enabled Default Assumed

8

PCI_GNT[3] PCI Debug Enable 1 1 PCI Debug is Disabled Default Assumed

8

PCI_GNT[4] PCI/PCI-X Bus Configuration

1 1 PCI Mode is Selected Default Assumed

8

MSRCID[0] Memory Debug Enable 1 1 Debug Data is driven on MSrcID and MDVAL Pins

DIP Switches —

MSRCID[1] DDR Debug Enable 1 1 Debug Data is not Driven on ECC

Default Assumed

—

LWE[0:1] PCI O/P Hold Config 11 11 Adjust Hold Times for PCI Drivers

DIP Switches 8

TSEC2_TxD[6:5] Local Bus Hold Config 11 11 Adjust Hold Times for Local Bus Drivers

DIP Switches 9



Processor

4.3 COP InterfaceThe COP - Common On-Chip Processor, is part of the MPC8560’s JTAG machine, implemented as a set of additional instructions and logic within the JTAG permissions. This port may be connected to a dedicated debug station for extensive system debug.

There are several third party debug solutions on the market. These debug-stations may be connected to the host computer via either Ethernet, Parallel-Port, RS232 or any other media.

To support debug station connection to the COP/JTAG port of each processor, five 16 pin headers are provided on Torridon, carrying the COP/JTAG signals as well as additional signals aiding in system debug.

2 Based on a 33.3MHz input clock, the core clock will run at 833Mhz3 For the Work Processors, this is set to 011 meaning the boot ROM location is RapidIO4 For the Work Processors, this is set to 01 meaning the processor is configured as a RapidIO agent5 For the Work Processors, this is set to 0 meaning the processor is prevented from booting until released by the Boot Processor6 Not used on the Work Processors; they only use TSEC17 The RapidIO device IDs are as followsBoot Processor ID = 1Work Processor 1 ID = 2Work Processor 2 ID = 3Work Processor 3 ID = 48 Not used on the Work Processors; they do not use PCI.9 Not used on Work Processors 2 & 3; they do not use their local bus

COP Interface



The pinout for each of the COP/JTAG connectors is shown in Table 4-2 below.

Table 4-2. COP/JTAG Connector

Pin# Signal Description

1 TDO Transmit Data Output. The MPC8560’s JTAG serial data output pin.

2 NC Not Connected

3 TDI Transmit Data Input. The MPC8560’s JTAG serial data input pin.

4 TRST* Test port Reset. Used to resets the JTAG logic on the MPC8560.

5 +3.3V +3.3 Volt Power.

6 +3.3V +3.3 Volt Power

7 TCLK Test port Clock. This clock shifts in / out data to / from the MPC8560’s JTAG logic.

8 CHK_STP_IN* Check Stop In.This pin is pulled up to 3.3V via a 10K resistor.

9 TMS Test Mode Select. This signal changes the state of the JTAG machines.

10 NC Not Connected

11 SRESET* Soft Reset. The MPC8560’s Soft Reset Signal.

12 NC Not Connected

13 HRESET* Hard Reset. The MPC8560’s Hard Reset Signal.

14 NC Not Connected

15 CHK_STP_OUT* Check Stop Out.This pin is pulled up to 3.3V via a 10K resistor.

16 GND Digital Ground



Processor

The diagram in Figure 4-2 shows the COP/JTAG connections.

Figure 4-2. COP/JTAG Connections

HRESET HRESET

From TargetBoard Sources

HRESET13

SRESET

SRESETSRESET

NC

NC

11

VDD_SENSE6

51

15

2 kΩ

10 kΩ

10 kΩ

10 kΩ

OVDD

OVDD

OVDD

OVDDCHKSTP_IN

CHKSTP_IN8TMS

TDO

TDI

TCK

TMS

TDO

TDI

TCK

9

1

3

4TRST

7

16

22

10

12

(if any)

CO

P H

eade

r

142Key

Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the part.

Connect pin 5 of the COP header to OVDD with a 10 KΩ pull-up resistor.2. Key location; Pins 2 and 14 are not physically present on the COP header

OVDD

OVDD

10 kΩOVDD

GND

TRST

10 kΩOVDD

10 kΩ

10 kΩ

CHKSTP_OUTCHKSTP_OUT

3

13

9

5

1

6

10

15

11

7

16

12

8

4

KEYNo pin

COP ConnectorPhysical Pin Out

1 KEYNo pin



Chapter 5 FlashThis section describes the flash sub-section on the Torridon Motherboard.

5.1 OverviewAlthough Torridon supports four processors, only one of these, the boot processor, uses local Flash ROM directly as its boot device. The other processors, the work processors, boot over RapidIO. Hence, Torridon only requires one bank of Flash memory.

The MPC8560 boots from a Flash ROM which is accessed using the MPC8560’s General Purpose Chip Select Machine (GPCM). The address and data on the local bus of the MPC8560 is multiplexed. An external demultiplexor, controlled by the local buses address latch enable (LALE) signal is used to separate the address and data bus.

5.2 FlashThe Flash is arranged as 32 bit wide Flash ROM and is physically implemented in two AMD 29LV641D Flash devices providing a total of 16Mbytes of Flash. This Flash is soldered directly onto the Torridon motherboard.



Flash

The diagram in Figure 5-1 shows the Flash ROM on the Boot processor.

Figure 5-1. Flash ROM

L C S 0 *

A M 2 9 L V 6 4 1 D

A [ 2 1 :3 ]

C E *

O E *

W E *

R E S E T *

D [ 1 5 :0 ]L A D [ 0 :1 5 ]

R E S E T *

L W E 0 * , L W E 2 *

L O E *

L A L E

L A D [0 :3 1 ]

D e m u x

L A [ 8 :2 6 ]

B u f fe r

A M 2 9 L V 6 4 1 D

A [ 2 1 :3 ]

C E *

O E *

W E *

R E S E T *

D [ 1 5 :0 ]

L W E 0 *

L W E 2 *

L A [ 8 :2 6 ]

A [ 2 :0 ]B L A [ 2 7 :2 9 ]

A [ 2 :0 ]

Flash



The schematics for the Flash interface are shown in Figure 5-2, Figure 5-3, and Figure 5-4.

Figure 5-2. Flash ROM Schematics - Local Bus Controller



Flash

Figure 5-3. Flash ROM Schematics - Address/Data Demuxing

Flash



Figure 5-4. Flash ROM Schematics - Flash



Flash

The following should be noted about the circuitry.• Although the local bus’s DLL is connected (LSYNC_IN, LSYNC_OUT), no synchronous

devices are connected to the local bus.• The external Transfer Acknowledge (/LGTA) signal is pulled up to ensure the cycle is not

terminated by a false transfer acknowledge cycle.• The ‘74ALVCH32973 devices provide both buffering and de multiplexing.• As the ‘74ALVCH32973 is 16 bits wide, two devices are required to de-multiplex the 32

bit bus.• Some of the control signals (e.g. LWE_N0, LGPL2 etc.) are used elsewhere in the design.

These are buffered to provide additional drive to cope with the additional loading.• As the processor is big endian, the least significant bit on the address and data bus is bit 31.• The flash devices are arranged as 32 bit wide devices, hence the two least significant

address bits are don’t cares.• The burst address pins (BLA(27:29]) allow burst accesses to be supported.• Note the write enable signals are different for each Flash device.



Chapter 6 DDRThis section describes the DDR sub-section on the Torridon Motherboard.

6.1 Overview

6.1.1 DDR MemoryDDR (Double Data Rate) memory is the next generation SDRAM. Like SDRAM, DDR is synchronous with the system clock however, DDR reads data on both the rising and falling edges of the clock signal. SDRAM only carries information on the rising edge of a signal. This enables the DDR module to transfer data twice as fast as traditional SDRAM. For example, using a clock rate of 133MHz on a SDRAM would yield a data rate of 133MHz. The same clock rate on DDR memory would transfer data at 266MHz.

6.1.2 The MPC8560’s DDR Memory ControllerThe MPC8560 has an integrated memory controller which supports JEDEC standard DDR Type 1 SDRAMs. The DDR memory controller is intended for use with x8 or x16 DDR SDRAMs. In addition, the memory controller will either be connected to all unbuffered DIMMs or all registered DIMMs. The memory controller does not support a mix of unbuffered and registered DIMMs in the same system.

The memory controller includes these distinctive features:• Support for DDR Type 1 SDRAM• 64/72-bit DRAM data bus• Programmable settings for meeting all DRAM timing parameters• Many different DRAM configurations supported• Support for up to four banks, each bank independently addressable• Support for 64 Mbit to 1 Gbit devices with x8/x16 data ports

6.1.2.1 Available SignalsThe DDR SDRAM memory is controlled directly by the processor’s memory controller. The memory controller provides all the signals necessary for this control.

The signals used by DDR can be split into three different groups.



DDR

Table 6-1 details the signals provided by the MPC8560’s memory controller.

6.2 Design ConsiderationsThe following section details design considerations.

6.2.1 Signal TerminationThe DDR SDRAM memory controller uses Stub Series Terminated Logic for 2.5 Volts, SSTL_2. To guard against unwanted signal reflections on the signal paths, these lines must be impedance matched. Typically this is achieved by the use of a series termination and a pull up resistor, connected to the termination voltage, VTT. The VTT voltage is implemented on the PCB as a split plane on the top layer. This is referred to as the “VTT Island”.

Table 6-1. DDR SDRAM Interface Signals

SignalGroup

SignalName Description

I/O(w.r.t.

Processor)

Address &

Control

BA[0:1] Bank Address Bus Output

A[0:14] Address Bus Output

RAS* Row Address Strobe Output

CAS* Column Address Strobe Output

WE* Write Enable Output

CS[0:3]* Chip Selects Output

Data DQ[0:63] Data Bus Input/Output

DQS[0:8] Data Strobes Input/Output

DM[0:8] Data Masks Outputs

ECC[0:7] Error Correction Codes Input/Output

Clock CLK[0:5] Clocks Output

CLK[0:5]* Complement Clocks Output

CKE[0:1] Clock Enable Output

MSYNC_IN Delay Locked Loop Synchronization In Input

MSYNC_OUT Delay Locked Loop Synchronization Out Output

Design Considerations



The diagram in Figure 6-1 shows a single ended termination scheme.

Figure 6-1. DDR Termination

Where RS = Series Resistance, RT = Termination Resistance.

On Torridon; RT = 27 Ohms, RS = 22Ohms.

6.2.2 Signal Connections

6.2.2.1 Address and Control SignalsAs well as fifteen address bits, A[0:14], the MPC8560’s memory controller provides two bank address bits, BA[0:1]. This allows a maximum address range of 1GBit. Four chip selects (CS[0:3]) provide connection to four separate physical banks. (As opposed to the Bank Address pins which select logical banks).

As with “normal” SDRAM, the row and column addresses are latched using a Row Address Strobe (RAS*) and a Column Address Strobe (CAS*) respectively. A Write Enable signal (WE*) indicates a write cycle is in progress.

6.2.2.2 DataThe data signal group is made up of four different types of signals; data bits, mask bits, strobe bits and parity bits. The data bus is 64 bits wide. Each byte of data has its own mask bit (used to mask specific data byte lanes during a write cycle) and its own strobe bit (used to latch the data).

As well as this, the entire data bus is protected by parity. As with the data bits, the parity bits have their own dedicated mask and strobe bits.

RT

Driver

Receiver

VREF

VTT

VIN

RS

VOUT

VSS

VDDQ

MPC8560

DDR



DDR

6.2.2.3 ClockThe MPC8560’s memory controller provides 6 clock / complement clock pairs. The number of clock pairs actually used will depend on the physical implementation. For example, a single 64 bit DDR DIMM would require 3 clock pairs.

6.2.2.4 Serial Presence DetectMost DDR SDRAM DIMMs support Serial Presence Detect (SPD). The DDR SDRAM configuration is contained in a non-volatile ROM on the DDR SDRAM DIMM. This ROM is accessed by the processor’s I2C bus. Using the interface, the processor may interrogate the memory to check for its presence, size, speed etc.

Note: The I2C signals are open drain and require pull ups.

6.2.2.5 DDR SDRAM PowerThe diagram in Figure 6-2 shows the voltage levels associated with the DDR SDRAM interface.

Figure 6-2. DDR SDRAM Voltage Levels

The SSTL_2 interface uses a reference voltage and differential input to determine the logic levels.

VREF = VDD / 2

VTT = VREF

Where: VDD is the supply voltage

VREF is the reference voltage

VTT is the termination voltage

Therefore,

VDD = 2.5 Volts

VTT = VREF = VDD / 2 = 1.25 Volts.

DDR SDRAM

VREF

VTT

VDD

RT

Physical Implementation



6.2.2.6 Voltage GenerationThe required termination voltage for each DDR SDRAM DIMM is generated locally. i.e. each DDR DIMM will have its own dedicated power supply.

The reference voltage, VREF, and the termination voltage, VTT, are generated from the input voltage, VDD, using a National Semiconductor LP2995 voltage regulator.

The diagram in Figure 6-3 shows the generation of these voltage levels.

Figure 6-3. DDR SDRAM Voltage Generation

6.3 Physical ImplementationThe diagram in Figure 6-4 shows the connection between the MPC8560 and the DDR SDRAM. On Torridon, the DDR is physically implemented as a SODIMM (Small Outline DRAM In Line Memory Module) however the connections shown will be very similar for a full sized DIMM or if using discrete devices.

LP2995 VREF = 1.25V

VTT = 1.25VVDD = 2.5V



DDR

Figure 6-4. 64 Bit DDR SDRAM

R TR T

M P C 8 5 6 0

D Q [ 0 : 6 3 ] 6 4 D [ 0 : 6 3 ]

E C C [ 0 : 7 ] 8 C B [ 0 : 7 ]

W E *

2

R A S *

1

C A S *

1

1

C S [ 0 : 1 ] *

C K E [ 0 : 1 ]

2

D Q S [ 0 : 8 ] 9

S D A / S C L2

D M [ 0 : 8 ]

A [ 0 : 1 2 ] 1 3

9

B A [ 0 : 1 ]

C L K [ 0 : 2 ] / * C L K [ 0 : 2 ] 6

M S Y N C _ O U T

M S Y N C _ I N

VTT

Island

* W E

* R A S

* C A S

D Q S [ 0 : 8 ]

D Q M [ 0 : 8 ]

S D A / S C L

A [ 0 : 1 2 ]

B A [ 0 : 1 ]

C K [ 0 : 2 ] /* C K [ 0 : 2 ]

C K E [ 0 : 1 ]

* S 0 [ 0 : 1 ]

S O D I M M S o c k e t

R T = 2 2 RR S = 2 7 RR p = 4 K 7

L P 2 9 9 5

V R E F = 1 . 2 5 V

V T T = 1 . 2 5 V

V D D = 2 . 5 V

R sR s

R sR s

R sR s

R sR s

A [ 1 3 : 1 4 ]

R sR s

R sR s

R sR s

R sR s

R sR s

R sR s

C S [ 2 : 3 ] *

R sR s

R sR s 2

C L K [ 3 : 5 ] / * C L K [ 3 : 5 ]

R TR T

R sR s

R TR T

R TR T

R TR T

R TR T

R TR T

R TR T

R TR T

R TR T

R TR T

V D D V D D

V R E F

Rp

Rp

3 . 3 V




The diagram in Figure 6-4 above shows the connection between the MPC8560 and the SODIMM on Torridon.

Each processor can support an SODIMM up to 1Gbit. Thirteen address signals, A[0:12], and the two bank address signals, BA[0:1], are used to support this address range. The other two address signals, A[13:14], are not used and are left unconnected.

Each processor support one SODIMM. As each SODIMM may have up to two banks, two chip selects, CS[0:1], are used. The other two chip selects, CS[2:3], which would be used if another DIMM were present on the design, are left unconnected.

Again, due to the fact that only one SODIMM is used, only three of the clock pairs are required.

Although not part of the DDR controller, the I2C interface is shown which supports the serial presence detect mechanism.

6.3.1 SchematicsThe schematics in Figure 6-5 show the MPC8560 - DDR SODIMM connection on Torridon.



DDR

Figure 6-5. MPC8560 DDR Controller




The schematics in Figure 6-5 above show the breakout from the MPC8560’s DDR controller

The following points should be noted.• Torridon supports four MPC8560 processors, each with its own dedicated DDR memory.

To differentiate the signals, the net names are preceded with a number: 0, 1, 2 or 3. • The undulating line connecting MSYNC_OUT and MSYNC_IN indicates that this signal

length must be of a certain length. The length of this signal will be determined during the layout process.

• Specific net names are given to the nets between the processor and the series resistor and the nets between the series resistor and the SODIMM. These specific net names are used when matching signal lengths during the layout.

• The use of discrete resistors, as opposed to resistor networks, makes the layout easier with respect to matching signal lengths. Using resistor networks would force several signals to converge to a single package. This makes line length matching more difficult as it limits flexibility.

The schematics in Figure 6-6 below show the connection to the SODIMM. The following points should be noted.

• In this case, resistor networks can be used as opposed to individual ones. The constraints on these signals (i.e. the distance to the VTT island) are not as stringent as on the previous signal, hence more variations on signal lengths can be tolerated.

• As a rule of thumb, two decoupling capacitors should be used for each resistor network.• In addition, two bulk capacitors (10uF) are also used.• A voltage tap is taken from the mid point of the VTT rail. This monitors the actual voltage

on this rail. This data is fed back to the voltage generator.



DDR

Figure 6-6. SODIMM Connection




The schematic in Figure 6-7 below shows the VTT voltage generation.

Figure 6-7. VTT Voltage Generation



DDR

6.4 LayoutThe following section details layout considerations.

6.4.1 Address and ControlThe diagram in Figure 6-8 below shows the usage of the address and control signals on Torridon.

Figure 6-8. Address and Control

The length of each signal is the length of the etch from the processor to the series resistor plus the length of the etch between the series resistor and the DDR SODIMM.

For example, the total length of the row address strobe is [RAS*] + [MRAS*].

To ensure correct operation, all the signals should be equal in length to each other to within 50mils.

The diagram in Figure 6-9 shows the layout of the address and control group.

MPC8560DDR

SDRAM

A[0:12] Rs MA[0:12]

CS[2:3]*

CS[0:1]* Rs MCS[0:1]*

WE* Rs MWE*

CAS* Rs MCAS*

RAS* Rs MRAS*

BA[0:1] Rs MBA[0:1]

A[13:14]

CKE[0:1] Rs MCKE[0:1]

Layout



Figure 6-9. Address and Control Layout

A[6]

A[9]

CKE1

A[11

]

Powe

rQUI

CCII

I

Vias

to S

eries

Res

istor

sA[

7]A[

5]

A[8]

A[3]

A[4]

A[2]



DDR

6.4.2 DataThe data group is made up of nine data lanes. Each data lane contains the byte of data, the strobe signal and the mask signal. The data signal group should be considered as nine separate byte lanes as detailed below in Table 6-2.

Although during normal operation, the designation of these signal groups is all but transparent to the user, the grouping of these signal lanes is important during the layout of the data signal group.

Table 6-2. Data Byte Lanes

Byte Lane Signal Name

0 DQ[0:7], DQS[0],DM[0]

1 DQ[8:15], DQS[1],DM[1]

2 DQ[16:23], DQS[2],DM[2]

3 DQ[24:31], DQS[3],DM[3]

3 DQ[32:39], DQS[4],DM[4]

3 DQ[40:47], DQS[5],DM[5]

6 DQ[48:55], DQS[6],DM[6]

7 DQ[56:63], DQS[7],DM[7]

8 ECC[0:7], DQS[8],DM[8]

Layout



The diagram below in Figure 6-10 shows the data lanes.

Figure 6-10. Data

The following rules should be applied when laying out the data signals.• Route each data byte lane on a single layer.• Each data byte lane consists of 10 signals. • Each signal has two sections - between the processor and the series resistor and between

the series resistor and the DIMM.• The 9 data byte lanes are as follows:

(xDQ + xMDQ)[7:0], (xDM+xMDM)[0], (xDQS+xMDQS)[0]








(xECC + xMECC[7:0], (xDM+xMDM)[8], (xDQS+xMDQS)[8]

Note: x = 0, 1, 2 or 3• All signals on a single byte lane should be equal +/- 25mils• All byte lanes should be equal +/- 250mils

MPC8560DDR

SDRAM

D[0:7], DQS0, DQM0 Rs MDQ[0:7], MDQS0, MDQM0

ECC[0:7], DQS8, DQM8 Rs MECC[0:7], MDQS8, MDQM8










DDR

The diagram in Figure 6-11 below shows the layout of one of the data lanes.

Figure 6-11. Data Layout

The diagram above shows the routing of the signals from the PowerQUICCIII to the series resistors, Rs.

DM3DQ[28] DQ[26] DQ[25] DQ[24] DQ[27]

DQ[29]

DQS3

DQ[30]

DQ[31]

PowerQUICCIII

Vias to Series Resistors

Layout



6.4.3 ClocksThe processor’s on chip DLLs (Delay Locked Loop) uses a PCB trace to measure how much delay is needed, so that the timing can be optimised. PCB traces allow extremely precise and predictable delays. The diagram in Figure 6-12 below shows this.

Figure 6-12. DLL Configuration

The DLL loop should exactly match the signal length of the clock path. i.e.

[MSYNC_OUT] + [MSYNC_IN] = [CLK0] + [MCLK0]

[MSYNC_OUT] + [MSYNC_IN] = [CLK0*] + [MCLK0*]

Where: CLK0 / CLK0* is the differential pair.

[x] denotes the length of signal x.

Rs is the series resistor.

Note: The same is true for any other clock pairs.

MPC8560

DLL

CLK3/CLK3*

MSYNC_IN

DDR SDRAM

Internal Clock

DLL

MSYNC_OUT

CLK4/CLK4*

CLK5/CLK5*

CKE0/CKE1

CLK0/CLK0*

CLK1/CLK1*

CLK2/CLK2*

Rs

Rs

Rs

Not Used

Rs

Rs

Rs

Rs

Rs

MCKE0/MCKE1

MCLK0/MCLK0*

MCLK1/MCLK1*

MCLK2/MCLK2*

DLL

DLL



DDR

Torridon uses one SODIMM per processor to implement its DDR. This required 3 pairs of clock signals. The diagram in Figure 6-13 below shows the signals used in the clocking scheme.

Figure 6-13. DDR Clock Signals

The following rules should be applied when laying out the clock signals.• Clock traces should be as short as possible• All the DDR clocks should be on the same PCB layer• The clocks must be treated as differential pairs. • Each clock signal must equal its differential partner +/- 10 mils.• They must be tightly coupled and remain (as far as possible) the same distance apart.• The clock pairs should not cross. If need be, the clock pairs can be swapped. i.e. clock pair

0 from the MPC8560 may be connected to clock pair 1 on the SODIMM. This is because all the clock pairs from the processor have identical timing.

• The clock pairs should all be equal +/- 25mils.• The length of the clock should be equal to the length of the longest address signal.• [MSYNC_IN] + [MSYNC_OUT] = longest clock signal +/- 10mils.

MPC8560

MSYNC_OUT

DDR SDRAM

MSYNC_IN

RsRs

RsRsCK0 MCK0

CKE0 RsRs

CKE1 RsRs

MCKE0

MCKE1

CK_N0 MCK_N0RsRs

RsRsCK1 MCK1

CK_N1 MCK_N1RsRs

RsRsCK2 MCK2

CK_N2 MCK_N2RsRs

Layout



The diagram in Figure 6-14 below shows the clock routing between the processor and an SODIMM.

Figure 6-14. Clock Layout

6.4.4 DDR PowerThe following points should be noted about the LP2995.

• AVIN and PVIN should be tied together for optimal performance. A local bypass capacitor should be placed as close as possible to the PVIN pin.

• GND should be connected to a ground plane with multiple vias for improved thermal performance.

• VSENCE, (used by the voltage regulator to monitor the voltage produced), should be connected to the VTT termination bus at the point where regulation is required. For mother-board applications an ideal location would be at the centre of the termination bus.

MSYNC_OUT MSYNC_IN

RS

Clock Pairs



DDR

• VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the memory controller. This provides the most accurate point for creating the reference voltage.

• VREF should be bypassed with a 0.01 uF or 0.1uF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the pin.

Figure 6-15. LP2995 Layout

The following points should be noted about the VREF voltage reference plane.• Use 30 mils trace between de coupling cap and destination• Maintain a 25 mils clearance from other nets.• Isolate VREF and/or shield with Ground.• Decouple using distributed 0.01uf and 0.1uf capacitors by the regulator, controller, and

SODIMM slot. • Place one 0.01uf and 0.1uf near pin one of the SODIMM. • Place one 0.1uf near the source of VREF, one near the VREF pin on the controller and two

between the controller and the SODIMM.

LP2995

By-PassCapacitor

Layout



Figure 6-16. VREF Layout

The following points should be noted about the VTT voltage reference plane.• Place the VTT island on the component side signals layer at the end of the bus behind the

DIMM slot.• Use a wide-island trace for current capacity• Place VTT generator as close to termination resistors as possible to minimize impedance

(inductance).• Place one or two 0.1uf de coupling capacitor by each termination RPACK on the VTT island

to minimize the noise on VTT. Other bulk (10-22uf) de coupling is also recommended to be placed on the VTT island.

L P 2995

D e-C oup lingC apacitor

30 m ilT race



DDR

The diagram in Figure 6-17 below shows an example of DDR layout.

Figure 6-17. VTT Island

To ensure the voltage on the Vtt island remains constant, it is monitored by the voltage regulator. The feedback from the island should be provided by tapping off the voltage at the mid point of the island. This is shown in Figure 6-18 below.

Figure 6-18. VTT Voltage Monitoring

VTT Island

LP2995 VTT tapped from mid point of VTT island



Chapter 7 RapidIOThis section describes the RapidIO sub-section on the Torridon Motherboard.

7.1 Overview

7.1.1 RapidIO InterconnectRapidIO is a point to point, packet switched interconnect. Developed as an open standard, the RapidIO architecture addresses the needs of present and future systems. RapidIO is focused as a processor, memory, and memory mapped I/O interface optimised for use inside a chassis.

7.1.2 The MPC8560’s RapidIO ControllerThe MPC8560 provides an integrated 8 bit parallel RapidIO interface which is based on the Rev 1.1 RapidIO Interconnect Specification. The port physically connects to other RapidIO devices via an 8/16 LP-LVDS (Link Protocol - Low Voltage Differential Signalling) physical layer.

The physical layer of the RapidIO unit can operate at up to 500 MHz. As the interface is defined as a source synchronous, double data rate, LVDS signaling interconnect, the theoretical unidirectional peak bandwidth is 1 Gbyte/s for an 8-bit port.

7.1.3 Signals DescriptionsRapidIO uses two distinct, uni-directional data paths; one for transmit and one for receive. Each data path is made up of the following components.

• Data Signals - The actual data being transmitted• Clock - Used to clock the data• Frame - Indicates the start of a frame

As RapidIO uses an LVDS interface, each signal is made up of two individual parts - the signal plus its differential compliment. Table 7-1 details the signals used for each point to point connection.



RapidIO

7.2 Design ConsiderationsThe following sections detail design considerations for RapidIO.

7.2.1 Signal TerminationDue to the high speed of LVDS, impedance matching is very important. Any discontinuities in the trace will cause reflections which can degrade the signal quality. The LVDS outputs need a termination resistor to close the loop. Without termination resistors, the interface will not work. The value of the termination resistor, (RT), should match the differential impedance of the transmission line to reduce the reflections. Typically this will range from 90 ohms to 100 ohms. See Figure 7-1

Figure 7-1. RapidIO Termination

As far as all Torridon is concerned, all of the RapidIO connections are between the MPC8560 processors and the Tundra TSI500 switch. Both the processors and the switch have the termination built in.

Table 7-1. RapidIO Interface Signals

Data Path SignalName Description

I/O(w.r.t.

Processor)

Receive RD[7:0]/RD[7:0]* 8 Bit Wide Data Input

RCLK/RCLK* Clock Input

RFRAME/RFRAME* Frame Input

Transmit TD[7:0]/TD[7:0]* 8 Bit Wide Data Output

TCLK/TCLK* Clock Output

TFRAME/TFRAME* Frame Output

RT

Driver Receiver

Signal

Signal*

Design Considerations



7.2.2 Signal ConnectionsThe connection between each processor and the switch is very straight forward. It is simply a point to point connection. No additional components are required.

The diagram in Figure 7-2 shows the connections of the RapidIO buses on Torridon.



RapidIO

Figure 7-2. RapidIO Signal Connections

Note: The receive port on the processor connects to the transmit port of the switch and vice-versa.

Torridon uses a 4 port, parallel RapidIO switch from Tundra Semiconductor, the TSI500.

M P C 8 5 6 0 T D [7 :0 ] /T D [7 :0 ] *T F R A M E /T F R A M E *T C L K /T C L K *

R D [7 :0 ] /R D [7 :0 ] *R F R A M E /R F R A M E *R C L K /R C L K *

T D [7 :0 ] /T D [7 :0 ] *T F R A M E /T F R A M E *T C L K /T C L K *

R D [7 :0 ] /R D [7 :0 ] *R F R A M E /R F R A M E *R C L K /R C L K *

TD[7

:0]/T

D[7

:0]*

TFR

AM

E/TF

RA

ME*

TCLK

/TC

LK*

RD

[7:0

]/RD

[7:0

]*R

FRAM

E/R

FRAM

E*R

CLK

/RC

LK*

TD[7

:0]/T

D[7

:0]*

TFR

AME/

TFR

AME*

TCLK

/TC

LK*

RD

[7:0

]/RD

[7:0

]*R

FRA

ME/

RFR

AM

E*

RC

LK/R

CLK

*

T S I 5 0 0

M P C 8 5 6 0

M P C 8 5 6 0

M P C 8 5 6 0

T r a n s m i tR e c e iv e

T r a n s m i t R e c e iv e

R e c e iv e

R e c e iv e

R e c e iv e

R e c e iv e

R e c e iv e

R e c e iv e

T r a n s m i t

T r a n s m i t

T r a n s m i t T r a n s m i t

T r a n s m i t

T r a n s m i t

Logic Analyser Connection



7.3 Logic Analyser ConnectionTo aid in the debug of RapidIO driver code and to allow the bus to be monitored, logic analyser connectors have been added to one of the RapidIO buses. Due to space constraints, it was only possible to add these connections onto one of the RapidIO buses, the one between the Boot Processor and the switch.

Torridon has been designed to support the Tektronix analyser. The TLA700 logic analyser with the TMS805 RapidIO Support Package directly supports RapidIO. See Figure 7-3.

Figure 7-3. Tektronix TLA700 System

The logic analyser connects to the motherboard using compression fit probes, the P6880. The P6880 is a 34-channel high-density compression probe with differential clock and differential data. This probe utilises a connector less probe attach mechanism for quick and reliable connection to the motherboard. See Figure 7-4.

Figure 7-4. P6880 Probes



RapidIO

The probes connect to the motherboard using compression fittings as shown in Figure 7-5.

Figure 7-5. Mother Board Connection

Each probe connects to a series of pads on the motherboard. As well as the 27 pads, the probe requires two holes. These holes are used to attach a back plate which ensures sufficient pressure can be applied to make a solid electrical connection. The diagram in Figure 7-6 shows the layout required for each probe.

Figure 7-6. Probe Layout

Physical Connections



7.4 Physical ConnectionsFour probes are required to allow access to bus, two for receive and two for transmit. On Torridon, these four probes are labelled as P30, P31, P32 & P33. Table 7-2, Table 7-3, Table 7-4, and Table 7-5 below detail the connections to these four probes.

Table 7-2. RapidIO Probe - P30


A1 RIO0_TXD0 RapidIO Transmit Data[0]

A2 GND 0 Volts

A3 RIO0_TXD0* RapidIO Transmit Data[0]*


A5 GND 0 Volts



A8 GND 0 Volts



A11 GND 0 Volts


A13 RIO0_TFRAME RapidIO Transmit Frame

A14 GND 0 Volts

A15 RIO0_TFRAME* RapidIO Transmit Frame*

B1 RIO0_TXD1 RapidIO Transmit Data[1]

B2 GND 0 Volts

B3 RIO0_TXD1* RapidIO Transmit Data[1]*


B5 GND 0 Volts



B8 GND 0 Volts



B11 GND 0 Volts




RapidIO



A1 NC Not Connected

A2 GND 0 Volts

A3 NC Not Connected

A4 NC Not Connected

A5 GND 0 Volts

A6 NC Not Connected

A7 NC Not Connected

A8 GND 0 Volts

A9 NC Not Connected

A10 NC Not Connected

A11 GND 0 Volts


A13 RIO0_TCLK RapidIO Transmit Clock

A14 GND 0 Volts

A15 RIO0_TCLK* RapidIO Transmit Clock*

B1 NC Not Connected

B2 GND 0 Volts

B3 NC Not Connected

B4 NC Not Connected

B5 GND 0 Volts

B6 NC Not Connected

B7 NC Not Connected

B8 GND 0 Volts

B9 NC Not Connected

B10 NC Not Connected

B11 GND 0 Volts


Physical Connections





A1 RIO0_RXD0 RapidIO Receive Data[0]

A2 GND 0 Volts

A3 RIO0_RXD0* RapidIO Receive Data[0]*


A5 GND 0 Volts



A8 GND 0 Volts



A11 GND 0 Volts


A13 RIO0_RFRAME RapidIO Receive Frame

A14 GND 0 Volts

A15 RIO0_RFRAME* RapidIO Receive Frame*

B1 RIO0_RXD1 RapidIO Receive Data[1]

B2 GND 0 Volts

B3 RIO0_RXD1* RapidIO Receive Data[1]*


B5 GND 0 Volts



B8 GND 0 Volts



B11 GND 0 Volts




RapidIO

Note: There are four distinct RapidIO busses on Torridon. Each bus is labelled RIOx_yyy where x is the bus number (0, 1, 2, or 3) and yyy is the signal name. (e.g. RCLK, TFRAME etc.)

RIO0 is the bus between the Boot Processor and the switch; RIO1 is the bus between Work Processor 1and the switch etc.



A1 NC Not Connected

A2 GND 0 Volts

A3 NC Not Connected

A4 NC Not Connected

A5 GND 0 Volts

A6 NC Not Connected

A7 NC Not Connected

A8 GND 0 Volts

A9 NC Not Connected


A11 GND 0 Volts


A13 RIO0_RCLK RapidIO Receive Clock

A14 GND 0 Volts

A15 RIO0_RCLK* RapidIO Receive Clock*

B1 NC Not Connected

B2 GND 0 Volts

B3 NC Not Connected

B4 NC Not Connected

B5 GND 0 Volts

B6 NC Not Connected

B7 NC Not Connected

B8 GND 0 Volts

B9 NC Not Connected


B11 GND 0 Volts


Layout Considerations



7.5 Layout ConsiderationsRapidIO uses differential signalling. This means that each individual signal is actually two separate wires. Care must be taken when routing these signals.

• The signals should be tightly coupled together.• Each signal should be equal to its complimentary signal to within a tolerance of +/- 10mils

(0.02mm)• Within a particular receive or transmit path, all signals should be equal to within a tolerance

of +/- 50mils (0.1mm)• The number of vias on any differential pair must be less than or equal to 4• The transmit signal path should routed on a separate layer to the receive signal path• RapidIO signals should be routed on a different plane than single ended signals• Each of the four RapidIO busses on Torridon (RIO0_yyy, RIO1_yyy, RIO2_yyy and

RIO3_yyy) are totally independent. There is no requirement to match signals between busses

• Within each RapidIO bus, the transmit and receive paths can be treated as independent. There is no requirement to match signals between receive and transmit paths

• The length of the bus should not exceed 3 inches.

The board shots in Figure 7-7 show some examples of RapidIO routing on Torridon.

Figure 7-7. RapidIO Receive Path Layout

Differential Pairs

PowerQUICCIII TSI500



RapidIO

The diagram above shows a receive path between one of the MPC8560’s and the TSI500 switch. Note that each signal pair has been tightly coupled and effectively routed as a single signal. Also note that the shortest signal has been lengthened to match the longest signal length.

The board shot above shows layer 8 of the PCB. The transmit path for this connection is routed separately on layer 11.

The diagram in Figure 7-8 shows the routing between the Boot Processor and the switch. This path incorporates the probes for the logic analyser.

Figure 7-8. RapidIO Receive Path Layout (With Logic Probes)

Differential Pairs

TSI500

PowerQUICCIII

Logic AnalyserProbe Connections



Chapter 8 GBit EthernetThis section describes the GBit Ethernet sub-section on the Torridon Motherboard.

8.1 OverviewTorridon provides five GBit Ethernet ports. The Boot Processor provides two of these ports, the other three are provided by each of the Work Processors. Connection to the outside world is made via IEEE 802.3 compliant twisted pair (T.P.) ports (10/100/1000-BaseT). Each port is controlled by the MPC8560’s triple speed Ethernet controller (TSEC). The TSEC incorporates a MAC that supports 10, 100,and 1000 Mbps Ethernet/802.3 networks. The TSEC includes address/data filtering, data insertion and extraction, 2-kbyte FIFOs, and DMA functions.The TSEC network interface supports multiple options. One is the Media Independent Interface (MII) option which uses 18 I/O pins and supports both data and a management interface to the PHY. The MII supports both 10 and 100 Mbps. The GBit Media Independent Interface (GMII) option is a super-set of the MII signals and supports data rates up to 1000Mbps.

8.2 GBit Ethernet ConnectionThe diagram in Figure 8-1 shows the basic parts to allow the MPC8560 to interface to the outside world via GBit Ethernet.

Figure 8-1. GBit Ethernet Connection

The MPC8560’s Triple Speed Ethernet Controller (TSEC) connects to the Ethernet physical device (PHY) via a GBit Media Independent Interface (GMII). Electrical isolation is provided between the PHY and the external connector, (RJ45), via a magnetic circuit. Each of these blocks will be discussed in more detail below.

MPC8560

TSEC

PHY

GMII

Magnetics RJ45



GBit Ethernet

8.3 GMII InterfaceAs 1000Mbps data rates are supported on Torridon, the GMII interface is used to interface the processor’s TSEC to its respective PHY device. Table 8-1 and Figure 8-2 detail the signals used in the GMII interface.

Table 8-1. TSEC GMII Interface Signals

Signal DescriptionI/O

(w.r.t. Processor)

COL Collision Input

CRS Carrier Sense Input

GTX_CLK GBit Transmit Clock Output

GTX_CLK125 GBit Transmit 125MHz Source Input

MDC Management Data Clock Output

MDIO Management Data Input/Output Input/Output

RX_CLK Receive Clock Input

RX_DV Receive Data Valid Input

RXD[7:0] Receive Data Input

RX_ER Receive Error Input

TX_CLK Transmit Clock Input

TXD[7:0] Transmit Data Output

TX_EN Transmit Enable Output

TX_ER Transmit Error Output

PHY Device



Figure 8-2. GMII Interface

8.4 PHY DeviceThe Marvell 88E1011 device provides the physical interface for the Ethernet connection on Torridon. The 88E1011 connects to the TSEC via the GBit Media Independent Interface, GMII, which is used for both the device’s control and data path.

The PHY may be reset independently by a general purpose pin on the MPC8560. It may also be reset by setting the most significant bit in the 88E1011’s control register via the MII management interface.

Each PHY has the ability to interrupt the MPC8560 by the assertion of its respective interrupt (*INT) pin. The polarity of this interrupt is programmable.

The initial power on status of the PHY is determined by seven configuration pins, CONFIG[6:0]. These pins determine various initial setting such as the PHY address, connection speed etc. Table 8-2 details the possible settings.

MPC8560

Transmit Data (TXD[7:0])

Transmit Enable (TX_EN)

Transmit Clock (TX_CLK)

Collision Detect (COL)

Receive Data (RXD[7:0])

Receive Error (RX_ER)

Receive Clock (RX_CLK)

Receive Data Valid (RX_DV])

Carrier Sense (CRS)

Management Data Clock (MDC)

Management Data I/O (MDIO)

88E1011

StatusLEDS

RJ45 with Built in Magnetics

Transmit Error (TX_ER)

Gigabyte Clock (GTX_CLK125)

Gigabyte Transmit Clock (GTX_CLK)

Reset PHY (Gx_RESET_N)

Interrupt PHY (Gx_INT_N)

ConfigurationPins



GBit Ethernet

Note: Refer to the 88E1011 Data Sheet for full details of the settings available

Each configuration pin defines three configuration bits. The three bit value is determined by tying the configuration pin to one of the other pins on the device.

Table 8-3 details the pins used to set the values of the configuration pins.

For example to set Config0 to 101, it must be connected to the LED_LINK100 pin.

Table 8-2. PHY Configuration Pins

Pin Bit[2] Bit[1] Bit[0]

Config0 PHYADR[2] PHYADR[1] PHYADR[0]

Config1 ENA_PAUSE PHYADR[4] PHYADR[3]

Config2 ANEG[3] ANEG[2] ANEG[1]

Config3 ANEG[0] ENA_XC DIS_125

Config4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_MODE[0]

Config5 DIS_FC DIS_SLEEP HWCFG_MODE[3]

Config6 SEL_BDT INT_POL 75/50 Ohm

Table 8-3. Setting PHY Configuration Pins

Pin Bit[2:0]

VDD0 111

LED_LINK10 110

LED_LINK100 101

LED_LINK1000 100

LED_DUPLEX 011

LED_RX 010

LED_TX 001

VSS 000

Magnetics & RJ45



Each one of the configuration pins must be tied to the appropriate pin. On Torridon each one of the PHY are configured as shown in Table 8-4.

This sets the PHYs up in the following initial state.• PHY address set to 0 1

• MAC Pause is not implemented• Auto negotiate - advertise all capabilities, force master operation• Disable MDI crossover• Enable generation of the 125MHz clock• Configure device to run in GMII to copper mode• Disable energy detect• Disable fibre/copper selection• Select the MDC/MDIO interface• Select the interrupt to be active high• Select 50 ohm termination to fibre. (Note: This is irrelevant as there is no support for fibre

on Torridon)1 Note: The second PHY on the Boot Processor is set to address 1 by connecting Config0 pin to LED_TX instead of VSS. All the other PHYs have an address of 0.

8.5 Magnetics & RJ45The PHY device provides an eight pin media dependent interface (MDI[3:0]+/-). This interface is made up of four differential pairs of signals which, via the magnetics, provide the connection to the RJ45 connector.

Table 8-4. PHY Configuration Pins on Torridon

Pin Connected to Bit[2:0]

Config0 VSS 000

Config1 VSS 000

Config2 LED_LINK10 110

Config3 VSS 000

Config4 VDD0 111

Config5 VDD0 111

Config6 VSS 000



GBit Ethernet

On Torridon, the magnetics and the RJ45 connector are integrated on a single device. As well as simplifying the design, this is a more space efficient solution. The device also includes two built in LEDs. See Figure 8-3 and Table 8-5.

Figure 8-3. RJ45 with Integrated Magnetics

8.6 Layout ConsiderationsAs far as layout was concerned, the routing of the signals on the GMII bus (between the MPC8560 and the PHY), was not overly critical.

Due to the fact that the PHY is situated close to the processor and the interface is digital, apart for following sound layout guidelines, no additional constraints were imposed on this interface.

However, the MDI bus between the PHY and the magnetics was more critical due to the relatively long signal lengths involved. The following constraints were imposed on the layout of the MDI bus.

• Each pair (e.g. Tx+ and TX-) should be routed so they are tightly coupled in the same layer and the separation between the two traces of the pair should remain constant over the entire length

• The signals in a pair should be equal in length to within a tolerance of +/- 10 mils (0.02mm)

Table 8-5. Ethernet Connections


1 Tx+ Transmit Data +ve

2 Tx- Transmit Data -ve

3 Rx+ Receive Data +ve

4 GND 0 Volts

5 GND 0 Volts

6 Rx- Receive Data -ve

7 GND 0 Volts

8 GND 0 Volts

Layout Considerations



• The signals across the bus should be equal in length to within a tolerance of +/- 50 mils (0.1mm)

• The number of vias on any signal should be less than or equal to 4. See Figure 8-4 below.

Figure 8-4. MDI Bus Layout

4 Pairs of Differential Signals

Signal pairs tightly coupled

Signals lengthened To match length



GBit Ethernet



Chapter 9 UARTThis section describes the UART sub-section on the Torridon Motherboard.

9.1 OverviewEach of the processors support a single RS232 port. The MPC8560’s SCC1 controller with a MAX3229 level translator, implements the standard RS232 serial I/O protocol. A DB9 connector is attached to the front of the board provides access to the boot processor’s serial port. The serial ports for the three work processors are accessible on three separate headers. See Figure 9-1.

Note the additional SCC control signals, Request to Send (RTS), Carrier Detect (CD) and Clear to Send (CTS) are not connected hence hardware flow control is not supported on this interface.

Figure 9-1. RS232 Interface

Table 9-1 shows the port usage on the MPC8560 for the serial ports.

Note: These signals are pin compatible with the MPC8540’s DUART controller. This means that the MPC8560 may be replaced with an MPC8540 and the RS232 interface will still function.

Table 9-1. Specific MPC8560 - UART Signals

Signal MPC8560 Pin Description

I/O(w.r.t.

Processor)

SCC1_RXD PD[31] RS232 Receive Data Input

SCC1_TXD PD[30] RS232 Transmit Data Output

MPC8560

MAX3229D-Connector

Transmit Data (TXD)

Receive Data (RXD)

SCC1



UART

Connection to the debug port is made via a standard 9 pin d-type connector. The pin out is shown in Table 9-2.

Table 9-2. RS232 Connector

Pin# Signal Connection

1 CD Not connected

2 RXD To SCC1 TXD

3 TXD To SCC1 RXD

4 DTR Not connected

5 GND 0 Volts

6 DSR Not connected

7 RTS Not connected

8 CTS Not connected

9 RI Not connected

Overview



The schematics are shown in Figure 9-2 and Figure 9-3.

Figure 9-2. MPC8560 CPM



UART

Figure 9-3. RS232 Transceiver

Overview



The following should be noted about the schematics:• Only the DEBUG_RXD and DEBUG_TXD signals from the CPM are used to drive the

RS232 interface. The other signals shown in the schematics are to control/monitor other devices on Torridon.

• The small package size of the MAX3229 helps limit board space



UART



Chapter 10 PCIThis section describes the PCI sub-section on the Torridon Motherboard.

10.1 OverviewAlthough Torridon supports four processors, only one of the PCI busses available is utilised. The boot processor provides a single 64 bit PCI slot. The PCI busses on the three Work Processors are not used, these busses are simply left as no connects on the motherboard.

As well as providing a 64 bit PCI slot, the Boot Processor also provides an interface to the Via Southbridge chip. This interface is further discussed in Chapter 11, “Peripheral Support”. The diagram in Figure 10-1 details the connection to the Boot Processor’s PCI bus.

Figure 10-1. Boot Processor’s PCI Bus

M PC8560

PCIBusCtrl.

64 Bit PCI BusREQ1*

PCI S

lot

GNT1*

Via

Sou

th B

ridg

e32 Bit PCI BusREQ0*GNT0*



PCI

The PCI connection to the PCI slot and the Via chip are very similar with a few notable differences.• Each “peripheral” uses a separate request/grant pair. The Via chip uses REQ0#/GNT0#, the

PCI slot uses REQ1#/GNT1#• The Via chip only uses 32 bits of the 64 bit bus.

10.2 PCI ClocksIn terms of clocks, the PCI bus sees three separate devices.

• The MPC8560• The PCI slot• The Via chip

All three devices are driven from a single 33MHz clock oscillator. The oscillator is passed through a fan out buffer to provide sufficient drive capability.

Refer to Section 14.2, “System Clocks” for details.

10.3 Bus ConnectivityFor the majority of the PCI signals, a straight point to point connection is made between the Boot processor, the interface connector and the Via chip.

10.4 PCI ConfigurationThe PCI interface on the Torridon board can be configured via switch settings. These switches are used to configure the following.

• The impedance of the interface• Switch between 32 and 64 bit mode• Enable/disable the internal arbitration unit• Enable/disable the PCI debug feature

Refer to Section 4.2, “MPC8560 Processor Configuration” for details.

10.5 SchematicsThe diagrams in Figure 10-2 and Figure 10-3 show the schematics pertaining to the PCI bus.

Schematics



Figure 10-2. MPC8560’s PCI Interface - Schematics



PCI

The following should be noted about the circuitry.• To guard against spurious requests/acknowledges, pull-ups are added to the

request/acknowledge lines• Pull-ups are added to the unused request inputs.• As the processor is the host, which initiates the PCI transactions, the IDSEL pin is pulled

low. This will guard against it replying to one of its own bus transactions.

Schematics



Figure 10-3. PCI Slot - Schematics



PCI

The following should be noted about the circuitry.• Control signals are pulled up• As the PCI bus on the MPC8560 is 3.3V only, the I/O voltage is set to 3.3V• As the PCI bus is limited to 33MHz (This is the maximum speed of the Via chip), the

M66EN signal, which advertises bus speed capability, is tied to 33MHz.• The IDSEL pin, which sets the address range for this PCI slot, is tied to address pin 19.

(This must be a unique address space on the bus)



Chapter 11 Peripheral SupportThis section describes the Peripheral sub-section on the Torridon Motherboard.

11.1 OverviewThe “Super South” South Bridge (VT82C686) from Via Technologies provides additional IO on Torridon; namely IDE, USB and PS2 interfaces.

The South Bridge is connected directly to the PCI bus on the boot processor. Please refer to Chapter 10, “PCI” for details of the interface.

11.2 IDE InterfaceTwo IDE interfaces, the Primary and the Secondary, are provided on Torridon. These are available at two separate 40 pin connectors, P23 and P24.

The IDE interfaces are driven directly from the Via Southbridge device. The schematics are shown in Figure 11-1 and Figure 11-2.

The following should be noted about the schematics• Series resistors are used to smooth out over/under shoots• A 2 pin header (HD23) allows a front panel LED to be added which will indicate when the

IDE interface is active.• An inverter is added on the reset drive signal (RSTDRV) to switch the polarity. (The

RSTDRV signal from the Via is active high, the IDE interface expects and active low signal)



Peripheral Support

Figure 11-1. Primary IDE Interface - Schematics

IDE Interface



Figure 11-2. Secondary IDE Interface - Schematics



Peripheral Support

11.2.1 Compact Flash Support

11.2.1.1 OverviewA CompactFlash card is essentially a small form factor card version of PCMCIA PC Card ATA (AT Attachment) specification and includes a True IDE (Integrated Drive Electronics) mode which is compatible with the ATA/ATAPI-4 specification. As such, there are 3 distinct interface modes that a CompactFlash card can use:

• PC Card Memory Mode (uses WE#, OE# to access memory locations)• PC Card I/O Mode (uses IOWR#, IORD# to access I/O locations)• True IDE Mode (uses IOWR#, IORD# to access I/O locations)

11.2.1.2 Implementation on TorridonThe CompactFlash card is essentially a solid state ATA disk drive. On Torridon, the CompactFlash is configured in True IDE mode. True IDE mode is selected by the OE* signal (also known as the ATA_SEL* pin) which is grounded during the assertion of reset.

Note: In True IDE mode, removal and hot insertion (i.e. insertion and removal of the card while the system is powered on) is not supported.

CompactFlash on Torridon is supported via a 3rd party adapter board which connects into one of the IDE headers on the board. These boards provide a standard IDE interface. See Table 11-1and Figure 11-3below.

Table 11-1. CompactFlash Interconnect

Signal Pin# Description

A[2:0] 18,19,20 Address Pins. Used to select one of eight registers in the task file.

A[10:3] 8,10,11,12,14,15,16,17

Address Pins. Not Used; connected to ground.

D[15:0] 31,30,29,28,27,49,48,47,6,5,4,3,2,23,

22,21

Data Pins. 0 is LSB, 15 is MSB. In True IDE mode, all task file operations are in byte mode on the low order bus and

all the data transfers use the 16 bit bus.

CS_N[1:0]

32,7 Chip Selects. Used to select either the task file registers or Alternate Status Register and Device Control Register.

ATA_SEL*

9 Enables True IDE Mode. Tied to ground.

IORD* 34 IO Read Strobe. Indicates when the CompactFlash Card should drive its data on the bus.

IOWD* 35 IO Write Strobe. Indicates valid data is on the bus.

IDE Interface



CSEL* 39 Used to configure the CompactFlash card as a master or a slave. Tied to ground to configure card as a master.

RESET* 41 Reset the Compact Flash.

INTRQ 37 Interrupt request to controller.

IORDY* 42 IO Ready.

PDIAG* 46 Passed Diagnostic. Not connected. (No slave device connected)

DASP* 45 Drive Active/Slave Present. Led indicates activity

CD[2:1]* 25,26 Card Detect. Not connected. (Hot Insertion not supported)

IOIS16* 24 16 Bit Access. Not connected. (16 bit transfer assumed)

VS[2:1]* 40,33 Voltage Sense. Not Connected.

INPACK* 43 Input Acknowledge. Not used in True IDE mode; connected to +3.3V

REG 44 Register Select. Not used in True IDE mode; connected to +3.3V

WE* 36 Write Enable. Not used in True IDE mode; connected to +3.3V

VCC 13,38 +3.3Volts

GND 1,50 0 Volts.

Table 11-1. CompactFlash Interconnect (continued)

Signal Pin# Description



Peripheral Support

Figure 11-3. CompactFlash Connection

11.3 USBThe Via chip provides two USB interfaces. A 10 pin header, HD27, allows connectivity to a standard USB connector. The schematics are shown in Figure 11-4.

The following should be noted• The USB interface is clocked from a separate 48MHz clock source• Fuses (F1, F2) protect against incorrect connectivity. In the event of a USB cable being

connected incorrectly, theses fuses will protect the power supply on the board. Incorrect connectivity may lead to the fuse being blown. In this event, the fuse would need to be replaced.

ID EC o n n ec to r

3 r d P a r tyC o m p a ctF la sh

A d a p terC a r d

A [2 :0 ]

IO R D _ N

D [1 5 :0 ]C S 1 _ N /C S 3 _ N

A [2 :0 ]

A [1 0 :3 ]

D [1 5 :0 ]C S [1 :0 ]

A T A _ S E L *

0 V

IO W D _ NIO R D _ NIO W D _ N

C S E L *

R E S E T _ NR S T D R V _ NIN T R QIR Q 1 5IO R D Y *

P D IA G *

D A S P *+ 3 .3 V

C D [2 :1 ]IO IS 1 6 *V S [2 :1 ]

+ 3 .3 V

IN P A C K *R E GW E *

V C C

G N D

IO R D Y

V IA ‘6 8 6

D R QD A C K

PS2



Figure 11-4. USB - Schematics

11.4 PS2The ability to use a PS2 keyboard and mouse is also provided by the Via chip. A stacked 6 pin DIN, P35, provides the interface. The schematics are shown in Figure 11-5.



Peripheral Support

Figure 11-5. PS2 - Schematics

The following should be noted.• A fuse (F3) protects the 5 Volt supply• Pull-ups are added to all the data/clock signals.



Chapter 12 CommunicationsThis section describes the Communications sub-section on the Torridon Motherboard.

12.1 Overview

12.2 TestIn addition to the five GBit Ethernet ports, Torridon provides connectivity to the outside world via

1. Two 128 pin connectors. These “QUADS” compatible connectors are pin compatible with the family of ADS boards from Motorola.

2. A UTOPIA Interface

12.3 QUADS Compatible HeadersThe QUADS compatible connectors are implemented using two 128 pin headers. These provide connection to the processor’s CPM and host bus. On Torridon, these connectors are controlled by Work Processor 1. These would allow the connection of an add on card which would typically provide additional PHYs.

For example, the TCOM card shown in Figure 12-1 provides the PHYS necessary to connect to an E1/T1 interface.



Communications

Figure 12-1. E1/T1 Card

QUADS Compatible Headers



As shown in Figure 12-2, two headers are provided for connectivity. As shown in Figure 12-3, one of these provides access to the CPM; the other to a de-multiplexed version of the host bus.

Figure 12-2. QUADS Compatible Headers

MP

C85

60

J316

Bit

UT

OP

IA

DD

R

MP

C85

60

MP

C85

60

TS

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Sw

itch

DD

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DD

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ype

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Gbi

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Bit

2G

Bit

3G

Bit

4

GB

it1

GB

it3

GB

it4

MP

C85

60

GB

it2

RJ4

5P

HY

RJ4

5P

HY

RJ4

5P

HY

RJ1

1R

J11

RJ1

1

PH

YU

AR

T1

UA

RT

2U

AR

T3

UA

RT

4

PH

YP

HY

PH

Y

UA

RT

1

UA

RT

2

UA

RT

3

UA

RT

4

GB

it5

GB

it5

RJ4

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Fla

sh+

Lat

ch

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ckG

ener

atio

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tage

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QU

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it P

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Acc

ess

Sou

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Bri

dge

IDEUSB IDE

J5P

ower

Wor

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roce

ssor

2

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roce

ssor

1

Wor

k P

roce

ssor

3

Boo

t Pro

cess

or



Communications

Figure 12-3. Connectivity to the QUADS Headers

The following tables (Table 12-1, Table 12-2, Table 12-3, Table 12-4, Table 12-5, Table 12-6, Table 12-7, and Table 12-8) detail the pinout required to allow QUADS compatible expansion cards to be used.

M PC8560

LocalBusCtrl.

LAD[0:31]LALELBCTL

Buffer&

Latch

LA[16:26]LD[0:15]Control

CPM

PA[31:0]

PB[31:4]PC[31:0]PD[31:4]




Table 12-1. ADS Compatible Expansion Connector - P28 - Row A

CONNECTOR PIN# SIGNAL DESCRIPTION

A1 LA16 Local Address Bus [16]











A12 BLA27 Burst Local Address Bus [27]





A17 +12V + 12 Volts

A18 +12V + 12 Volts


A20 +3.3V + 3.3 Volts

A21 +3.3V + 3.3 Volts

A22 +3.3V + 3.3 Volts

A23 +3.3V + 3.3 Volts

A24 +3.3V + 3.3 Volts


A26 +5V + 5 Volts

A27 +5V + 5 Volts

A28 +5V + 5 Volts

A29 +5V + 5 Volts

A30 +5V + 5 Volts

A31 +5V + 5 Volts

A32 +5V + 5 Volts



Communications

Table 12-2. ADS Compatible Expansion Connector - P28 - Row B


B1 0V 0 Volts

B2 0V 0 Volts

B3 0V 0 Volts

B4 NC Not Connected

B5 NC Not Connected

B6 NC Not Connected

B7 NC Not Connected

B8 NC Not Connected

B9 NC Not Connected







B16 0V 0 Volts

B17 0V 0 Volts




B21 +3.3V + 3.3 Volts

B22 +3.3V + 3.3 Volts

B23 +3.3V + 3.3 Volts

B24 +3.3V + 3.3 Volts


B26 +5V + 5 Volts

B27 +5V + 5 Volts

B28 +5V + 5 Volts

B29 +5V + 5 Volts

B30 +5V + 5 Volts

B31 +5V + 5 Volts

B32 +5V + 5 Volts




Table 12-3. ADS Compatible Expansion Connector - P28 - Row C


C1 0V 0 VoltsC2 BCLK2 Buffered Clock 2C3 0V 0 VoltsC4 BLCS_N6 Buffered Local Chip Select 6C5 BLCS_N7 Buffered Local Chip Select 7C6 0V 0 VoltsC7 NC Not ConnectedC8 NC Not ConnectedC9 NC Not ConnectedC10 HRESET Hard ResetC11 IRQ6* Interrupt 6C12 IRQ7* INterrupt 7C13 0V 0 VoltsC14 LD0 Local Data Bus [0]C15 LD1 Local Data Bus [1]C16 LD2 Local Data Bus [2]C17 LD3 Local Data Bus [3]C18 LD4 Local Data Bus [4]C19 LD5 Local Data Bus [5]C20 LD6 Local Data Bus [6]C21 LD7 Local Data Bus [7]C22 LD8 Local Data Bus [8]C23 LD9 Local Data Bus [9]C24 LD10 Local Data Bus [10]C25 LD11 Local Data Bus [11]C26 LD12 Local Data Bus [12]C27 LD13 Local Data Bus [13]C28 LD14 Local Data Bus [14]C29 LD15 Local Data Bus [15]C30 NC Not ConnectedC31 NC Not ConnectedC32 NC Not Connected



Communications



D1 0V 0 Volts

D2 0V 0 Volts

D3 0V 0 Volts

D4 BLWE_N0 Buffered Local Write Enable 0

D5 BLWE_N0 Buffered Local Write Enable 0

D6 0V 0 Volts

D7 BLGPL0 Buffered Local General Purpose Line 0






D13 0V 0 Volts

D14 BALE Buffered Address Latch Enable

D15 BLBCTL Buffered Local Bus Control

D16 0V 0 Volts

D17 0V 0 Volts

D18 0V 0 Volts

D19 0V 0 Volts

D20 0V 0 Volts

D21 0V 0 Volts

D22 0V 0 Volts

D23 0V 0 Volts

D24 0V 0 Volts

D25 0V 0 Volts

D26 0V 0 Volts

D27 0V 0 Volts

D28 0V 0 Volts

D29 0V 0 Volts

D30 0V 0 Volts

D31 0V 0 Volts

D32 0V 0 Volts




Table 12-5. ADS Compatible Expansion Connector - P29 - Row A


A1 PD[31] Port D [31]

A2 PD[30] Port D [30]

A3 PD[29] Port D [29]

A4 PD[28] Port D [28]

A5 PD[27] Port D [27]

A6 PD[26] Port D [26]

A7 PD[25] Port D [25]

A8 PD[24] Port D [24]

A9 PD[23] Port D [23]

A10 PD[22] Port D [22]

A11 PD[21] Port D [21]

A12 PD[20] Port D [20]

A13 PD[19] Port D [19]

A14 PD[18] Port D [18]

A15 PD[17] Port D [17]

A16 PD[16] Port D [16]

A17 PD[15] Port D [15]

A18 PD[14] Port D [14]

A19 PD[13] Port D [13]

A20 PD[12] Port D [12]

A21 PD[11] Port D [11]

A22 PD[10] Port D [10]

A23 PD[9] Port D [9]






A29 +5V + 5 Volts

A30 +5V + 5 Volts

A31 +5V + 5 Volts

A32 +5V + 5 Volts



Communications



B1 PA[31] Port A [31]

B2 PA[30] Port A [30]

B3 PA[29] Port A [29]

B4 PA[28] Port A [28]

B5 PA[27] Port A [27]

B6 PA[26] Port A [26]

B7 PA[25] Port A [25]

B8 PA[24] Port A [24]

B9 PA[23] Port A [23]

B10 PA[22] Port A [22]

B11 PA[21] Port A [21]

B12 PA[20] Port A [20]

B13 PA[19] Port A [19]

B14 PA[18] Port A [18]

B15 PA[17] Port A [17]

B16 PA[16] Port A [16]

B17 PA[15] Port A [15]

B18 PA[14] Port A [14]

B19 PA[13] Port A [13]

B20 PA[12] Port A [12]

B21 PA[11] Port A [11]

B22 PA[10] Port A [10]

B23 PA[9] Port A [9]













Table 12-7. ADS Compatible Expansion Connector - P29 - Row C


C1 PB[31] Port B [31]

C2 PB[30] Port B [30]

C3 PB[29] Port B [29]

C4 PB[28] Port B [28]

C5 PB[27] Port B [27]

C6 PB[26] Port B [26]

C7 PB[25] Port B [25]

C8 PB[24] Port B [24]

C9 PB[23] Port B [23]

C10 PB[22] Port B [22]

C11 PB[21] Port B [21]

C12 PB[20] Port B [20]

C13 PB[19] Port B [19]

C14 PB[18] Port B [18]

C15 PB[17] Port B [17]

C16 PB[16] Port B [16]

C17 PB[15] Port B [15]

C18 PB[14] Port B [14]

C19 PB[13] Port B [13]

C20 PB[12] Port B [12]

C21 PB[11] Port B [11]

C22 PB[10] Port B [10]

C23 PB[9] Port B [9]






C29 NC Not Connected

C30 0V 0 Volts

C31 0V 0 Volts

C32 0V 0 Volts



Communications

Table 12-8. ADS Compatible Expansion Connector - P29 - Row D


D1 PC[31] Port C [31]

D2 PC[30] Port C [30]

D3 PC[29] Port C [29]

D4 PC[28] Port C [28]

D5 PC[27] Port C [27]

D6 PC[26] Port C [26]

D7 PC[25] Port C [25]

D8 PC[24] Port C [24]

D9 PC[23] Port C [23]

D10 PC[22] Port C [22]

D11 PC[21] Port C [21]

D12 PC[20] Port C [20]

D13 PC[19] Port C [19]

D14 PC[18] Port C [18]

D15 PC[17] Port C [17]

D16 PC[16] Port C [16]

D17 PC[15] Port C [15]

D18 PC[14] Port C [14]

D19 PC[13] Port C [13]

D20 PC[12] Port C [12]

D21 PC[11] Port C [11]

D22 PC[10] Port C [10]

D23 PC[9] Port C [9]










UTOPIA Interface



12.4 UTOPIA InterfaceSome of the CPM pins from Work Processor 1are pinned out to a 105 pin connector to provide access to a 16 bit UTOPIA interface. This header is compatible with the Compact PCI specification. This interface is purely digital, Torridon does not support any UTOPIA PHYs. The pinout of this connector is shown in the following tables (Table 12-9, Table 12-10, Table 12-11, Table 12-12, Table 12-13, and Table 12-14.

Table 12-9. 16 Bit UTOPIA Connector - P7 - Row A


A1 +3.3V + 3.3 Volts

A2 0V 0 Volts

A3 0V 0 Volts

A4 TXADD4 Transmit Address [4]



A7 TXCLAV Transmit Cell Available

A8 TXSOC Transmit Start of Cell





A13 0V 0 Volts





A18 0V 0 Volts

A19 +3.3V + 3.3 Volts



Communications

Table 12-10. 16 Bit UTOPIA Connector - P7 - Row B


B1 0V 0 Volts

B2 +3.3V + 3.3 Volts

B3 0V 0 Volts

B4 TXADD3 Transmit Address [3]

B5 TXADD1 Transmit Address [1]

B6 TXPRTY Transmit Data Parity

B7 TXENB Transmit Enable

B8 TXD15 Transmit Data [15]




B12 TCLK Transmit Clock





B17 0V 0 Volts

B18 +3.3V + 3.3 Volts

B19 0V 0 Volts

Table 12-11. 16 Bit UTOPIA Connector - P7 - Row C


C1 0V 0 Volts

C2 0V 0 Volts

C3 0V 0 Volts

C4 0V 0 Volts

C5 0V 0 Volts

C6 0V 0 Volts

C7 0V 0 Volts

C8 0V 0 Volts

C9 0V 0 Volts

C10 0V 0 Volts

UTOPIA Interface



C11 0V 0 Volts

C12 0V 0 Volts

C13 0V 0 Volts

C14 0V 0 Volts

C15 0V 0 Volts

C16 0V 0 Volts

C17 0V 0 Volts

C18 0V 0 Volts

C19 0V 0 Volts

Table 12-12. 16 Bit UTOPIA Connector - P7- Row D


D1 0V 0 Volts

D2 +3.3V + 3.3 Volts

D3 0V 0 Volts

D4 RXADD3 Receive Address [3]

D5 RXADD1 Receive Address [1]

D6 RXPRTY Receive Data Parity

D7 RXENB Receive Enable

D8 RXD15 Receive Data [15]




D12 RCLK Receive Clock





D17 0V 0 Volts

D18 +3.3V + 3.3 Volts

D19 0V 0 Volts

Table 12-11. 16 Bit UTOPIA Connector - P7 - Row C (continued)




Communications

Table 12-13. 16 Bit UTOPIA Connector - P7 - Row E


E1 +3.3V + 3.3 Volts

E2 0V 0 Volts

E3 0V 0 Volts

E4 RXADD4 Receive Address [4]



E7 RXCLAV Receive Cell Available

E8 RXSOC Receive Start of Cell





E13 0V 0 Volts





E18 0V 0 Volts

E19 +3.3V + 3.3 Volts

Table 12-14. 16 Bit UTOPIA Connector - P7 - Row F


F1 0V 0 Volts

F2 0V 0 Volts

F3 0V 0 Volts

F4 0V 0 Volts

F5 0V 0 Volts

F6 0V 0 Volts

F7 0V 0 Volts

F8 0V 0 Volts

F9 0V 0 Volts

F10 0V 0 Volts



Chapter 13 ResetThis section describes the reset sub-section on the Torridon Motherboard.

13.1 OverviewAll the reset signals on the motherboard are handled by a CPLD. The CPLD monitors the various reset sources and asserts the required outputs.

13.2 Reset SourcesThere are four main sources of reset on the motherboard.

• Power On - After initial power on, the CPLD ensures all peripherals are brought out of reset in a controlled sequence

• Push Button - A board reset can be issued at any time by pressing the reset switch.• COP Reset - A debugger, connected to the COP interface of any of the four processors, may

cause a reset.• Boot Processor - The boot processor is capable of resetting the other processors on the

board



Reset

13.3 Reset SchemeThe diagram in Figure 13-1 shows the reset scheme utilised on Torridon. A CPLD responsible for controlling the resets on the board.

Figure 13-1. Reset Scheme

Table 13-1 details the reset signals used on Torridon.

BP_C

OP_H

RESET_N

WP1_C

OP_H

RESET_N

WP2_C

OP_H

RESET_N

WP3_C

OP_H

RESET_N

BP_C

OP_SR

ESET_N

WP1_C

OP_SR

ESET_N

WP2_C

OP_SR

ESET_N

WP3_C

OP_SR

ESET_N

BP_C

OP_TR

ST_N

WP1_C

OP_TR

ST_N

WP2_C

OP_TR

ST_N

WP3_C

OP_TR

ST_N

WP1_R

ESET_N

WP2_R

ESET_N

WP3_R

ESET_N

POR

ST

BP_R

ST_CO

NF_N

BP_H

RESET_N

BP_SR

ESET_N

BP_TR

ST_N

BP_H

RESET_R

EQ_N

WP1_R

ST_CO

NF_N

WP1_H

RESET_N

WP1_SR

ESET_N

WP1_TR

ST_N

WP1_H

RESET_R

EQ_N

WP2_H

RESET_R

EQ_N

WP2_R

ST_CO

NF_N

WP2_H

RESET_N

WP2_SR

ESET_N

WP2_TR

ST_N

WP3_H

RESET_R

EQ_N

WP3_R

ST_CO

NF_N

WP3_H

RESET_N

WP3_SR

ESET_N

WP3_TR

ST_N

BP_G

1_RESET_N

BP_G

2_RESET_N

WP1_G

1_RESET_N

WP2_G

1_RESET_N

WP3_G

1_RESET_N

VIA

_RST_R

EQ_N

AD

S_HR

ESET_N

PCI_R

ST_N

VIA

_RESET_N

TSI500_HW

_RST_N

BP COPW P1 COPW P2 COPW P3 COPB

P

Latch

WP1

Latch

WP2

Latch

WP3

Latch

Gbit

PHY

s

TSI500

Via

PCI Slot

QU

AD

SC

onn.

Voltage

Monitor

FPGA

Push to Make R

eset

Reset Scheme



Table 13-1. Reset Signals

Signal Description Asserted When? I/O(w.r.t. CPLD)

PORST Power on Reset On system power up Input

Push to Make Reset Push to Make Reset By user depressing switch Input

BP_COP_HRESET_N Boot Processor COP Hard Reset By COP toolsBy processor following a system reset

Input/Output

BP_COP_SRESET_N Boot Processor COP Soft Reset By COP toolsBy processor following a system reset

Input/Output

BP_COP_TRST_N Boot Processor COP Test Reset By COP tools Input

BP_HRESET_N Boot Processor Hard Reset By CPLD following system reset, COP hard reset or Boot Processor hard reset

request

Output

BP_SRESET_N Boot Processor Soft Reset By CPLD following system reset, COP soft reset

Output

BP_TRST_N Boot Processor Test Reset By CPLD following COP test reset Output

BP_HRESET_REQ_N Boot Processor Hard Reset Request By Boot Processor Input

BP_RST_CONF_N Boot Processor Reset Configuration On power up or any hard reset. Used to latch configuration pins

Output

WP1_COP_HRESET_N Work Processor 1 COP Hard Reset By COP toolsBy processor following a system reset

Input/Output

WP1_COP_SRESET_N Work Processor 1 COP Soft Reset By COP toolsBy processor following a system reset

Input/Output

WP1_COP_TRST_N Work Processor 1 COP Test Reset By COP tools Input

WP1_HRESET_N Work Processor 1 Hard Reset By CPLD following system reset, COP hard reset or Work Processor 1 hard reset

request

Output

WP1_SRESET_N Work Processor 1 Soft Reset By CPLD following system reset, COP soft reset

Output

WP1_TRST_N Work Processor 1 Test Reset By CPLD following COP test reset Output

WP1_HRESET_REQ_N Work Processor 1 Hard Reset Request By Work Processor 1 Input

WP1_RST_CONF_N Work Processor 1 Reset Configuration On power up or any hard reset. Used to latch configuration pins

Output


Input/Output


Input/Output



request

Output



Reset


Output




Output


Input/Output


Input/Output



request

Output


Output




Output

BP_G1_RESET_N Boot Processor’s TSEC PHY1 Reset On power up or any hard reset. Used to reset PHY

Output

BP_G2_RESET_N Boot Processor’s TSEC PHY2 Reset On power up or any hard reset. Used to reset PHY

Output

WP1_G1_RESET_N Work Processor 1’s TSEC PHY1 Reset On power up or any hard reset. Used to reset PHY

Output


Output


Output

TSI500_HW_RST_N TSI500 RapidIO Switch Reset On power on or Boot Processor reset Output

VIA_RESET_N Via Southbridge Reset On power on or Boot Processor reset Output

VIA_RESET_REQ_N Via Southbridge Reset Request Via requires a reset. (Software controlled) Input

PCI_RST_N PCI Bus Reset On power on or Boot Processor reset Output

ADS_HRESET_N Reset for QUADS Compatible Connections

On power on or Boot Processor reset Output

Table 13-1. Reset Signals (continued)

Signal Description Asserted When? I/O(w.r.t. CPLD)

Reset Scheme



The following diagram in Figure 13-2 shows how the resets are handled.

The majority of the reset signals are simply ANDed together. As they are all active low, this effectively act as an active low ORing function.

A delay is added to some of the signals (e.g. the reset of the PHYS) to ensure they power up in a specific order.

A delay is also added to the signals used to latch in the configuration pins. (e.g. BP_RST_CONF_N, WP1_RST_CONF_N etc.). The timing of this signal is critical. Refer to the MPC8560 User Manual for mode details.

Please note: This diagram illustrates the functionally of the CPLD, not the actual implementation.



Reset

Figure 13-2. Resets

B P _ C O P _ H R E S E T _ N

B P _ C O P _ S R E S E T _ N

B P _ C O P _ T R S T _ N

W P 1 _ C O P _ T R S T _ N

W P 2 _ C O P _ T R S T _ N

W P 3 _ C O P _ T R S T _ N

W P 1 _ R E S E T _ N

W P 2 _ R E S E T _ N

W P 3 _ R E S E T _ N

P O R S T

B P _ R S T _ C O N F _ N

B P _ H R E S E T _ N

B P _ S R E S E T _ N

B P _ T R S T _ N

B P _ H R E S E T _ R E Q _ N

W P 1 _ R S T _ C O N F _ N

W P 1 _ T R S T _ N

W P 2 _ R S T _ C O N F _ N

W P 2 _ T R S T _ N

W P 3 _ R S T _ C O N F _ N

W P 3 _ T R S T _ N

B P _ G 1 _ R E S E T _ N

B P _ G 2 _ R E S E T _ N

W P 1 _ G 1 _ R E S E T _ N

W P 2 _ G 1 _ R E S E T _ N

W P 3 _ G 1 _ R E S E T _ N

A D S _ H R E S E T _ N

P C I _ R S T _ N

V I A _ R E S E T _ N

T S I 5 0 0 _ H W _ R S T _ N

F P G A

W P 1 _ C O P _ H R E S E T _ N

W P 1 _ C O P _ S R E S E T _ N

W P 1 _ H R E S E T _ N

W P 1 _ S R E S E T _ N

W P 1 _ H R E S E T _ R E Q _ N

W P 2 _ C O P _ S R E S E T _ N

W P 2 _ H R E S E T _ N

W P 2 _ S R E S E T _ N

W P 2 _ H R E S E T _ R E Q _ N

W P 2 _ C O P _ H R E S E T _ N

W P 3 _ C O P _ S R E S E T _ N

W P 3 _ H R E S E T _ N

W P 3 _ S R E S E T _ N

W P 3 _ H R E S E T _ R E Q _ N

W P 3 _ C O P _ H R E S E T _ N

˜

˜

˜

˜

Reset Scheme





Reset



Chapter 14 ClockingThis section describes the Clocking sub-section on the Torridon Motherboard.

14.1 OverviewAll of the clocks used on the Torridon system are generated locally, it does not rely on any external stimulus.

There are four distinct clocking environments on the board• System Clocks• RapidIO Clocks• Processor Real Time Clock• GBit Ethernet PHY Clocks• Southbridge Real Time Clock

14.2 System ClocksThe system clock is provided by a 33.33MHz crystal oscillator. This clock is distributed, via a zero delay buffer, to produce the required system clocks. (i.e. processor, PCI, Southbridge and logic analyser.)



Clocking

The diagram in Figure 14-1 shows the clocking mechanism.

Figure 14-1. System Clocks

The diagram in Figure 14-2 shows the schematics for the system clock circuitry.

MPC9448ClockBuffer

33.33MHz

Oscillator

MPC8560

MPC8560

MPC8560

MPC8560

Boot Processor

Work Processor 1

Work Processor 2

Work Processor 3

VIA ‘686 Southbridge

PCI 64 Bit PCI Slot

Mictor Logic AnalyserConnector

System Clocks



Figure 14-2. System Clocks - Schematics



Clocking

The following should be noted about the circuitry.• The oscillator is socketed to allow different frequencies to be used (if required)• Series resistors (27 ohm) are inserted on all the clock lines to avoid any over/under shoot• The CLK_SEL input on the MPC9448 fan out buffer is pulled high to select the TTL clock

input. (as opposed to the differential input)• Adequate de coupling is added to the 3.3V power rail

14.3 RapidIO Clocks

14.3.1 OverviewThe RapidIO interface has independent receive and transmit clocks. These are referred to as inbound and outbound clocks.

A RapidIO endpoint receives the inbound clock as a LVDS pair from an adjacent RapidIO device through the RapidIO interface, then generates an internal clock using its own clock synchronizer.

The outbound (transmit) clock is generated from an internal PLL clock generator which provides the transmit clock by multiplexing the input clock (LVTTL).

RapidIO Clocks



The diagram in Figure 14-3 shows the RapidIO clocking scheme.

Figure 14-3. RapidIO Clocking

A RapidIO system can be designed to operate either asynchronously or synchronously to each RapidIO device. For asynchronous operation, each RapidIO device has its own separate outbound clock input. For synchronous operation, each RapidIO device shares a common clock source.

14.3.2 Torridon’s RapidIO Sub-SystemAs shown in Figure 14-4, Torridon’s RapidIO sub-system consists of four PowerQUICCIIIs connected to a four port RapidIO switch. All the connections to the respective ports are identical apart from the connection between the boot processor and Port 0 of the TSI500. Although this particular link also incorporates the connections to allow the bus to be probed by a logic analyser, this does not influence the clocking scheme.

RapidIO Device A

Clock Source

Transmit Clock –Device APLL

RapidIO Device B

ClockSynchroniser

Internal Logic

Receive Clock–Device B

Clock SourcePLL

Transmit Clock –Device BClockSynchroniser

Receive Clock–Device A

Internal Logic



Clocking

Figure 14-4. RapidIO Sub-System

RapidIOSwitch

BootProcessor

W ork Processor

W ork Processor

W orkProcessor

Tektronix Test Probe

Key:

RapidIO Clocks



14.3.3 Processor ClocksThe processor can generate the source of its RapidIO transmit clock from one of three separate sources. These sources are

• The RapidIO receive Clock• The internal CCB clock• The RapidIO_TX_CLK+/RapidIO_TX_CLK- inputs

The diagram in Figure 14-5 shows the different clock options available.

On Torridon, these options can be chosen using DIP switches, which set the appropriate configuration pins (LGPL0, LGPL1) on the PowerQUICCIII.

Figure 14-5. RapidIO Clock Options

14.3.4 TSI500 ClocksThe TSI500 switch may be clocked from one of two sources.

• A “slow speed” TTL clock• A high speed differential clock

Configuration Pins

Clock Source

RIO_TX_CLK+

RIO_TX_CLK-

CCB

RIO_RX_CLK+

RIO_RX_CLK-

RIO_TX_CLK+

RIO_TX_CLK-



Clocking

As with the processor, the selection of the clock source is made via configurations pins as shown in Figure 14-6.

Figure 14-6. TSI500 RapidIO Clock Options

/5

R E G _ C L K

1 G H z

P 0 _ C L K _ S E L [ 1 :0 ]

P 0 _ T X _ C L K +

P 0 _ T X _ C L K -

P 1 _ T X _ C L K +

P 1 _ T X _ C L K -

P 2 _ T X _ C L K +

P 2 _ T X _ C L K -

P 3 _ T X _ C L K +

P 3 _ T X _ C L K -

P 1 _ C L K _ S E L [ 1 :0 ]

P 2 _ C L K _ S E L [ 1 :0 ]

P 3 _ C L K _ S E L [ 1 :0 ]

5 0 0 M H z1 0 0 M H z

L S 0 _ C L K

H S P L L

H S P L L _ R A N G E _ S E L [ 1 :0 ]

H S P L L _ B Y P A S S _ C L K

L S 1 _ C L K

C O R E _ C L K _ S E L [ 1 :0 ]

RapidIO Clocks



The selection of clock is made on a per port basis; each port being individually configurable.

The “slow” speed clock is provided by two separate clock signals, LS0_CLK and LS1_CLK. Although these are running at the same frequency, they must be provided to the TSI500 out of sync. This is achieved by a “RoboClock” device which skews the two clocks by a fixed amount, again, selectable on Torridon via jumpers/switches.

The high speed clock pair is generated from the same circuitry as the processors RapidIO_TX_CLK+/RapidIO_TX_CLK- clocks.

14.3.5 Clock Distribution on TorridonThe RapidIO sub-system in Torridon can operate either synchronously or asynchronously.

For synchronous operation, each RapidIO device shares a common clock source. The clock source is generated by a 16MHz oscillator. This clock source is fed into a clock synthesizer (ICS8442) where the frequency is multiplied by a PLL. The multiplication factor is set via switches. This multiplied clock frequency is distributed around the board via a clock buffer (ICS8516).

Asynchronous operation is very similar. The four processors operate from a common clock as described above but the switch operates from a separate source.



Clocking

The diagram in Figure 14-7 shows the RapidIO clock distribution around Torridon.

Figure 14-7. RapidIO Clock Distribution on Torridon

The schematics in Figure 14-8 show how this is implemented.

R a p i d I OS w i t c h

B o o tP r o c e s s o r

W o r k P r o c e s s o r

W o r k P r o c e s s o r

W o r kP r o c e s s o r

L S 0 _ C L KL S 1 _ C L K

“ R o b o C l o c k ”

T X _ C L K _ I N +T X _ C L K _ I N -

T X _ C L K _ I N +T X _ C L K _ I N -

T X _ C L K _ I N +T X _ C L K _ I N -

T X _ C L K _ I N +T X _ C L K _ I N -

T X _ C L K _ I N +T X _ C L K _ I N -

0 T X _ C L K _ I N +

0 T X _ C L K _ I N -

2 T X _ C L K _ I N +

2 T X _ C L K _ I N -

3 T X _ C L K _ I N +

3 T X _ C L K _ I N -

1 T X _ C L K _ I N +

1 T X _ C L K _ I N -

5 0 0 _ T X _ C L K _ I N +

5 0 0 _ T X _ C L K _ I N -

0 T X _ C L K _ I N +

0 T X _ C L K _ I N -

1 T X _ C L K _ I N +

1 T X _ C L K _ I N -

2 T X _ C L K _ I N +

2 T X _ C L K _ I N -

3 T X _ C L K _ I N +

3 T X _ C L K _ I N -

5 0 0 _ T X _ C L K _ I N +

5 0 0 _ T X _ C L K _ I N -

F a n O u tB u f f e r

M u l t i p l i e r2 5 M H z

2 5 M H z

RapidIO Clocks



Figure 14-8. High Speed Clock Generation



Clocking

The following should be noted about the circuitry.• The base clock frequency is provided by a 25MHz crystal• Switches select the multiplication factor• A separate push to make switch allows the frequency multiplication to be changed on the

fly without the need to power cycle the system• Multiple, exact copies of the clock pairs are generated via a fan out buffer• In line resistors reduce any over/under shoot on the clock lines.• Adequate de coupling is required

RapidIO Clocks



Figure 14-9. Slow Speed Clock Generation



Clocking

The following should be noted about the circuitry.• The configurations pins which adjust the frequency multiplication and skew are set via

jumpers (not shown for simplicity)• In line resistors reduce any over/under shoot on the clock lines.• Adequate de coupling is required

14.4 Processor Real Time ClockAs well as the main clock, each processor uses a separate real time clock input. This clock has to be separate from the system clock and must be driven independently of the system clock.

On Torridon, a 16MHz crystal produces this clock input. As shown in Figure 14-10, a fan out buffer is used to distribute this clock signal so it may be driven to all four processors.

Figure 14-10. Processor Real Time Clocks

The diagram in Figure 14-11 shows the schematics for the real time clock circuitry

MPC905ClockBuffer

16MHz

Crystal

MPC8560

MPC8560

MPC8560

MPC8560

Boot Processor

Work Processor 1

Work Processor 2

Work Processor 3

Processor Real Time Clock



Figure 14-11. Processor Real Time Clocks - Schematics



Clocking

The following should be noted about the circuitry.• The capacitors (C413, C416) have been chosen to match the characteristics of the crystal• Series resistors (27 ohm) are inserted on all the clock lines to avoid any over shoot• As only four clock signals are required, a smaller part (MPC905) fan out buffer is used• Adequate de coupling is required to the 3.3V power rail

14.5 GBit Ethernet ClocksThe MPC8560’s Triple Speed Ethernet Controller (TSEC) requires an external clock to provide the stimulus for its transmit operation. A 125MHz clock input is require to operate the TSEC block. As shown in Figure 14-12, both of the TSEC blocks in an MPC8560 operate from the same clock input so only a single input is required.

On Torridon, Marvel 88E1011 devices provide the on-board GBit PHYs. The Marvel device provides the 125MHz clock to the MPC8560 from a 25MHz clock input.

Figure 14-12. GBit Ethernet Clocks

Note: Although both PHYs produce a 125MHz clock, only one is required to drive both PHYs. The other is a no connect on the board.

14.6 Southbridge Real Time ClockThe Via Southbridge chip provides a real time clock. This clock is required by some operating systems, e.g. Linux, to monitor the absolute time. This is used for various operations such as time stamping files, monitoring file backups etc.

MPC8560

TSEC1

125MHz x5TSEC2

88E1011

25MHz

x5

88E1011

25MHz125MHz

Southbridge Real Time Clock



On Torridon, this clock is provided by a dedicated 32kHz crystal. To enable the real time clock to operate when the main power supply is not present, a battery may be fitted to the system. A “standard” 3.3 V battery (similar to those used in personal computers) may be plugged into a 4 pin header. (HD33 in the schematics below).

A 3 pin jumper, JP19, is used to select the source of power. When the battery is fitted, a jumper between pin 2 and 3 on JP19 will select the battery as the power source for the real time clock.

To operate the real time clock in the event of the battery not being present, a jumper should be placed across pins 1 and 2 on JP19. This will route the boards main 3.3V power supply to the real time clock. Although this will allow the real time clock to function, it will only run when the main power is applied to the system. Hence, if this mode of operation is used, the real time clock will not correctly indicate the actual time.



Clocking

Figure 14-13. Real Time Clock Schematics



Chapter 15 Voltage RegulationThis section describes the Voltage Regulation sub-section on the Torridon Motherboard.

15.1 OverviewThe Torridon system requires a number of different voltages to power the various components on board. In fact, the board uses seventeen different power supplies. The majority of these voltages are generated on board.

15.2 Power AvailableThe board receives its power from one of two sources.

• The backplane• An ATX power supply.

The backplane will be provided by the end customer, so the supplied current will be variable depending on the specific implementation.

Table 15-1 shows the current supplied from an ATX power supply.

NB: Numbers given for a 300W, ATX 12V supply.

Table 15-1. Power Supplied from an ATX Power Supply

Voltage(Volts)

Current(Amps)

+3.3 V 28 A

+5 V 30 A

+12 V 15 A

+5VSB 2 A

-12 V 0.8 A

- 5 V 0.3 A



Voltage Regulation

15.3 Power RequiredTable 15-2 shows the main components on the board and their respective power requirements.

15.4 Power DistributionTorridon requires four voltages to operate correctly. These are as follows

• +12V• +5V• +3.3V• +5VSB

All the other voltages are generated from these stimulus.

The diagram in Figure 15-1 shows the power distribution around the board.

Table 15-2. Power Required

Device no. On Board

I/O Voltage(Volts)

CoreVoltage(Volts)

Power per Device(Watts)

Total POwer(Watts)

MPC8560 4 3.3 V 1.2 V 8 W 32 W

RapidIO Switch 1 3.3 V 3.3 V 1.5 W 1.5 W

DDR SDRAM 4 2.5 V 2.5 V 2.5 W 10 W

Clock Buffer 1 3.3 V 3.3 V 2.6 W 2.6 W

GBit PHY 5 3.3 V 3.3 V 1.2 W 6 W

Total 52.1 W

Power Distribution



Figure 15-1. Power Distribution

From Backplane / ATX Power Supply

Filter

Vdd (1.05 –

1.825V @

40A)

12V to

1.2V

AV

dd3 (1.05 –1.825V

@ 0.4A

)Filter

AV

dd2 (1.05 –1.825V

@ 0.4A

)Filter

AV

dd1 (1.05 –1.825V

@ 0.4A

)A

Vdd1

AV

dd2

AV

dd3

Vdd

MPC

8560

Vdd Sense

VssSense

12V to

2.5V

Vdd Sense

VssSense

GV

ddG

Vdd

(2.5V @

8A)

GV

ddD

DR

DIM

MG

Vdd

(2.5V @

12A)

2.5V to

1.25VC

onversion

Vref

Vref(1.25V

@ 0.5A

)V

tt(1.25V @

6A)

Vtt Term

inatioIslands

VttSense

Vtt Sense

OV

ddO

Vdd

(3.3V @

10A)

+3.3VO

therLogic

Ethernet PHY

Vddo

(3.3V @

3A)

Vddo

AV

ddlA

Vddl(2.5V

@ 1A

)D

Vddl(1.5V

@ 1A

)D

Vddl

5V to

2.5V

5V to

1.5V

+12V

+3.3V

+5V

+5V

+12V

TSI500V

dd

VddIO

VR

EF

Vdd (1.3V

@ 2A

)5V

to1.3V

VddIO

(2.5V @

2A)

5V to

2.5V

VR

EF (1.2V @

2A)

5V to

1.2V+5V

+5V

+5V

+3.3VC

PLD

5V to

3.3V

+5VSB

Isolator+3.3V

BP/A

TX

+5V B

P/ATX

+5V

+12V

3.3V

CPLD

Isolator



Voltage Regulation

The board must be supplied by four separate power supplies; +3.3V, +5V, +12V and +5VSB. All the other voltages are produced on board. The +5VSB is used to power the CPLD which is responsible for system reset and power up sequencing. Two separate isolators are used to turn the 5V and 3.3V onto the board. These switches allow the voltages to be turned on in a specific sequence. The sequence is detailed in Section 15.6, “Power Sequencing”.

15.5 Voltage GenerationThe diagram in Figure 15-1 above shows the power distribution around the system. The areas to be discussed are

• CPLD Power• 5V/3.3V Switching• MPC8560• DDR SDRAM• GBit Ethernet• TSI500 RapidIO Switch

Each of these will be discussed in detail.

15.5.1 CPLD PowerThe CPLD is responsible for controlling the resets and sequencing the power supply. This means that the CPLD must be powered on first. The 3.3V power supply for the CPLD is generated from the 5V Stand By (+5VSB). This voltage is present even before the ATX power supply is turned on with its “Power ON” signal. The CPLD is responsible for turning on the ATX power supply so it can not be powered from the “normal” 5V or 3.3V supply as they will not be present initially.

The 3.3V power is generated from the +5VSB using a MAXIM MAX1831 voltage regulator. See Figure 15-2.

Voltage Generation



Figure 15-2. CPLD Power - Schematics



Voltage Regulation

The following should be noted about the schematics in Figure 15-2 above:• The stand by voltage (+5VSB) provides the input power• Connecting the FBSEL pin directly to the REF pins sets the voltage to 3.3V. No resistor

divider network is required.

15.5.2 5V/3.3V SwitchingThe 5V and 3.3V power supplies, which come directly from the ATX (or the backplane), are turned on via FETs. This allows the various voltages on the board to be turned on in a specific sequence. See Figure 15-3.

Voltage Generation



Figure 15-3. 3.3V/5V Isolator - Schematics



Voltage Regulation

The following should be noted about the schematics in Figure 15-3 above: The sense resistors are not used. (This simplifies layout)

15.5.3 MPC8560

15.5.3.1 MPC8560 Power RequirementsTable 15-3 details the power requirements for one of the processors.

15.5.3.2 Core & PLL VoltageThe MPC8560’s core and PLL circuitry requires a voltage of between 0.8 and 1.5V at a maximum current of 20.1A. Hence for the four processors, a maximum current of 80.4A should be available. This power supply is generated from the 12V power rail using a POL (Point of Load) power module from Artesyn, the NXI100, shown in Figure 15-4.

Figure 15-4. NXI100 Power Module

Table 15-3. MPC8560 Power Requirements

Characteristic Power Source Voltage Est. Current

Max. Current

Core Supply Voltage VDD 0.8V - 1.5V 10A 20A

PLL Supply Voltage AVDD[1:3] 0.8V - 1.5V 0.1A 0.1A

DDR DRAM I/O Voltage GVDD 2.5V XA 2A

Three-speed Ethernet I/O, MII Management Voltage

LVDD 3.3V xA 1A

PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet,

DUART, system control and power management, I2C,

and JTAG I/O voltage

OVDD 3.3V XA 1.5V

Voltage Generation



The NXI100 is a point of load DC/DC convertor capable of delivering up to 81A. The module complies to the VRM9.0 specification.

The output voltage from the NXI100 is set using five configuration pins, VID0–VID4. The NXI100 uses an internal 5-bit DAC as a feedback-resistor voltage divider. The output voltage can be digitally set in 25mV increments from 1.1V to 1.85V using the VID0–VID4 inputs. The schematics in Figure 15-5 and Figure 15-6 show how the NXI100 module is used on Torridon.



Voltage Regulation

Figure 15-5. Vdd Power - Schematics

Voltage Generation



Figure 15-6. Vdd Power - Feedback- Schematics



Voltage Regulation

The following should be noted about the schematics in Figure 15-5 and Figure 15-6 above.• The VID settings are configured using DIP switches. This allows the voltages to be easily

changed. For example, to allow for a subsequent, low power version of the processor• Low ESR (Equivalent Series Resistance) capacitors are used to de couple the output (Vdd)

voltage• The NXI100 uses a feedback network to monitor the voltage at point of load and, if

necessary, adjust to allow for any voltage drop. (For example, if the point of load was physically a long distance away). Zero ohm resistors are used to allow the point of testing to be changed.

Voltage Generation



As well as the core voltage, the NXI100 also provides the voltage for the processors PLL circuitry. The Vdd power is fed through an RC network to provide the PLL voltage. See Figure 15-7.

Figure 15-7. PLL Power - Schematics



Voltage Regulation

15.5.3.3 DDR DRAM I/O VoltageThe MPC8560’s DDR DRAM I/O circuitry requires a voltage of 2.5V at a maximum current of 2A. This power supply is generated from the 12V power rail using an Artesyn module, DDR12, shown in Figure 15-8.

Figure 15-8. DDR12 Module

The DDR12 is also a point of load DC/DC convertor capable of producing 2.5V at 25A and 1.25V at 8A.

Note: Although the module is capable of generating the Vdd voltage (2.5 V) and the Vtt voltage (1.25V); on Torridon the DDR12 module is only used to supply the Vdd voltage (2.5V). The termination voltage (VTT) is generated locally for each individual VTT island. This method simplified the board layout.

Unlike the NXI100 module which used voltage ID pins (VIDs) to specify the output voltage, the DDR12 uses a simple resistor divider network to set the required output voltage. This voltage can be adjusted from 2.25V to 2.75V by changing a resistor value from open circuit to 41.7 ohms. The schematics in Figure 15-9 show how the 2.5V is generated on Torridon.

Voltage Generation



Figure 15-9. 2.5V Voltage Generation



Voltage Regulation

The following should be noted about the schematics in Figure 15-9 above:• The output voltage is set to 2.5V using R1376. • Low ESR (Equivalent Series Resistance) capacitors are used to de couple the output (Vdd)

voltage• Power On/Power Good signals are available for control/monitoring by the power on state

machine.

15.5.3.4 I/O VoltageThe MPC8560’s I/O circuitry requires a voltage of 3.3V at a maximum current of 2.5A. This power supply is taken directly from the 3.3V power rail provided.

15.5.4 DDR SDRAMAs well as 2.5V, the DDR SDRAM requires a termination voltage of 1.25V. Although it is possible to produce this voltage rail from the DDR12 module, the 1.25V required for each DIMM is generated locally. This method simplifies signal routing and layout.

Voltage Generation



A National Semiconductor LP2995 device is used to generate a 1.25V signal from the 2.5 V signal. The schematics are shown in Figure 15-10.

Figure 15-10. 1.25V Signal Generation



Voltage Regulation

The following should be noted about the schematics in Figure 15-10 above:• To distinguish the four separate 1.25V islands on Torridon, they are labeled VTT0, VTT1,

VTT2 and VTT3.• A sense signal, VTTx_Sense, is a tap taken from the midpoint of the VTT island. This

tracks the voltage and adjusts, if required.

15.5.5 GBit EthernetIn addition to a 3.3V supply, (which is taken from the 3.3V ATX power rail/backplane), the Ethernet PHYS also require 2.5V and 1.5V. Both of these voltage are generated using two separate MAXIM ‘1831 devices. The schematics are shown in Figure 15-11 and Figure 15-12.

Voltage Generation



Figure 15-11. GBit Ethernet - 2.5V Generation

The following should be noted about the schematics in Figure 15-11 above: The output voltage is fixed at 2.5V by tying the FBSEL pin to VCC (+5V)



Voltage Regulation

Figure 15-12. GBit Ethernet - 1.5V Generation

The following should be noted about the schematics in Figure 15-12 above: The output voltage is fixed at 1.5V by leaving the FBSEL pin unconnected.

Voltage Generation



15.5.6 TSI500In addition to a 3.3V supply, (which is taken from the 3.3V ATX power rail), the TSI500 also requires 2.5V, 1.3V and 1.2V. These voltages are generated using three separate MAXIM ‘1831 devices. The schematics are shown in Figure 15-13, Figure 15-14, and Figure 15-15.



Voltage Regulation

Figure 15-13. TSI500 - 2.5V Generation

The following should be noted about the schematics in Figure 15-13 above: The output voltage is fixed at 2.5V by tying the FBSEL pin to VCC (+5V)

Voltage Generation




The following should be noted about the schematics in Figure 15-14 above:• The output voltage is fixed at 1.3V using a resistor divider network. (R1372 & R285)• FBSEL is tied to ground



Voltage Regulation


The following should be noted about the schematics in Figure 15-15 above:• The output voltage is fixed at 1.2V using a resistor divider network. (R682 & R683)• FBSEL is tied to ground

Power Sequencing



15.6 Power SequencingTo ensure correct operation, it is imperative that the board is powered up in a controlled manner. This is achieved by the use of a simple state machine implemented in a CPLD.

A CPLD (EMP3128) is responsible for the power up sequence of the board. The diagram in Figure 15-16 shows the sequence of events.



Voltage Regulation

Figure 15-16. Power-Up Sequence

F ro m A T X / B ack p lan e

Reset+5VSB

Power onReset

PowerOn

ControlPLD

On

PS_ON

1122

33

44

66

7788

991010

+5V

+3.3V

PWR_OK5 555

Core_Power_On

Core_Power_GoodVdd

12V to 1.2VRegulator(NXI100)

DDR_Power_On

DDR_Power_Good

+2.5V12V to 2.5V

Regulator(DDR12)

+5V3.3V_Power_On

+3.3V

11 11

+3.3V

+1.25V2.5V to 1.25V

Regulator(LP2995)

VRef

Vtt

0V

1212

IO_LV_Power_On

+5V5V to 2.5V/1.5V/1.2VRegulator

(MAX1831s)

+2.5V_GEther+1.5V_GEther+2.5V_tsi500+1.2V_tsi500

+5V5V_Power_On

5V_Power_Good1313

1414

3.3V_Power_Good15 15

1616

Power Sequencing



The power up sequence for Torridon is as follows:1. The ATX/Backplane Power Supply supplies +5VSB (+5V Stand By) immediately after

power is applied. PS_Ready LED lights2. This voltage (+5VSB) is used by a DS1818 voltage monitor chip to generate a system

power on reset signal, (PORST), to the CPLD only. At this point, the sequence stops, awaiting intervention from the user.

3. Operator pushes the on/off switch to turn the system on.4. A Power Supply On (PS_ON) signal is sent back to the power supply.5. The power supply generates all the required voltages (i.e. 3.3V, 5V and 12V)6. The power supply sends a Power OK (PWR_OK) signal to Torridon to indicate that the

power is on.7. Torridon turns on the 5V power rail via the 5V_Power_On Signal.8. A voltage monitoring device (MAX5918) checks the 5V rail and sends a 5V_Power_Good

signal to the power on state machine9. Torridon turns on the core power rail via the Core_Power_On Signal10. A voltage monitor (NXI100) checks the Vdd rail and sends a Core_Power_Good signal to

the power on state machine11. Torridon turns on the +2.5V power rail (for DDR) via the DDR_Power_On Signal12. A voltage monitor (DDR12) checks the +2.5V rail and sends a DDR_Power_Good signal

to the power on state machine13. The +2.5V power rail is regulated via four National Semiconductor ('2995) devices (one

per processor) to generate the other required voltages for DDR (+1.25V, VRef, Vtt)14. Torridon turns on the 3.3V power rail via the 3.3V_Power_On Signal15. A voltage monitoring device (MAX5918) checks the 3.3V rail and sends a

3.3V_Power_Good signal to the power on state machine16. Torridon turns on the lower voltages to the peripherals (2.5V, 1.5V, 1.2V) via the

IO_LV_Power_On Signal



Voltage Regulation



Chapter 16 Processor SocketsThis section describes the processor socket used on the Torridon Motherboard.

16.1 OverviewDuring the development of the Torridon system, the PowerQUICCIII silicon was very new and fresh out of fabrication. In such an situation, it was deemed necessary to be able to easily change the processors on the motherboard. This prompted the decision to use sockets for the processors.

16.2 The Need For SocketsTypically during the initial release of new silicon, different behaviors can been seen over the range of parts available. These differences in behavior can be due to numerous reasons such as differences in process, test screening or device errata. Whatever the reason, it is advantageous to be able to easily replace processors on the motherboard.

Typically, processors would be removed simply by de soldering. However, as well as being time consuming, this adds undue stress to the board as it is baked to remove moisture and then locally heated to attach the new processor.

As well as allowing for faulty processors to be replaced, a socket also allows for new revisions of the processor to be tested.

16.3 Socket CriteriaNumerous solutions exist in the market place for processor sockets. When choosing a socket, the following criteria were considered.

• Cost: With each motherboard requiring up to 4 sockets, cost was particularly sensitive.• Size: Both in terms of height and width. An excessively tall socket could potentially foul

on an adjacent board when Torridon is plugged into a rack environment. A wide socket would use up valuable real estate limiting the number of components that could be placed on the board.

• Board Attachment: Some sockets require special modifications to the board. For example additional fixing holes may be required. The addition of fixing holes will adversely impact the available board space for other components both on top and bottom of the board. Some sockets may require a “rear bracket” for board attachment and rigidity. This has the potential problem of fouling on adjacent boards in a rack environment or against the metal box in a chassis environment.



Processor Sockets

• Socket Foot Print: Ideally, the same foot print should be used for both the socket and the processor. Typically sockets are only used in the first few boards. Once the silicon is deemed stable, the sockets are no longer necessary and the processors can be mounted directly on the motherboard. This means that during assembly, either a socket or a processor may be populated. Alternatively, a board may be fitted with a socket during initial debug. This socket may then be removed, and potentially re-used, and a processor fitted in its place. Some sockets use a different foot print than the processor itself. Using such a socket will obviously not allow processors and sockets to be swapped in/out of boards. Using such a socket will dictate that two versions of the mother board be manufactured, a version to take sockets and a version to take processors.

• Heat Sink Attachment: Depending on the environment (e.g. ambient temperature, air flow etc.), it may be necessary to add a heat sink to the processor. Ideally the heat sink used with the socket should also be usable on the “bare processor”. This means only one type of heat sink is required. Again, this allows flexibility where, at the assembly stage, a board may be populated with or without sockets.

16.4 The Choice of a SocketBased on the criteria detailed above, a socket solution from Emulation Technology was chosen. The socket had the following advantages.

• Low Cost (Approximately $300 each)• Reliability: This socket technology has been used by many customers in numerous systems

operating in various environments.• Foot Print: The socket uses the same foot print as the silicon. This would allow a socketed

and a non-socketed processor to be used on the same motherboard.• Size: The socket is only 2mm wider and 2mm deeper than the processor itself.• Height: The socket only adds 3mm to the overall height of the processor.• Board Attachment: No board changes (e.g. fitting holes) are required to accommodate the

socket• Heat Sink: The socket does not impair the top or sides of the processor meaning the same

heat sink may be used on a socketed and non-socketed processor.

16.5 Socket MechanicsThe socket solution is made up of two component parts.

1. The BPE (Base Package Emulator) is soldered to the motherboard. The BPE provides a 783 female connector into which a male socket can be inserted.

Socket Mechanics



2. The processor itself is soldered onto an FPA (Flat Pin Array).The FPA provides the processor with pins which mate with the BPE. Effectively the FPA turns the processor from a BGA (Ball Grid Array) package to a PGA (Pin Grid Array) package

The diagram in Figure 16-1 shows how the component parts fit together.

Figure 16-1. Socket Mechanics

The foot print of the BPE is identical to that of the PowerQUICCIII processor. This allows the BPE and the processor to be easily interchanged.

Torridon Motherboard 783 Pads

BPE-0783-3BG028-BL

FPA-783-3BG028-NS

PowerQUICCIIISoldered

Soldered

“Push to fit”



Processor Sockets

The diagram in Figure 16-2 illustrates how the processor and the socket may be inter-changed.

Figure 16-2. Processor - Socket Swapping

16.6 The Base Package Emulator (BPE)The Base Package Emulator (BPE) is soldered directly onto the motherboard. 783 spheres present on the bottom of the BPE are used to attach it to the motherboard. The socket provides 783 female sockets on top. They accept the pins on the bottom of the FPA (Flat Pin Array) adapter. See Figure 16-3.

Torridon Motherboard 783 Pads

PowerQUICCIIIBPE-0783-3BG028-BL

FPA-783-3BG028-NS

PowerQUICCIIISoldered

Soldered

“Push to fit”

The Base Package Emulator (BPE)



Figure 16-3. The BPE



Processor Sockets

16.7 The Flat Pin Array (FPA)The Flat Pin Array (FPA) adapter allows the processor to mate with the BPE. 783 pads are present on top of the FPA. The PowerQUICCIII is soldered directly on to these pads. The bottom of the adapter provides pins which fit directly into the BPE. See Figure 16-4.

The Flat Pin Array (FPA)



Figure 16-4. The FPA



Processor Sockets

16.8 Alternative PartsAlthough Torridon used the parts from Emulation Technology, similar socket are available from other companies. Table 16-1 provides alternative sockets that may be used.

16.9 Sockets on TorridonThe following pictures show the sockets on the Torridon motherboard: Table 16-5, Table 16-6, Table 16-7, Table 16-8, and Table 16-9.

Figure 16-5. BPE

Table 16-1. Alternative Socket Vendors

Component Part Vendor Part Number

BPE Emulation Technology

BPE-0783-3BG028-BL

BPE Advanced Interconnect

FHA783-715G

FPA Emulation Technology

FPA-783-3BG028-NS

FPA Advanced Interconnect

FHS783-715-GG

Sockets on Torridon



Figure 16-6. PowerQUICCIII in FPA

Figure 16-7. PowerQUICCIII in FPA - Side View



Processor Sockets

Figure 16-8. PowerQUICCIII + FPA + BPE

Figure 16-9. Heat Sink Attached



Chapter 17 Heat SinksThis section describes the Heat Sinks used on the Torridon Motherboard.

17.1 OverviewThe processors on Torridon are each fitted with a heat sink. The choice of size and type of heat sink is dependant on the environment in which the board is situated. Factors such as processor speed, ambient temperature and air flow all dictate the specific characteristics of the heat sink used.

17.2 Processor Thermal CharacteristicsTable 17-1 details the package thermal characteristics for the MPC8560 processor.

Table 17-1. Package Thermal Characteristics

Characteristic Symbol Value Unit Notes

Junction-to-ambient resistance (Natural convection on 1S board) θJA 30 °C/W 1,2

1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

Junction-to-ambient resistance (Natural convection on 2S2P board) θJMA 19 °C/W 1,3

3 Per JEDEC JESD51-6 with the board horizontal.

Junction-to-ambient resistance (Forced airflow (200 ft/min) on 1S board) θJMA 24 °C/W 1,3

Junction-to-ambient resistance (Forced airflow (200 ft/min) on 2S2P board)

θJMA 16 °C/W 1,3

Die junction-to-board thermal resistance θJB 10 °C/W 4

4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

Junction-to-case thermal resistance θJC 0.3 °C/W 5

5 Thermal resistance between the die and the case top surface without thermal grease.



Heat Sinks

17.3 Thermal Management InformationProper thermal control design is primarily dependent upon the system-level design i.e. the heat sink, airflow and thermal interface material. The recommended attachment method to the heat sink is illustrated in Figure 17-1. The heat sink should be attached to the printed circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force.

Figure 17-1. Heat Sink Attachment

17.4 Adhesives and Thermal Interface MaterialsA thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, the diagram in Figure 17-2 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a thermal resistance approximately six times greater than the thermal grease joint.

Thermal Interface Material

Heat SinkFC-PBGA Package

Heat SinkClip

Printed-Circuit Board

Die

Lid

Adhesiveor

Heat Sink Selection



Heat sinks are attached to the package by means of a spring clip to holes in the PCB. Therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure.

Figure 17-2. Thermal Performance of Interface Material

17.5 Heat Sink SelectionThe choice of the heat sink is dependant on a number of factors such as the space available, the air flow across the heat sink and the availability of a fan. This will be ultimately be determined by the mechanical constraints of a system.

For preliminary heat sink sizing, the die junction temperature can be expressed as

Tj = Ti + Tr + (θjc + θint + θsa) x Pd

0

0.5

1

1.5

2

0 10 20 30 40 50 60 70 80

Silicone Sheet (0.006 inch)Bare JointFloroether Oil Sheet (0.007 inch)Graphite/Oil Sheet (0.005 inch)Synthetic Grease

Contact Pressure (psi)

Spec

ific

Ther

mal

Res

ista

nce

(Kin

2 /W

)



Heat Sinks

Where:Tj is the die-junction temperature Ti is the inlet cabinet ambient temperatureTr is the air temperature rise within the computer cabinetθjc is the junction-to-case thermal resistanceθint is the adhesive or interface material thermal resistanceθsa is the heat sink base-to-ambient thermal resistancePd is the power dissipated by the device

During operation the die-junction temperatures (Tj) should be maintained within the specified range of 0 - 105°C.

The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30° to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5° to 10°C. The thermal resistance of some thermal interface material (θint) may be about 1°C/W. Assuming a Ti of 30°C, a Tr of 5°C, a FC-PBGA package θjc = 0.3, and a power consumption (Pd) of 7.0 W, the following expression for Tj is obtained:

Die-junction temperature: Tj = 30°C + 5°C + (0.3°C/W + 1.0°C/W + θsa) * 7.0 W

The heat sink-to-ambient thermal resistance (θsa) versus airflow velocity for a Aavid Thermalloy heat sink 10-THMA-01 is shown in the diagram in Figure 17-3.

Figure 17-3. Aavid Thermalloy 10-THMA-01 Thermal Characteristics

Assuming an air velocity of 1m/s.

Fans



1m/s is equal to 200 LFM. (Linear Feet per minute)

From the graph above, this will equate to an effective θsa of about 4°C/W, thus

Tj = 30°C + 5°C + (0.3°C/W +1.0°C/W + 4°C/W) x 7.0 W,

resulting in a die-junction temperature of approximately 72.1°C which is well within the maximum operating temperature of the component.

The diagram in Figure 17-4 shows the physical dimensions of the Aavid Thermalloy 10-THMA-01.

Figure 17-4. Aavid Thermalloy 10-THMA-01 Dimensions

17.6 FansTo aid in thermal dissipation, each heat sink is fitted with a fan. Running off a 12V supply, the 25mm x 25mm x 10mm fan is capable of providing an air flow of 1m/s.



Heat Sinks

17.7 Heat Sinks On TorridonThe photo in Figure 17-5 shows a heat sink on Torridon fitted with a fan.

Figure 17-5. Heat Sink on Torridon


Freescale Semiconductor A-1PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Appendix A SchematicsThe schematics for Torridon are shown on the following pages.


A-2 Freescale SemiconductorPRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Schematics

Figure A-1. Top Level

55

44

33

22

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_P

ow

er_

Go

od

WP

2_

CO

P_

TR

ST

_N

BP

_S

RE

SE

T_

N

RIO

3_

TX

CL

K_

IN

RIO

0_

TF

RA

ME

_N

Co

re_

Po

we

r_G

oo

d

WP

2_

HR

ES

ET

_R

EQ

_N

BP

_H

RE

SE

T_

N

BP

_R

ST

_C

ON

F_

N

BP

_S

YS

_C

LK

WP

3_

CO

P_

HR

ES

ET

_N

+5

V

BP

_C

OP

_S

RE

SE

T_

N

+2

.5V

tsi5

00

RIO

3_

TX

CL

K_

IN

tsi5

00

_V

DD

SH

UT

DO

WN

WP

1_

RT

C_

CL

K

WP

2_

HR

ES

ET

_N

+1

.2V

tsi5

00

VIA

_R

ES

ET

_R

EQ

_N

+1

2V

TS

I50

0_

LS

1_

CL

K

WP

2_

SR

ES

ET

_N

+5

V_

BP

TS

I50

0_

LS

0_

CL

K

RIO

2_

RF

RA

ME

_N

VIA

_C

LK

Co

re_

Po

we

r_O

n

RIO

2_

TC

LK

_N

5V

_P

ow

er_

On

DD

R_

Po

we

r_O

n

TS

I50

0_

INT

0_

N

+1

.5V

GE

the

r

WP

3_

CO

P_

TR

ST

_N

WP

3_

RT

C_

CL

K

TS

I50

0_

LS

0_

CL

K

+3

.3V

PS

_O

N

WP

2_

CO

P_

HR

ES

ET

_N

SY

ST

EM

_R

ES

ET

_N

SY

ST

EM

_R

ES

ET

_N

VIA

_IN

T

VIA

_IN

T

PC

I_IN

TA

_N

PC

I_IN

TA

_N

PC

I_C

LK

PC

I_R

ST

_N

-12

V

-12

V

AD

S_

HR

ES

ET

_N

AD

S_

HR

ES

ET

_N

LA

LE

DL

AL

E

DL

AL

EL

AL

E

ID[3

:0]

ID[3

:0]

WP

3_

INT

_N

WP

1_

INT

_N

BP

_IN

T_

N

WP

2_

INT

_N

BP

_IN

T_

N

WP

2_

INT

_N

WP

1_

INT

_N

WP

3_

INT

_N

WP

2_

INT

_N

WP

1_

INT

_N

BP

_IN

T_

NW

P3

_IN

T_

N

BP

_IN

T_

N

WP

2_

INT

_N

WP

3_

INT

_N

WP

1_

INT

_N

+5

V

CG

ND

BP

_G

1_

RE

SE

T_

NB

P_

G2

_R

ES

ET

_N

BP

_G

2_

RE

SE

T_

NB

P_

G1

_R

ES

ET

_N

WP

1_

G1

_R

ES

ET

_N

WP

2_

G1

_R

ES

ET

_N

WP

3_

G1

_R

ES

ET

_N

WP

1_

G1

_R

ES

ET

_N

WP

2_

G1

_R

ES

ET

_N

WP

3_

G1

_R

ES

ET

_N

LA

8

LA

8F

LA

8

FL

A8

US

R4

US

R4

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

To

p L

eve

l0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

37

2M

on

da

y, S

ep

tem

be

r 29

, 20

03

Pa

ge

59

Ra

pid

IO S

witc

h

DG

ND

tsi5

00_V

DD

+2

.5V

tsi5

00

+3

.3V

TS

I50

0_

LS

0_

CL

K

TS

I50

0_

INT

1_

NT

SI5

00

_IN

T0

_N

TS

I50

0_

HW

_R

ST

_N

TS

I50

0_

SW

_R

ST

_N

RIO

0_

TC

LK

_N

RIO

0_

TD

[0:7

]

RIO

0_R

FR

AM

E_N

RIO

0_R

FR

AM

E

RIO

0_

TD

_N

[0:7

]

RIO

0_

RC

LK

_N

RIO

0_

TC

LK

RIO

0_R

D_N

[0:7

]

RIO

0_

TF

RA

ME

_N

RIO

0_

RC

LK

RIO

0_T

FR

AM

E

RIO

0_R

D[0

:7]

RIO1_RD_N[0:7]

RIO1_RD[0:7]

RIO1_TD[0:7]

RIO1_TD_N[0:7]

RIO1_TCLK_N

RIO1_TFRAME_N

RIO1_TCLKRIO1_TFRAME

RIO1_RFRAMERIO1_RCLK

RIO1_RFRAME_N

RIO1_RCLK_N

RIO

2_

RC

LK

RIO

2_R

D_N

[0:7

]

RIO

2_

TC

LK

_N

RIO

2_R

D[0

:7]

RIO

2_T

FR

AM

E

RIO

2_R

FR

AM

E_N

RIO

2_

RC

LK

_N

RIO

2_

TF

RA

ME

_N

RIO

2_

TD

[0:7

]

RIO

2_

TD

_N

[0:7

]

RIO

2_

TC

LK

RIO

2_R

FR

AM

E

RIO3_RD_N[0:7]

RIO3_RFRAME_N

RIO3_RCLK_N

RIO3_RD[0:7]

RIO3_RFRAMERIO3_RCLK

RIO3_TCLK_N

RIO3_TD[0:7]

RIO3_TCLK

RIO3_TD_N[0:7]

RIO3_TFRAMERIO3_TFRAME_N

TS

I500_T

XC

LK

_IN

TS

I50

0_

TX

CL

K_

IN_

N

TS

I50

0_

LS

1_

CL

K

+1

.2V

tsi5

00

Pa

ge

67

Re

se

t

SY

S_R

ES

ET

_N

DG

ND

BP

_H

RE

SE

T_R

EQ

_N

WP

1_H

RE

SE

T_R

EQ

_N

WP

2_H

RE

SE

T_R

EQ

_N

WP

3_H

RE

SE

T_R

EQ

_N

TS

I50

0_

SW

_R

ST

_N

TS

I50

0_

HW

_R

ST

_N

WP

3_H

RE

SE

T_N

WP

2_H

RE

SE

T_N

WP

1_H

RE

SE

T_N

BP

_H

RE

SE

T_N

WP

3_S

RE

SE

T_N

WP

2_S

RE

SE

T_N

WP

1_S

RE

SE

T_N

BP

_S

RE

SE

T_N

WP

3_C

OP

_H

RE

SE

T_N

WP

2_C

OP

_H

RE

SE

T_N

WP

1_C

OP

_H

RE

SE

T_N

BP

_C

OP

_H

RE

SE

T_N

BP

_C

OP

_S

RE

SE

T_N

WP

2_C

OP

_S

RE

SE

T_N

WP

1_C

OP

_S

RE

SE

T_N

WP

3_C

OP

_S

RE

SE

T_N

BP

_T

RS

T_

NW

P1

_T

RS

T_

N

WP

2_

TR

ST

_N

WP

3_

TR

ST

_N

BP

_C

OP

_T

RS

T_

NW

P1

_C

OP

_T

RS

T_

N

WP

2_

CO

P_

TR

ST

_N

WP

3_

CO

P_

TR

ST

_N

BP

_R

ST

_C

ON

F_N

PS

_O

N

+5V

SB

PW

R_O

K

Co

re_

Po

we

r_O

nD

DR

_P

ow

er_

Go

od

Co

re_

Po

we

r_G

oo

d

3.3

V_

Po

we

r_O

n

5V

_P

ow

er_

On

IO_

LV

_P

ow

er_

On

5V

_P

ow

er_

Go

od

3.3

V_

Po

we

r_G

oo

dD

DR

_P

ow

er_

On

PC

I_R

ST

_N

WP

1_R

ES

ET

_N

WP

2_R

ES

ET

_N

WP

3_R

ES

ET

_N

VIA

_R

ES

ET

_R

EQ

_N

VIA

_O

NV

IA_R

ES

ET

_N

AT

X_B

PS

HU

TD

OW

N

WP

1_R

ST

_C

ON

F_N

WP

2_R

ST

_C

ON

F_N

WP

3_R

ST

_C

ON

F_N

SY

ST

EM

_R

ES

ET

_N

VIA

_IN

T

PC

I_IN

TA

_N

AD

S_H

RE

SE

T_N

DL

AL

EL

AL

E

ID[3

:0]

BP

_G

1_

RE

SE

T_

NB

P_

G2

_R

ES

ET

_N

WP

1_

G1

_R

ES

ET

_N

WP

2_

G1

_R

ES

ET

_N

WP

3_

G1

_R

ES

ET

_N

LA

8F

LA

8

US

R4

Pa

ge

72

WP

- De

bu

g P

orts

+3

.3V

DG

ND

WP

1_T

XD

WP

1_R

XD

WP

2_T

XD

WP

3_T

XD

WP

2_R

XD

WP

3_R

XD

Pa

ge

68

Po

we

r Su

pp

ly

DG

ND

+3

.3V

Vd

d

+5

V

+2

.5V

PS

_O

N

PW

R_O

K

+2

.5V

tsi5

00

+1

.5V

GE

the

r+

2.5

VG

Eth

er

tsi5

00_V

DD

CG

ND

+5V

SB

Co

re_

Po

we

r_O

n

DD

R_

Po

we

r_G

oo

dC

ore

_P

ow

er_

Go

od

5V

_P

ow

er_

On

IO_

LV

_P

ow

er_

On

5V

_P

ow

er_

Go

od

3.3

V_

Po

we

r_O

n

3.3

V_

Po

we

r_G

oo

d

DD

R_

Po

we

r_O

n

SE

NS

E_V

DD

SE

NS

E_V

SS

+3

.3V

_B

P

+5

V_

BP

+5V

SB

_B

P

+1

2V

+1

.2V

tsi5

00

-12

V

Pa

ge

4

Bo

ot P

roce

sso

r

RIO

0_

TC

LK

RIO

0_R

D[0

:7]

RIO

0_

TC

LK

_N

RIO

0_

TD

_N

[0:7

]

RIO

0_R

D_N

[0:7

]

RIO

0_T

FR

AM

ER

IO0

_T

FR

AM

E_

N

RIO

0_

TD

[0:7

]

RIO

0_R

FR

AM

ER

IO0

_R

CL

K_

NR

IO0

_R

CL

K

RIO

0_R

FR

AM

E_N

RIO

0_T

XC

LK

_IN

RIO

0_T

XC

LK

_IN

_N

SY

S_R

ES

ET

_N

DG

ND

+3

.3V

+2

.5V

+3

.3V

+2

.5V

GE

the

r+

1.5

VG

Eth

er

CG

ND

Vd

d

BP

_R

TC

_C

LK

BP

_S

YS

_C

LK

BP

_H

RE

SE

T_R

EQ

_N

BP

_S

RE

SE

T_N

BP

_H

RE

SE

T_N

BP

_C

OP

_S

RE

SE

T_N

BP

_C

OP

_H

RE

SE

T_N

BP

_T

RS

T_

NB

P_

CO

P_

TR

ST

_N

TS

I50

0_

INT

1_

NT

SI5

00

_IN

T0

_N

BP

_R

ST

_C

ON

F_N

WP

1_R

ES

ET

_N

WP

2_R

ES

ET

_N

WP

3_R

ES

ET

_N

LA

_C

LK

SE

NS

E_V

DD

SE

NS

E_V

SS

VIA

_C

LK

VIA

_O

NV

IA_R

ES

ET

_N

VIA

_R

ES

ET

_R

EQ

_N

SH

UT

DO

WN

+1

2V

+5

V

SY

ST

EM

_R

ES

ET

_N

VIA

_IN

T

PC

I_IN

TA

_N

PC

I_C

LK

PC

I_R

ST

_N

-12

V

DL

AL

EL

AL

EID

[3:0

]

BP

_IN

T_

N

WP

1_

INT

_N

WP

2_

INT

_N

WP

3_

INT

_N

BP

_G

1_

RE

SE

T_

NB

P_

G2

_R

ES

ET

_N

LA

8F

LA

8

US

R4

Pa

ge

47

Wo

rk P

roce

sso

r 3

RIO3_RFRAME_N

RIO3_RCLK

RIO3_TFRAME_N

RIO3_TD_N[0:7]

RIO3_RD[0:7]

RIO3_TFRAME

RIO3_RCLK_N

RIO3_TCLK

RIO3_RFRAME

RIO3_TD[0:7]

RIO3_TCLK_N

RIO3_RD_N[0:7]

RIO

3_T

XC

LK

_IN

RIO

3_T

XC

LK

_IN

_N

DG

ND

+3

.3V

WP

3_

SY

S_

CL

K

WP

3_C

OP

_S

RE

SE

T_N

WP

3_H

RE

SE

T_N

WP

3_

RT

C_

CL

K

WP

3_C

OP

_H

RE

SE

T_N

WP

3_

TR

ST

_N

WP

3_

CO

P_

TR

ST

_N

WP

3_H

RE

SE

T_R

EQ

_N

WP

3_S

RE

SE

T_N

+2

.5V

Vd

d

WP

3_R

ST

_C

ON

F_N

+2

.5V

GE

the

r+

1.5

VG

Eth

er

WP

3_T

XD

WP

3_R

XD

+1

2V

WP

3_

INT

_N

WP

1_

INT

_N

WP

2_

INT

_N

BP

_IN

T_

N

CG

ND

WP

3_

G1

_R

ES

ET

_N

Pa

ge

64

Clo

ckin

g

RIO

1_T

XC

LK

_IN

RIO

1_T

XC

LK

_IN

_N

RIO

2_T

XC

LK

_IN

_N

RIO

2_T

XC

LK

_IN

RIO

3_T

XC

LK

_IN

_N

RIO

3_T

XC

LK

_IN

BP

_R

TC

_C

LK

BP

_S

YS

_C

LK

WP

1_

SY

S_

CL

KW

P1

_R

TC

_C

LK

WP

2_

SY

S_

CL

KW

P2

_R

TC

_C

LK

WP

3_

SY

S_

CL

KW

P3

_R

TC

_C

LK

RIO

0_T

XC

LK

_IN

_N

RIO

0_T

XC

LK

_IN

PC

I_C

LK

+3

.3V

DG

ND

TS

I50

0_

LS

0_

CL

K

LA

_C

LK

TS

I500_T

XC

LK

_IN

TS

I50

0_

TX

CL

K_

IN_

N

VIA

_C

LK

TS

I50

0_

LS

1_

CL

K

Pa

ge

35

Wo

rk P

roce

sso

r 2

RIO

2_T

XC

LK

_IN

RIO

2_T

XC

LK

_IN

_N

RIO

2_R

D[0

:7]

RIO

2_

TF

RA

ME

_N

RIO

2_T

FR

AM

E

RIO

2_

RC

LK

RIO

2_

TD

_N

[0:7

]

RIO

2_R

FR

AM

E

RIO

2_

TD

[0:7

]

RIO

2_

TC

LK

_N

RIO

2_

RC

LK

_N

RIO

2_R

D_N

[0:7

]

RIO

2_R

FR

AM

E_N

RIO

2_

TC

LK

DG

ND

WP

2_

TR

ST

_N

+3

.3V

WP

2_C

OP

_H

RE

SE

T_N

WP

2_S

RE

SE

T_N

WP

2_H

RE

SE

T_R

EQ

_N

WP

2_

CO

P_

TR

ST

_N

WP

2_

RT

C_

CL

KW

P2

_S

YS

_C

LK

WP

2_H

RE

SE

T_N

WP

2_C

OP

_S

RE

SE

T_N

+2

.5V

Vd

d

WP

2_R

ST

_C

ON

F_N

+2

.5V

GE

the

r+

1.5

VG

Eth

er

WP

2_R

XD

WP

2_T

XD

+1

2V

BP

_IN

T_

N

WP

1_

INT

_N

WP

3_

INT

_N

WP

2_

INT

_N

WP

2_

G1

_R

ES

ET

_N

Pa

ge

23

Wo

rk P

roce

sso

r 1

RIO1_RFRAME

RIO1_TCLK

RIO1_TFRAME_N

RIO1_RCLK

RIO1_TCLK_N

RIO1_RCLK_N

RIO1_RFRAME_NRIO1_RD[0:7]

RIO1_TD[0:7]

RIO1_TFRAME

RIO1_TD_N[0:7]

RIO1_RD_N[0:7]

RIO

1_T

XC

LK

_IN

_N

RIO

1_T

XC

LK

_IN

DG

ND

WP

1_C

OP

_H

RE

SE

T_N

WP

1_S

RE

SE

T_N

WP

1_C

OP

_S

RE

SE

T_N

WP

1_

SY

S_

CL

KW

P1

_R

TC

_C

LK

WP

1_

CO

P_

TR

ST

_N

WP

1_H

RE

SE

T_R

EQ

_N

+3

.3V

WP

1_

TR

ST

_N

WP

1_H

RE

SE

T_N

+2

.5V

Vd

d

WP

1_R

ST

_C

ON

F_N

+2

.5V

GE

the

r+

1.5

VG

Eth

er

WP

1_T

XD

WP

1_R

XD

+5

V_

BP

+3

.3V

_B

P

+5V

SB

_B

P

+1

2V

AT

X_B

P

AD

S_H

RE

SE

T_N

WP

1_

INT

_N

WP

2_

INT

_N

WP

3_

INT

_N

BP

_IN

T_

N

+5

V

WP

1_

G1

_R

ES

ET

_N



Figure A-2. Boot Processor—Top Level

55

44

33

22

11

DD

CC

BB

AA

BP

_H

RE

SE

T_

RE

Q_

N

I2C

_S

CL

RIO

0_

RC

LK

_N

DG

ND

MS

RC

ID0

RIO

0_

RD

[0:7

]

DG

ND

G1

GT

XC

LK

BP

_S

RE

SE

T_

N

G2

_IR

Q_

N

+3

.3V

RIO

0_

RD

_N

[0:7

]

RIO

0_

TD

_N

[0:7

]

DG

ND

G1

_IR

Q_

N

MD

IO

DG

ND

+3

.3V

BP

_C

OP

_T

RS

T_

N

SY

S_

RE

SE

T_

NR

IO0

_T

XC

LK

_IN

BP

_C

OP

_S

RE

SE

T_

N

Vd

d

+2

.5V

LG

PL

2

BP

_H

RE

SE

T_

N

TS

I50

0_

INT

1_

N

CG

ND

G2

TX

D[7

:2]

BL

A[2

7:3

1]

+3

.3V

G1

TX

D[7

:4]

RIO

0_

TD

[0:7

]

+1

.5V

GE

the

r

+3

.3V

LA

LE

BP

_T

RS

T_

N

RIO

0_

TF

RA

ME

_N

LG

PL

0

RIO

0_

RF

RA

ME

+3

.3V

MD

C

BP

_C

OP

_H

RE

SE

T_

N

LW

E_

N[0

:3]

RIO

0_

TX

CL

K_

IN_

N

LC

S_

N[0

:4]

RIO

0_

TC

LK

DG

ND

G2

GT

XC

LK

BP

_R

TC

_C

LK

BP

_S

YS

_C

LK

TS

I50

0_

INT

0_

N

I2C

_S

DA

LG

PL

1

CG

ND

+2

.5V

GE

the

r

+3

.3V

RIO

0_

TC

LK

_N

RIO

0_

RF

RA

ME

_N

RIO

0_

RC

LK

RIO

0_

TF

RA

ME

WP

1_

RE

SE

T_

NW

P2

_R

ES

ET

_N

WP

3_

RE

SE

T_

N

LA

_C

LK

SE

NS

E_

VS

S

SE

NS

E_

VD

D

+3

.3V

PC

I_G

NT

_N

1G

2G

TX

CL

K

+3

.3V

LG

PL

2B

P_

RS

T_

CO

NF

_N

LG

PL

0

LC

S_

N[0

:4]

LW

E_

N[0

:3]

BL

A[2

7:3

1]

LG

PL

1

LA

LE

G1

GT

XC

LK

DG

ND

MS

RC

ID0

G1

TX

D[7

:4]

G2

TX

D[7

:2]

PC

I_A

D[6

3:0

]

PC

I_C

BE

_N

[7:0

]

PC

I_C

LK

PC

I_R

ST

_N

PC

I_IN

TA

_N

DG

ND

+1

2V

SH

UT

DO

WN

PC

I_IR

DY

_N

PC

I_P

ER

R_

NP

CI_

AC

K6

4_

N

PC

I_S

TO

P_

N

PC

I_S

ER

R_

N

PC

I_D

EV

SE

L_

N

PC

I_F

RA

ME

_N

PC

I_T

RD

Y_

N

PC

I_P

AR

_N

PC

I_R

EQ

_N

[1:0

]

PC

I_G

NT

_N

[1:0

]

PC

I_R

EQ

64

_N

PC

I_IN

TB

_N

PC

I_IN

TD

_N

PC

I_IN

TC

_N

PC

I_IN

TB

_N

PC

I_IN

TA

_N

PC

I_IN

TD

_N

PC

I_IN

TC

_N

PC

I_G

NT

_N

1

VIA

_R

ES

ET

_R

EQ

_N

VIA

_IN

T

VIA

_C

LK

VIA

_O

NV

IA_

RE

SE

T_

NT

RIG

_O

UT

TR

IG_

OU

T

SY

ST

EM

_R

ES

ET

_N

-12

V

+3

.3V

+5

V

+1

2V

DG

ND

PC

I_P

AR

64

DL

AL

E

ID[3

:0]

WP

1_

INT

_N

WP

2_

INT

_N

WP

3_

INT

_N

BP

_IN

T_

N

DG

ND

DG

ND

BP

_G

1_

RE

SE

T_

NB

P_

G2

_R

ES

ET

_N

CG

ND

LA

8

FL

A8

US

R4

RIO

0_

TC

LK

_N

RIO

0_

TC

LK

SY

S_

RE

SE

T_

N

RIO

0_

RD

[0:7

]

+3

.3V

+1

.5V

GE

the

r

DG

ND

BP

_C

OP

_T

RS

T_

N

+3

.3V

CG

ND

DG

ND

DG

ND

+2

.5V

RIO

0_

TX

CL

K_

IN_

N

RIO

0_

RF

RA

ME

_N

+2

.5V

GE

the

r

RIO

0_

TF

RA

ME

_N

RIO

0_

RD

_N

[0:7

]

BP

_C

OP

_H

RE

SE

T_

N

RIO

0_

TX

CL

K_

IN

BP

_R

TC

_C

LK

BP

_C

OP

_S

RE

SE

T_

N

BP

_R

ST

_C

ON

F_

N

+3

.3V

BP

_S

YS

_C

LK

RIO

0_

TF

RA

ME

CG

ND

RIO

0_

TD

[0:7

]

+3

.3V

DG

ND

BP

_S

RE

SE

T_

N

+3

.3V

BP

_H

RE

SE

T_

N

DG

ND

RIO

0_

RF

RA

ME

TS

I50

0_

INT

0_

N

BP

_T

RS

T_

N

DG

ND

RIO

0_

TD

_N

[0:7

]

BP

_H

RE

SE

T_

RE

Q_

N

RIO

0_

RC

LK

_N

RIO

0_

RC

LK

Vd

d

TS

I50

0_

INT

1_

N

+3

.3V

+3

.3V

WP

1_

RE

SE

T_

NW

P2

_R

ES

ET

_N

WP

3_

RE

SE

T_

N

LA

_C

LK

SE

NS

E_

VD

D

SE

NS

E_

VS

S

+3

.3V

PC

I_C

LK

PC

I_R

ST

_N

DG

ND

+1

2V

SH

UT

DO

WN

VIA

_R

ES

ET

_N

VIA

_O

N

VIA

_R

ES

ET

_R

EQ

_N

VIA

_C

LK

SY

ST

EM

_R

ES

ET

_N

DG

ND

+3

.3V

+5

V

+1

2V

-12

V

VIA

_IN

TP

CI_

INT

A_

N

DL

AL

E

LA

LE

ID[3

:0]

BP

_IN

T_

NW

P3

_IN

T_

N

WP

1_

INT

_N

WP

2_

INT

_N

DG

ND

DG

ND

BP

_G

1_

RE

SE

T_

NB

P_

G2

_R

ES

ET

_N

CG

ND

LA

8

FL

A8

US

R4

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - To

p L

eve

l0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

47

2M

on

da

y, S

ep

tem

be

r 29

, 20

03

Pa

ge

14

BP

- AU

X

MD

CM

DIO

G1

_IR

Q_

NG

2_

IRQ

_N

I2C

_S

CL

I2C

_S

DA

BP

_S

RE

SE

T_N

BP

_H

RE

SE

T_N

BP

_C

OP

_H

RE

SE

T_N

BP

_C

OP

_S

RE

SE

T_N

BP

_T

RS

T_

NB

P_

CO

P_

TR

ST

_N

BP

_H

RE

SE

T_R

EQ

_N

PC

I_IN

TA

_N

BP

_R

TC

_C

LK

BP

_S

YS

_C

LK

+3

.3V

DG

ND

TS

I50

0_

INT

0_

NT

SI5

00

_IN

T1

_N

MS

RC

ID0

PC

I_IN

TB

_N

PC

I_IN

TC

_N

PC

I_IN

TD

_N

TR

IG_O

UT

WP

3_

INT

_N

WP

1_

INT

_N

WP

2_

INT

_N

BP

_IN

T_

N

Pa

ge

17

BP

- Po

we

r

Vd

d

+3

.3V

DG

ND

SE

NS

E_V

DD

SE

NS

E_V

SS

+1

2V

Pa

ge

7

BP

- PC

I

+3

.3V

PC

I_A

D[6

3:0

]

PC

I_C

BE

[7:0

]

PC

I_P

AR

_N

PC

I_F

RA

ME

_N

PC

I_T

RD

Y_N

PC

I_IR

DY

_N

PC

I_S

TO

P_

NP

CI_

DE

VS

EL_N

PC

I_S

ER

R_N

DG

ND

PC

I_R

EQ

_N

[1:0

]

PC

I_G

NT

_N

[1:0

]

PC

I_P

ER

R_N

PC

I_R

EQ

64

_N

PC

I_A

CK

64

_N

PC

I_P

AR

64

Pa

ge

16

BP

- PC

I Exp

an

sio

n

PC

I_C

BE

[7:0

]

+3

.3V

+1

2V

PC

I_G

NT

_N

[1:0

]

PC

I_A

D[6

3:0

]

PC

I_S

TO

P_

N

PC

I_T

RD

Y_N

PC

I_C

LK

+5

V

PC

I_P

AR

_N

PC

I_R

EQ

_N

[1:0

]

PC

I_IR

DY

_N

PC

I_D

EV

SE

L_N

DG

ND

PC

I_S

ER

R_N

PC

I_F

RA

ME

_N

PC

I_IN

TA

_N

PC

I_IN

TB

_N

PC

I_IN

TC

_N

PC

I_IN

TD

_N

PC

I_A

CK

64

_N

PC

I_R

EQ

64

_N

-12

V

PC

I_R

ST

_N

PC

I_P

ER

R_N

VIA

_C

LK

VIA

_O

NV

IA_R

ES

ET

_N

VIA

_R

ES

ET

_R

EQ

_N

VIA

_IN

T

PC

I_P

AR

64

CG

ND

Pa

ge

15

BP

- Co

nfig

BP

_R

ST

_C

ON

F_

N

LA

LE

LG

PL

2

LG

PL

0L

GP

L1

G1

TX

D[7

:4]

G2

TX

D[7

:2]

MS

RC

ID0

DG

ND

+3

.3V

BL

A[2

7:3

1]

G1

GT

XC

LK

G2

GT

XC

LK

LW

E_

N[0

:3]

LC

S_

N[0

:4]

PC

I_G

NT

_N

1T

RIG

_O

UT

Pa

ge

9

BP

- TS

EC

- To

p

BP

_G

1_

RE

SE

T_

NB

P_

G2

_R

ES

ET

_N

G2

_IR

Q_

N

MD

CM

DIO

G1

_IR

Q_

N

DG

ND

+3

.3V

+1

.5V

GE

the

r

+2

.5V

GE

the

r

G1

GT

XC

LK

G2

GT

XC

LK

G1

TX

D[7

:4]

G2

TX

D[7

:2]

CG

ND

Pa

ge

6

BP

- DD

R S

DR

AM

I2C

_S

DA

I2C

_S

CL

DG

ND

+2

.5V

+3

.3V

Pa

ge

13

BP

- CP

M

+3

.3V

DG

ND

CG

ND

WP

1_R

ES

ET

_N

WP

2_R

ES

ET

_N

WP

3_R

ES

ET

_N

SH

UT

DO

WN

SY

ST

EM

_R

ES

ET

_N

ID[3

:0]

US

R4

Pa

ge

8

BP

- RIO

RIO

0_T

XC

LK

_IN

RIO

0_

TX

CL

K_

IN_

N

RIO

0_

TC

LK

RIO

0_

TC

LK

_N

RIO

0_

TF

RA

ME

_N

RIO

0_T

FR

AM

E

RIO

0_

TD

[0:7

]

RIO

0_

TD

_N

[0:7

]

RIO

0_

RC

LK

RIO

0_

RC

LK

_N

RIO

0_R

FR

AM

ER

IO0_R

FR

AM

E_N

RIO

0_R

D_N

[0:7

]

RIO

0_R

D[0

:7]

DG

ND

Pa

ge

5

BP

- Lo

ca

l Bu

s - F

lash

RE

SE

T_N

+3

.3V

DG

ND

LG

PL

0L

GP

L1

LG

PL

2

LA

LE

BL

A[2

7:3

1]

LW

E_

N[0

:3]

LC

S_

N[0

:4]

LA

_C

LK

DL

AL

E

FLA

8

LA

8



Schematics

Figure A-3. Boot Processor—Local Bus—Flash

55

44

33

22

11

DD

CC

BB

AA

LD

5

LD

14

BL

CS

_N

0

LA

D2

1

LA

11

LA

15

BL

A2

7

BL

A2

8

LA

13

LD

12

LA

D2

2

LA

D5

LA

27

LC

S_

N1

LC

S_

N0

LD

23

LD

9

LC

S_

N3

LG

PL

2

LA

20

LD

1

LA

17

LA

D6

+3

.3V

LA

12

LA

D1

8

LC

S_

N4

LA

D1

3L

D1

8

LD

6

LA

16

LD

25

LA

14

BL

CS

_N

0

LA

D2

4

LA

9

LA

18

BL

A3

0

LD

20

LA

16

LA

22

LD

27

LA

27

LA

D2

9

LA

28

LA

D1

0

LD

4

LD

30

LA

D3

RE

SE

T_

N

LD

28

LD

13

LD

3

RE

SE

T_

N

LD

19

LA

D2

0

LD

15

LA

D1

2

LD

26

BL

A2

9

LA

D4

LA

17

LA

22

BL

A2

9

LA

20

BL

A2

8

LA

D2

7

LA

D1

9

BL

A2

9

LA

24

BL

A2

7

LA

21

LA

14

LA

D1

7

LD

31

LD

2

LA

D0

LA

D7

LD

17

BL

A3

1

LA

12

LA

D1

1

DG

ND

LA

10

ILA

8

LA

D9

LD

21

LA

25

LD

11

LA

10

LD

29

LA

23

LA

29

BL

GP

L2

LA

13

LA

D2

LD

7

LA

D3

1

LD

24

LA

D2

8

LA

29

LA

D3

0

LA

D1

LA

D2

5

LG

PL

0

LA

18

LA

26

BL

A2

7

LG

PL

1

ILA

8

LA

D1

5

LA

24

BL

GP

L2

LA

D2

3

LA

D8

LA

21

LA

D1

4

LD

16

LA

28

LD

8

LA

25

LD

10

LA

26

LB

CT

L

LA

D2

6

LA

D1

6

LA

23

LA

19

LA

19

BL

A2

8

BL

WE

_N

2

LA

9L

CS

_N

2

BL

WE

_N

0

LA

11

LA

LE

LD

0

LD

22

LA

15

LW

E_

N1

LW

E_

N0

LW

E_

N3

LW

E_

N2

LA

_C

LK

LA

14

LA

26

LA

13

LA

23

LA

21

LA

19

LA

24

LA

16

LA

20

LA

15

LA

22

LA

25

LA

18

LA

17

BL

A3

0

BL

A2

7

BL

A2

9

BL

A3

1

BL

A2

8

BL

WE

_N

0

BL

GP

L2

LA

29

LA

31

LA

28

LA

30

LA

27

LD

2L

D3

LD

1

LD

7

LD

5L

D6

LD

4

LD

0

BL

CS

_N

0

LA

D1

1

LD

8 LA

24

LA

D1

5

LD

18

LA

25

LD

14

LA

D4

LA

11

LA

27

LA

D1

7

LA

20

LD

5

LA

D1

4

LA

D0

LA

28

LD

2 LD

21

LD

11

LA

D1

9

LD

26

LA

19

LA

26

LB

CT

L

LD

16

LD

24

LD

15

LD

3

LA

D3

1

LA

31

LD

23

LD

22

LD

28

BL

CS

_N

0

LA

10

LA

23

LA

D5

LD

12

LW

E_

N2

BL

GP

L2

LA

D2

3

LD

19

LA

D2

LD

6

LD

13

LA

D2

7

LA

D1

3

LD

20

LA

9 LD

30

LA

22

BL

WE

_N

0

LA

D2

2

LA

D1

LA

8

LA

D1

8

BL

WE

_N

2

LA

D1

0

LA

D1

6

LD

27

LD

10

LA

D2

8

LD

4

LD

1

LA

13

LW

E_

N0

LA

12

LA

D8

LA

15

LA

29

LC

S_

N0

LA

30

LD

17

LA

D7

LA

17

LA

18

LA

D3

LA

D6

LD

0

LG

PL

2

LA

14

LA

D2

1

LD

29

LA

D2

4

LA

D9

LA

D2

5

LD

7

LA

D2

0

LA

D3

0

LA

D1

2

LA

D2

9

LA

21

LD

25

LA

16

LD

9

LB

CT

L

LA

D2

6

LD

31

DL

AL

E

LA

_C

LK

LA

D2

4

LA

D1

9

LA

D2

2

LA

D2

7

LA

D1

7L

AD

16

LA

D2

9

LA

D2

3

LA

D2

0

LA

D3

1

LA

D2

8

LA

D3

0

LA

D2

6

LA

D2

1

LA

D2

5

LA

D1

8

LA

D8

LA

D4

LA

D1

1

LA

D2

LA

D3

LA

D1

3

LA

D5

LA

D1

4

LA

D7

LA

D0

LA

D1

LA

D1

2

LA

D6

LA

D1

0L

AD

9

LA

D1

5

LW

E_

N2

LW

E_

N0

LW

E_

N3

LW

E_

N1

LG

PL

1L

GP

L2

LG

PL

0

FL

AL

E

FL

AL

EL

AL

E

FL

AL

E

FL

A8

ILA

8

LA

8

LW

E_

N[0

:3]

LA

LE

LG

PL

0

DG

ND

LG

PL

2BL

A[2

7:3

1]

LC

S_

N[0

:4]

RE

SE

T_

N

LG

PL

1

+3

.3V

LA

_C

LK

DL

AL

E

LA

_C

LK

LA

8

FL

A8

+3

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+3

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+3

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+3

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+3

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+3

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+3

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+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

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+3

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Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - Lo

ca

l Bu

s - F

lash

0.6

To

rrido

n - R

ap

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En

ab

led

Mu

lti-Pro

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En

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att, N

CS

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latfo

rms G

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p, M

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st K

ilbrid

e

C

57

2F

rida

y, S

ep

tem

be

r 26

, 20

03

Decoupling

Power

Do Not Fit

Do Not Fit

DecouplingDecoupling

Decoupling

Do Not Fit

Decoupling

Do Not Fit

R3

59

0R

TP

33

6

TP

23

5

R3

48

0R

R3

49

0R

R1

31

10

K

0.1uFC425

R3

52

0R

R7

81

0R

TP

33

7

R1

30

10

K

TP

23

4

TP

33

8

R1

38

00

R

TP

24

0

TP

24

3

TP

24

6

R3

53

0R

R1

30

41

K

TP

17

5

R3

50

0R

TP

33

9

R7

64

0R

TP

24

2

TP

24

5

TP

34

0

TP

17

6

TP

23

8

TP

24

1

TP

24

4

TP

24

7

R3

56

0R

R3

54

0R

R7

80

0R

4M x 16 FLASH

U2

1

AM

29

LV

64

1D

A0

25

A1

24

A2

23

A3

22

A4

21

A5

20

A6

19

A7

18

A8

8

A9

7

A1

06

A1

15

A1

24

A1

33

A1

42

A1

51

A1

64

8

A1

71

7

A1

81

6

CE

26

WE

11

A1

91

5

DQ

02

9

DQ

13

1

DQ

23

3

DQ

33

5

DQ

43

8

DQ

54

0

DQ

64

2

DQ

74

4

DQ

83

0

DQ

93

2

DQ

10

34

DQ

11

36

DQ

12

39

DQ

13

41

DQ

14

43

DQ

15

/A-1

45

VIO

47

OE

28

RE

SE

T1

2

A2

19

A2

01

0

AC

C1

3W

P1

4

VS

S2

7V

SS

46

VC

C3

7

TP

34

1

+

C1094

10uF,6.3V Tants

TP

17

7

R7

63

0R

R3

57

0R

TP

23

7

BUS Transceiver

& Latch

U2

3

SN

74

AL

VC

H3

29

73

KR

1L

EH

3

2L

ET

3

1A

1A

1

1A

2B

1

1A

3C

1

1A

4D

1

1A

5E

1

1A

6F

1

1A

7G

1

1A

8H

1

2A

1J1

2A

2K

1

2A

3L

1

2A

4M

1

2A

5N

1

2A

6P

1

2A

7R

1

2A

8T

1

1Q

1A

6

1Q

2B

6

1Q

3C

6

1Q

4D

6

1Q

5E

6

1Q

6F

6

1Q

7G

6

1Q

8H

6

2Q

1J6

2Q

2K

6

2Q

3L

6

2Q

4M

6

2Q

5N

6

2Q

6P

6

2Q

7R

6

2Q

8T

6

1B

1A

5

1B

2B

5

1B

3C

5

1B

4D

5

1B

5E

5

1B

6F

5

1B

7G

5

1B

8H

5

2B

1J5

2B

2K

5

2B

3L

5

2B

4M

5

2B

5N

5

2B

6P

5

2B

7R

5

2B

8T

5

1T

OE

A3

2T

OE

J3

1D

IRA

4

2D

IRJ4

1L

OE

H4

2L

OE

T4

3V3C3

3V3C4

3V3F4

3V3F3

3V3P4

3V3P3

3V3L4

3V3L3

DGNDB4

DGNDB3

DGNDD4

DGNDD3

DGNDE4

DGNDE3

DGNDK4

DGNDK3

DGNDM4

DGNDM3

DGNDN4

DGNDN3

DGNDR4

DGNDR3

D1

A2

Y1

B2

D2

C2

D3

E2

D4

G2

D5

J2

D6

L2

D7

N2

D8

R2

Y2

D2

Y3

F2

Y4

H2

Y5

K2

Y6

M2

Y7

P2

Y8

T2

BUS Transceiver

& Latch

U2

0

SN

74

AL

VC

H3

29

73

KR 1L

EH

3

2L

ET

3

1A

1A

1

1A

2B

1

1A

3C

1

1A

4D

1

1A

5E

1

1A

6F

1

1A

7G

1

1A

8H

1

2A

1J1

2A

2K

1

2A

3L

1

2A

4M

1

2A

5N

1

2A

6P

1

2A

7R

1

2A

8T

1

1Q

1A

6

1Q

2B

6

1Q

3C

6

1Q

4D

6

1Q

5E

6

1Q

6F

6

1Q

7G

6

1Q

8H

6

2Q

1J6

2Q

2K

6

2Q

3L

6

2Q

4M

6

2Q

5N

6

2Q

6P

6

2Q

7R

6

2Q

8T

6

1B

1A

5

1B

2B

5

1B

3C

5

1B

4D

5

1B

5E

5

1B

6F

5

1B

7G

5

1B

8H

5

2B

1J5

2B

2K

5

2B

3L

5

2B

4M

5

2B

5N

5

2B

6P

5

2B

7R

5

2B

8T

5

1T

OE

A3

2T

OE

J3

1D

IRA

4

2D

IRJ4

1L

OE

H4

2L

OE

T4

3V3C3

3V3C4

3V3F4

3V3F3

3V3P4

3V3P3

3V3L4

3V3L3

DGNDB4

DGNDB3

DGNDD4

DGNDD3

DGNDE4

DGNDE3

DGNDK4

DGNDK3

DGNDM4

DGNDM3

DGNDN4

DGNDN3

DGNDR4

DGNDR3

D1

A2

Y1

B2

D2

C2

D3

E2

D4

G2

D5

J2

D6

L2

D7

N2

D8

R2

Y2

D2

Y3

F2

Y4

H2

Y5

K2

Y6

M2

Y7

P2

Y8

T2

0.1uFC422

0.1uFC421

0.1uFC423

0.1uFC426

R3

55

0R

4M x 16 FLASH

U2

2

AM

29

LV

64

1D

A0

25

A1

24

A2

23

A3

22

A4

21

A5

20

A6

19

A7

18

A8

8

A9

7

A1

06

A1

15

A1

24

A1

33

A1

42

A1

51

A1

64

8

A1

71

7

A1

81

6

CE

26

WE

11

A1

91

5

DQ

02

9

DQ

13

1

DQ

23

3

DQ

33

5

DQ

43

8

DQ

54

0

DQ

64

2

DQ

74

4

DQ

83

0

DQ

93

2

DQ

10

34

DQ

11

36

DQ

12

39

DQ

13

41

DQ

14

43

DQ

15

/A-1

45

VIO

47

OE

28

RE

SE

T1

2

A2

19

A2

01

0

AC

C1

3W

P1

4

VS

S2

7V

SS

46

VC

C3

7

TP

23

6

GND

39

40

41

42

43

P2

1

MIC

TO

R 3

8 S

OC

KE

T

5V

1S

CL

2

GN

D3

SD

A4

CLK

A5

CLK

B6

D1

5A

7D

15

B8

D1

4A

9D

14

B1

0

D1

3A

11

D1

3B

12

D1

2A

13

D1

2B

14

D1

1A

15

D1

1B

16

D1

0A

17

D1

0B

18

D9

A1

9D

9B

20

D8

A2

1D

8B

22

D7

A2

3D

7B

24

D6

A2

5D

6B

26

D5

A2

7D

5B

28

D4

A2

9D

4B

30

D3

A3

1D

3B

32

D2

A3

3D

2B

34

D1

A3

5D

1B

36

D0

A3

7D

0B

38

R1

37

90

R

R3

58

0R

TP

33

5

GND

39

40

41

42

43

P3

4

MIC

TO

R 3

8 S

OC

KE

T

5V

1S

CL

2

GN

D3

SD

A4

CLK

A5

CLK

B6

D1

5A

7D

15

B8

D1

4A

9D

14

B1

0

D1

3A

11

D1

3B

12

D1

2A

13

D1

2B

14

D1

1A

15

D1

1B

16

D1

0A

17

D1

0B

18

D9

A1

9D

9B

20

D8

A2

1D

8B

22

D7

A2

3D

7B

24

D6

A2

5D

6B

26

D5

A2

7D

5B

28

D4

A2

9D

4B

30

D3

A3

1D

3B

32

D2

A3

3D

2B

34

D1

A3

5D

1B

36

D0

A3

7D

0B

38

LO

CA

L B

US

U2

F

MP

C8

56

0

LA

D0

AD

26

LA

D1

AD

27

LA

D2

AD

28

LA

D3

AC

26

LA

D4

AC

27

LA

D5

AC

28

LA

D6

AA

22

LA

D7

AA

23

LA

D8

AA

26

LA

D9

Y2

1

LA

D1

0Y

22

LA

D1

1Y

26

LA

D1

2W

20

LA

D1

3W

22

LA

D1

4W

26

LA

D1

5V

19

LA

D1

6T

22

LA

D1

7R

24

LA

D1

8R

23

LA

D1

9R

22

LA

D2

0R

21

LA

D2

1R

18

LA

D2

2P

26

LA

D2

3P

25

LA

D2

4P

20

LA

D2

5P

19

LA

D2

6P

18

LA

D2

7N

22

LA

D2

8N

23

LA

D2

9N

24

LA

D3

0N

25

LA

D3

1N

26

LD

P0

AA

27

LD

P1

AA

28

LD

P2

T2

6

LD

P3

P2

1

LA

LE

V2

1

LB

CT

LV

20

LG

PL

0/L

SD

A1

0U

19

LG

PL1/L

SD

WE

U2

2

LG

PL2/L

OE

/LS

DR

AS

V2

8

LG

PL3/L

SD

CA

SV

27

LG

PL4/L

GT

A/L

UP

WA

IT/L

PB

SE

V2

3

LG

PL

5V

22

LW

E0/L

BS

0A

B2

8

LW

E1/L

BS

1A

B2

7

LW

E2/L

BS

2T

23

LW

E3/L

BS

3P

24

LA

27

U1

8

LA

28

T1

8

LA

29

T1

9

LA

30

T2

0

LA

31

T2

1

LC

S0

Y2

7

LC

S1

Y2

8

LC

S2

W2

7

LC

S3

W2

8

LC

S4

R2

7

LC

S5/D

MA

_D

RE

Q2

R2

8

LC

S6/D

MA

_D

AC

K2

P2

7

LC

S7/D

MA

_D

DO

NE

2P

28

LC

LK

0U

27

LC

LK

1U

28

LC

LK

2V

18

LC

KE

U2

3

LS

YN

C_IN

T2

7

LS

YN

C_O

UT

T2

8

0.1uFC424

R3

51

0R



Figure A-4. Boot Processor—DDR SDRAM

55

44

33

22

11

DD

CC

BB

AA

0M

DQ

S6

0M

CK

_N

2

0M

A3

0D

M4

0E

CC

4

0M

A8

0D

M8

0M

DQ

0

0M

DQ

2

0M

DM

0

0D

Q1

8

0C

K2

0M

DQ

S8

0M

EC

C4

0M

DM

0

0A

12

0D

Q0

0N

CK

4

0M

EC

C6

0D

M1

0E

CC

7

0D

Q2

0

0M

DQ

S1

0M

DQ

20

0D

Q2

1

0M

DQ

1

0M

CK

_N

1

0D

Q1

6

0M

DQ

3

0M

DM

3

0D

QS

6

0E

CC

6

0M

A1

1

0M

DM

5

0N

CK

2

0D

Q2

4

0M

SY

NC

_O

UT

0M

A6

0M

DM

4

0D

Q2

5

0D

Q2

2

0M

DM

6

0E

CC

3

0M

CS

3_

N

0M

DQ

3

0D

Q1

7

0M

DM

7

0M

A4

0M

A7

0D

QS

2

0A

2

0M

DQ

5

0A

10

0M

DQ

6

0M

DM

1

0A

6

0M

DQ

19

0M

CK

4

0A

14

0E

CC

5

+3

.3V

0C

K4

0M

CS

1_

N

0A

11

0M

EC

C5

0D

QS

8

0M

CK

_3

0D

QS

4

+2

.5V

0N

CK

5

0M

CK

2

0M

DQ

S7

0M

DQ

16

0M

DM

2

0A

13

0A

9

0M

CK

_N

4

0M

CS

0_

N

0A

8

0M

CK

_N

0

0M

CA

S_

N

0M

A0

0M

DQ

S0

0M

DQ

S2

0M

DQ

18

0C

KE

1

0D

M2

0D

Q5

0M

WE

_N

0C

K3

0D

QS

5

0M

BA

1

0M

RA

S_

N

0M

CK

_N

5

0M

DQ

17

0M

A1

3

0M

A1

0A

4

0D

M7

0M

CK

5

0M

DM

8

0E

CC

10

EC

C0

0R

AS

_N

0D

Q2

0M

DQ

S0

0C

K5

0D

QS

1

0M

DQ

6

0M

CK

0

0M

BA

0

0D

M3

0B

A0

0M

DQ

7

0A

1

0M

DQ

S3

0C

S2

_N

0C

AS

_N

0A

5

0C

S3

_N

0D

Q1

0D

Q3

0M

A1

0

0M

DQ

S5

0C

K0

0M

SY

NC

_IN

0D

M5

0M

A9

0M

A1

2

0D

M0

0M

DQ

2

0M

CK

_N

3

0M

CK

E0

0N

CK

3

0M

CK

E1

0D

Q4

0C

S0

_N

0B

A1

0M

EC

C3

0A

3

0M

EC

C1

0D

QS

3

0M

DQ

5

0D

M6

0D

QS

7

0E

CC

2

0M

DQ

S4

0M

EC

C7

0N

CK

0

0M

A2

0C

K1

0M

A1

4

0M

CS

2_

N

0D

Q6

0M

CK

1

0M

EC

C0

0A

7

0N

CK

1

0C

S1

_N

0D

QS

0

0C

KE

0

0W

E_

N

0M

DQ

4

0M

A5

0D

Q1

9

0M

CK

_N

2

0M

CS

1_

N

0M

DQ

30

0M

A3

0M

CK

_N

0

0M

DQ

24

0M

DQ

3

0M

DQ

1

0M

DQ

58

0M

DQ

S7

0M

DQ

38

0M

BA

1

0M

DQ

29

0M

DQ

12

0M

DQ

5

0M

DQ

34

0M

BA

0

0M

CK

_N

1

0M

RA

S_

N

0M

EC

C5

0M

EC

C4

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DQ

32

0M

A5

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0

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DQ

46

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DQ

20

0M

DQ

56

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DQ

35

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A1

2

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DQ

59

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DM

6

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A2

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EC

C6

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DQ

28

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DQ

22

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DQ

40

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CS

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DQ

54

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DQ

21

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DQ

42

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EC

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DQ

26

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DQ

2

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DQ

63

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CA

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51

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27

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17

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57

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53

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52

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15

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41

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16

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10

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49

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60

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44

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37

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3

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DQ

43

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DQ

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25

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5

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39

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60

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DQ

23

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48

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19

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36

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31

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4

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33

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18

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11

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55

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70

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20

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16

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17

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18

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DQ

22

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DQ

23

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DQ

19

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DQ

28

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DQ

24

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A6

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A5

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A7

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DQ

29

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DQ

25

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DM

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DM

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ME

CC

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ME

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EC

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EC

C3

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CK

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CS

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MC

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1

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RA

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MB

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DQ

32

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DQ

36

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DQ

37

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33

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35

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39

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45

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41

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46

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42

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47

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43

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52

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48

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DQ

53

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DQ

49

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6

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54

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55

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51

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60

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DQ

56

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DQ

61

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57

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DM

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DQ

43

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37

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59

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56

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55

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52

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41

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DQ

22

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28

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DQ

23

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27

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DQ

26

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24

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21

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DQ

30

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36

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DQ

31

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DQ

35

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DQ

34

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DQ

32

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DQ

33

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DQ

29

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DQ

38

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DQ

44

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DQ

39

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DQ

43

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DQ

42

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DQ

40

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DQ

41

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DQ

37

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46

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52

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47

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51

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48

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DQ

49

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54

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DQ

60

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DQ

55

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DQ

59

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58

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DQ

57

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DQ

53

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DQ

63

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DQ

62

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VT

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VT

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VT

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VT

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+2

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Place Near Pin 1

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Place Near Pin N27

Decoupling


Decoupling

Bulk Decoupling

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R8

24

22

R

R8

74

22

R

R8

61

22

R

0.1uFC575

R8

62

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R8

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0.01uFC976

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R8

98

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R9

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0.1uFC580

R8

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RR

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R8

47

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R

R8

77

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R

R7

87

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R

R8

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R

R8

94

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R

R8

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R7

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R8

33

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R

R8

26

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R

R8

76

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R8

63

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R

R8

93

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41(42)

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64

72

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R9

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R

R9

09

22

R

0.1uFC1199

R8

48

22

R

RN

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4

27

R, R

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123456789 1

01

11

21

31

41

51

6

R8

80

22

R

R7

89

22

R

R8

19

22

R

R8

49

22

R

R8

79

22

R

TP

6

R8

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22

R

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11

31

51

71

92

12

32

52

72

93

13

33

53

73

94

14

34

54

74

95

15

35

55

75

96

16

36

56

76

97

17

37

57

77

98

18

38

58

78

99

19

39

59

79

91

01

10

31

05

10

71

09

11

11

13

11

51

17

11

91

21

12

31

25

12

71

29

13

11

33

13

51

37

13

91

41

14

31

45

14

71

49

15

11

53

15

51

57

15

91

61

16

31

65

16

71

69

17

11

73

17

51

77

246810

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

10

01

02

10

41

06

10

81

10

11

21

14

11

61

18

12

01

22

12

41

26

12

81

30

13

21

34

13

61

38

14

01

42

14

41

46

14

81

50

15

21

54

15

61

58

16

01

62

16

41

66

16

81

70

17

21

74

17

61

78

17

91

81

18

31

85

18

71

89

19

11

93

19

51

97

19

9

18

01

82

18

41

86

18

81

90

19

21

94

19

61

98

20

0

RN

28

27

R, R

N

123456789 1

01

11

21

31

41

51

6

0.1uFC1023

R1210K

RN

22

5

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R8

40

22

R

R8

05

22

R

0.1uFC1017

R8

37

22

R

R7

92

22

R

R8

28

22

R

R8

78

22

R

R8

65

22

R

R8

97

22

R

RN

20

27

R, R

N

123456789 1

01

11

21

31

41

51

6

+

C983

10uF,6.3V Tants

R154K7

0.1uFC1190

0.1uFC583

R8

50

22

R

R9

02

22

R

0.1uFC1019

0.1uFC586

0.1uFC1196

C2

47

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0.1uFC980

R8

82

22

R

R7

91

22

R

R8

02

22

R

R8

21

22

R

R8

51

22

R

R8

81

22

R

0.1uFC1016

R8

64

22

R

C1167

220uF, Tants

12

R8

42

22

R

0.1uFC1012

R8

35

22

R

TP

9

RN

21

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R8

07

22

R

0.1uFC558

0.1uFC577

RN

13

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R7

94

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R

R8

30

22

R

R8

67

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R

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R8

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0.1uFC1018

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R9

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0.1uFC1024

0.1uFC565

RN

26

27

R, R

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123456789 1

01

11

21

31

41

51

6

TP

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0.1uFC1204

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RN

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3

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R8

04

22

R

R8

84

22

R

R7

93

22

R

0.1uFC1195

R8

23

22

R

0.1uFC574

RN

16

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R8

16

22

R

R8

66

22

R

R8

53

22

R

R8

83

22

R

0.1uFC579

0.1uFC585

R8

44

22

R

+

C1026

10uF,6.3V Tants

R7

86

22

R

R7

96

22

R

R8

09

22

R

R8

39

22

R

R8

69

22

R

RN

27

27

R, R

N

123456789 1

01

11

21

31

41

51

6

0.1uFC562

0.1uFC557

0.1uFC571

R8

99

22

R

0.1uFC1013

R8

54

22

R

0.1uFC578

0.1uFC1025

0.1uFC1191

0.1uFC570

R9

06

22

R

R144K7

0.1uFC587

R8

06

22

R

C3

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12

0.1uFC978

R8

86

22

R

R7

95

22

R

0.1uFC1205

R8

25

22

R

R8

18

22

R

R8

68

22

R

R8

55

22

R

0.1uFC975

0.1uFC564

R8

46

22

R

R8

85

22

R

0.1uFC560

0.1uFC572

R164K7

0.1uFC982

R7

98

22

R

R8

56

22

R

R8

13

22

R

R8

41

22

R

R8

71

22

R

R9

01

22

R

0.1uFC1208

0.1uFC588

R9

08

22

R

0.1uFC1014

0.1uFC567

RN

12

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R8

08

22

R

0.1uFC1020

0.1uFC1200

0.1uFC1197

R8

32

22

R

R8

88

22

R

R7

97

22

R

RN

6

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R8

27

22

R

R8

20

22

R

R8

70

22

R

R8

57

22

R

+

C1075

10uF,6.3V Tants

R8

87

22

R

0.1uFC582

0.1uFC559

R8

58

22

R

0.1uFC1011

0.1uFC1210

RN

17

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R7

88

22

R

R9

03

22

R

R8

11

22

R

R8

43

22

R

R8

73

22

R

0.1uFC569

0.1uFC563

R1110K

LP2995

U3

LP

29

95

NC

1

GN

D2

VS

EN

SE

3

VR

EF

4V

DD

Q5

AV

IN6

PV

IN7

VT

T8

R9

10

22

R

R8

10

22

R

R7

83

22

R

R9

11

22

R

0.1uFC977

0.1uFC981

TP

4

R8

34

22

R

R8

90

22

R

R7

99

22

R

0.1uFC1198

0.1uFC1209

R8

29

22

R

0.1uFC584

R8

22

22

R

R8

72

22

R

R8

59

22

R

0.1uFC1021

R8

89

22

R

R8

60

22

R

0.1uFC573

0.01uFC979

RN

29

27

R, R

N

123456789 1

01

11

21

31

41

51

6

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22

R

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22

R

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0.1uFC1192

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22

R

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R

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RN

7

27

R, R

N

123456789 1

01

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31

41

51

6

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220uF, Tants

12

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RD

DR

SD

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M

U2

B

MP

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0

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ME

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1M

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19

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3E

19

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4C

21

ME

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5A

21

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6G

19

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7A

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MD

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MD

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8

MD

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MD

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L2

1

MD

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8

MD

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6

MD

M6

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MD

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MD

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MD

QS

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26

MD

QS

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25

MD

QS

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22

MD

QS

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18

MD

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16

MD

QS

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14

MD

QS

7C

13

MD

QS

8C

20

MA

0N

19

MA

1B

21

MA

2F

21

MA

3K

21

MA

4M

21

MA

5C

23

MA

6A

23

MA

7B

24

MA

8H

23

MA

9G

24

MA

10

K1

9

MA

11

B2

5

MA

12

D2

7

MA

13

J1

4

MA

14

J1

3

MD

Q0

M2

6

MD

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7

MD

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2

MD

Q3

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4

MD

Q4

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4

MD

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MD

Q6

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7

MD

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MD

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MD

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MD

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MD

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27

MD

Q1

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6

MD

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3

MD

Q1

4H

26

MD

Q1

5G

26

MD

Q1

6C

26

MD

Q1

7E

25

MD

Q1

8C

24

MD

Q1

9E

23

MD

Q2

0D

26

MD

Q2

1C

25

MD

Q2

2A

24

MD

Q2

3D

23

MD

Q2

4B

23

MD

Q2

5F

22

MD

Q2

6J2

1

MD

Q2

7G

21

MD

Q2

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22

MD

Q2

9D

22

MD

Q3

0H

21

MD

Q3

1E

21

MD

Q3

2N

18

MD

Q3

3J1

8

MD

Q3

4D

18

MD

Q3

5L

17

MD

Q3

6M

18

MD

Q3

7L

18

MD

Q3

8C

18

MD

Q3

9A

18

MD

Q4

0K

17

MD

Q4

1K

16

MD

Q4

2C

16

MD

Q4

3B

16

MD

Q4

4G

17

MD

Q4

5L

16

MD

Q4

6A

16

MD

Q4

7L

15

MD

Q4

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15

MD

Q4

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15

MD

Q5

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14

MD

Q5

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MD

Q5

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15

MD

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15

MD

Q5

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MD

Q5

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MD

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MD

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MD

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MB

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MB

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MC

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MC

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MC

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MC

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MC

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MC

KE

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MC

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MC

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MC

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MC

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MC

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MC

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MC

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MC

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MC

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MC

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MC

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MC

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MS

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6A

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8F

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GV

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9D

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GV

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10

J1

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11

E1

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12

B1

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13

G1

8

GV

dd

14

H1

9

GV

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15

F1

9

GV

dd

16

D1

9

GV

dd

17

K2

0

GV

dd

18

G2

0

GV

dd

19

A2

0

GV

dd

20

N2

1

GV

dd

21

D2

1

GV

dd

22

J2

2

GV

dd

23

E2

2

GV

dd

24

B2

2

GV

dd

25

L2

3

GV

dd

26

G2

3

GV

dd

27

H2

4

GV

dd

28

D2

4

GV

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29

M2

5

GV

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30

K2

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31

F2

5

GV

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32

A2

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33

A2

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34

J2

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35

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7

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L2

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37

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0.1uFC561



Schematics

Figure A-5. Boot Processor—PCI Interface

55

44

33

22

11

DD

CC

BB

AA

PC

I_P

AR

64

PC

I_A

D1

4

PC

I_S

ER

R_

N

PC

I_A

D2

6

PC

I_C

BE

0

PC

I_A

D6

PC

I_A

D3

1

PC

I_A

D2

2

PC

I_A

D1

PC

I_A

D1

9

PC

I_A

D2

4

PC

I_A

D0

PC

I_A

D5

PC

I_A

D3

0

PC

I_A

D2

5

PC

I_T

RD

Y_

N

PC

I_A

D1

7

PC

I_S

TO

P_

N

PC

I_A

CK

64

_N

PC

I_A

D1

2

PC

I_D

EV

SE

L_

N

PC

I_A

D8

PC

I_C

BE

7

PC

I_A

D2

8P

CI_

AD

29

PC

I_P

AR

_N

PC

I_A

D9

PC

I_A

D2

3

PC

I_A

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8

PC

I_F

RA

ME

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PC

I_A

D2

0

PC

I_A

D2

PC

I_A

D1

5

PC

I_C

BE

2P

CI_

AD

3

PC

I_A

D1

1

PC

I_A

D4

PC

I_A

D7

PC

I_A

D1

0

PC

I_A

D2

7

PC

I_A

D2

1

PC

I_A

D1

3

PC

I_A

D1

6

PC

I_C

BE

3

PC

I_C

BE

6

PC

I_IR

DY

_N

PC

I_C

BE

1

PC

I_R

EQ

64

_N

PC

I_C

BE

4P

CI_

CB

E5

PC

I_ID

SE

L

PC

I_P

ER

R_

N

DG

ND

+3

.3V

PC

I_G

NT

_N

1P

CI_

GN

T_

N0

PC

I_R

EQ

_N

1P

CI_

RE

Q_

N0

PC

I_A

D3

2P

CI_

AD

33

PC

I_A

D3

4P

CI_

AD

35

PC

I_A

D3

8

PC

I_A

D3

6P

CI_

AD

37

PC

I_A

D3

9

PC

I_A

D4

2

PC

I_A

D4

0

PC

I_A

D4

7P

CI_

AD

46

PC

I_A

D4

4

PC

I_A

D4

1

PC

I_A

D4

5

PC

I_A

D4

3

PC

I_A

D5

8

PC

I_A

D5

0

PC

I_A

D6

3

PC

I_A

D4

8

PC

I_A

D6

0

PC

I_A

D5

7

PC

I_A

D6

2

PC

I_A

D5

5

PC

I_A

D5

9

PC

I_A

D5

4

PC

I_A

D5

6

PC

I_A

D5

2

PC

I_A

D4

9

PC

I_A

D6

1

PC

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3

PC

I_A

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1

PC

I_A

D[6

3:0

]P

CI_

CB

E[7

:0]

PC

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AR

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RA

ME

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NP

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N

DG

ND

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]

PC

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64

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AR

64

+3

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Sy

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m :

Siz

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Re

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to

f

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r - PC

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To

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ap

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12346789

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PC

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0

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12

PC

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11

PC

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PC

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AH

8

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PC

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PC

I_C

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13

PC

I_C

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13

PC

I_A

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PC

I_A

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PC

I_A

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3

PC

I_A

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12

PC

I_A

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PC

I_A

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12

PC

I_A

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AD

12

PC

I_A

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PC

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PC

I_A

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I_A

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PC

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11

PC

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11

PC

I_A

D14

AF

11

PC

I_A

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11

PC

I_A

D16

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10

PC

I_A

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0

PC

I_A

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PC

I_A

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9

PC

I_A

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AG

9

PC

I_A

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PC

I_A

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PC

I_A

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AD

9

PC

I_A

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PC

I_A

D25

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PC

I_A

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AC

8

PC

I_A

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PC

I_A

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AH

7

PC

I_A

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AE

7

PC

I_A

D30

AD

7

PC

I_A

D31

AH

6

PC

I_A

D32

AF

18

PC

I_A

D33

AF

17

PC

I_A

D34

AE

17

PC

I_A

D35

AB

17

PC

I_A

D36

AA

17

PC

I_A

D37

Y1

7

PC

I_A

D38

W1

7

PC

I_A

D39

V1

7

PC

I_A

D40

AF

16

PC

I_A

D41

AE

16

PC

I_A

D42

AD

16

PC

I_A

D43

AC

16

PC

I_A

D44

AB

16

PC

I_A

D45

W1

6

PC

I_A

D46

V1

6

PC

I_A

D47

AH

15

PC

I_A

D48

AG

15

PC

I_A

D49

AD

15

PC

I_A

D50

AC

15

PC

I_A

D51

AB

15

PC

I_A

D52

AA

15

PC

I_A

D53

Y1

5

PC

I_A

D54

W1

5

PC

I_A

D55

V1

5

PC

I_A

D56

AH

14

PC

I_A

D57

AG

14

PC

I_A

D58

AF

14

PC

I_A

D59

AE

14

PC

I_A

D60

AD

14

PC

I_A

D61

AC

14

PC

I_A

D62

AB

14

PC

I_A

D63

AA

14

PC

I_P

AR

AA

11

PC

I_P

AR

64

Y1

4

PC

I_F

RA

ME

AC

10

PC

I_T

RD

YA

G1

0

PC

I_IR

DY

AD

10

PC

I_S

TO

PV

11

PC

I_D

EV

SE

LA

H1

0

PC

I_ID

SE

LA

A9

PC

I_R

EQ

64

AE

13

PC

I_A

CK

64

AD

13

PC

I_P

ER

RW

11

PC

I_S

ER

RY

11

PC

I_R

EQ

0A

F5

PC

I_R

EQ

1A

F3

PC

I_R

EQ

2A

E4

PC

I_R

EQ

3A

G4

PC

I_R

EQ

4A

E5

PC

I_G

NT

0A

E6

PC

I_G

NT

1A

G5

PC

I_G

NT

2A

H5

PC

I_G

NT

3A

F6

PC

I_G

NT

4A

G6

R6

63

4K

7



Figure A-6. Boot Processor—RapidIO Interface

55

44

33

22

11

DD

CC

BB

AA

RIO

0_

TD

3

RIO

0_

TD

_N

0

RIO

0_

RD

3

RIO

0_

TF

RA

ME

_N

RIO

0_

TD

_N

2

RIO

0_

TD

_N

6

RIO

0_

TC

LK

_N

RIO

0_

TD

6

RIO

0_

TD

_N

7R

IO0

_T

D_

N6R

IO0

_R

D0

RIO

0_

RC

LK

RIO

0_

RF

RA

ME

RIO

0_

RF

RA

ME

RIO

0_

RD

7

RIO

0_

RF

RA

ME

_N

RIO

0_

TD

_N

5

RIO

0_

RD

_N

0

RIO

0_

RD

_N

3

RIO

0_

TC

LK

_N

RIO

0_

TD

_N

2

RIO

0_

RD

3

RIO

0_

RD

5

RIO

0_

RC

LK

RIO

0_

RD

0

RIO

0_

TX

CL

K_

IN

RIO

0_

TF

RA

ME

RIO

0_

RD

_N

7

RIO

0_

RD

2

RIO

0_

TC

LK

RIO

0_

RD

6

RIO

0_

TX

CL

K_

IN_

N

RIO

0_

TD

5

RIO

0_

RC

LK

_N

RIO

0_

RD

1

RIO

0_

TD

_N

3

RIO

0_

TD

_N

5

RIO

0_

RD

_N

3

RIO

0_

RD

_N

4

RIO

0_

TD

2RIO

0_

RD

_N

6

RIO

0_

TD

2

RIO

0_

TD

0

RIO

0_

RD

_N

0

RIO

0_

RD

_N

2

RIO

0_

RD

4

RIO

0_

TD

_N

0R

IO0

_T

D_

N1

RIO

0_

TD

_N

4

RIO

0_

RD

_N

5

RIO

0_

TD

_N

7

RIO

0_

RF

RA

ME

_N

RIO

0_

TF

RA

ME

_N

RIO

0_

RC

LK

_N

RIO

0_

TD

6

RIO

0_

TD

5

RIO

0_

TD

4

RIO

0_

RD

_N

2

RIO

0_

TD

3

RIO

0_

RD

2

RIO

0_

RD

_N

1

RIO

0_

TD

_N

1

RIO

0_

TC

LK

RIO

0_

TD

_N

3

RIO

0_

RD

1

RIO

0_

TD

7RIO

0_

RD

_N

1

RIO

0_

TD

1

RIO

0_

TD

1

RIO

0_

TF

RA

ME

RIO

0_

TD

7

RIO

0_

TD

_N

4

RIO

0_

TD

4

RIO

0_

TD

0

RIO

0_

RD

7

RIO

0_

RD

6

RIO

0_

RD

_N

4R

IO0

_R

D4

RIO

0_

RD

_N

7

RIO

0_

RD

_N

5

RIO

0_

RD

_N

6

RIO

0_

RD

5

RIO

0_

RD

_N

4

RIO

0_

TD

4

RIO

0_

TD

1

RIO

0_

RD

_N

3

RIO

0_

TD

_N

5

RIO

0_

TC

LK

_N

RIO

0_

RD

7

RIO

0_

TD

5

RIO

0_

RD

3

RIO

0_

RD

1

RIO

0_

TD

_N

0

RIO

0_

TD

_N

6

RIO

0_

RC

LK

_N

RIO

0_

TD

3

RIO

0_

RD

_N

2

RIO

0_

TD

0

RIO

0_

TC

LK

RIO

0_

RD

6

RIO

0_

TF

RA

ME

RIO

0_

RD

0

RIO

0_

TD

2

RIO

0_

TD

_N

7

RIO

0_

TD

7

RIO

0_

RF

RA

ME

_N

RIO

0_

TD

_N

4

RIO

0_

RF

RA

ME

RIO

0_

RD

_N

0

RIO

0_

RD

5

RIO

0_

RD

2

RIO

0_

TD

6

RIO

0_

TD

_N

3

RIO

0_

TF

RA

ME

_N

RIO

0_

RC

LK

RIO

0_

RD

_N

1

RIO

0_

RD

_N

7

RIO

0_

RD

_N

5

RIO

0_

TD

_N

1R

IO0

_T

D_

N2

RIO

0_

RD

4

RIO

0_

RD

_N

6

DG

ND

RIO

0_

TD

[0:7

]

RIO

0_

RF

RA

ME

RIO

0_

RD

[0:7

]

RIO

0_

RC

LK

RIO

0_

RF

RA

ME

_N

RIO

0_

TX

CL

K_

IN

RIO

0_

TX

CL

K_

IN_

N

RIO

0_

TC

LK

_N

RIO

0_

TF

RA

ME

_N

RIO

0_

RC

LK

_N

RIO

0_

RD

_N

[0:7

]

RIO

0_

TD

_N

[0:7

]

RIO

0_

TC

LK

RIO

0_

TF

RA

ME

DG

ND

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - Ra

pid

IO In

terfa

ce

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

87

2F

rida

y, S

ep

tem

be

r 26

, 20

03

Power

P3

3P6

86

0/6

88

0 P

rob

e

A1

A1

A2

A2

A3

A3

A4

A4

A5

A5

A6

A6

A7

A7

A8

A8

A9

A9

A1

0A

10

A1

1A

11

A1

2A

12

A1

3A

13

A1

4A

14

A1

5A

15

B1

B1

B2

B2

B3

B3

B4

B4

B5

B5

B6

B6

B7

B7

B8

B8

B9

B9

B1

0B

10

B1

1B

11

B1

2B

12

P3

1P6

86

0/6

88

0 P

rob

e

A1

A1

A2

A2

A3

A3

A4

A4

A5

A5

A6

A6

A7

A7

A8

A8

A9

A9

A1

0A

10

A1

1A

11

A1

2A

12

A1

3A

13

A1

4A

14

A1

5A

15

B1

B1

B2

B2

B3

B3

B4

B4

B5

B5

B6

B6

B7

B7

B8

B8

B9

B9

B1

0B

10

B1

1B

11

B1

2B

12

P3

2P6

86

0/6

88

0 P

rob

e

A1

A1

A2

A2

A3

A3

A4

A4

A5

A5

A6

A6

A7

A7

A8

A8

A9

A9

A1

0A

10

A1

1A

11

A1

2A

12

A1

3A

13

A1

4A

14

A1

5A

15

B1

B1

B2

B2

B3

B3

B4

B4

B5

B5

B6

B6

B7

B7

B8

B8

B9

B9

B1

0B

10

B1

1B

11

B1

2B

12

P3

0P6

86

0/6

88

0 P

rob

e

A1

A1

A2

A2

A3

A3

A4

A4

A5

A5

A6

A6

A7

A7

A8

A8

A9

A9

A1

0A

10

A1

1A

11

A1

2A

12

A1

3A

13

A1

4A

14

A1

5A

15

B1

B1

B2

B2

B3

B3

B4

B4

B5

B5

B6

B6

B7

B7

B8

B8

B9

B9

B1

0B

10

B1

1B

11

B1

2B

12

U2

C

MP

C8

56

0

RIO

_T

CL

KA

C2

0

RIO

_T

CLK

-A

E2

1

RIO

_T

FR

AM

E-

AE

25

RIO

_T

FR

AM

EA

E2

4

RIO

_T

D0

AE

18

RIO

_T

D1

AC

18

RIO

_T

D2

AD

19

RIO

_T

D3

AE

20

RIO

_T

D4

AD

21

RIO

_T

D5

AE

22

RIO

_T

D6

AC

22

RIO

_T

D7

AD

23

RIO

_T

D0

-A

D1

8

RIO

_T

D1

-A

E1

9

RIO

_T

D2

-A

C1

9

RIO

_T

D3

-A

D2

0

RIO

_T

D4

-A

C2

1

RIO

_T

D5

-A

D2

2

RIO

_T

D6

-A

E2

3

RIO

_T

D7

-A

C2

3

RIO

_R

CL

KY

25

RIO

_R

CLK

-Y

24

RIO

_R

FR

AM

EA

E2

7

RIO

_R

FR

AM

E-

AE

26

RIO

_R

D0

T2

5

RIO

_R

D1

U2

5R

IO_R

D0-

T2

4

RIO

_R

D2

V2

5

RIO

_R

D3

W2

5

RIO

_R

D4

AA

25

RIO

_R

D5

AB

25

RIO

_R

D6

AC

25

RIO

_R

D7

AD

25

RIO

_R

D1-

U2

4

RIO

_R

D2-

V2

4

RIO

_R

D3-

W2

4

RIO

_R

D4-

AA

24

RIO

_R

D5-

AB

24

RIO

_R

D6-

AC

24

RIO

_R

D7-

AD

24

RIO

_T

XC

LK

_IN

AF

24

RIO

_T

XC

LK

_IN

-A

F2

5



Schematics

Figure A-7. Boot Processor—GigaByte Ethernet Interface—Top

55

44

33

22

11

DD

CC

BB

AA

G1

RX

DV

G1T

XE

R

G1

RX

CL

K

G2

TX

D[7

:0]

G2T

XE

R

G1

_IR

Q_

N

G2T

XE

N

MD

CM

DIO

G1T

XE

N

G1

TX

CL

K

BP

_G

1_

RE

SE

T_

N

G1

RX

D[7

:0]

+1

.5V

GE

the

r

G1

GT

XC

LK

G1

TX

D[7

:4]

DG

ND

+2

.5V

GE

the

r

G1

TX

D[7

:0]

G2

CR

S

BP

_G

2_

RE

SE

T_

N

+3

.3V

G2

RX

D[7

:0]

G2

RX

CL

K

G2

RX

ER

G1

RX

ER

G1

CO

L

DG

ND

MD

IO

MG

TX

125

G2

RX

DV

+3

.3V

G2

GT

XC

LK

+1

.5V

GE

the

r

G2

_IR

Q_

N

G2

TX

D[7

:2]

+3

.3V

G1

CR

S

+2

.5V

GE

the

r

DG

ND

G2

TX

CL

K

MD

C

G2

CO

L

CG

ND

+2

.5V

GE

the

r

+2

.5V

GE

the

r

DG

ND

+3

.3V

G1

TX

D[7

:4]

BP

_G

2_

RE

SE

T_

N G1

GT

XC

LK

MD

IO

G2

_IR

Q_

N

DG

ND

+1

.5V

GE

the

r

+3

.3V

BP

_G

1_

RE

SE

T_

NG2

GT

XC

LK

DG

ND

G2

TX

D[7

:2]

+1

.5V

GE

the

r

MD

C

G1

_IR

Q_

N

+3

.3V

CG

ND

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - Gig

aB

yte

Eth

ern

et In

terfa

ce

- To

p0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

97

2F

rida

y, S

ep

tem

be

r 05

, 20

03

Pa

ge

12

BP

- TS

EC

- PH

Y2

G2T

XE

N

G2

_IR

Q_

N

G2R

XE

R

G2C

RS

G2

TX

CL

K

G2

TX

D[7

:0]

G2T

XE

R

G2

RX

CL

K

BP

_G

2_

RE

SE

T_

N

G2

GT

XC

LK

MD

C

G2

CO

L

G2

RX

D[7

:0]

G2R

XD

V

MD

IO+

3.3

V

+2

.5V

GE

the

r

+1

.5V

GE

the

r

DG

ND

Pa

ge

11

BP

- TS

EC

- PH

Y1

G1

GT

XC

LK

G1

RX

CL

K

G1

CO

L

G1

TX

CL

K

G1R

XE

RG

1R

XD

V

BP

_G

1_

RE

SE

T_

N

G1T

XE

R

G1

RX

D[7

:0]

MD

C

G1T

XE

N

MG

TX

12

5

G1

_IR

Q_

N

G1

TX

D[7

:0]

G1C

RS

MD

IO

DG

ND

+3

.3V

+2

.5V

GE

the

r

+1

.5V

GE

the

r

CG

ND

Pa

ge

10

BP

- TS

EC

G2

TX

D[7

:0]

G1R

XD

V

G1

TX

CL

K

G1T

XE

N

G1

RX

D[7

:0]

G1C

RS

G1T

XE

R

G1R

XE

R

G1

GT

XC

LK

G1

RX

CL

K

G2

RX

D[7

:0]

G1

CO

L

G1

TX

D[7

:0]

G2T

XE

NG

2T

XE

RG

2T

XC

LK

G2

GT

XC

LK

G2R

XE

R

G2

RX

CL

K

G2

CO

LG

2C

RS

MG

TX

12

5

G2R

XD

V

DG

ND

+3

.3V



Figure A-8. Boot Processor—GigaByte Ethernet Interface

55

44

33

22

11

DD

CC

BB

AA

G1

RX

D1

G2

RX

D3

MG

TX

125

G1

RX

D7

G2

TX

D1

G2

TX

D2

G1

CO

L

G1

TX

D7

G1

RX

CL

K

G2

TX

D4

G1

RX

D3

G1

RX

DV

G2

RX

D7

G2

RX

D0

G1

RX

D4

G1T

XE

R

G2

TX

D[7

:0]

G1

RX

D1

G2T

XE

NG

2T

XD

1

G2

CO

L

G1

TX

D1

G2

TX

D2

G2

TX

D3

G1

TX

D[7

:0]

G2

TX

D6

G2

RX

D2

G2

RX

D1

G2T

XE

R

G2

RX

D2

G2

TX

D0

G2

GT

XC

LK

G2

TX

D5

G2

RX

D1

G1

TX

D0

G2

RX

D6

G2

RX

D0

G1

TX

D3

G1

RX

D6

G1

RX

D5

G1

TX

D5

G1

RX

D7

G1

TX

D3

G1

RX

D4

G1

TX

D4

G2

TX

D0

G1

CR

S

G1

TX

D2

G2

RX

D6

G2

RX

D4

G2

CR

S

G2

TX

D3

G2

RX

D2

G2

RX

D1

G1

RX

D2

DG

ND

G2

TX

D6

G2

TX

D7

G2

RX

D5

G2

TX

D4

G1

RX

D3

G1

TX

D2G

1T

XC

LK

G1

RX

D2

G1

RX

D5

G1

TX

D0

G1

RX

D2

G2

RX

CL

K

G1

TX

D6

G2

TX

D5

MG

TX

125

G1

RX

D0

G2

TX

D1

G1

TX

D1

G1

TX

D6

G2

RX

DV

G2

TX

D2

G1

TX

D7G

1R

XD

[7:0

]

G1

RX

D6

G1

RX

D4

G2

RX

D7

G2

RX

D3

G1

TX

D1

G1

RX

D5

G1

RX

D7

G1

TX

D3

G1

TX

D0

+3

.3V

G1

RX

D0

G2

RX

D6

G2

RX

D3

G2

TX

D7

G1

TX

D6

G1

TX

D4

G1

TX

D4G

1T

XE

N

G2

RX

D7

G2

RX

D5

G1

TX

D5

G1

TX

D5

G2

RX

D4

G2

TX

D6

G2

TX

D0

G2

RX

D[7

:0]

G2

RX

D0

G1

TX

D7

G1

GT

XC

LK

G2

RX

D5

G1

RX

ER

G1

RX

D3

G1

TX

D2

G1

RX

D6

G2

TX

D4

G1

RX

D0

G1

RX

D1

G2

TX

D3

G2

RX

ER

G2

TX

CL

K

G2

RX

D4

G2

TX

D7

G2

TX

D5

G1T

XE

NG

1T

XE

RG

1T

XC

LK

G1

GT

XC

LK

G1

RX

DV

G1

RX

ER

G1

RX

CL

KG

1C

RS

G1

CO

L

G2T

XE

R

G2G

TX

CLK

G2T

XE

N

G2

RX

CL

KG

2C

OL

G2

RX

DV

G2

RX

ER

G2

CR

S

G2

TX

CL

K

G2

RX

D[7

:0]

G1

RX

DV

G1

CR

S

G2

GT

XC

LK

G1

CO

L

G1

TX

D[7

:0]

G1

RX

D[7

:0]

MG

TX

125

G1

TX

CL

K

G1

RX

ER

G2

RX

DV

G1

GT

XC

LK

G1

RX

CL

K

G2

TX

D[7

:0]

G2

RX

ER

G2

TX

CL

KG

2T

XE

R

+3

.3V

G2

CO

LG

2C

RS

G1T

XE

R

G2

RX

CL

K

DG

ND

G1T

XE

N

G2T

XE

N

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - Gig

aB

yte

Eth

ern

et In

terfa

ce

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

10

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

Power

Decoupling

Decoupling

100pF C861

R564330RR570330R R558330R

R5

49

22

0R

TS

EC

1

TS

EC

2

Gb

EC

lock

ing

U2

G

MP

C8

56

0

TS

EC

1_T

XD

0E

8

TS

EC

1_T

XD

1G

8

TS

EC

1_T

XD

2A

7

TS

EC

1_T

XD

3B

7

TS

EC

1_T

XD

4C

7

TS

EC

1_T

XD

5D

7

TS

EC

1_T

XD

6F

7

TS

EC

1_T

XD

7A

6

TS

EC

1_T

X_E

NC

8

TS

EC

1_T

X_E

RB

8

TS

EC

1_

TX

_C

LK

C6

TS

EC

1_

GT

X_

CL

KB

6

TS

EC

1_R

XD

0E

6

TS

EC

1_R

XD

1F

6

TS

EC

1_R

XD

2A

5

TS

EC

1_R

XD

3B

5

TS

EC

1_R

XD

4D

5

TS

EC

1_R

XD

5D

3

TS

EC

1_R

XD

6B

4

TS

EC

1_R

XD

7D

4

TS

EC

1_R

X_D

VD

2

TS

EC

1_R

X_E

RE

5

TS

EC

1_

RX

_C

LK

D6

TS

EC

1_C

RS

C3

TS

EC

1_

CO

LG

7

TS

EC

2_T

XD

0E

11

TS

EC

2_T

XD

1G

11

TS

EC

2_T

XD

2H

11

TS

EC

2_T

XD

3J1

1

TS

EC

2_T

XD

4K

11

TS

EC

2_T

XD

5J1

0

TS

EC

2_T

XD

6A

10

TS

EC

2_T

XD

7B

10

TS

EC

2_T

X_E

NB

11

TS

EC

2_T

X_E

RD

11

TS

EC

2_

TX

_C

LK

D1

0

TS

EC

2_

GT

X_

CL

KC

10

TS

EC

2_R

XD

0F

10

TS

EC

2_R

XD

1G

10

TS

EC

2_R

XD

2H

9

TS

EC

2_R

XD

3A

9

TS

EC

2_R

XD

4B

9

TS

EC

2_R

XD

5C

9

TS

EC

2_R

XD

6E

9

TS

EC

2_R

XD

7F

9

TS

EC

2_R

X_D

VH

8

TS

EC

2_R

X_E

RA

8

TS

EC

2_

RX

_C

LK

E1

0

TS

EC

2_C

RS

D9

TS

EC

2_

CO

LF

8

EC

_G

TX

_C

LK

12

5E

2

LV

dd

1A

4

LV

dd

2C

5

LV

dd

3E

7

LV

dd

4H

10

+

C1095

10uF,6.3V Tants

100pF C869

R582330R

R5

55

22

0R

R5

79

22

0R

0.1uFC700

100pF C868

R1

86

22

R 0

.1W

CN

31

00

pF

, CN

1234

8765

100pF C865

RN

10

7

33

0R

, R

N

123456789 1

01

11

2

13

14

15

16

100pF C871

100pF C860

100pF C876

R556330R

R576330R

R562330R

RN

10

8

33

0R

, R

N

123456789 1

01

11

2

13

14

15

16

100pF C873

R5

81

22

0R

CN

41

00

pF

, CN

1234

8765

100pF C877

R5

61

22

0R

R5

57

22

0R

R5

67

22

0R

CN

71

00

pF

, CN

1234

8765

R5

83

22

0R

R578330R

R1

81

22

R 0

.1W

R566330R

100pF C866

R5

53

22

0R

RN

10

0

22

0R

, R

N

123456789 1

01

11

21

31

41

51

6

RN

99

22

R, R

N

123456789 1

01

11

21

31

41

51

6

100pF C874

R568330R

CN

81

00

pF

, CN

1234

8765

R5

59

22

0R

R5

73

22

0R

100pF C875

R1

83

22

R 0

.1W

CN

11

00

pF

, CN

1234

8765

R554330R

R1

87

22

0R

RN

10

1

22

0R

, R

N

123456789 1

01

11

21

31

41

51

6

R5

65

22

0R

0.1uFC702

100pF C863100pF C872

R1

82

22

R 0

.1W

100pF C864

R574330R

R5

77

22

0R

0.1uFC699

CN

21

00

pF

, CN

1234

8765

100pF C862

100pF C136

R5

51

22

0R

RN

10

5

22

0R

, R

N

123456789 1

01

11

21

31

41

51

6

0.1uFC701

100pF C867

R5

69

22

0R

R560330R

R1

84

22

R 0

.1W

RN

10

42

2R

, RN

123456789 1

01

11

21

31

41

51

6

CN

51

00

pF

, CN

1234

8765

100pF C870

R580330R

R552330R

RN

10

2

33

0R

, R

N

123456789 1

01

11

2

13

14

15

16

RN

10

6

22

0R

, R

N

123456789 1

01

11

21

31

41

51

6

R5

75

22

0R

CN

61

00

pF

, CN

1234

8765

R188330R R550330R

R584330R

R5

63

22

0R

R572330R

R5

71

22

0R

R1

85

22

R 0

.1W

RN

10

3

33

0R

, R

N

123456789 1

01

11

2

13

14

15

16



Schematics

Figure A-9. Boot Processor—GigaByte Ethernet Interface—PHY1

55

44

33

22

11

DD

CC

BB

AA

G1T

XE

N

G1

TX

D3

BP

_P

H1

_M

0

G1

RX

D2

BP

_P

H1

_P

0

G1

TX

D4

G1

TX

D6

G1

RX

D6

G1

RX

CL

K

G1

RX

D7

G1

RX

D3

MG

TX

125

G1

RX

D0

G1

_IR

Q_

N

G1

GT

XC

LK

G1

RX

ER

G1

TX

D7

G1T

XE

R

+3

.3V

+2

.5V

GE

the

r

+1

.5V

GE

the

r

G1

RX

D1

G1

CR

S

G1

TX

D2

G1

RX

D5

G1

RX

DV

G1

RX

D4

G1

CO

L

G1

TX

D1

G1

TX

CL

K

G1

TX

D0

BP

_G

1_

RE

SE

T_

N

G1

TX

D5

CG

ND

BP

_P

H1

_P

1

BP

_P

H1

_M

1

BP

_P

H1

_P

2

BP

_P

H1

_M

2

BP

_P

H1

_P

3

BP

_P

H1

_M

3

G1AVDDH

DG

ND

MD

CM

DIO

G1

CR

S

BP

_G

1_

RE

SE

T_

N

G1

_IR

Q_

N

G1

RX

ER

+3

.3V

G1

RX

CL

K

G1

RX

DV

G1

TX

D[7

:0]

MD

C

G1T

XE

N

+2

.5V

GE

the

r

G1

RX

D[7

:0]

MD

IO

G1T

XE

R

G1

CO

L

+1

.5V

GE

the

r

MG

TX

125

G1

TX

CL

K

G1

GT

XC

LK

DG

ND

CG

ND

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+1

.5V

GE

the

r

+2

.5V

GE

the

r

+3

.3V

+2

.5V

GE

the

r

+1

.5V

GE

the

r

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roc

esso

r - Gig

aB

yte

Eth

ern

et In

terfa

ce

- PH

Y1

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

11

72

Mo

nd

ay, S

ep

tem

be

r 29

, 20

03

2.5

V3

.3V

GR

OU

ND

Se

pa

rate

Power

must be 50

mill trace

1.5

VNOTE: When PHY register 24.4:3='01',

LED_LINK1000 is used as a global link indicator.

LED on => Link Up

LED off => Link Down

NOTE: When PHY register 24.2:0='111',

LED_TX is used as a global activity indicator.

LED on => Link Up


LED flashing => Transmitting or Receiving

Pin

Bit[2] Bit[1] Bit[0]

Pin


CONFIG0 0 0

0

CONFIG1 0 0

0

CONFIG2 1 1

0

CONFIG3 0 0

0

CONFIG4 1 1

1

CONFIG5 1 1

1

CONFIG6 0 0

0

CONFIG0 PHYADR[2] PHYADR[1] PHYADR[0]

CONFIG1 ENA_PAUSE PHYADR[4] PHYADR[3]

CONFIG2 ANEG[3] ANEG[2] ANEG[1]

CONFIG3 ANEG[0] ENA_XC DIS_125

CONFIG4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_MODE[0]

CONFIG5 DIS_FC DIS_SLEEP HWCFG_MODE[3]

CONFIG6 SEL_BDT INT_POL 75/50 OHM

VDD0 1 1 1

LED_LINK10 1 1 0

LED_LINK100 1 0 1

LED_LINK1000 1 0 0

LED_DUPLEX 0 1 1

LED_RX 0 1 0

LED_TX 0 0 1

VSS 0 0 0

Pin Bit[2:0]

Pin Setting

CONFIG0 VSS

CONFIG1 VSS

CONFIG2 LED_LINK10

CONFIG3 VSS

CONFIG4 VDDO

CONFIG5 VDDO

CONFIG6 VSS

LD1

LED_YELLOW

2 1

0.01uF C51

R129910K

0.1uF C47

0.01uF C34

49

R9

R9

6

49R9R323

0.1uF C46

0.01uF C53

R13060R

49

R9

R1

07

R1

13

22

R 0

.1W

0.01uF C32

33

0R

R1

25

0.01uF C44

0.01uF C41

33

0R

R1

29

0.0

1u

F

C72 0.0

1u

F

C59

10

K

R3

24

TP41

0.01uF C33

L5

3P

IN_

FE

RR

ITE1

3

2

0.1uF C57

0.01uF C43

R1

11

22

R 0

.1W

R13070R

0.01uF C31

LD3

LED_YELLOW

2 1

R1

31

31

K

0.01uF C40

R1

21

0R

R13080R

0.1uF C54

0.1uF C35

0.1uF C39

R1

04

22

R 0

.1W

0.1uF C38

0.1uF C45

49

R9

R1

06

0.1uF C48

0.1uF C49

TP42

R1

16

22

R 0

.1W

C2

61

18

pF

C2

62

18

pF

4K

7R

12

3

R13050R

RN

64

22

R, R

N

123456789 1

01

11

21

31

41

51

6

TP43

0.1uF C419

49

R9

R1

00

33

0R

R1

26

R13090R

49

R9

R1

17

0.1uF C37

LD5

LED_YELLOW

2 1

0.01uF C50

49

R9

R9

9

0.1uF C56

33

0R

R1

27

0.0

1u

F

C67

TP44

R1222K49

R13100R

0.01uF C42

49

R9

R1

12

R1

03

22

R 0

.1W

49R9R322

0.1uF C55

0.1uF C36

0.01uF C52

LD6

LED_RED

2 1

U1

7

88

E1

01

1S

RX

D_2

A8

RX

D_1

B7

RX

D_0

A7

RX

_D

VA

6

RX

_C

LK

B6

VDDOC6

TX

_C

LK

B4

CO

LA

5

RX

_E

RB

5

VDDOC5

DGNDD5

DGNDD4

DGNDC4

CR

SA

4

SC

LK

_M

C3

GT

X_

CL

KB

3

TX

_E

RA

3

TX

D_

0B

2

TX

_E

NA

2

CO

MA

A1

AVDDLB1

SIN

_M

C1

SO

UT

_M

C2

SIN

_P

D1

SO

UT

_P

D2

TX

D_

6H

1

SC

LK

_P

D3

TX

D_

1E

1

CTRL_15E2

DGNDG4

DVDDLE3

DGNDE4

TX

D_

2F

1

TX

D_

3F

2

TX

D_

4G

1DVDDH

F3

DGNDF4

TX

D_

5G

2

DVDDHG3

DGNDG5

TX

D_

7H

2

DVDDLH3

DGNDH4

DGNDH5

XT

AL

2J1

XT

AL

1J2

VDDOJ3

DGNDJ4

TCKK1

RE

SE

TK

2

VS

SC

K3

DGNDK4

AVDDLL2

TMSL1

DGNDL3

TRSTM1

RSETM2

MD

I0_

PN

1

MD

I0_M

N2

AVDDLM3

MD

I1_

PN

3

DGNDL4

CTRL25M4

MD

I1_M

N4

DGNDJ5

DGNDK5

DGNDL5

HDAC_PM5

AVDDHN5

DGNDL6

HDAC_NM6

DGNDK6

MD

I2_

PN

6

MD

I2_M

N7

DGNDL7

AVDDLM7

MD

I3_

PN

8

AVDDLM8

MD

I3_M

N9

TDIM9

TDOL8

CONFIG_4L9

CONFIG_3K9

CONFIG_2K8

CONFIG_6K7

CONFIG_1J9

CONFIG_5J7

CONFIG_0J8

DGNDJ6

VDDOH7

LED_TXH9

DGNDH6

LED_RXH8

DVDDLG7

DGNDG6

LED_DPLXG9

LED_LINK1000G8

SE

L_

2_

5V

F7

LED_LINK100F9

DGNDF6

LED_LINK10F8

DGNDF5

DGNDE6

MD

CE

8

DGNDE5

VDDOE7

INT

E9

MD

IOD

9

CL

K1

25

D8

DVDDLD7

DGNDD6

DGNDC7

RX

D_6

C8

RX

D_7

C9

RX

D_3

B8

RX

D_5

B9

RX

D_4

A9

0.0

1u

F

C77

R1

18

22

R 0

.1W

0.01uF C30

1:1

1:1

1:1

1:1

1:1

P5

A

RJG

5-7

G0

5

9A

10

A

7A

8A

5A

6A

2A

3A

4A

1A

D1

AD

2A

D3

AD

4A

11

A

R1

05

22

R 0

.1W

Y4

25

MH

z

14

23

R13110R

R1

31

21

K

49

R9

R1

10



Figure A-10. Boot Processor—GigaByte Ethernet Interface—PHY2

55

44

33

22

11

DD

CC

BB

AA

G2T

XE

N

G2

TX

D7

G2T

XE

R

G2

GT

XC

LK

+2

.5V

GE

the

r

G2

CR

S

G2

RX

D1

G2

RX

D0

G2

TX

CL

K

G2

RX

D4

BP

_G

2_

RE

SE

T_

N

G2

CO

L

G2

TX

D4

G2

RX

D6

G2

TX

D2

MD

IO

G2

RX

ER

G2AVDDH

+3

.3V

G2

TX

D6

G2

RX

D5

G2

TX

D1

G2

_IR

Q_

N

DG

ND

G2

RX

D2

+1

.5V

GE

the

r

G2

RX

D7

G2

TX

D0

MD

C

G2

RX

D3

G2

TX

D3

G2

RX

CL

K

G2

TX

D5

G2

RX

DV

BP

_P

H2

_P

0

BP

_P

H2

_M

0

BP

_P

H2

_P

1

BP

_P

H2

_M

1

BP

_P

H2

_P

2

BP

_P

H2

_M

2

BP

_P

H2

_P

3

BP

_P

H2

_M

3

BP

_G

2_

RE

SE

T_

N

MD

C

G2

TX

D[7

:0]

+2

.5V

GE

the

r

G2

RX

D[7

:0]

+1

.5V

GE

the

r

G2

GT

XC

LK

MD

IO

G2

CO

L

G2

_IR

Q_

N

G2T

XE

RG

2T

XC

LK

G2T

XE

N

DG

ND

+3

.3V

G2

RX

ER

G2

RX

CL

K

G2

CR

S

G2

RX

DV

+3

.3V

+2

.5V

GE

the

r

+3

.3V

+2

.5V

GE

the

r

+1

.5V

GE

the

r

+3

.3V

+3

.3V

+1

.5V

GE

the

r

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roc

esso

r - Gig

aB

yte

Eth

ern

et In

terfa

ce

- PH

Y2

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

12

72

Mo

nd

ay, S

ep

tem

be

r 29

, 20

03

must be 50

mill trace

1.5

V3

.3V

GR

OU

ND

Se

pa

rate

2.5

V

Power



LED on => Link Up




LED on => Link Up



Pin


Pin


CONFIG0 0 0

1

CONFIG1 0 0

0

CONFIG2 1 1

0

CONFIG3 0 0

0

CONFIG4 1 1

1

CONFIG5 1 1

1

CONFIG6 0 0

0








VDD0 1 1 1

LED_LINK10 1 1 0

LED_LINK100 1 0 1

LED_LINK1000 1 0 0

LED_DUPLEX 0 1 1

LED_RX 0 1 0

LED_TX 0 0 1

VSS 0 0 0

Pin Bit[2:0]

Pin Setting

CONFIG0 LED_TX

CONFIG1 VSS

CONFIG2 LED_LINK10

CONFIG3 VSS

CONFIG4 VDDO

CONFIG5 VDDO

CONFIG6 VSS

LD7

LED_YELLOW

2 1

0.01uF C101

0.1uF C97

R1

40

22

R 0

.1W

R13170R

49

R9

R1

32

0.01uF C84

R1

51

0R

0.01uF C103

0.1uF C96

TP48

1:1

1:1

1:1

1:1

1:1

P5

B

RJG

5-7

G0

5

9B

10

B

7B

8B

5B

6B

2B

3B

4B

1B

D1

BD

2B

D3

BD

4B

49

R9

R1

43

0.01uF C82

TP50

R13180R

33

0R

R1

60

0.01uF C91

0.01uF C94

33

0R

R1

64

0.0

1u

F

C122

10

K

R3

27

0.0

1u

F

C109

0.01uF C83

L6

3P

IN_

FE

RR

ITE1

3

2

0.1uF C107

0.01uF C93

R13190R

R1

53

0R

0.01uF C81

LD9

LED_YELLOW

2 1

0.01uF C90

R13200R

R1

56

0R

TP51

0.1uF C89

0.1uF C85

0.1uF C104

0.1uF C88

49

R9

R1

42

0.1uF C95

0.1uF C98

0.1uF C99

Y5

25

MH

z

14

23

C2

63

18

pF

C2

64

18

pF

4K

7R

15

8

TP

49

49

R9

R1

36

33

0R

R1

61

49

R9

R1

52

R1

41

22

R 0

.1W

LD11

LED_YELLOW

2 1

0.1uF C420

0.1uF C87

49

R9

R1

35

0.01uF C100

R13140R

33

0R

R1

62

0.1uF C106

0.0

1u

F

C117

R1572K49

0.01uF C92

49

R9

R1

47

RN

69

22

R, R

N

123456789 1

01

11

21

31

41

51

6

TP47

49R9R326

R13150R

R1

48

0R

R1

39

22

R 0

.1W

0.1uF C105

0.1uF C86

0.01uF C102

U2

5

88

E1

01

1S

RX

D_2

A8

RX

D_1

B7

RX

D_0

A7

RX

_D

VA

6

RX

_C

LK

B6

VDDOC6

TX

_C

LK

B4

CO

LA

5

RX

_E

RB

5

VDDOC5

DGNDD5

DGNDD4

DGNDC4

CR

SA

4

SC

LK

_M

C3

GT

X_

CL

KB

3

TX

_E

RA

3

TX

D_

0B

2

TX

_E

NA

2

CO

MA

A1

AVDDLB1

SIN

_M

C1

SO

UT

_M

C2

SIN

_P

D1

SO

UT

_P

D2

TX

D_

6H

1

SC

LK

_P

D3

TX

D_

1E

1CTRL_15

E2

DGNDG4

DVDDLE3

DGNDE4

TX

D_

2F

1

TX

D_

3F

2

TX

D_

4G

1

DVDDHF3

DGNDF4

TX

D_

5G

2

DVDDHG3

DGNDG5

TX

D_

7H

2

DVDDLH3

DGNDH4

DGNDH5

XT

AL

2J1

XT

AL

1J2

VDDOJ3

DGNDJ4

TCKK1

RE

SE

TK

2

VS

SC

K3

DGNDK4

AVDDLL2

TMSL1

DGNDL3

TRSTM1

RSETM2

MD

I0_

PN

1

MD

I0_M

N2

AVDDLM3

MD

I1_

PN

3

DGNDL4

CTRL25M4

MD

I1_M

N4

DGNDJ5

DGNDK5

DGNDL5

HDAC_PM5

AVDDHN5

DGNDL6

HDAC_NM6

DGNDK6

MD

I2_

PN

6

MD

I2_M

N7

DGNDL7

AVDDLM7

MD

I3_

PN

8

AVDDLM8

MD

I3_M

N9

TDIM9

TDOL8

CONFIG_4L9

CONFIG_3K9

CONFIG_2K8

CONFIG_6K7

CONFIG_1J9

CONFIG_5J7

CONFIG_0J8

DGNDJ6

VDDOH7

LED_TXH9

DGNDH6

LED_RXH8

DVDDLG7

DGNDG6

LED_DPLXG9

LED_LINK1000G8

SE

L_

2_

5V

F7

LED_LINK100F9

DGNDF6

LED_LINK10F8

DGNDF5

DGNDE6

MD

CE

8

DGNDE5

VDDOE7

INT

E9

MD

IOD

9

CL

K1

25

D8

DVDDLD7

DGNDD6

DGNDC7

RX

D_6

C8

RX

D_7

C9

RX

D_3

B8

RX

D_5

B9

RX

D_4

A9

LD12

LED_RED

2 1

0.0

1u

F

C127

R130010K

0.01uF C80

R13160R

49R9R325

49

R9

R1

46



Schematics

Figure A-11. Boot Processor—Communications Processor Module

55

44

33

22

11

DD

CC

BB

AA

DG

ND

+3

.3V

CG

ND

DE

BU

G_

RX

DD

EB

UG

_T

XD

RE

V2

RE

V3

RE

V1

RE

V0

RE

V1

RE

V2

RE

V3

RE

V0

GN

D

ID0

ID1

ID3

ID2

ID3

ID2

ID1

ID0

WP

1_

RE

SE

T_

N

SH

UT

DO

WN

SY

ST

EM

_R

ES

ET

_N

WP

3_

RE

SE

T_

NW

P2

_R

ES

ET

_N

RE

V4

RE

V5

RE

V6

RE

V7

RE

V5

RE

V4

RE

V6

ID1

ID0

SY

ST

EM

_R

ES

ET

_N

SH

UT

DO

WN

ID2

ID3

TX

D

RX

D

DE

BU

G_T

XD

DE

BU

G_

RX

D

US

R4

RE

V7

+3

.3V

DG

ND

CG

ND

ID[3

:0]

WP

2_

RE

SE

T_

N

SH

UT

DO

WN

SY

ST

EM

_R

ES

ET

_N

WP

3_

RE

SE

T_

N

WP

1_

RE

SE

T_

N

US

R4

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - Co

mm

un

ica

tion

s P

roce

sso

r Mo

du

le0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

13

72

We

dn

esd

ay, O

cto

be

r 01

, 20

03

Power

Do Not Fit

Decoupling

R132310K

R2494K7

R132110K

C2

51

0.1

uFR771

4K7

R132510K

R132410K

R24710K

C2

53

10

00

pF

R7734K7

R76710K

R132610K

CP

M

Alt. DUART

A lt. DUART

Alt. 10/100 Eth.

Alt. 10/100 Eth.

U2

H

MP

C8

56

0

PA

0H

1

PA

1H

2

PA

2J1

PA

3J2

PA

4J3

PA

5J4

PA

6J5

PA

7J6

PA

8J7

PA

9J8

PA

10

K8

PA

11

K7

PA

12

K6

PA

13

K3

PA

14

K2

PA

15

K1

PA

16

L1

PA

17

L2

PA

18

L3

PA

19

L4

PA

20

L5

PA

21

L8

PA

22

L9

PA

23

L1

0

PA

24

L1

1

PA

25

M1

0

PA

26

M9

PA

27

M8

PA

28

M7

PA

29

M6

PA

30

M3

PA

31

M2

PB

4/F

EC

_T

XD

3M

1

PB

5/F

EC

_T

XD

2N

1

PB

6/F

EC

_T

XD

1N

4

PB

7/F

EC

_T

XD

0N

5

PB

8/F

EC

_R

XD

0N

6

PB

9/F

EC

_R

XD

1N

7

PB

10/F

EC

_R

XD

2N

8

PB

11/F

EC

_R

XD

3N

9

PB

12/F

EC

_C

RS

N1

0

PB

13/F

EC

_C

OL

N1

1

PB

14/F

EC

_T

X_E

NP

11

PB

15/F

EC

_T

X_E

RP

10

PB

16/F

EC

_R

X_E

RP

9

PB

17/F

EC

_R

X_D

VP

8

PB

18

P7

PB

19

P6

PB

20

P5

PB

21

P4

PB

22

P3

PB

23

P2

PB

24

P1

PB

25

R1

PB

26

R2

PB

27

R3

PB

28

R4

PB

29

R5

PB

30

R6

PB

31

R7

PC

0R

8

PC

1R

9

PC

2R

10

PC

3R

11

PC

4T

9

PC

5T

6

PC

6T

5

PC

7T

4

PC

8T

1

PC

9U

1

PC

10

U2

PC

11

U3

PC

12

U4

PC

13/U

AR

T_C

TS

1U

7

PC

14

U8

PC

15/U

AR

T_C

TS

0U

9

PC

16

U1

0

PC

17/F

EC

_R

X_C

LK

V9

PC

18

/FE

C_

TX

_C

LK

V6

PC

19

V5

PC

20

V4

PC

21

V3

PC

22

V2

PC

23

V1

PC

24

W1

PC

25

W2

PC

26

W3

PC

27

W6

PC

28

W7

PC

29

W8

PC

30

W9

PC

31

Y9

PD

4Y

1

PD

5Y

2

PD

6Y

3

PD

7Y

4

PD

8Y

5

PD

9Y

6

PD

10

AA

8

PD

11

AA

7

PD

12

AA

4

PD

13

AA

3

PD

14

AA

2

PD

15

AA

1

PD

16

AB

1

PD

17

AB

2

PD

18

AB

3

PD

19

AB

5

PD

20

AB

6

PD

21

AC

7

PD

22

AC

4

PD

23

AC

3

PD

24

AC

2

PD

25

AC

1

PD

26/U

AR

T_R

TS

1A

D1

PD

27/U

AR

T_S

OU

T1

AD

2

PD

28/U

AR

T_S

IN1

AD

5

PD

29/U

AR

T_R

TS

0A

D6

PD

30/U

AR

T_S

OU

T0

AE

3

PD

31/U

AR

T_S

IN0

AE

2

C2

48

0.1

uF

U3

8

MA

X3229

VccA1

C1

+C

1

C1

-D

1

C2

+A

2

C2

-A

3

Tin

A6

NC

1B

2

NC

2B

3

FO

RC

EO

FF

C5

FO

RC

EO

NB

5

NC

9D

4

Ro

ut

C6

NC

5C

3

NC

6C

4

NC

7D

2N

C8

D3

GNDE1

V+

B1

V-

A4

To

ut

E3

NC

3B

4

NC

4C

2

INV

ALID

E2

Rin

E5

NC

10

D5

NC

11

B6

NC

12

D6

NC

13

E4

Vl

A5

NC

14

E6

R24810K

R7724K7

C2

49

0.1

uF

R76810K

C2

54

0.1

uF

R2504K7

C2

52

0.1

uF

R76910K

R2524K7

0.1uFC842

R2514K7

R76610K

R24610K

R132210K

R24510K

C2

50

0.1

uF

R7704K7

P6

CO

NN

EC

TO

R D

B9

-P

5 9 4 8 3 7 2 6 1

1011



Figure A-12. Boot Processor—Auxiliary Functions

55

44

33

22

11

DD

CC

BB

AA

BP

_H

RE

SE

T_

RE

Q_

N

TS

I50

0_

INT

1_

N

CH

KS

TO

P_

IN_

N

BP

_S

RE

SE

T_

N

WP

3_

INT

_N

BP

_S

YS

_C

LK

CH

KS

TO

P_

IN_

N

BP

_IN

T_

N

BP

_H

RE

SE

T_

RE

Q_

NB

P_

HR

ES

ET

_N

MD

IO

TD

IT

DO

MC

P_

N

MD

C

BP

_T

RS

T_

N

BP

_C

OP

_T

RS

T_

N

PC

I_IN

TB

_N

PC

I_IN

TA

_N

G1

_IR

Q_

N

PC

I_IN

TC

_N

BP

_H

RE

SE

T_

N

TC

K

WP

1_

INT

_N

BP

_S

RE

SE

T_

N

UD

E_

N

CH

KS

TO

P_

OU

T_

NG

2_

IRQ

_N

BP

_C

OP

_S

RE

SE

T_

N

TM

S

TD

O

BP

_C

OP

_S

RE

SE

T_

NB

P_

CO

P_

HR

ES

ET

_N

PC

I_IN

TD

_N

TM

S

WP

2_

INT

_N

IRQ

0_

N

CL

K_

OU

T

BP

_T

RS

T_

N

TH

ER

M0

TD

I

BP

_C

OP

_H

RE

SE

T_

N

TC

K

CH

KS

TO

P_

OU

T_

N

TH

ER

M1

BP

_R

TC

_C

LK

BP

_C

OP

_T

RS

T_

N

AS

LE

EP

TS

I50

0_

INT

0_

N

+3

.3V

DG

ND

MS

RC

ID1

MS

RC

ID2

MD

VA

LM

SR

CID

4M

SR

CID

3

I2C

_S

CL

I2C

_S

DA

TR

IG_

OU

TM

SR

CID

0

I2C

_S

CL

MD

IO

BP

_C

OP

_S

RE

SE

T_

N

BP

_H

RE

SE

T_

N

TS

I50

0_

INT

0_

N

I2C

_S

DA

BP

_S

YS

_C

LK

BP

_T

RS

T_

NB

P_

CO

P_

TR

ST

_N

BP

_C

OP

_H

RE

SE

T_

N

MD

C

G2

_IR

Q_

N

TS

I50

0_

INT

1_

N

G1

_IR

Q_

N

BP

_H

RE

SE

T_

RE

Q_

N

BP

_R

TC

_C

LK

BP

_S

RE

SE

T_

N

DG

ND

+3

.3V

PC

I_IN

TB

_N

PC

I_IN

TC

_N

PC

I_IN

TD

_N

TR

IG_

OU

TM

SR

CID

0

PC

I_IN

TA

_N

WP

1_

INT

_N

WP

2_

INT

_N

WP

3_

INT

_N

BP

_IN

T_

N

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot

Pro

ce

sso

r - Au

xila

ry F

un

ctio

ns

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

14

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

Power

TP

33

R8

91

0K

TP

40

KEY

KEY

HD

2

2x8

He

ad

er

15

16

12

34

56

78

91

01

11

21

31

4

R8

81

0K

R8

61

0K

TP

32

TP

35

TP

15

5T

P1

56

R6

31

0R

TP

15

7

AU

XIL

IAR

Y F

UN

CT

ION

PIC

DMA

Eth.MI

AN

AL

OG

JT

AG

DEBUG

SP

AR

ES

CL

OC

KIN

G

DFT

I2C

SY

S. C

NT

RL

PW

R M

ng

.

U2

D

MP

C8

56

0

MC

PA

G1

7

UD

EA

G1

6

IRQ

0A

A1

8

IRQ

1Y

18

IRQ

2A

B1

8

IRQ

3A

G2

4

IRQ

4A

A2

1

IRQ

5Y

19

IRQ

6A

A1

9

IRQ

7A

G2

5

IRQ

8A

B2

0

IRQ

9/D

MA

_D

RE

Q3

Y2

0

IRQ

10/D

MA

_D

AC

K3

AF

26

IRQ

11/D

MA

_D

DO

NE

3A

H24

IRQ

_O

UT

AB

21

DM

A_D

RE

Q0

H5

DM

A_D

RE

Q1

G4

DM

A_D

AC

K0

H6

DM

A_D

AC

K1

G5

DM

A_D

DO

NE

0H

7

DM

A_D

DO

NE

1G

6

EC

_M

DC

F1

EC

_M

DIO

E1

L1

_T

ST

CL

KA

B2

2

CLK

_O

UT

AF

22

TH

ER

M0

AG

2

TH

ER

M1

AH

3

L2

_T

ST

CL

KA

G2

2

TD

OA

F1

9

TM

SA

F2

3

TD

IA

G2

1

TC

KA

F2

1

TR

ST

AG

23

TR

IG_IN

N1

2

TR

IG_O

UT

/RE

AD

Y/Q

UIE

SC

EG

2

MS

RC

ID0

J9

MS

RC

ID1

G3

MS

RC

ID2

F3

MS

RC

ID3

F5

MS

RC

ID4

F2

MD

VA

LF

4

SP

AR

E1

T1

1

SP

AR

E2

U1

1

SP

AR

E3

AF

1

SP

AR

E4

C1

RT

CA

B2

3

SY

SC

LK

AH

21

LS

SD

_M

OD

EA

G1

9

TE

ST

_S

EL

(Dra

co

/Dra

co

m)

AH

20

AS

LE

EP

AG

18

IIC_S

CL

AH

23

IIC_S

DA

AH

22

CK

ST

P_IN

M1

1

CK

ST

P_O

UT

G1

SR

ES

ET

AF

20

HR

ES

ET

_R

EQ

AG

20

HR

ES

ET

AH

16

NC

2A

H1

NC

3A

G1

NC

4A

H2

NC

5B

1

NC

6B

2

NC

7A

2

NC

8A

3

NC

9A

H2

5

NC

10

AH

26

NC

11

AH

27

NC

12

AH

28

NC

13

AG

28

NC

14

AF

28

NC

15

AE

28

R8

51

0K

R9

02

K

TP

15

4

TP

34

TP

15

3

R9

34

K7

R8

71

0K

R6

23

4K

7

RN

62

10

K, R

N

10

12346789

5

R9

11

0K

R6

32

0R

R9

24

K7

R9

44

K7

R9

54

K7

R8

44

K7

RN

63

10

K, R

N

10

12346789

5

TP

36

R6

24

4K

7



Schematics

Figure A-13. Boot Processor—Power On Configuration

55

44

33

22

11

DD

CC

BB

AA

G1

TX

D5

LW

E_

N1

LW

E_

N0

G1

TX

D7

G2

TX

D6

G2

TX

D7

LW

E_

N2

G2

TX

D5

LW

E_

N3

G2

TX

D4

MS

RC

ID0

+3

.3V

PC

I_G

NT

_N

1

DG

ND

LA

LE

BL

A3

0

LG

PL

2L

GP

L0

LG

PL

1

BL

A2

8

LW

E_

N2

G1

TX

D4

LW

E_

N3

LC

S_

N4

G1

TX

D6

BL

A3

1

BL

A2

9

LC

S_

N3

BL

A2

7

LC

S_

N0

LC

S_

N1

LC

S_

N2

BL

A2

7

G1

GT

XC

LK

G2

GT

XC

LK

TR

IG_

OU

T

G2

TX

D3

G2

TX

D2

G2

TX

D5

G2

TX

D6

G2

TX

D7

G2

TX

D4

G2

TX

D3

G2

TX

D2 P

CI_

GN

T_

N1

LW

E_

N[0

:3]

BP

_R

ST

_C

ON

F_

N

+3

.3V

G1

TX

D[7

:4]

MS

RC

ID0

LG

PL

2

DG

ND

LG

PL

1L

GP

L0

LA

LE

BL

A[2

7:3

1]

LC

S_

N[0

:4]

G2

GT

XC

LK

G1

GT

XC

LK

TR

IG_

OU

T

G2

TX

D[7

:2]

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - Co

nfig

ura

tion

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

15

72

Frid

ay, S

ep

tem

be

r 05

, 20

03

"D

ev

ice ID

6"

"H

ost/A

gen

t 0"

"L

B H

old

1"

PC

I/RIO

"H

ost/A

gen

t 1"

"D

ev

ice ID

5"

"S

ys P

LL

3"

"D

ev

ice ID

4"

Mem

ory

"C

ore P

LL

0"

Pro

cesso

r

RIO

"D

ev

ice ID

0"

Power

LB

"T

SE

C2

Mo

de"

"T

SE

C1

Mo

de"

"C

ore P

LL

1"

"S

ys P

LL

1"

"S

ys P

LL

0"

"D

eb

ug

En

ab

le"

"P

CI H

old

1"

"P

CI H

old

0"

"R

IO C

lk 1

"

"D

ev

ice ID

3"

"L

B H

old

0"

RIOP

CI

"CONFIGURATION"

"D

ev

ice ID

1"

"D

ev

ice ID

2"

TS

EC

"S

ys P

LL

2"

PC

I

Pro

cesso

r

"D

ev

ice ID

7"

"I/O

Imp

d"

"R

IO C

lk 0

"

"C

PU

Bo

ot"

"R

OM

Lo

c.0

"

"R

OM

Lo

c.2

""

RO

M L

oc.1

"

Decoupling

Un

use

d"

Un

use

d"

BIS

T"

BIS

T E

nab

le"

Do Not Fit

Note : Configuration shown is for Rev 1 Silicon.

For Rev 2 silicon;

Remove R731,R732,R735,R736,R737,R738,R740,R741

Add R733,R734

SW

17

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

0.1uFC772

TP

22

8

0.1uFC773

R7

31

0R

SW

14

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

R7

37

0R

SW

15

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

R7

36

0R

R7

41

0R

R7

34

0R

RN

11

31

0K

, RN

10

12346789

5

R7

40

0R

R7

32

0R

R7

38

0R

R7

33

0R

RN

11

61

0K

, RN

10

12346789

5

0.1uFC771

R7

35

0R

RN

11

41

0K

, RN

10

12346789

5

U1

9

74

AL

VT

16

24

4

1A

14

7

1A

24

6

1A

34

4

1A

44

3

2A

14

1

2A

24

0

2A

33

8

2A

43

7

OE

11

OE

24

8

3A

13

6

3A

23

5

3A

33

3

3A

43

2

4A

13

0

4A

22

9

4A

32

7

4A

42

6

OE

42

4

1Y

12

1Y

23

1Y

35

1Y

46

2Y

18

2Y

29

2Y

31

1

2Y

41

2

3Y

11

3

3Y

21

4

3Y

31

6

3Y

41

7

4Y

11

9

4Y

22

0

4Y

32

2

4Y

42

3

3V37

3V318

3V331

3V342

DGND4

DGND10

DGND15

DGND21

DGND28

DGND34

DGND39

DGND45

OE

32

5

U1

8

74

AL

VT

16

24

4

1A

14

7

1A

24

6

1A

34

4

1A

44

3

2A

14

1

2A

24

0

2A

33

8

2A

43

7

OE

11

OE

24

8

3A

13

6

3A

23

5

3A

33

3

3A

43

2

4A

13

0

4A

22

9

4A

32

7

4A

42

6

OE

42

4

1Y

12

1Y

23

1Y

35

1Y

46

2Y

18

2Y

29

2Y

31

1

2Y

41

2

3Y

11

3

3Y

21

4

3Y

31

6

3Y

41

7

4Y

11

9

4Y

22

0

4Y

32

2

4Y

42

3

3V37

3V318

3V331

3V342

DGND4

DGND10

DGND15

DGND21

DGND28

DGND34

DGND39

DGND45

OE

32

5

SW

16

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

RN

11

51

0K

, RN

10

12346789

5



Figure A-14. Boot Processor—PCI Expansion

55

44

33

22

11

DD

CC

BB

AA

VIA

_C

LK

DG

ND

+1

2V

+3

.3V

+5

V

VIA

_R

ES

ET

_N

VIA

_O

N

PC

I_P

AR

64

PC

I_R

ST

_N

PC

I_P

ER

R_

N

PC

I_S

TO

P_

N

PC

I_R

EQ

64

_N

PC

I_C

LK

PC

I_T

RD

Y_

N

PC

I_D

EV

SE

L_

N

PC

I_A

D[3

1:0

]

PC

I_C

BE

[3:0

]

PC

I_R

EQ

_N

0

PC

I_G

NT

_N

0

VIA

_R

ES

ET

_R

EQ

_N

VIA

_IN

T

PC

I_S

ER

R_

N

PC

I_P

AR

_N

PC

I_C

BE

[7:0

]

PC

I_P

AR

_N

PC

I_A

D[6

3:0

]

PC

I_R

EQ

_N

1

PC

I_D

EV

SE

L_

N

PC

I_A

CK

64

_N

PC

I_F

RA

ME

_N

PC

I_IN

TD

_N

PC

I_F

RA

ME

_N

PC

I_S

ER

R_

N

PC

I_R

EQ

_N

[1:0

]

PC

I_G

NT

_N

[1:0

]

PC

I_G

NT

_N

1

PC

I_IR

DY

_N

PC

I_IR

DY

_N

PC

I_T

RD

Y_

N

PC

I_S

TO

P_

NP

CI_

INT

A_

N

PC

I_IN

TC

_N

PC

I_IN

TB

_N

+3

.3V

+1

2V

+5

V

DG

ND

-12

V

CG

ND

PC

I_IN

TA

_N

+3

.3V

VIA

_C

LK

DG

ND

+5

V

+1

2V

VIA

_R

ES

ET

_N

VIA

_O

N

PC

I_P

ER

R_

N

PC

I_P

AR

_N

PC

I_R

ST

_N

PC

I_C

LK

PC

I_P

AR

64

PC

I_D

EV

SE

L_

N

PC

I_R

EQ

64

_N

PC

I_A

CK

64

_N

PC

I_IR

DY

_N

PC

I_T

RD

Y_

NP

CI_

SE

RR

_N

VIA

_R

ES

ET

_R

EQ

_N

VIA

_IN

T

PC

I_C

BE

[7:0

]

PC

I_R

EQ

_N

[1:0

]

PC

I_A

D[6

3:0

]

PC

I_F

RA

ME

_N

PC

I_G

NT

_N

[1:0

]

PC

I_IN

TD

_N

PC

I_IN

TC

_N

PC

I_IN

TB

_N

PC

I_S

TO

P_

N

DG

ND

+3

.3V

+5

V

+1

2V

-12

VP

CI_

INT

A_

N

CG

ND

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - PC

I Exp

an

sio

n0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

16

72

Tu

esd

ay, O

cto

be

r 07

, 20

03

Pa

ge

17

So

uth

brid

ge

PC

I_T

RD

Y_N

PC

I_S

TO

P_

N

PC

I_C

BE

[3:0

]

PC

I_F

RA

ME

_N

VIA

_O

N

PC

I_A

D[3

1:0

]

VIA

_IN

T

VIA

_R

ES

ET

_N

PC

I_P

AR

_N

PC

I_S

ER

R_N

VIA

_R

ES

ET

_R

EQ

_N

PC

I_IR

DY

_N

PC

I_G

NT

_N

0

PC

I_R

EQ

_N

0

PC

I_D

EV

SE

L_N

VIA

_C

LK

+3

.3V

DG

ND

+5

V

+1

2V

CG

ND

PC

I_IN

TA

_N

Pa

ge

21

BP

- PC

I Slo

t

PC

I_C

BE

[7:0

]

+3

.3V

+1

2V

PC

I_G

NT

_N

1

PC

I_A

D[6

3:0

]

PC

I_S

TO

P_

N

PC

I_T

RD

Y_N

PC

I_C

LK

+5

V

PC

I_P

AR

_N

PC

I_IR

DY

_N

PC

I_D

EV

SE

L_N

DG

ND

PC

I_S

ER

R_N

PC

I_F

RA

ME

_N

PC

I_IN

TA

_N

PC

I_IN

TB

_N

PC

I_IN

TC

_N

PC

I_IN

TD

_N

PC

I_A

CK

64

_N

PC

I_R

EQ

64

_N

-12

V

PC

I_R

ST

_N

PC

I_P

ER

R_N

PC

I_R

EQ

_N

1

PC

I_P

AR

64



Schematics

Figure A-15. Southbridge—Top Level

55

44

33

22

11

DD

CC

BB

AA

PD

D_

IRQ

SD

D_

IRQ

SD

D[1

5:0

]

RS

TD

RV

DG

ND

+3

.3V

DG

ND

+3

.3V

US

BC

LK

US

BD

T0

+U

SB

DT

0-

US

BD

T1

+U

SB

DT

1-

OC

0_

NO

C1

_N

+5

V

+5

V

CG

ND

DA

CK

3_

N

DA

CK

5_

N

PC

I_A

D[3

1:0

]

SD

A[2

:0] D

AC

K3

_N

SD

DR

Q

SD

RD

Y

VIA

_R

ES

ET

_N

PC

I_R

EQ

_N

0P

DD

RQ

PD

DIO

R_

NP

CI_

DE

VS

EL

_N

SD

CS

1_

N

VIA

_R

ES

ET

_R

EQ

_N

PD

CS

3_

NP

CI_

ST

OP

_N

PC

I_S

ER

R_

N

S_

80

P

PD

DIO

W_

N

SD

DIO

R_

NS

DC

S3

_N D

AC

K5

_N

SD

DA

CK

_N

PD

CS

1_

NP

CI_

FR

AM

E_

N

SD

DIO

W_

N

PD

D[1

5:0

]

PD

DA

CK

_N

PC

I_IR

DY

_N

PC

I_C

BE

[3:0

]

PC

I_G

NT

_N

0

+1

2V

PD

RD

Y

VIA

_C

LK

PC

I_P

AR

_N

PD

A[2

:0]

+3

.3V

P_

80

P

+5

V

PC

I_T

RD

Y_

N

VIA

_O

N

DG

ND

VIA

_IN

T

PC

I_IN

TA

_N

PC

I_T

RD

Y_

NP

CI_

ST

OP

_N

PC

I_C

BE

[3:0

]

PC

I_F

RA

ME

_N

VIA

_O

N

PC

I_A

D[3

1:0

]

VIA

_IN

T

VIA

_R

ES

ET

_N

PC

I_P

AR

_N

PC

I_S

ER

R_

N

VIA

_R

ES

ET

_R

EQ

_N

PC

I_IR

DY

_N

PC

I_G

NT

_N

0

PC

I_R

EQ

_N

0

PC

I_D

EV

SE

L_

N

VIA

_C

LK

+3

.3V

DG

ND

+3

.3V

DG

ND

+3

.3V

DG

ND

+5

V

+1

2V

+5

V

+5

V

CG

ND

PC

I_IN

TA

_N

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

So

uth

brid

ge

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

17

72

Tu

esd

ay, O

cto

be

r 07

, 20

03

Pa

ge

18

SB

- PC

I,PID

E,A

C9

7

SD

A[2

:0]

VIA

_IN

T

PD

A[2

:0]

VIA

_O

N

PC

I_P

AR

_N

VIA

_R

ES

ET

_R

EQ

_N

PC

I_S

ER

R_N

SD

CS

1_N

PC

I_C

BE

[3:0

]

SD

CS

3_N

SD

DIO

R_N

PC

I_IR

DY

_N

PC

I_S

TO

P_

NP

CI_

DE

VS

EL_N

PC

I_F

RA

ME

_N

PD

DIO

R_N

P_

80

P

PD

DA

CK

_N

PD

DR

Q

PC

I_T

RD

Y_N

PD

CS

1_N

PC

I_G

NT

_N

0

PD

DIO

W_N

PD

D[1

5:0

]

VIA

_C

LK

PD

RD

Y

PC

I_R

EQ

_N

0

SD

RD

Y

PD

CS

3_N

SD

DIO

W_N

VIA

_R

ES

ET

_N

PC

I_A

D[3

1:0

]

+3

.3V

DG

ND

+5

V

+1

2V

S_

80

P

SD

DA

CK

_N

SD

DR

Q

DA

CK

3_N

DA

CK

5_N

PC

I_IN

TA

_N

Pa

ge

20

SB

- IO

PD

D_IR

Q

PD

D[1

5:0

]

RS

TD

RV

PD

RD

YP

DD

IOW

_N

PD

CS

3_N

PD

DR

Q

PD

DIO

R_N

PD

DA

CK

_N

PD

CS

1_N

PD

A[2

:0]

P_

80

P

+3

.3V

DG

ND

SD

D[1

5:0

]

SD

RD

Y

SD

CS

3_N

SD

DIO

W_N

SD

A[2

:0]

SD

DR

Q

SD

D_IR

Q

SD

DIO

R_N

SD

DA

CK

_N

SD

CS

1_N

S_

80

P

US

BD

T0+

US

BD

T0-

US

BD

T1-

US

BD

T1+

US

BC

LK

OC

0_

NO

C1

_N

+5

VP

ag

e 1

9

SB

- SID

E,IS

A,P

erip

he

ral

SD

D_IR

Q

SD

D[1

5:0

]

RS

TD

RV

PD

D_IR

Q+

3.3

V

DG

ND

US

BC

LK

US

BD

T0+

US

BD

T0-

US

BD

T1-

US

BD

T1+

OC

0_

NO

C1

_N

+5

V

CG

ND

DA

CK

3_N

DA

CK

5_N



Figure A-16. Southbridge—PCI, PIDE, AC97

55

44

33

22

11

DD

CC

BB

AA

PC

I_F

RA

ME

_N

PC

I_A

D2

PD

DR

Q

PC

I_A

D2

7

INT

D_

N

PC

I_T

RD

Y_

N

FA

N1

SD

IN2

PD

CS

3_

N

PD

D8

FA

N2

PD

D1

4

PC

I_A

D3

1

PD

CS

1_

N

PD

D9

PC

I_C

BE

3

PC

I_A

D2

6

PD

DIO

W_

N

VIA

_O

N

PD

D6

PC

I_C

BE

1

PC

I_S

ER

R_

N

PD

A2

INT

B_

N

FA

N1

PC

I_A

D7

PC

I_C

BE

0

SD

OU

T

SD

A1

SD

A2

SY

NC

PD

D1

3

INT

A_

N

PD

D5

PC

I_A

D1

4

PC

I_A

D2

0

PC

I_R

EQ

_N

0

PD

D4

PC

I_A

D2

9

PD

D1

0

SD

DIO

W_

N

PC

I_A

D1

0

SD

DR

Q

PC

I_A

D1

8

PC

I_A

D1

5

PC

I_A

D2

2

VIA

_R

ES

ET

_N

PC

I_A

D1

8

PC

I_A

D2

1

PD

A0

PC

I_IR

DY

_N

VIA

_R

ES

ET

_R

EQ

_N

PD

A1

SD

IN

PC

I_G

NT

_N

0

PC

I_A

D1

1

PC

I_P

AR

_N

BIT

CL

K

PD

RD

Y

P_

80

P

PC

I_A

D9

EX

TS

MI_

N

PD

D3

PC

I_A

D2

5

PC

I_A

D1

9

PC

I_A

D6

PC

I_A

D1

7

PC

I_S

TO

P_

N

PD

D1

1

PC

I_A

D3

0

PC

I_A

D4

SD

DIO

R_

N

PC

I_A

D1

2

SD

CS

1_

N

SD

A0

PC

I_A

D1

PD

D0

INT

C_

N

PC

I_A

D0

PC

I_D

EV

SE

L_

N

SD

RD

Y

AC

RS

T_

N

VIA

_C

LK

PC

I_A

D1

6

PC

I_A

D2

8

PC

I_A

D2

3

SD

DA

CK

_N

PC

I_A

D3

INT

C_

N

INT

A_

N

INT

D_

N

FA

N2

SD

CS

3_

N

PC

I_C

BE

2

PC

I_A

D1

3

PD

D1

2

PC

I_A

D2

4

PC

I_A

D5

PD

D1

5

PD

D2

PD

D1

PC

I_A

D8

PD

DA

CK

_N

INT

B_

N

VIA

_IN

T

PD

D7

PD

DIO

R_

N

DG

ND

+3

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+5

V

+1

2V

S_

80

P

PC

I_A

D1

3

AC

RS

T_

NS

DO

UT

SY

NC

SD

IN2

SD

INB

ITC

LK

DA

CK

3_

ND

AC

K5

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PC

I_IN

TA

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SD

A[2

:0]

VIA

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T

PD

A[2

:0]

VIA

_O

N

PC

I_P

AR

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VIA

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ES

ET

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EQ

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PC

I_S

ER

R_

N

SD

CS

1_

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PC

I_C

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[3:0

]

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CS

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PC

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PC

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CI_

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RA

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P_

80

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PD

DA

CK

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PD

DR

Q

PC

I_T

RD

Y_

N

PD

CS

1_

N

PC

I_G

NT

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0

PD

DIO

W_

N

PD

D[1

5:0

]

VIA

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LK

PD

RD

Y

PC

I_R

EQ

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0

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RD

Y

PD

CS

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N

SD

DIO

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VIA

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ET

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PC

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1:0

]

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DG

ND

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SD

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CK

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Q

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CK

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ND

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K5

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PC

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.3V

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V

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12

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Sy

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Power

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Fe

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RN

18

11

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12346789

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TP

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9

RN

18

41

0K

, RN

10

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R6

52

33

R

R6

55

10

K

TP

18

7

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57

10

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TP

19

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TP

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5

U7

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82

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BP

CI, P

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97

PD

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6

PD

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8

PD

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P2

0

PD

D3

R1

7

PD

D4

R1

9

PD

D5

T1

6

PD

D6

T1

8

PD

D7

T2

0

PD

D8

T1

9

PD

D9

T1

7

PD

D10

R2

0

PD

D11

R1

8

PD

D12

R1

6

PD

D13

P1

9

PD

D14

P1

7

PD

D15

N2

0

PD

A0

M1

7

PD

A1

M1

9

PD

A2

M1

8

PD

CS

1L

20

PD

CS

3M

16

PD

DA

CK

M2

0

PD

DR

QN

19

PD

IOR

N1

7

PD

IOW

N1

8

PD

RD

YN

16

AD

0L

17

AD

1L

16

AD

2K

20

AD

3K

19

AD

4K

18

AD

5K

17

AD

6K

16

AD

7J2

0

AD

8J1

8

AD

9J1

7

AD

10

J1

6

AD

11

H2

0

AD

12

H1

9

AD

13

H1

8

AD

14

H1

7

AD

15

H1

6

AD

16

F1

6

AD

17

E2

0

AD

18

E1

9

AD

19

E1

8

AD

20

E1

7

AD

21

D2

0

AD

22

D1

9

AD

23

D1

8

AD

24

B2

0

AD

25

A2

0

AD

26

A1

9

AD

27

B1

9

AD

28

A1

8

AD

29

B1

8

AD

30

C1

8

AD

31

A1

7

C_B

E0

J1

9

C_B

E1

G2

0

C_B

E2

F1

7

C_B

E3

C1

9

FR

AM

EF

18

IRD

YF

19

TR

DY

F2

0

ST

OP

G1

7

DE

VS

EL

G1

6

SE

RR

G1

8

PA

RG

19

IDS

EL

C2

0

RE

QL

18

GN

TL

19

PC

IRS

TB

16

PIN

TA

A1

6

PIN

TB

D1

7

PIN

TC

C1

7

PIN

TD

B1

7

PC

ICLK

E1

6

RT

CX

1Y

5

RT

CX

2W

5

VC

CS

R9

VB

AT

Y6

VC

CH

15

VC

CJ1

5

VC

CK

15

VC

CM

15

VC

CN

15

VC

CR

7

VC

CR

8

VC

CR

11

VC

CR

14

SD

D0/B

ITC

LK

W1

8

SD

D1/S

DIN

V1

7

SD

D2/S

DIN

2Y

17

SD

D3/S

YN

CV

16

SD

D4/S

DO

UT

Y1

6

SD

D5/-A

CR

ST

U1

5

SD

D6/J

BY

W1

5

SD

D7/J

BX

U1

4

SD

D8/J

AY

Y1

5

SD

D9/J

AX

V1

5

SD

D10/J

AB

2T

15

SD

D11/J

AB

1W

16

SD

D12/J

BB

2U

16

SD

D13/J

BB

1W

17

SD

D14/M

SO

Y1

8

SD

D15/M

SI

Y1

9

SD

A0

U1

9

SD

A1

V1

8

SD

A2

U2

0

SD

CS

1U

17

SD

CS

3U

18

SD

DA

CK

V1

9

SD

DR

QY

20

SD

IOR

W1

9

SD

IOW

W2

0

SD

RD

YV

20

A2

0M

Y7

CP

UR

ST

V8

FE

RR

V7

IGN

NE

Y8

INIT

T6

INT

RW

8

NM

IU

7

SL

P/G

PO

7T

7

SM

IU

6

ST

PC

LK

W7

SM

BC

LK

U9

SM

BD

AT

AT

9

PW

RG

DW

6

CLK

RU

NW

12

SP

KR

V5

GP

I1/IR

Q8

W1

1

GP

IOA

/GP

IO8

T1

4

GP

IOD

U8

GP

O0

T8

CP

US

TP

/GP

O4

Y1

2

PC

IST

P/G

PO

5V

12

SU

SS

T1/G

PO

3V

10

SU

SC

LK

T1

0

EX

TS

MI

Y1

0

RIN

G/G

PI7

V1

1

PM

E/G

PI5

/TH

RM

T1

1

BA

TLO

W/G

PI2

U1

1

PW

RB

TN

Y1

1

RS

MR

ST

V6

LID

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ICR

EQ

/GP

I3U

10

SM

BA

LT

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I6W

10

SU

SA

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ICA

CK

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O1

V9

SU

SB

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ICC

S/G

PO

2W

9

SU

SC

Y9

GN

DF

15

GN

DG

15

GN

DL

15

GN

DP

15

GN

DR

15

IN12

Y1

4

IN2

AU

13

IN2

BV

13

CH

AS

/GP

IOC

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IO10

V1

4

TS

EN

1W

13

VR

EF

T1

3

TS

EN

2Y

13

FA

N1

T1

2

FA

N2/G

PIO

B/G

PIO

9U

12

GN

DH

WM

R1

3

VC

CH

WM

R1

2

IN5

W1

4

VC

CS

R1

0

R6

59

10

K

R6

51

10

0R

TP

19

2

TP

18

6

L2

2

Fe

rrite B

ea

d1

2

TP

18

5

D1

3M

BR

S1

30

L2

1

R1

37

7

33

R

R6

77

4K

7

R6

80

53

K,1

%

RN

18

21

0K

, RN

10

12346789

5

R6

53

10

K

Y1

23

2K

Hz

12

R6

54

16

K,1

%

TP

19

5

R6

58

10

K

TP

19

6

TP

19

3

HD

33

HE

AD

ER

4x1

13 24

C8

98

10

pF

R6

79

10

K

RN

18

31

0K

, RN

10

12346789

5

C8

99

10

pF

+

C904

10uF,6.3V Tants

JP

19

13

2C

90

00

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F

C9

02

0.1

uF

TP

19

0

HD

37

2x8

He

ad

er

15

16

12

34

56

78

91

01

11

21

31

4

TP

18

4

R6

78

0R

HD

29

HE

AD

ER

4x1

13 24

TP

19

1



Schematics

Figure A-17. Southbridge—Side, ISA, Peripheral

55

44

33

22

11

DD

CC

BB

AA

SD

D1

3

SD

D9

SD

D2

SD

D1

2

RS

TD

RV SD

D1

SD

D0

SD

D8

PD

D_

IRQ

SD

D4

SD

D1

1

SD

D3

SD

D_

IRQ

SD

D5

14

.31

8M

HZ

_C

LK

SD

D1

0

SD

D7

SD

D1

4S

DD

15

SD

D6

US

BC

LK

US

BD

T0

+U

SB

DT

0-

US

BD

T1

+U

SB

DT

1-

OC

1_

NO

C0

_N

OC

0_

NO

C1

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OC

1_

N_

PU

OC

0_

N_

PU

OC

1_

N_

PU

OC

0_

N_

PU

KB

CL

KK

BD

TM

SC

LK

MS

DT

MS

DT

MS

CL

K

KB

CL

K

KB

DT

CG

ND

+3

.3V

DG

ND

+5

V

SD

D_

IRQ

SD

D[1

5:0

]

RS

TD

RV

PD

D_

IRQ

US

BD

T1

-U

SB

DT

1+

US

BD

T0

-U

SB

DT

0+

US

BC

LK

OC

1_

NO

C0

_N

DG

ND

CG

ND

+3

.3V

+5

V

DA

CK

3_

ND

AC

K5

_N

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+5

V

+5

V

+3

.3V

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V

Sy

ste

m :

Siz

eP

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e T

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Re

v

Da

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Sh

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to

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SB

- SID

E,IS

A,P

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0.6

To

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ap

idIO

En

ab

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Mu

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m

En

gin

ee

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att, N

CS

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19

72

We

dn

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, 20

03

Decoupling

Decoupling

Power

F3

Po

lyF

use

12

TP

21

4

TP

20

4

TP

21

3T

P2

12

TP

21

0

R13274K7

TP

21

5

TP

22

4

0.1uFC1092

RN

19

51

0K

, RN

10

12346789

5

+

C906

10uF,6.3V Tants TP

19

8

TP

21

1

RN

19

91

0K

, RN

10

12346789

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TP

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2

0.1uFC1091

RN

19

84

K7

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10

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5

TP

20

9

TP

20

0

RN

19

11

0K

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5

R13284K7

RN

19

01

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5

0.1uFC1089

TP

20

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N1

97

10

K, R

N

10

12346789

5

TP

22

5

TP

22

1

TP

22

7

TP

20

7

TP

22

3

TP

20

8

RN

18

81

0K

, RN

10

12346789

5

U7

6B

VT

82

C6

86

BS

IDE

, ISA

, PE

RIP

HE

RA

L

*SA

0/S

DD

0W

1

*SA

1/S

DD

1V

2

*SA

2/S

DD

2V

1

*SA

3/S

DD

3U

3

*SA

4/S

DD

4U

2

*SA

5/S

DD

5U

1

*SA

6/S

DD

6T

4

*SA

7/S

DD

7T

3

*SA

8/S

DD

8T

2

*SA

9/S

DD

9T

1

*SA

10/S

DD

10

R5

*SA

11/S

DD

11

R4

*SA

12/S

DD

12

R3

*SA

13/S

DD

13

R2

*SA

14/S

DD

14

R1

*SA

15/S

DD

15

P5

SA

16

P4

SA

17

P3

SA

18

K2

SA

19

K1

LA

20

J5

LA

21

J4

LA

22

J3

LA

23

J2

SD

0Y

1

SD

1Y

2

SD

2W

2

SD

3Y

3

SD

4W

3

SD

5V

3

SD

6Y

4

SD

7W

4

SD

8L

5

SD

9M

2

SD

10

M4

SD

11

N1

SD

12

N3

SD

13

N5

SD

14

P1

SD

15

P2

DA

CK

0L

2

DA

CK

1E

1

DA

CK

3D

2

DA

CK

5L

4

DA

CK

6M

3

DA

CK

7N

2

DR

Q0

L3

DR

Q1

E2

DR

Q3

D3

DR

Q5

M1

DR

Q6

M5

DR

Q7

N4

AE

NB

2

BA

LE

H2

SB

HE

F2

RE

FR

ES

HE

3

IOR

D1

IOW

C2

ME

MR

U4

ME

MW

V4

SM

EM

RA

1

SM

EM

WB

1

IOC

S16

F3

ME

MC

S16

F1

IOC

HR

DY

A2

IOC

HK

/GP

I0F

4

TC

H1

RS

TD

RV

J1

OS

CE

4

BC

LK

H5

IRR

X/G

PO

15

D1

2

IRQ

3G

4

IRQ

4G

3

IRQ

5G

2

*IRQ

6/S

LP

BT

NG

1

IRQ

7F

5

IRQ

9H

4

IRQ

10

K3

IRQ

11

K4

IRQ

14

L1

IRQ

15

K5

IRT

X/G

PO

14

E1

2

XD

IR/G

PO

12

T5

SO

E/G

PO

13

U5

VC

CF

7

VC

CF

10

VC

CF

12

VC

CF

13

VC

CF

14

VC

CH

6

VC

CJ6

VC

CK

6

VC

CM

6

VC

CN

6

PR

D0

B1

5

PR

D1

D1

5

PR

D2

A1

4

PR

D3

B1

4

PR

D4

C1

4

PR

D5

D1

4

PR

D6

E1

4

PR

D7

A1

3

AC

KB

13

BU

SY

C1

3

PE

D1

3

SLC

TE

13

ER

RO

RA

15

PIN

ITC

15

AU

TO

FD

C1

6

SLC

TIN

E1

5

ST

RO

BE

D1

6

TX

D1

A1

1

DT

R1

D1

1

RT

S1

B1

1

CT

S1

C1

1

DS

R1

C1

2

DC

D1

A1

2

RI1

E1

1

RX

D1

B1

2

TX

D2

D1

0

DT

R2

B9

RT

S2

E1

0

CT

S2

A9

DS

R2

C1

0

DC

D2

A1

0

RI2

C9

RX

D2

B1

0

VC

CU

SB

F9

GN

DU

SB

F8

*US

BC

LK

C3

*US

BP

0+

A3

*US

BP

0-

B3

*US

BP

1+

C4

*US

BP

1-

D4

*DR

Q2/O

C1/S

ER

IRQ

/GP

IOE

H3

*DA

CK

2/O

C0/G

PIO

FG

5

*US

BP

2+

A4

*US

BP

2-

B4

*US

BP

3+

B5

*US

BP

3-

E6

*KB

CK

/KA

20G

E5

KB

DT

/KB

RC

A5

MS

CK

/IRQ

1D

5

MS

DT

/IRQ

12

C5

*RO

MC

S/K

BC

SC

1

DR

VD

EN

0D

9

DR

VD

EN

1D

6

IND

EX

D7

MT

R0

E9

DS

1A

8

DS

0B

8

MT

R1

C8

DIR

D8

ST

EP

E8

WD

AT

AA

7

WG

AT

EB

7

TR

AK

00

E7

WR

TP

RT

A6

RD

AT

AB

6

HD

SE

LC

7

DS

KC

HG

C6

GN

DF

6

GN

DF

11

GN

DG

6

GN

DJ9

GN

DJ1

0

GN

DJ1

1

GN

DJ1

2

GN

DK

9

GN

DK

10

GN

DK

11

GN

DK

12

GN

DL

6

GN

DL

9

GN

DL

10

GN

DL

11

GN

DL

12

GN

DM

9

GN

DM

10

GN

DM

11

GN

DM

12

GN

DP

6

GN

DR

6

TP

19

7

Top

Bottom

P3

5

Sta

cke

dP

S2

12

108

7 9 11

64231 5

G1G2G3G4G5

L2

4F

errite

Be

ad

12

TP

20

2

R13294K7

TP

22

0

RN

18

61

0K

, RN

10

12346789

5

RN

18

91

0K

, RN

10

12346789

5

0.1uFC1090

+

C1093

10uF,6.3V Tants

CLK

OUT

Vdd

gnd

Y1

3

14

.31

8M

Hz

42

31

L2

5F

errite

Be

ad

12

RN

19

61

0K

, RN

10

12346789

5

0.1uFC908

R13304K7

TP

21

8

R7

05

0R

TP

19

9

TP

21

9

RN

18

71

0K

, RN

10

12346789

5

RN

19

21

0K

, RN

10

12346789

5T

P2

01

TP

21

7

C9

07

0.1

uF

R7

04

0R

TP

22

6

TP

21

6



Figure A-18. Southbridge—IO

55

44

33

22

11

DD

CC

BB

AA

PD

RD

Y

PD

D1

2

PD

D1

0

PD

D7

PD

D8

PD

D4

PD

D9

PD

A0

PD

D0

PD

CS

1_

NP

DC

S3

_N

PD

D5

PD

D_

IRQ

PD

DIO

R_

N

PD

D1

4P

DD

13

PD

DA

CK

_N

PD

D1

PH

D_

LE

D

P_

80

P

PD

D3

PD

D1

1

PD

D6

PD

DIO

W_

NP

DD

RQ

RS

TD

RV

PD

D1

5

PD

D2

PD

A2

PD

A1

+3

.3V

SD

D0

SD

A1

SD

D1

0

SD

D_

IRQ

SD

D1

4

S_

80

P

SD

DIO

R_

N

SD

D6

SD

D3

SD

CS

1_

N

SD

D1

2S

DD

2

SD

D1

5

RS

TD

RV

SD

D8

SD

D7

SD

DIO

W_

N

SD

D1

SD

D5

SD

DR

Q

SD

A0

SD

D1

3

SD

D4

SD

RD

YS

DD

AC

K_

N

SD

CS

3_

NS

DA

2

SD

D1

1

SH

D_

LE

D

SD

D9

SH

D_

LE

D

US

BD

T0

+U

SB

DT

0-

US

BD

T1

-U

SB

DT

1+

US

BD

1+

US

BD

1-

US

BD

0+

US

BD

0-

US

BD

0+

US

BD

0-

US

BD

1+

US

BD

1-

+5

V

OC

1_

NO

C0

_N

US

BC

LK

DG

ND

PD

D_

IRQ

PD

D[1

5:0

]

RS

TD

RV

PD

RD

Y

PD

DIO

W_

N

PD

CS

3_

N

PD

DR

Q

PD

DIO

R_

N

PD

DA

CK

_N

PD

CS

1_

N

PD

A[2

:0]

P_

80

P

+3

.3V

DG

ND

SD

D[1

5:0

]

SD

RD

Y

SD

CS

3_

N

SD

DIO

W_

N

SD

A[2

:0]

SD

DR

Q

SD

D_

IRQ

SD

DIO

R_

N

SD

DA

CK

_N

SD

CS

1_

N

S_

80

P

US

BD

T0

-U

SB

DT

0+

US

BD

T1

-U

SB

DT

1+

+5

V

OC

1_

NO

C0

_N

US

BC

LK

+5

V

+5

V

+5

V

+5

V

+3

.3V

+3

.3V

+5

V

VC

C+

3.3

V

+5

V

+5

V

+5

V

+5

V+

5V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

So

uth

brid

ge

- IO0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

20

72

We

dn

esd

ay, O

cto

be

r 01

, 20

03

Hard Disk

LED

Header

Primary Hard Disk Drive

Power

Secondary Hard Disk Drive

USB

Decoupling

RN

18

03

3R

, RN

123456789 1

01

11

21

31

41

51

6

RN

21

13

3R

, RN

123456789 1

01

11

21

31

41

51

6

R698560K

R6

48

47

0R

47pFC942

U7

5B

74

AC

T1

4

34

147

R6

47

4K

7

+

C950

10uF,6.3V Tants

R6

94

27

R

HD

23

12

R697560K

P2

4

Sh

rou

de

d H

ea

de

r 20

x2

246810

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

135791

11

31

51

71

92

12

32

52

72

93

13

33

53

73

9

L28Ferrite Bead12

R7

82

22

R 0

.1W

R6

88

47

0R

1000pFC946

47pFC943

R6

46

47

0R

R6

85

1K

R6

43

1K

1uF,10VC947

RN

21

03

3R

, RN

123456789 1

01

11

21

31

41

51

6

R6

86

10

K

0.1uFC952

R700 15K

R6

96

47

0K

RN

20

83

3R

, RN

123456789 1

01

11

21

31

41

51

6

MM

SD

41

48

T1

D1

5

21

MM

SD

41

48

T1

D1

2

21

47pFC944

1000pFC949

L2

9

Fe

rrite B

ea

d1

2

RN

17

73

3R

, RN

123456789 1

01

11

21

31

41

51

6

R69915K

RN

20

93

3R

, RN

123456789 1

01

11

21

31

41

51

6

L27Ferrite Bead12

RN

17

83

3R

, RN

123456789 1

01

11

21

31

41

51

6

R6

92

27

R

CLK

OUT

Vdd

gnd

Y1

4

48

MH

z

42

31

47pFC945

RN

17

93

3R

, RN

123456789 1

01

11

21

31

41

51

6

R701 15K

R6

93

27

R

R6

91

27

R+

C951

10uF,6.3V Tants

F2

Po

lyF

use

120.1uF

C953

R6

87

10

K

F1

Po

lyF

use

12

R6

45

10

K

R6

89

4K

7

R70215K

1uF,10VC948

P2

3

Sh

rou

de

d H

ea

de

r 20

x2

246810

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

135791

11

31

51

71

92

12

32

52

72

93

13

33

53

73

9

R6

44

10

K

R6

49

1K

U7

5A

74

AC

T1

4

12

147

R6

90

1K

HD

27

2x5

He

ad

er

13579

246810

R6

95

47

0K

0.1uFC974



Schematics

Figure A-19. Boot Processor—PCI Slot

55

44

33

22

11

DD

CC

BB

AA

PC

I_A

D1

8P

CI_

AD

19

PC

I_A

D4

PC

I_A

D2

8

PC

I_A

D1

6P

CI_

AD

15

PC

I_A

D2

7

PC

I_A

D2

9

PC

I_C

LK

PC

I_A

D8

PC

I_IR

DY

_N

PC

I_A

D1

7

PC

I_A

D2

4

PC

I_A

D6

PC

I_A

D2

0

PC

I_T

RD

Y_

N

+5

V

PC

I_A

D0

PC

I_A

D1

4

PC

I_A

D2

PC

I_A

D2

6

PC

I_A

D2

1

PC

I_D

EV

SE

L_

N

PC

I_A

D3

1

PC

I_S

ER

R_

N

PC

I_F

RA

ME

_N

PC

I_A

D1

3

DG

ND

PC

I_A

D2

3

PC

I_A

D9

PC

I_A

D1

0

+3

.3V

PC

I_A

D1

2

PC

I_A

D3

PC

I_A

D1

PC

I_A

D2

2

PC

I_S

TO

P_

N

PC

I_A

D1

1

PC

I_A

D2

5

PC

I_A

D7

PC

I_A

D5

PC

I_P

AR

_N

+1

2V

PC

I_A

D3

0

PC

I_IN

TA

_N

PC

I_IN

TB

_N

PC

I_IN

TC

_N

PC

I_IN

TD

_N

PC

I_IN

TB

_N

PC

I_IN

TD

_N

PC

I_C

LK

PC

I_R

EQ

_N

1

PC

I_A

D3

1P

CI_

AD

29

PC

I_A

D2

7P

CI_

AD

25

PC

I_A

D2

3

PC

I_A

D2

1P

CI_

AD

19

PC

I_A

D1

7

PC

I_A

D1

4

PC

I_A

D1

2P

CI_

AD

10

PC

I_A

D8

PC

I_A

D7

PC

I_A

D5

PC

I_A

D3

PC

I_A

D1

PC

I_A

D0

PC

I_A

D2

PC

I_A

D4

PC

I_A

D6

PC

I_A

D9

PC

I_A

D1

1P

CI_

AD

13

PC

I_A

D1

5

PC

I_A

D1

6P

CI_

AD

18

PC

I_A

D2

0P

CI_

AD

22

PC

I_A

D2

4

PC

I_A

D2

6P

CI_

AD

28

PC

I_A

D3

0

PC

I_IN

TA

_N

PC

I_IN

TC

_N

PC

I_G

NT

_N

1

PC

I_C

BE

1

PC

I_C

BE

3

PC

I_C

BE

0

PC

I_C

BE

2

PC

I_C

BE

0

PC

I_C

BE

1

PC

I_S

ER

R_

N

PC

I_P

ER

R_

N

PC

I_D

EV

SE

L_

N

PC

I_IR

DY

_N

PC

I_C

BE

2

PC

I_C

BE

3

PC

I_A

CK

64

_N

PC

I_R

EQ

64

_N

PC

I_P

AR

_N

PC

I_F

RA

ME

_N

PC

I_S

TO

P_

N

PC

I_T

RD

Y_

N

PC

I_M

66

EN

PC

I_R

ST

_N

PC

I_A

D1

9

PC

I_G

NT

_N

1

PC

I_A

CK

64

_N

PC

I_R

EQ

64

_N

-12

VP

CI_

RS

T_

N

PC

I_P

ER

R_

N

PC

I_M

66

EN

PC

I_A

D3

2P

CI_

AD

33

PC

I_A

D3

4P

CI_

AD

35

PC

I_A

D3

6P

CI_

AD

37

PC

I_A

D3

9P

CI_

AD

38

PC

I_A

D4

7

PC

I_A

D4

0

PC

I_A

D4

5P

CI_

AD

46

PC

I_A

D4

1

PC

I_A

D4

3P

CI_

AD

42

PC

I_A

D5

6

PC

I_A

D5

9

PC

I_A

D6

2

PC

I_A

D5

5

PC

I_A

D4

8

PC

I_A

D5

3

PC

I_A

D5

8

PC

I_A

D5

4

PC

I_A

D5

2

PC

I_A

D4

9

PC

I_A

D6

1

PC

I_A

D5

1

PC

I_A

D6

0

PC

I_A

D5

0

PC

I_A

D5

7

PC

I_A

D5

2

PC

I_A

D4

0

PC

I_A

D4

3

PC

I_A

D4

6P

CI_

AD

48

PC

I_A

D6

1

PC

I_A

D4

9

PC

I_A

D5

4

PC

I_A

D3

9

PC

I_A

D3

2

PC

I_A

D5

6

PC

I_A

D3

7

PC

I_A

D5

9

PC

I_A

D4

2

PC

I_A

D3

8

PC

I_A

D4

7

PC

I_A

D6

2

PC

I_A

D3

6

PC

I_A

D3

3

PC

I_A

D4

5

PC

I_A

D5

0

PC

I_A

D3

5

PC

I_A

D6

0

PC

I_A

D5

1

PC

I_A

D5

3P

CI_

AD

55

PC

I_A

D4

4

PC

I_A

D5

8

PC

I_A

D3

4

PC

I_A

D5

7

PC

I_A

D4

1

PC

I_A

D6

3

PC

I_A

D6

3

PC

I_C

BE

6

PC

I_C

BE

4P

CI_

CB

E5

PC

I_C

BE

7

PC

I_C

BE

4

PC

I_C

BE

7P

CI_

CB

E6

PC

I_C

BE

5

PC

I_R

EQ

_N

1

PC

I_P

AR

64

PC

I_P

AR

64

PC

I_S

TO

P_

N

PC

I_IR

DY

_N

PC

I_S

ER

R_

N

PC

I_F

RA

ME

_N

PC

I_T

RD

Y_

N

PC

I_D

EV

SE

L_

N

PC

I_P

ER

R_

N

PC

I_R

EQ

64

_N

PC

I_A

CK

64

_N

PC

I_A

D4

4

PC

I_C

BE

[7:0

]

+3

.3V

+1

2V

PC

I_G

NT

_N

1

PC

I_A

D[6

3:0

]

PC

I_S

TO

P_

NP

CI_

TR

DY

_N

PC

I_C

LK

+5

V

PC

I_P

AR

_N

PC

I_IR

DY

_N

PC

I_D

EV

SE

L_

N

DG

ND

PC

I_S

ER

R_

N

PC

I_F

RA

ME

_N

PC

I_IN

TA

_N

PC

I_IN

TB

_N

PC

I_IN

TC

_N

PC

I_IN

TD

_N

PC

I_A

CK

64

_N

PC

I_R

EQ

64

_N

-12

VP

CI_

RS

T_

N

PC

I_P

ER

R_

N

PC

I_R

EQ

_N

1

PC

I_P

AR

64

+1

2V

+5

V

+3

.3V

-12

V+

5V

+3

.3V

+1

2V

+5

V+

3.3

V

-12

V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - PC

I Exp

an

sio

n0

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To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

21

72

Mo

nd

ay, S

ep

tem

be

r 29

, 20

03

Power

KEY

KEY

PCI_32_bit_3.3VKEY

KEY

P2

6

PC

I CO

NN

EC

TO

R 6

4 B

it

Re

se

rve

d4

B1

4

GN

DB

15

CL

KB

16

GN

DB

17

RE

Q#

B1

8

+3

.3V

B1

9

AD

[31

]B

20

AD

[29

]B

21

GN

DB

22

AD

[27

]B

23

AD

[25

]B

24

+3

.3V

B2

5

C/B

E[3

]#B

26

AD

[23

]B

27

GN

DB

28

AD

[21

]B

29

AD

[19

]B

30

+3

.3V

B3

1

AD

[17

]B

32

C/B

E[2

]#B

33

GN

DB

34

IRD

Y#

B3

5

+3

.3V

B3

6

DE

VS

EL#

B3

7

GN

DB

38

LO

CK

#B

39

PE

RR

#B

40

+3

.3V

B4

1

SE

RR

#B

42

+3

.3V

B4

3

C/B

E[1

]#B

44

AD

[14

]B

45

GN

DB

46

AD

[12

]B

47

AD

[10

]B

48

M6

6E

NB

49

GN

DB

50

GN

DB

51

AD

[08

]B

52

AD

[07

]B

53

+3

.3V

B5

4

AD

[05

]B

55

AD

[03

]B

56

GN

DB

57

AD

[01

]B

58

+3

.3V

B5

9

AC

K6

4#

B6

0

+5

VB

61

+5

VB

62

3.3

Va

ux

A1

4

RS

T#

A1

5

+3

.3V

A1

6

GN

T#

A1

7

GN

DA

18

PM

E#

A1

9

AD

[30

]A

20

+3

.3V

A2

1

AD

[28

]A

22

AD

[26

]A

23

GN

DA

24

AD

[24

]A

25

IDS

EL

A2

6

+3

.3V

A2

7

AD

[22

]A

28

AD

[20

]A

29

GN

DA

30

AD

[18

]A

31

AD

[16

]A

32

+3

.3V

A3

3

FR

AM

E#

A3

4

GN

DA

35

TR

DY

#A

36

GN

DA

37

ST

OP

#A

38

+3

.3V

A3

9

SD

ON

EA

40

SB

O#

A4

1

GN

DA

42

PA

RA

43

AD

[15

]A

44

+3

.3V

A4

5

AD

[13

]A

46

AD

[11

]A

47

GN

DA

48

AD

[09

]A

49

GN

DA

50

GN

DA

51

C/B

E[0

]#A

52

+3

.3V

A5

3

AD

[06

]A

54

AD

[04

]A

55

GN

DA

56

AD

[02

]A

57

AD

[00

]A

58

+3

.3V

A5

9

RE

Q6

4#

A6

0

+5

VA

61

+5

VA

62

-12

VB

1

TC

KB

2

GN

DB

3

TD

OB

4

+5

VB

5

+5

VB

6

INT

B#

B7

INT

D#

B8

PR

SN

T1#

B9

Re

se

rve

d3

B1

0

PR

SN

T2#

B1

1

TR

ST

#A

1

+1

2V

A2

TM

SA

3

TD

IA

4

+5

VA

5

INT

A#

A6

INT

C#

A7

+5

VA

8

Re

se

rve

d1

A9

+3

.3V

A1

0

Re

se

rve

d2

A1

1

Re

se

rve

d5

B6

3

GN

DB

64

C/B

E[6

]#B

65

C/B

E[4

]#B

66

GN

DB

67

AD

[63

]B

68

AD

[61

]B

69

+3

.3V

B7

0

AD

[59

]B

71

AD

[57

]B

72

GN

DB

73

AD

[55

]B

74

AD

[53

]B

75

GN

DB

76

AD

[51

]B

77

AD

[49

]B

78

+3

.3V

B7

9

AD

[47

]B

80

AD

[45

]B

81

GN

DB

82

AD

[43

]B

83

AD

[41

]B

84

GN

DB

85

AD

[39

]B

86

AD

[37

]B

87

+3

.3V

B8

8

AD

[35

]B

89

AD

[33

]B

90

GN

DB

91

Re

se

rve

d6

B9

2

Re

se

rve

d7

B9

3

GN

DB

94

GN

DA

63

C/B

E[7

]#A

64

C/B

E[5

]#A

65

+3

.3V

A6

6

PA

R64

A6

7

AD

[62

]A

68

GN

DA

69

AD

[60

]A

70

AD

[58

]A

71

GN

DA

72

AD

[56

]A

73

AD

[54

]A

74

+3

.3V

A7

5

AD

[52

]A

76

AD

[50

]A

77

GN

DA

78

AD

[48

]A

79

AD

[46

]A

80

GN

DA

81

AD

[44

]A

82

AD

[42

]A

83

+3

.3V

A8

4

AD

[40

]A

85

AD

[38

]A

86

GN

DA

87

AD

[36

]A

88

AD

[34

]A

89

GN

DA

90

AD

[32

]A

91

Re

se

rve

d8

A9

2

GN

DA

93

Re

se

rve

d9

A9

4

R7

28

10

K

R7

29

33

R

R1

38

3

0R

RN

21

31

0K

, RN

10

12346789

5



Figure A-20. Boot Processor—Power

55

44

33

22

11

DD

CC

BB

AA

+3

.3V

Vd

d

DG

ND

SE

NS

E_

VD

D

SE

NS

E_

VS

S

+1

2V

DG

ND

+3

.3V

Vd

d

SE

NS

E_

VD

D

SE

NS

E_

VS

S

+1

2V

Vd

dV

dd

Vd

d

+3

.3V

+3

.3V

Vd

d

Vd

d

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+1

2V

+1

2V

+3

.3V

Vd

d

+3

.3V

Vd

d

Vd

d

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

+3

.3V

+3

.3V

Vd

d

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Bo

ot P

roce

sso

r - Po

we

r0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

22

72

We

dn

esd

ay, O

cto

be

r 01

, 20

03

Power

Decoupling

Decoupling

Decoupling

DecouplingBulk Decoupling

Header for

12V fan

Bulk Decoupling

0.1uFC808

10uF, 6.3V

C955

0.1uFC829

10

R R2

70

0.1uFC1106

S1

DO

57

0.1uFC823

0.1uFC825

0.1uFC821

S2

DO

57

0.1uFC1111

0.1uFC833

0.1uFC814

HD

22

12

0.1uFC824

2.2uF

C3170.1uF

C810

C1116

220uF, Tants

12

0.1uFC1110

0.1uFC835

L3

0

Fe

rrite B

ea

d1

2

0.1uFC827

0.1uFC809

0.1uFC820

HS

1

10

-TH

MA

-01

0.1uFC816

C1117

220uF, Tants

12

0.1uFC813

0.1uFC1259

0.1uFC822

0.1uFC818

0.1uFC815

+

C1085

10uF,6.3V Tants

0.1uFC1107

C1114

220uF, Tants

12

2.2uF

C318

0.1uFC1113

2.2uF

C320

0.1uFC826

0.1uFC1260

0.1uFC1109

0.1uFC830

0.1uFC832

0.1uFC807

C1115

220uF, Tants

12

0.1uFC828

2.2uF

C316

0.1uFC831

0.1uFC812

10

R R2

71

10

R R2

72

+

C1084

10uF,6.3V Tants

0.1uFC817

PO

WE

R

U2

I

MP

C8

56

0

OV

dd

1A

E1

OV

dd

2D

1

OV

dd

3T

2

OV

dd

4N

3

OV

dd

5H

3

OV

dd

6A

H4

OV

dd

7A

D4

OV

dd

8W

4

OV

dd

9K

4

OV

dd

10

E4

OV

dd

11

AC

5

OV

dd

12

AA

5

OV

dd

13

U5

OV

dd

14

M5

OV

dd

15

AF

7

OV

dd

16

AB

7

OV

dd

17

Y7

OV

dd

18

T7

OV

dd

19

L7

OV

dd

20

AE

8

OV

dd

21

V8

OV

dd

22

AB

9

OV

dd

23

AE

10

OV

dd

24

K1

0

OV

dd

25

AC

11

OV

dd

26

AF

12

OV

dd

27

AA

12

OV

dd

28

W1

3

OV

dd

29

AE

15

OV

dd

30

AA

16

OV

dd

31

AC

17

OV

dd

32

W1

9

OV

dd

33

R1

9

OV

dd

34

AA

20

OV

dd

35

U2

0

OV

dd

36

W2

1

OV

dd

37

P2

2

OV

dd

38

Y2

3

OV

dd

39

R2

5

OV

dd

40

AB

26

OV

dd

41

U2

6

OV

dd

42

AG

27

GN

D1

AF

2

GN

D2

N2

GN

D3

C2

GN

D4

AG

3

GN

D5

AD

3

GN

D6

T3

GN

D7

E3

GN

D8

B3

GN

D9

AF

4

GN

D1

0A

B4

GN

D1

1M

4

GN

D1

2H

4

GN

D1

3C

4

GN

D1

4W

5

GN

D1

5K

5

GN

D1

6A

C6

GN

D1

7A

A6

GN

D1

8U

6

GN

D1

9L

6

GN

D2

0A

G7

GN

D2

1V

7

GN

D2

2A

D8

GN

D2

3Y

8

GN

D2

4T

8

GN

D2

5D

8

GN

D2

6A

C9

GN

D2

7K

9

GN

D2

8G

9

GN

D2

9A

F1

0

GN

D3

0V

10

GN

D3

1T

10

GN

D3

2A

B1

1

GN

D3

3F

11

GN

D3

4C

11

GN

D3

5T

12

GN

D3

6P

12

GN

D3

7M

12

GN

D3

8H

12

GN

D3

9G

12

GN

D4

0E

12

GN

D4

1A

12

GN

D4

2A

F1

3

GN

D4

3A

A1

3

GN

D4

4U

13

GN

D4

5R

13

GN

D4

6N

13

GN

D4

7T

14

GN

D4

8P

14

GN

D4

9M

14

GN

D5

0H

14

GN

D5

1B

14

GN

D5

2A

F1

5

GN

D5

3U

15

GN

D5

4R

15

GN

D5

5N

15

GN

D5

6Y

16

GN

D5

7U

16

GN

D5

8T

16

GN

D5

9P

16

GN

D6

0M

16

GN

D6

1A

D1

7

GN

D6

2U

17

GN

D6

3R

17

GN

D6

4N

17

GN

D6

5H

17

GN

D6

6C

17

GN

D6

7A

17

GN

D6

8W

18

GN

D6

9K

18

GN

D7

0F

18

GN

D7

1A

B1

9

GN

D7

2J1

9

GN

D7

3C

19

GN

D7

4R

20

GN

D7

5L

20

GN

D7

6H

20

GN

D7

7B

20

GN

D7

8U

21

GN

D7

9M

22

GN

D8

0H

22

GN

D8

1C

22

GN

D8

2W

23

GN

D8

3P

23

GN

D8

4K

23

GN

D8

5F

23

GN

D8

6J2

4

GN

D8

7E

24

GN

D8

8L

25

GN

D8

9G

25

GN

D9

0A

G2

6

GN

D9

1V

26

GN

D9

2R

26

GN

D9

3B

26

GN

D9

4A

F2

7

GN

D9

5M

27

GN

D9

6H

27

GN

D9

7C

27

GN

D9

8B

27

GN

D9

9K

28

0.1uFC1112

0.1uFC834

0.1uFC811

0.1uFC1261

10uF, 6.3V

C954

CO

RE

&P

LL

Su

pp

ly

U2

E

MP

C8

56

0

VD

D1

U1

2

VD

D2

R1

2

VD

D3

T1

3

VD

D4

P1

3

VD

D5

M1

3

VD

D6

U1

4

VD

D7

R1

4

VD

D8

N1

4

VD

D9

T1

5

VD

D10

P1

5

VD

D11

M1

5

VD

D12

R1

6

VD

D13

N1

6

VD

D14

T1

7

VD

D15

P1

7

VD

D16

M1

7

AV

dd

1A

H1

9

AV

dd

2A

H1

8

AV

dd

3A

H1

7

SE

NS

E_V

DD

L1

2

SE

NS

E_V

SS

K1

2

0.1uFC1108

2.2uF

C319

0.1uFC819

2.2uF

C321



Schematics

Figure A-21. Work Processor 1—Top Level

55

44

33

22

11

DD

CC

BB

AA

RIO

1_

RD

_N

[0:7

]

RIO

1_

RC

LK

RIO

1_

RF

RA

ME

_N

RIO

1_

TC

LK

RIO

1_

RD

[0:7

]

RIO

1_

TD

_N

[0:7

]

RIO

1_

TF

RA

ME

_N

RIO

1_

TC

LK

_N

RIO

1_

RC

LK

_N

RIO

1_

TD

[0:7

]

RIO

1_

TF

RA

ME

RIO

1_

RF

RA

ME

RIO

1_

TX

CL

K_

INR

IO1

_T

XC

LK

_IN

_N

WP

1_

CO

P_

HR

ES

ET

_N

WP

1_

SY

S_

CL

K

WP

1_

HR

ES

ET

_N

WP

1_

CO

P_

TR

ST

_N

WP

1_

SR

ES

ET

_N

WP

1_

RT

C_

CL

K

WP

1_

HR

ES

ET

_R

EQ

_N

WP

1_

TR

ST

_N

WP

1_

CO

P_

SR

ES

ET

_N

DG

ND

+2

.5V

+3

.3V

Vd

d

DG

ND

+3

.3V

WP

1_

RS

T_

CO

NF

_N

+3

.3V

DG

ND

G2

TX

D[7

:2]

LG

PL

1

LW

E_

N[2

:3]

LA

LE

LG

PL

0

BL

A[2

7:3

1]

G1

TX

D[7

:4]

LG

PL

2

MS

RC

ID0

LC

S_

N[0

:2]

LC

S_

N[0

:2]

LG

PL

1

LG

PL

2

LG

PL

0

LW

E_

N[2

:3]

LA

LE

BL

A[2

7:3

1]

MS

RC

ID0

G1

GT

XC

LK

+2

.5V

GE

the

r

DG

ND

+3

.3V

G2

TX

D[7

:2]

+1

.5V

GE

the

r

G1

GT

XC

LK

G1

TX

D[7

:4]

WP

1_

RX

DW

P1

_T

XD

DG

ND

+3

.3V

DG

ND

IRQ

6_

NIR

Q7

_N

+3

.3V

DG

ND

+1

2V

IRQ

6_

N

IRQ

7_

N

+5

VS

B_

BP

+5

V_

BP

AT

X_

BP

+3

.3V

_B

P

AD

S_

HR

ES

ET

_N

WP

2_

INT

_N

BP

_IN

T_

N

WP

1_

INT

_N

WP

3_

INT

_N

G1

_IR

Q_

N

MD

C

MD

IO

I2C

_S

DA

I2C

_S

CL

+1

2V

+5

V

WP

1_

G1

_R

ES

ET

_N

+3

.3V

_B

P

+5

V

RIO

1_

RF

RA

ME

RIO

1_

TC

LK

RIO

1_

TF

RA

ME

_N

RIO

1_

RC

LK

RIO

1_

TC

LK

_N

RIO

1_

RC

LK

_N

RIO

1_

RF

RA

ME

_N

RIO

1_

RD

[0:7

]

RIO

1_

TD

[0:7

]

RIO

1_

TF

RA

ME

RIO

1_

TD

_N

[0:7

]

RIO

1_

RD

_N

[0:7

]

RIO

1_

TX

CL

K_

IN_

NR

IO1

_T

XC

LK

_IN

WP

1_

SY

S_

CL

KW

P1

_R

TC

_C

LK

WP

1_

HR

ES

ET

_R

EQ

_N

+3

.3V

+2

.5V

DG

ND

Vd

d

DG

ND

+3

.3V

WP

1_

HR

ES

ET

_N

WP

1_

CO

P_

SR

ES

ET

_N

WP

1_

CO

P_

HR

ES

ET

_N

WP

1_

CO

P_

TR

ST

_N

WP

1_

TR

ST

_N

WP

1_

SR

ES

ET

_N

WP

1_

RS

T_

CO

NF

_N

DG

ND

+3

.3V

DG

ND

+2

.5V

GE

the

r

+1

.5V

GE

the

r

+3

.3V

WP

1_

TX

DW

P1

_R

XD

DG

ND

+3

.3V

DG

ND

+3

.3V

DG

ND

+3

.3V

_B

P

+1

2V

+5

V_

BP

+5

VS

B_

BP

AT

X_B

P

+3

.3V

_B

P

AD

S_

HR

ES

ET

_N

BP

_IN

T_

N

WP

2_

INT

_N

WP

1_

INT

_N

WP

3_

INT

_N

+5

V

+1

2V

+5

V

WP

1_

G1

_R

ES

ET

_N

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 1 - T

op

Le

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AD

28

LA

D3

AC

26

LA

D4

AC

27

LA

D5

AC

28

LA

D6

AA

22

LA

D7

AA

23

LA

D8

AA

26

LA

D9

Y2

1

LA

D1

0Y

22

LA

D1

1Y

26

LA

D1

2W

20

LA

D1

3W

22

LA

D1

4W

26

LA

D1

5V

19

LA

D1

6T

22

LA

D1

7R

24

LA

D1

8R

23

LA

D1

9R

22

LA

D2

0R

21

LA

D2

1R

18

LA

D2

2P

26

LA

D2

3P

25

LA

D2

4P

20

LA

D2

5P

19

LA

D2

6P

18

LA

D2

7N

22

LA

D2

8N

23

LA

D2

9N

24

LA

D3

0N

25

LA

D3

1N

26

LD

P0

AA

27

LD

P1

AA

28

LD

P2

T2

6

LD

P3

P2

1

LA

LE

V2

1

LB

CT

LV

20

LG

PL

0/L

SD

A1

0U

19

LG

PL1/L

SD

WE

U2

2

LG

PL2/L

OE

/LS

DR

AS

V2

8

LG

PL3/L

SD

CA

SV

27

LG

PL4/L

GT

A/L

UP

WA

IT/L

PB

SE

V2

3

LG

PL

5V

22

LW

E0/L

BS

0A

B2

8

LW

E1/L

BS

1A

B2

7

LW

E2/L

BS

2T

23

LW

E3/L

BS

3P

24

LA

27

U1

8

LA

28

T1

8

LA

29

T1

9

LA

30

T2

0

LA

31

T2

1

LC

S0

Y2

7

LC

S1

Y2

8

LC

S2

W2

7

LC

S3

W2

8

LC

S4

R2

7

LC

S5/D

MA

_D

RE

Q2

R2

8

LC

S6/D

MA

_D

AC

K2

P2

7

LC

S7/D

MA

_D

DO

NE

2P

28

LC

LK

0U

27

LC

LK

1U

28

LC

LK

2V

18

LC

KE

U2

3

LS

YN

C_IN

T2

7

LS

YN

C_O

UT

T2

8

TP

27

1



Schematics

Figure A-23. Work Processor 1—DDR SDRAM

55

44

33

22

11

DD

CC

BB

AA

+2

.5V

+3

.3V

1M

DQ

40

1M

DQ

10

1M

A0

1M

DQ

54

1M

DQ

5

1M

DQ

45

1M

DQ

S8

1M

DQ

6

1M

DQ

1

1M

DQ

33

1M

DQ

20

1M

CA

S_

N

1M

DQ

29

1M

CK

E1

1M

DQ

32

1M

DQ

34

1M

DM

8

1M

DQ

56

1M

DQ

52

1M

DQ

39

1M

DQ

60

1M

DQ

42

1M

DQ

51

1M

DQ

S7

1M

DQ

31

1M

EC

C2

1M

A9

1M

DQ

28

1M

A6

1M

DQ

S1

1M

DQ

36

1M

DQ

3

1M

DQ

37

1M

CK

_N

0

1M

DQ

11

1M

DQ

47

VR

EF

1

1M

DQ

30

1M

DQ

50

1M

DQ

S3

VR

EF

1

1M

DQ

62

1M

CS

1_

N

1M

DQ

43

1M

DM

4

1M

DQ

14

1M

DQ

17

1M

EC

C3

1M

DM

1

1M

DQ

25

1M

DQ

22

1M

A8

1M

DQ

8

1M

DQ

S0

1M

EC

C4

1M

WE

_N

1M

DQ

41

1M

DQ

55

1M

DQ

4

1M

DQ

S6

1M

DM

0

1M

CK

_N

1

1M

DQ

24

1M

DQ

S5

1M

A3

1M

A5

1M

DQ

16

1M

DQ

44

I2C

_S

CL

1M

DM

2

1M

CK

1

1M

DQ

12

1M

A4

1M

DQ

26

I2C

_S

DA

1M

A2

1M

DQ

58

1M

CK

E0

1M

DQ

S4

1M

CK

2

1M

A1

1M

DQ

13

1M

DQ

21

1M

CK

0

1M

DQ

35

1M

EC

C7

1M

DM

5

1M

CK

_N

2

1M

EC

C1

1M

EC

C0

1M

DQ

63

1M

DQ

9

1M

DQ

38

1M

A1

0

1M

A1

2

1M

EC

C6

1M

DQ

0

1M

DQ

15

1M

DQ

19

1M

DQ

53

1M

EC

C5

1M

DQ

2

1M

CS

0_

N

1M

DQ

27

1M

DQ

46

1M

BA

1

1M

DQ

57

1M

DQ

61

1M

DQ

48

1M

DQ

7

1M

DM

3

1M

DQ

49

1M

A1

1

1M

DQ

59

1M

DQ

18

1M

DM

6

1M

A7

1M

BA

0

1M

DM

7

1M

RA

S_

N

1M

DQ

23

1M

DQ

S2

DG

ND

Vd

dS

PD

VR

EF

1

1M

DQ

11

MD

Q0

1M

CS

3_

N

1E

CC

5

1M

DQ

S2

1E

CC

0

1D

M0

1E

CC

2

1M

A1

4

1M

CS

2_

N

1E

CC

4

1D

M1

1E

CC

71

EC

C6

1E

CC

3

1D

M2

1E

CC

1

1D

M3

1D

M4

1D

M8

1D

QS

2

1D

M7

1D

QS

1

1D

M6

1D

QS

0

1A

12

1A

6

1A

11

1D

QS

8

1A

5

1A

0

1A

7

1A

10

1D

QS

4

1A

8

1A

4

1A

1

1A

3

1D

QS

3

1D

QS

71

DQ

S6

1A

14

1A

13

1A

9

1D

QS

5

1B

A0

1B

A1

1W

E_

N

1C

KE

1

1R

AS

_N

1C

S2

_N

1C

AS

_N

1C

S3

_N

1C

S0

_N

1C

S1

_N

1C

KE

0

1C

K2

1N

CK

21

CK

3

1C

K0

1N

CK

3

1N

CK

01

CK

11

NC

K1

1M

DM

0

1M

EC

C6

1M

DM

3

1M

DM

5

1M

EC

C2

1M

DM

2

1M

DQ

S0

1M

EC

C1

1M

DQ

S1

1M

DM

4

1M

DM

6

1M

EC

C5

1M

EC

C3

1M

EC

C7

1M

EC

C0

1M

DQ

S6

1M

EC

C4

1M

DM

1

1M

A0

1M

DM

8

1M

DQ

S3

1M

A2

1M

DQ

S8

1M

DQ

S7

1M

A1

3

1M

A1

1M

A1

01

MA

9

1M

A1

2

1M

A3

1M

A8

1M

A1

1

1M

A6

1M

A4

1M

A7

1M

CS

1_

N

1M

A5

1M

CS

0_

N1

MC

AS

_N

1M

WE

_N

1M

BA

1

1M

RA

S_

N

1M

BA

0

1M

CK

_N

4

1M

CK

_N

51

MC

K5

1M

CK

_N

31

MC

K4

1M

CK

_3

1M

CK

_N

2

1M

CK

_N

11

MC

K2

1M

CK

_N

01

MC

K0

1M

CK

E1

1M

CK

1

1N

CK

4

1M

SY

NC

_O

UT

1C

K4

1N

CK

51

CK

5

1M

SY

NC

_IN

1M

CK

E0

1M

DQ

81

MD

Q1

2

1M

DQ

91

MD

Q1

3

1M

DQ

S1

1M

DM

1

1M

DQ

15

1M

DQ

10

1M

DQ

11

1M

A1

2

1M

DQ

16

1M

DQ

21

1M

DQ

17

1M

DM

21

MD

QS

2

1M

A1

1

1M

A9

1M

DQ

18

1M

DQ

22

1M

DQ

23

1M

DQ

19

1M

DQ

28

1M

DQ

24

1M

A6

1M

A5

1M

A8

1M

A7

1M

DQ

29

1M

DQ

25

1M

DM

31

MD

QS

31

MD

Q3

01

MD

Q2

61

MD

Q3

11

MD

Q2

7

1M

EC

C4

1M

EC

C0

1M

EC

C5

1M

EC

C1

1M

A4

1M

A3

1M

DM

81

MD

QS

81

ME

CC

61

ME

CC

2

1M

EC

C7

1M

A2

1M

A1

1M

EC

C3

1M

CK

E0

1M

CK

E1

1M

A0

1M

DM

01

MD

Q1

1M

DQ

7

1M

DQ

5

1M

DQ

2

1M

DQ

3

1M

DQ

S0

1M

DQ

6

1M

DQ

41

MD

Q0

1M

DQ

14

1M

A1

0

1M

CS

2_

N1

MC

S3

_N

1M

BA

1

1M

RA

S_

N1

MB

A0

1M

DQ

32

1M

DQ

36

1M

DQ

37

1M

DQ

33

1M

WE

_N

1M

CA

S_

N

1M

CS

1_

N1

MC

S0

_N

1M

DM

41

MD

QS

4

1M

DQ

34

1M

DQ

38

1M

DQ

35

1M

DQ

44

1M

DQ

39

1M

DQ

45

1M

DQ

40

1M

DQ

41

1M

DM

51

MD

QS

5

1M

DQ

46

1M

DQ

42

1M

DQ

47

1M

DQ

43

1M

DQ

52

1M

DQ

48

1M

DQ

53

1M

DQ

49

1M

DM

6

1M

A1

3

1M

DQ

S6

1M

DQ

54

1M

DQ

50

1M

DQ

55

1M

DQ

51

1M

DQ

60

1M

DQ

56

1M

DQ

61

1M

DQ

57

1M

DM

71

MD

QS

71

MD

Q6

21

MD

Q5

81

MD

Q6

31

MD

Q5

9

1M

A1

4

1M

DQ

20

1D

M5

1M

DM

7

1M

DQ

S4

1M

DQ

S5

1A

2

1D

Q6

31

DQ

62

1D

Q6

11

DQ

60

1D

Q5

91

DQ

58

1D

Q5

71

DQ

56

1D

Q5

51

DQ

54

1D

Q5

31

DQ

52

1D

Q5

11

DQ

50

1D

Q4

91

DQ

48

1D

Q4

71

DQ

46

1D

Q4

51

DQ

44

1D

Q4

31

DQ

42

1D

Q4

11

DQ

40

1D

Q3

91

DQ

38

1D

Q3

71

DQ

36

1D

Q3

51

DQ

34

1D

Q3

31

DQ

32

1D

Q3

11

DQ

30

1D

Q2

91

DQ

28

1D

Q2

71

DQ

26

1D

Q2

51

DQ

24

1D

Q2

31

DQ

22

1D

Q2

11

DQ

20

1D

Q1

91

DQ

18

1D

Q1

71

DQ

16

1D

Q1

51

DQ

14

1D

Q1

31

DQ

12

1D

Q1

11

DQ

10

1D

Q9

1D

Q8

1D

Q7

1D

Q6

1D

Q5

1D

Q4

1D

Q3

1D

Q2

1D

Q1

1D

Q0

1M

DQ

2

1M

DQ

41

MD

Q3

1M

DQ

6

1M

DQ

81

MD

Q7

1M

DQ

5

1M

DQ

10

1M

DQ

12

1M

DQ

11

1M

DQ

14

1M

DQ

16

1M

DQ

15

1M

DQ

13

1M

DQ

9

1M

DQ

18

1M

DQ

20

1M

DQ

19

1M

DQ

22

1M

DQ

24

1M

DQ

23

1M

DQ

21

1M

DQ

26

1M

DQ

28

1M

DQ

27

1M

DQ

30

1M

DQ

32

1M

DQ

17

1M

DQ

31

1M

DQ

29

1M

DQ

25

1M

DQ

34

1M

DQ

36

1M

DQ

35

1M

DQ

38

1M

DQ

40

1M

DQ

39

1M

DQ

37

1M

DQ

42

1M

DQ

44

1M

DQ

43

1M

DQ

46

1M

DQ

48

1M

DQ

33

1M

DQ

47

1M

DQ

45

1M

DQ

41

1M

DQ

50

1M

DQ

52

1M

DQ

51

1M

DQ

54

1M

DQ

56

1M

DQ

55

1M

DQ

53

1M

DQ

58

1M

DQ

60

1M

DQ

59

1M

DQ

62

1M

DQ

49

1M

DQ

63

1M

DQ

61

1M

DQ

57

+2

.5V

DG

ND

+3

.3V

I2C

_S

DA

I2C

_S

CL

+3

.3V

+2

.5V

+2

.5V

VT

T1

+3

.3V

+2

.5V

+2

.5V

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

+3

.3V

VT

T1

+2

.5V

VT

T1

_S

en

ce

VR

EF

1

VR

EF

1

+2

.5V

VT

T1

VT

T1

VT

T1

_S

en

ce

VT

T1

VT

T1

VT

T1

VT

T1

VR

EF

1V

RE

F1

VR

EF

1

VR

EF

1V

RE

F1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

VT

T1

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

.5V

+2

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+2

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Sy

ste

m :

Siz

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v

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to

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To

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ap

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, 20

03

Power

Decoupling

Decoupling

Do Not Fit

1.25V @ 1.5A


Decoupling

Decoupling

Place Near Pin 1

Decoupling

Place Near Pin N27

Decoupling


Decoupling

Bulk Decoupling

Decoupling

R9

91

22

R

0.1uFC1229

0.1uFC1226

RN

44

27

R, R

N

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01

11

21

31

41

51

6

0.1uFC607

R9

33

22

R

R1

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82

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02

72

2R

R9

24

22

R

RN

39

27

R, R

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123456789 1

01

11

21

31

41

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6

TP

18

R9

58

22

R

0.1uFC1032

R9

75

22

R

0.1uFC606

R9

17

22

R

TP

22

R9

92

22

R

R1

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92

2R

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R9

51

22

R

RN

61

27

R, R

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01

11

21

31

41

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6

R674K7

0.01uFC985

R9

40

22

R

TP

20

0.1uFC599

0.1uFC600

R9

76

22

R

+

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10uF,6.3V Tants

0.1uFC612

R9

93

22

R

0.1uFC1038

0.1uFC1230

RN

22

6

27

R, R

N

123456789 1

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11

21

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41

51

6

0.1uFC608

0.01uFC988

R9

35

22

R

TP

19

R1

01

02

2R

0.1uFC1221

0.1uFC1218

0.1uFC619

R1

02

52

2R

R9

26

22

R

1(2)

39(40)

41(42)

199(200)


SO

DIM

M2

MT

18

VD

DT

64

72

R9

60

22

R

0.1uFC1231

R9

77

22

R

0.1uFC593

0.1uFC594

R9

19

22

R

R9

94

22

R

R1

01

12

2R

TP

21

R1

02

82

2R

0.1uFC1033

R9

53

22

R

0.1uFC1227

R9

46

22

R

0.1uFC1041

RN

58

27

R, R

N

123456789 1

01

11

21

31

41

51

6

R664K7

R9

61

22

R

R9

78

22

R

R9

95

22

R

R9

37

22

R

R1

01

22

2R

R1

02

92

2R

R9

28

22

R

RN

53

27

R, R

N

123456789 1

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AB

25

RIO

_R

D6

AC

25

RIO

_R

D7

AD

25

RIO

_R

D1-

U2

4

RIO

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D2-

V2

4

RIO

_R

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W2

4

RIO

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AA

24

RIO

_R

D5-

AB

24

RIO

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AC

24

RIO

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AD

24

RIO

_T

XC

LK

_IN

AF

24

RIO

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XC

LK

_IN

-A

F2

5



Schematics

Figure A-25. Work Processor 1—PCI Interface

55

44

33

22

11

DD

CC

BB

AA

Sy

ste

m :

Siz

eP

ag

e T

itle :

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v

Da

te:

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ee

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rk P

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To

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C

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72

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ay, S

ep

tem

be

r 26

, 20

03

PC

IX/P

CI

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A

MP

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56

0

PC

I_C

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12

PC

I_C

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AD

11

PC

I_C

_B

E2

AB

10

PC

I_C

_B

E3

AH

8

PC

I_C

_B

E4

W1

4

PC

I_C

_B

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V1

4

PC

I_C

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AH

13

PC

I_C

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AG

13

PC

I_A

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AC

13

PC

I_A

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AB

13

PC

I_A

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Y1

3

PC

I_A

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V1

3

PC

I_A

D4

AH

12

PC

I_A

D5

AG

12

PC

I_A

D6

AE

12

PC

I_A

D7

AD

12

PC

I_A

D8

AB

12

PC

I_A

D9

Y1

2

PC

I_A

D10

W1

2

PC

I_A

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2

PC

I_A

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AH

11

PC

I_A

D13

AG

11

PC

I_A

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AF

11

PC

I_A

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AE

11

PC

I_A

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10

PC

I_A

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0

PC

I_A

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PC

I_A

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9

PC

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9

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9

PC

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9

PC

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AD

9

PC

I_A

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8

PC

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8

PC

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8

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8

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7

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PC

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AF

18

PC

I_A

D33

AF

17

PC

I_A

D34

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17

PC

I_A

D35

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17

PC

I_A

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17

PC

I_A

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7

PC

I_A

D38

W1

7

PC

I_A

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V1

7

PC

I_A

D40

AF

16

PC

I_A

D41

AE

16

PC

I_A

D42

AD

16

PC

I_A

D43

AC

16

PC

I_A

D44

AB

16

PC

I_A

D45

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6

PC

I_A

D46

V1

6

PC

I_A

D47

AH

15

PC

I_A

D48

AG

15

PC

I_A

D49

AD

15

PC

I_A

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AC

15

PC

I_A

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AB

15

PC

I_A

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AA

15

PC

I_A

D53

Y1

5

PC

I_A

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5

PC

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5

PC

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AH

14

PC

I_A

D57

AG

14

PC

I_A

D58

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14

PC

I_A

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14

PC

I_A

D60

AD

14

PC

I_A

D61

AC

14

PC

I_A

D62

AB

14

PC

I_A

D63

AA

14

PC

I_P

AR

AA

11

PC

I_P

AR

64

Y1

4

PC

I_F

RA

ME

AC

10

PC

I_T

RD

YA

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0

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EV

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EQ

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CK

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11

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ER

RY

11

PC

I_R

EQ

0A

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I_R

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G5

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I_G

NT

2A

H5

PC

I_G

NT

3A

F6

PC

I_G

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4A

G6



Figure A-26. Work Processor 1—GigaByte Ethernet Interface—Top

55

44

33

22

11

DD

CC

BB

AA

G1

RX

DV

G1

RX

D[7

:0]

G1

TX

CL

K

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CR

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MD

C

WP

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ET

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N

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L

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IO

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125

+3

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R

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the

r

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:0]

G1

RX

ER

+1

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GE

the

r

G1

RX

CL

K

G1T

XE

N

DG

ND

G2

TX

D[7

:2]

DG

ND

+3

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G1

GT

XC

LK

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TX

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:4]

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the

r

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_IR

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N

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GN

D

WP

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ET

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itle :

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v

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rk P

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Byte

Eth

ern

et In

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ap

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Mo

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SE

C - P

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N

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R

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R

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ET

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5



Schematics

Figure A-27. Work Processor 1—GigaByte Ethernet Interface

55

44

33

22

11

DD

CC

BB

AA

G2

TX

D7

G2

TX

D4

G2

TX

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G2

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TX

12

5

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TX

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G1

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G1

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RX

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G1

RX

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G1

TX

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G1

RX

D[7

:0]

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G1

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TX

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G1

TX

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G1

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G1

RX

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G1

TX

D3

G1

CO

L

G1

RX

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G1

TX

D4

G1

RX

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G1

RX

D5

G1

RX

DV

G1

RX

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G1T

XE

N

G1

TX

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G1

TX

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G1

RX

CL

K

G1

RX

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G1

TX

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TX

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G1

TX

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G1

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G1

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125

+3

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+3

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+3

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+3

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+3

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+3

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Sy

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ee

to

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Byte

Eth

ern

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R546330R R540330R

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2_T

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9

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8765



Figure A-28. Work Processor 1—GigaByte Ethernet Interface—PHY

55

44

33

22

11

DD

CC

BB

AA

G1

TX

D0

G1AVDDH

+3

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G1

RX

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G1

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the

r

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G1

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G1

TX

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the

r

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D1

G1

TX

CL

K

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RX

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_IR

Q_

N

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R

MG

TX

125

G1

RX

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TX

D2

G1

TX

D4

G1

RX

D4

G1

RX

D6

G1

RX

D7

G1

CO

L

G1

RX

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G1

TX

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DG

ND

WP

1_

PH

1_

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WP

1_

PH

1_

M0

WP

1_

PH

1_

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1_

PH

1_

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WP

1_

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1_

P2

WP

1_

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1_

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WP

1_

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1_

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WP

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MD

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the

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the

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the

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ern

et In

terfa

ce

- PH

Y0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

30

72

Tu

esd

ay, S

ep

tem

be

r 30

, 20

03

Power

2.5

V3

.3V

1.5

V

must be 50

mill trace

GR

OU

ND

Se

pa

rate



LED on => Link Up




LED on => Link Up



Pin


Pin


CONFIG0 0 0

0

CONFIG1 0 0

0

CONFIG2 1 1

0

CONFIG3 0 0

0

CONFIG4 1 1

1

CONFIG5 1 1

1

CONFIG6 0 0

0








VDD0 1 1 1

LED_LINK10 1 1 0

LED_LINK100 1 0 1

LED_LINK1000 1 0 0

LED_DUPLEX 0 1 1

LED_RX 0 1 0

LED_TX 0 0 1

VSS 0 0 0

Pin Bit[2:0]

Pin Setting

CONFIG0 VSS

CONFIG1 VSS

CONFIG2 LED_LINK10

CONFIG3 VSS

CONFIG4 VDDO

CONFIG5 VDDO

CONFIG6 VSS

LD20

LED_YELLOW

2 1

0.01uF C450

Y9

25

MH

z

14

23

0.1uF C446

49

R9

R3

81

0.01uF C433

R3

86

22

R 0

.1W

R13380R

49R9R380

0.01uF C452

0.1uF C445

49

R9

R3

88

R130210K

0.01uF C431

R13390R

33

0R

R4

01

0.01uF C440

0.01uF C443

33

0R

R4

05

0.0

1u

F

C460

10

K

R3

97

0.0

1u

F

C458

R3

90

22

R 0

.1W

0.01uF C432

TP141

L1

93

PIN

_F

ER

RIT

E13

2

0.01uF C442

0.1uF C457

R13400R

0.01uF C430

R1

33

21

K

LD22

LED_YELLOW

2 1

0.01uF C439

R3

92

22

R 0

.1WR3

96

0R

0.1uF C438

0.1uF C454

0.1uF C434

0.1uF C437

49

R9

R3

87

0.1uF C444

0.1uF C447

0.1uF C448

R1

33

31

K

TP142

C4

62

18

pF

C4

63

18

pF

4K

7R

39

9

R3

93

22

R 0

.1W

0.1uF C453

TP143

49

R9

R3

83

R13340R

33

0R

R4

02

49

R9

R3

94

LD24

LED_YELLOW

2 1

0.1uF C436

49

R9

R3

82

0.01uF C449

33

0R

R4

03

0.0

1u

F

C459

0.1uF C456

R13350R

R3

84

22

R 0

.1W

R3

95

22

R 0

.1W

R3982K49

TP144

0.01uF C441

49

R9

R3

91

RN

16

32

2R

, RN

123456789 1

01

11

21

31

41

51

6

R13360R

49R9R379

0.1uF C435

0.1uF C455

0.01uF C451

LD25

LED_RED

2 1

U6

0

88

E1

01

1S

RX

D_2

A8

RX

D_1

B7

RX

D_0

A7

RX

_D

VA

6

RX

_C

LK

B6

VDDOC6

TX

_C

LK

B4

CO

LA

5

RX

_E

RB

5

VDDOC5

DGNDD5

DGNDD4

DGNDC4

CR

SA

4

SC

LK

_M

C3

GT

X_

CL

KB

3

TX

_E

RA

3

TX

D_

0B

2

TX

_E

NA

2

CO

MA

A1

AVDDLB1

SIN

_M

C1

SO

UT

_M

C2

SIN

_P

D1

SO

UT

_P

D2

TX

D_

6H

1

SC

LK

_P

D3

TX

D_

1E

1

CTRL_15E2

DGNDG4

DVDDLE3

DGNDE4

TX

D_

2F

1

TX

D_

3F

2

TX

D_

4G

1

DVDDHF3

DGNDF4

TX

D_

5G

2

DVDDHG3

DGNDG5

TX

D_

7H

2

DVDDLH3

DGNDH4

DGNDH5

XT

AL

2J1

XT

AL

1J2

VDDOJ3

DGNDJ4

TCKK1

RE

SE

TK

2

VS

SC

K3

DGNDK4

AVDDLL2

TMSL1

DGNDL3

TRSTM1

RSETM2

MD

I0_

PN

1

MD

I0_M

N2

AVDDLM3

MD

I1_

PN

3

DGNDL4

CTRL25M4

MD

I1_M

N4

DGNDJ5

DGNDK5

DGNDL5

HDAC_PM5

AVDDHN5

DGNDL6

HDAC_NM6

DGNDK6

MD

I2_

PN

6

MD

I2_M

N7

DGNDL7

AVDDLM7

MD

I3_

PN

8

AVDDLM8

MD

I3_M

N9

TDIM9

TDOL8

CONFIG_4L9

CONFIG_3K9

CONFIG_2K8

CONFIG_6K7

CONFIG_1J9

CONFIG_5J7

CONFIG_0J8

DGNDJ6

VDDOH7

LED_TXH9

DGNDH6

LED_RXH8

DVDDLG7

DGNDG6

LED_DPLXG9

LED_LINK1000G8

SE

L_

2_

5V

F7

LED_LINK100F9

DGNDF6

LED_LINK10F8

DGNDF5

DGNDE6

MD

CE

8

DGNDE5

VDDOE7

INT

E9

MD

IOD

9

CL

K1

25

D8

DVDDLD7

DGNDD6

DGNDC7

RX

D_6

C8

RX

D_7

C9

RX

D_3

B8

RX

D_5

B9

RX

D_4

A9

0.0

1u

F

C461

R3

85

22

R 0

.1W

1:1

1:1

1:1

1:1

1:1

P5

C

RJG

5-7

G0

5

9C

10

C

7C

8C

5C

6C

2C

3C

4C

1C

D1

CD

2C

D3

CD

4C

0.01uF C429

R13370R

49

R9

R3

89



Schematics

Figure A-29. Work Processor 1—Communications Processor Module

55

44

33

22

11

DD

CC

BB

AA

WP

1_

RX

DW

P1

_T

XD

UT

OP

IA_

RxC

lav

UT

OP

IA_

TX

D5

UT

OP

IA_

TX

D1

0

UT

OP

IA_

TxP

rty

UT

OP

IA_

RX

D1

3

UT

OP

IA_

TX

CL

K

UT

OP

IA_

TX

D1

2

UT

OP

IA_

RX

D6

UT

OP

IA_

RX

D2

UT

OP

IA_

RxP

rty

UT

OP

IA_

TxA

DD

3

UT

OP

IA_

RX

D1

1

UT

OP

IA_

RX

D3

UT

OP

IA_

TxA

DD

2U

TO

PIA

_T

xA

DD

4

UT

OP

IA_

RX

D1

5

UT

OP

IA_

RxA

DD

3

UT

OP

IA_

TxS

OC

UT

OP

IA_

RxS

OC

UT

OP

IA_

RxA

DD

4

UT

OP

IA_

RX

D9

UT

OP

IA_

RxA

DD

2

UT

OP

IA_

RX

D7

UT

OP

IA_

RX

D1

0

UT

OP

IA_

TxE

nb

_N

UT

OP

IA_

TX

D4

UT

OP

IA_

RxA

DD

0

UT

OP

IA_

RX

CL

K

UT

OP

IA_

TX

D1

UT

OP

IA_

TX

D9

UT

OP

IA_

RX

D4

UT

OP

IA_

TxA

DD

0

UT

OP

IA_

TX

D3

UT

OP

IA_

TX

D2

UT

OP

IA_

RX

D8

UT

OP

IA_

RxE

nb

_N

UT

OP

IA_

TxA

DD

1

UT

OP

IA_

RX

D1

UT

OP

IA_

TX

D0

UT

OP

IA_

TX

D7

UT

OP

IA_

RX

D5

UT

OP

IA_

TX

D1

1U

TO

PIA

_R

XD

12

UT

OP

IA_

TX

D6

UT

OP

IA_

RX

D0

UT

OP

IA_

TX

D1

5U

TO

PIA

_T

xC

lav

UT

OP

IA_

TX

D8

UT

OP

IA_

RX

D1

4

UT

OP

IA_

RxA

DD

1

UT

OP

IA_

TX

D1

4U

TO

PIA

_T

XD

13

+3

.3V

_B

P

DG

ND

UT

OP

IA_

RX

D1

4

UT

OP

IA_

RX

D8

UT

OP

IA_

TxS

OC

PA

7

UT

OP

IA_

TX

D1

4

UT

OP

IA_

TX

D1

2

PA

9

UT

OP

IA_

RX

D1

3

UT

OP

IA_

TX

D8

UT

OP

IA_

RX

D1

1U

TO

PIA

_R

XD

10

UT

OP

IA_

RX

D1

5

UT

OP

IA_

TxE

nb

_N

UT

OP

IA_

RxE

nb

_N

PA

6

UT

OP

IA_

RX

D1

2

PA

8

UT

OP

IA_

TX

D1

3

UT

OP

IA_

RX

D9

UT

OP

IA_

TX

D9

UT

OP

IA_

TxC

lav

PA

4

UT

OP

IA_

TX

D1

1

UT

OP

IA_

TX

D1

5

UT

OP

IA_

RxS

OC

PA

5

UT

OP

IA_

TX

D1

0

UT

OP

IA_

RxC

lav

UT

OP

IA_

TxA

DD

1

PC

28

UT

OP

IA_

RX

D7

UT

OP

IA_

TX

D6

PC

1

UT

OP

IA_

TX

D3

UT

OP

IA_

RxA

DD

2

UT

OP

IA_

TxP

rty

UT

OP

IA_

RX

D2

PC

29

PD

8

UT

OP

IA_

TX

CL

K

UT

OP

IA_

TX

D4

UT

OP

IA_

TX

D1

PC

0

UT

OP

IA_

RX

D6

UT

OP

IA_

TX

D7

PC

25

PC

27

UT

OP

IA_

RX

CL

K

PC

17

UT

OP

IA_

RX

D0

UT

OP

IA_

TxA

DD

4

UT

OP

IA_

TX

D0

PC

26

UT

OP

IA_

RxA

DD

3

PC

19

PC

23

UT

OP

IA_

RX

D5

PD

4

PC

4

UT

OP

IA_

TxA

DD

2

UT

OP

IA_

RX

D4

UT

OP

IA_

TxA

DD

0

UT

OP

IA_

RX

D1

UT

OP

IA_

TxA

DD

3

PC

31

PC

24

PC

18

PC

3

UT

OP

IA_

RxA

DD

0

UT

OP

IA_

RX

D3

UT

OP

IA_

TX

D2

PC

30

PC

22

PC

16

PC

2

UT

OP

IA_

RxA

DD

1

UT

OP

IA_

RxP

rty

PC

5

PC

11

UT

OP

IA_

TX

D5

UT

OP

IA_

RxA

DD

4

PA

3

PA

0P

A1

PA

2

PD

13

PD

9P

D1

0P

D1

1

UT

OP

IA_

RX

D8

UT

OP

IA_

TX

D1

1

UT

OP

IA_

TX

D1

2

UT

OP

IA_

TX

D9

UT

OP

IA_

TX

D8

UT

OP

IA_

RX

D1

1

UT

OP

IA_

TX

D1

5

UT

OP

IA_

TxE

nb

_N

UT

OP

IA_

RxC

lav

UT

OP

IA_

RxS

OC

UT

OP

IA_

RxE

nb

_N

UT

OP

IA_

TxC

lav

PA

3

UT

OP

IA_

TxS

OC

PA

6

PA

4

PA

0

PA

5

UT

OP

IA_

RX

D1

2

UT

OP

IA_

RX

D1

0

PA

1

PA

7

PA

8

UT

OP

IA_

RX

D1

5

UT

OP

IA_

TX

D1

4

PA

2

UT

OP

IA_

TX

D1

3

UT

OP

IA_

RX

D1

4

UT

OP

IA_

TX

D1

0

UT

OP

IA_

RX

D9

UT

OP

IA_

RX

D1

3U

TO

PIA

_R

XD

0

UT

OP

IA_

TX

D3

PD

9

UT

OP

IA_

RX

D3

UT

OP

IA_

TxA

DD

4

PD

10

UT

OP

IA_

RX

D6

UT

OP

IA_

TX

D5

UT

OP

IA_

TxP

rty

UT

OP

IA_

RX

D1

UT

OP

IA_

RX

D4

PD

11

UT

OP

IA_

RxA

DD

4

UT

OP

IA_

RX

D2

UT

OP

IA_

TxA

DD

3

UT

OP

IA_

RxA

DD

3

WP

1_

RX

D

WP

1_

TX

D

UT

OP

IA_

RX

D7

UT

OP

IA_

TX

D6

UT

OP

IA_

RX

D5

UT

OP

IA_

TX

D4

UT

OP

IA_

RxP

rty

PD

4

PD

13

UT

OP

IA_

TX

D7

PA

9P

D8

PB

22

PB

8

PB

17

PB

26

PB

15

PB

7

PB

16

PB

18

PB

27

PB

14

PB

30

PB

25

PB

29

PB

6

PB

28

PB

10

PB

24

PB

31

PB

4

PB

13

PB

5

PB

19

PB

21

PB

11

PB

9

PB

12

PB

23

PB

20

PB

13

PB

5

PB

24

PB

17

PB

26

PB

16

PB

10

PB

14

PB

7

PB

11

PB

8

PB

22

PB

6

PB

29

PB

9

PB

20

PB

23

PB

30

PB

31

PB

21

PB

18

PB

15

PB

25

PB

19

PB

28

PB

12

PB

27

PB

4

PC

5

PC

4

PC

0

PC

11

UT

OP

IA_

RxA

DD

2

UT

OP

IA_

TxA

DD

0

UT

OP

IA_

TxA

DD

2

UT

OP

IA_

TX

D2

UT

OP

IA_

TX

D0

PC

30

PC

26

PC

25

PC

22

UT

OP

IA_

TxA

DD

1

PC

29

PC

31

PC

16

PC

28

PC

19

PC

24

PC

27

PC

2

PC

23

UT

OP

IA_

TX

CL

K

PC

18

UT

OP

IA_

RX

CL

K

UT

OP

IA_

RxA

DD

1

PC

3

PC

17

PC

1

UT

OP

IA_

TX

D1

UT

OP

IA_

RxA

DD

0

+5

V

PD

12

PD

12

WP

1_

TX

DW

P1

_R

XD

DG

ND

+3

.3V

_B

P

+5

V

+3

.3V

_B

P

+3

.3V

_B

P

+3

.3V

_B

P+

3.3

V_

BP

+3

.3V

_B

P

+5

V

+5

V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 1 - C

om

mu

nic

atio

ns P

roce

sso

r Mo

du

le0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

31

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

Power

P7

EcP

CI_

J3

E1

E1

E2

E2

E3

E3

E4

E4

E5

E5

E6

E6

E7

E7

E8

E8

E9

E9

E1

0E

10

E1

1E

11

E1

2E

12

E1

3E

13

E1

4E

14

E1

5E

15

E1

6E

16

E1

7E

17

E1

8E

18

E1

9E

19

TP

33

3

P7

BcP

CI_

J3

B1

B1

B2

B2

B3

B3

B4

B4

B5

B5

B6

B6

B7

B7

B8

B8

B9

B9

B1

0B

10

B1

1B

11

B1

2B

12

B1

3B

13

B1

4B

14

B1

5B

15

B1

6B

16

B1

7B

17

B1

8B

18

B1

9B

19

P7

CcP

CI_

J3

C1

C1

C2

C2

C3

C3

C4

C4

C5

C5

C6

C6

C7

C7

C8

C8

C9

C9

C1

0C

10

C1

1C

11

C1

2C

12

C1

3C

13

C1

4C

14

C1

5C

15

C1

6C

16

C1

7C

17

C1

8C

18

C1

9C

19

P7

DcP

CI_

J3

D1

D1

D2

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D7

D8

D8

D9

D9

D1

0D

10

D1

1D

11

D1

2D

12

D1

3D

13

D1

4D

14

D1

5D

15

D1

6D

16

D1

7D

17

D1

8D

18

D1

9D

19

P7

FcP

CI_

J3

S1

F1

S2

F2

S3

F3

S4

F4

S5

F5

S6

F6

S7

F7

S8

F8

S9

F9

S1

0F

10

CP

MAlt. DUART

A lt. DUART

Alt. 10/100 Eth.

Alt. 10/100 Eth.

U1

H

MP

C8

56

0

PA

0H

1

PA

1H

2

PA

2J1

PA

3J2

PA

4J3

PA

5J4

PA

6J5

PA

7J6

PA

8J7

PA

9J8

PA

10

K8

PA

11

K7

PA

12

K6

PA

13

K3

PA

14

K2

PA

15

K1

PA

16

L1

PA

17

L2

PA

18

L3

PA

19

L4

PA

20

L5

PA

21

L8

PA

22

L9

PA

23

L1

0

PA

24

L1

1

PA

25

M1

0

PA

26

M9

PA

27

M8

PA

28

M7

PA

29

M6

PA

30

M3

PA

31

M2

PB

4/F

EC

_T

XD

3M

1

PB

5/F

EC

_T

XD

2N

1

PB

6/F

EC

_T

XD

1N

4

PB

7/F

EC

_T

XD

0N

5

PB

8/F

EC

_R

XD

0N

6

PB

9/F

EC

_R

XD

1N

7

PB

10/F

EC

_R

XD

2N

8

PB

11/F

EC

_R

XD

3N

9

PB

12/F

EC

_C

RS

N1

0

PB

13/F

EC

_C

OL

N1

1

PB

14/F

EC

_T

X_E

NP

11

PB

15/F

EC

_T

X_E

RP

10

PB

16/F

EC

_R

X_E

RP

9

PB

17/F

EC

_R

X_D

VP

8

PB

18

P7

PB

19

P6

PB

20

P5

PB

21

P4

PB

22

P3

PB

23

P2

PB

24

P1

PB

25

R1

PB

26

R2

PB

27

R3

PB

28

R4

PB

29

R5

PB

30

R6

PB

31

R7

PC

0R

8

PC

1R

9

PC

2R

10

PC

3R

11

PC

4T

9

PC

5T

6

PC

6T

5

PC

7T

4

PC

8T

1

PC

9U

1

PC

10

U2

PC

11

U3

PC

12

U4

PC

13/U

AR

T_C

TS

1U

7

PC

14

U8

PC

15/U

AR

T_C

TS

0U

9

PC

16

U1

0

PC

17/F

EC

_R

X_C

LK

V9

PC

18

/FE

C_

TX

_C

LK

V6

PC

19

V5

PC

20

V4

PC

21

V3

PC

22

V2

PC

23

V1

PC

24

W1

PC

25

W2

PC

26

W3

PC

27

W6

PC

28

W7

PC

29

W8

PC

30

W9

PC

31

Y9

PD

4Y

1

PD

5Y

2

PD

6Y

3

PD

7Y

4

PD

8Y

5

PD

9Y

6

PD

10

AA

8

PD

11

AA

7

PD

12

AA

4

PD

13

AA

3

PD

14

AA

2

PD

15

AA

1

PD

16

AB

1

PD

17

AB

2

PD

18

AB

3

PD

19

AB

5

PD

20

AB

6

PD

21

AC

7

PD

22

AC

4

PD

23

AC

3

PD

24

AC

2

PD

25

AC

1

PD

26/U

AR

T_R

TS

1A

D1

PD

27/U

AR

T_S

OU

T1

AD

2

PD

28/U

AR

T_S

IN1

AD

5

PD

29/U

AR

T_R

TS

0A

D6

PD

30/U

AR

T_S

OU

T0

AE

3

PD

31/U

AR

T_S

IN0

AE

2

TP

33

2

AB

CD

AB

CD

P2

9

CO

NN

RC

PT

10

0x2

A1

A2

A3

A4

A5

A6

A7

A8

A9

A1

0

A1

1

A1

2

A1

3

A1

4

A1

5

A1

6

A1

7

A1

8

A1

9

A2

0

A2

1

A2

2

A2

3

A2

4

A2

5

A2

6

A2

7

A2

8

A2

9

A3

0

A3

1

A3

2

B1

B2

B3

B4

B5

B6

B7

B8

B9

B1

0

B1

1

B1

2

B1

3

B1

4

B1

5

B1

6

B1

7

B1

8

B1

9

B2

0

B2

1

B2

2

B2

3

B2

4

B2

5

B2

6

B2

7

B2

8

B2

9

B3

0

B3

1

B3

2

C1

C2

C3

C4

C5

C6

C7

C8

C9

C1

0

C1

1

C1

2

C1

3

C1

4

C1

5

C1

6

C1

7

C1

8

C1

9

C2

0

C2

1

C2

2

C2

3

C2

4

C2

5

C2

6

C2

7

C2

8

C2

9

C3

0

C3

1

C3

2

D1

D2

D3

D4

D5

D6

D7

D8

D9

D1

0

D1

1

D1

2

D1

3

D1

4

D1

5

D1

6

D1

7

D1

8

D1

9

D2

0

D2

1

D2

2

D2

3

D2

4

D2

5

D2

6

D2

7

D2

8

D2

9

D3

0

D3

1

D3

2

P7

AcP

CI_

J3

A1

A1

A2

A2

A3

A3

A4

A4

A5

A5

A6

A6

A7

A7

A8

A8

A9

A9

A1

0A

10

A1

1A

11

A1

2A

12

A1

3A

13

A1

4A

14

A1

5A

15

A1

6A

16

A1

7A

17

A1

8A

18

A1

9A

19



Figure A-30. Work Processor 1—Auxiliary Functions

55

44

33

22

11

DD

CC

BB

AA

MD

CM

DIO

G1

_IR

Q_

N

WP

1_

TR

ST

_N

WP

1_

SY

S_

CL

K

WP

1_

HR

ES

ET

_N

IRQ

11

_N

WP

1_

CO

P_

SR

ES

ET

_N

TM

S

WP

1_

CO

P_

HR

ES

ET

_N

WP

1_

CO

P_

TR

ST

_N

MC

P_

N

WP

1_

SR

ES

ET

_N

UD

E_

N

WP

1_

SR

ES

ET

_N

TC

K

WP

1_

CO

P_

HR

ES

ET

_N

TD

IT

DO

+3

.3V

IRQ

10

_N

WP

1_

HR

ES

ET

_R

EQ

_N

WP

1_

CO

P_

SR

ES

ET

_N

CH

KS

TO

P_

OU

T_

N

DG

ND

IRQ

8_

N

CH

KS

TO

P_

IN_

N

WP

1_

HR

ES

ET

_N

TM

S

MS

RC

ID0

WP

1_

RT

C_

CL

K

TC

K

CH

KS

TO

P_

OU

T_

N

AS

LE

EP

IRQ

9_

N

WP

1_

TR

ST

_N

IRQ

0_

N

CH

KS

TO

P_

IN_

N

WP

1_

HR

ES

ET

_R

EQ

_N

TD

O

WP

1_

CO

P_

TR

ST

_N

CL

K_

OU

T

TD

I

MD

VA

L

MS

RC

ID1

MS

RC

ID2

MS

RC

ID4

MS

RC

ID3

I2C

_S

DA

I2C

_S

CL

TH

ER

M0

TH

ER

M1

WP

2_

INT

_N

BP

_IN

T_

NW

P3

_IN

T_

N

IRQ

2_

N

WP

1_

INT

_N

IRQ

6_

NIR

Q7

_N

TR

IG_

OU

T

MD

IOM

DC

G1

_IR

Q_

N

DG

ND

+3

.3V

WP

1_

CO

P_

SR

ES

ET

_N

I2C

_S

DA

WP

1_

SY

S_

CL

K

WP

1_

HR

ES

ET

_N

WP

1_

CO

P_

TR

ST

_N

WP

1_

TR

ST

_N

WP

1_

HR

ES

ET

_R

EQ

_N

WP

1_

CO

P_

HR

ES

ET

_N

I2C

_S

CL

WP

1_

SR

ES

ET

_N

MS

RC

ID0

WP

1_

RT

C_

CL

K

IRQ

7_

NIR

Q6

_N

WP

2_

INT

_N

WP

3_

INT

_N

BP

_IN

T_

N

WP

1_

INT

_N

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 1 - A

uxila

ry F

un

ctio

ns

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

32

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

Power

TP

73

R2

14

10

K

TP

80

KEY

KEY

HD

10

2x8

He

ad

er

15

16

12

34

56

78

91

01

11

21

31

4

R2

13

10

K

R7

06

10

K

R2

11

10

K

AU

XIL

IAR

Y F

UN

CT

ION

PIC

DMA

Eth.MI

AN

AL

OG

JT

AG

DEBUG

SP

AR

ES

CL

OC

KIN

G

DFT

I2C

SY

S. C

NT

RL

PW

R M

ng

.

U1

D

MP

C8

56

0

MC

PA

G1

7

UD

EA

G1

6

IRQ

0A

A1

8

IRQ

1Y

18

IRQ

2A

B1

8

IRQ

3A

G2

4

IRQ

4A

A2

1

IRQ

5Y

19

IRQ

6A

A1

9

IRQ

7A

G2

5

IRQ

8A

B2

0

IRQ

9/D

MA

_D

RE

Q3

Y2

0

IRQ

10/D

MA

_D

AC

K3

AF

26

IRQ

11/D

MA

_D

DO

NE

3A

H2

4

IRQ

_O

UT

AB

21

DM

A_D

RE

Q0

H5

DM

A_D

RE

Q1

G4

DM

A_D

AC

K0

H6

DM

A_D

AC

K1

G5

DM

A_D

DO

NE

0H

7

DM

A_D

DO

NE

1G

6

EC

_M

DC

F1

EC

_M

DIO

E1

L1

_T

ST

CL

KA

B2

2

CLK

_O

UT

AF

22

TH

ER

M0

AG

2

TH

ER

M1

AH

3

L2

_T

ST

CL

KA

G2

2

TD

OA

F1

9

TM

SA

F2

3

TD

IA

G2

1

TC

KA

F2

1

TR

ST

AG

23

TR

IG_IN

N1

2

TR

IG_O

UT

/RE

AD

Y/Q

UIE

SC

EG

2

MS

RC

ID0

J9

MS

RC

ID1

G3

MS

RC

ID2

F3

MS

RC

ID3

F5

MS

RC

ID4

F2

MD

VA

LF

4

SP

AR

E1

T1

1

SP

AR

E2

U1

1

SP

AR

E3

AF

1

SP

AR

E4

C1

RT

CA

B2

3

SY

SC

LK

AH

21

LS

SD

_M

OD

EA

G1

9

TE

ST

_S

EL

(Dra

co

/Dra

co

m)

AH

20

AS

LE

EP

AG

18

IIC_S

CL

AH

23

IIC_S

DA

AH

22

CK

ST

P_IN

M1

1

CK

ST

P_O

UT

G1

SR

ES

ET

AF

20

HR

ES

ET

_R

EQ

AG

20

HR

ES

ET

AH

16

NC

2A

H1

NC

3A

G1

NC

4A

H2

NC

5B

1

NC

6B

2

NC

7A

2

NC

8A

3

NC

9A

H2

5

NC

10

AH

26

NC

11

AH

27

NC

12

AH

28

NC

13

AG

28

NC

14

AF

28

NC

15

AE

28

TP

72

TP

75

TP

16

0T

P1

61

RN

14

4

10

K, R

N

10

12346789

5

R6

33

0R

TP

16

2

JP

39

12

R2

10

10

KR

21

52

K

TP

15

9T

P1

58

TP

74

R2

18

4K

7

R2

12

10

K

R6

25

4K

7

R2

16

10

KR

63

40

R

R2

17

4K

7

RN

14

31

0K

, RN

10

12346789

5

R2

20

4K

7R

21

94

K7

R2

09

4K

7

TP

76

R6

26

4K

7



Schematics

Figure A-31. Work Processor 1—Power On Configuration

55

44

33

22

11

DD

CC

BB

AA

+3

.3V

G2

TX

D5

G1

TX

D7

G2

TX

D6

G1

TX

D4

G2

TX

D7

G1

TX

D6

G1

TX

D5

G2

TX

D4

G2

TX

D2

G2

TX

D4

G2

TX

D3

G2

TX

D6

G2

TX

D7

G2

TX

D5

BL

A3

1

LG

PL

2

LW

E_

N2

LA

LE

BL

A2

7

LG

PL

0

BL

A2

7

LC

S_

N2

BL

A2

9B

LA

28

MS

RC

ID0

LC

S_

N1

LC

S_

N0

LG

PL

1

LW

E_

N3

DG

ND

G1

GT

XC

LK

BL

A3

0

G2

TX

D2

G2

TX

D3

+3

.3V

WP

1_

RS

T_

CO

NF

_N

DG

ND

LG

PL

1

LW

E_

N[2

:3]

LG

PL

2

MS

RC

ID0

LC

S_

N[0

:2]

LG

PL

0

LA

LE

BL

A[2

7:3

1]

G1

GT

XC

LK

G1

TX

D[7

:4]

G2

TX

D[7

:4]

G2

TX

D[7

:2]

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 1 - C

on

figu

ratio

n0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

33

72

Mo

nd

ay, S

ep

tem

be

r 08

, 20

03

"D

ev

ice ID

7"

"R

OM

Lo

c.2

"

"R

IO C

lk 1

"

"D

ev

ice ID

2"

"CONFIGURATION"

"R

OM

Lo

c.0

"

"D

ev

ice ID

3"

Pro

cesso

r

RIO

"R

IO C

lk 0

"

"S

ys P

LL

3"

"C

PU

Bo

ot"

"C

ore P

LL

1"

RIO

"D

ev

ice ID

6"

"R

OM

Lo

c.1

"

"S

ys P

LL

0"

"S

ys P

LL

2"

Mem

ory

"D

eb

ug

En

ab

le"

"H

ost/A

gen

t 0"

Power

"D

ev

ice ID

1"

"H

ost/A

gen

t 1"

"D

ev

ice ID

5"

"D

ev

ice ID

0"

"S

ys P

LL

1"

"D

ev

ice ID

4"

PC

I/RIO

"C

ore P

LL

0"

Pro

cesso

r

"T

SE

C1

Mo

de"

TS

EC

Decoupling


For Rev 2 silicon;

Remove R744,R745,R746,R747,R748

Add R742,R743

Do Not Fit

R7

47

0R

0.1uFC850

SW

6

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

SW

7

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

RN

65

10

K, R

N

10

12346789

5

R7

45

0R

RN

67

10

K, R

N

10

12346789

5

0.1uFC849

R7

44

0R

R7

43

0R

RN

66

10

K, R

N

10

12346789

5

R7

46

0R

R7

42

0R

U2

7

74

AL

VT

16

24

4

1A

14

7

1A

24

6

1A

34

4

1A

44

3

2A

14

1

2A

24

0

2A

33

8

2A

43

7

OE

11

OE

24

8

3A

13

6

3A

23

5

3A

33

3

3A

43

2

4A

13

0

4A

22

9

4A

32

7

4A

42

6

OE

42

4

1Y

12

1Y

23

1Y

35

1Y

46

2Y

18

2Y

29

2Y

31

1

2Y

41

2

3Y

11

3

3Y

21

4

3Y

31

6

3Y

41

7

4Y

11

9

4Y

22

0

4Y

32

2

4Y

42

3

3V37

3V318

3V331

3V342

DGND4

DGND10

DGND15

DGND21

DGND28

DGND34

DGND39

DGND45

OE

32

5

SW

8

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9R

74

80

R

74

LV

CH

24

4

U2

8

2Y

43

2Y

35

2Y

27

2Y

19

1Y

41

21Y

31

41Y

21

61Y

11

8

2A

41

72A

31

52A

21

32A

11

1

1A

48

1A

36

1A

24

1A

12

VC

C 20

2O

E1

9

GN

D

10

1O

E1



Figure A-32. Work Processor 1—Power

55

44

33

22

11

DD

CC

BB

AA

Vd

d

+3

.3V

DG

ND

+1

2V

DG

ND

+3

.3V

Vd

d

+1

2V

Vd

d

+3

.3V

Vd

d

Vd

dV

dd

+3

.3V

+3

.3V

Vd

d

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Vd

d

+3

.3V

+3

.3V

Vd

d+

3.3

V+

3.3

VV

dd

+3

.3V

+3

.3V

+3

.3V

Vd

d

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Vd

d

+3

.3V

+3

.3V

Vd

dV

dd

+1

2V

Vd

d

+1

2V

+3

.3V

Vd

d

+3

.3V

+3

.3V

Vd

d

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

+3

.3V

+3

.3V

Vd

dV

dd

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 1 - P

ow

er

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

34

72

We

dn

esd

ay, O

cto

be

r 01

, 20

03

Decoupling

Decoupling

Power

Decoupling

Decoupling

Header for

12V fan

Bulk Decoupling

Bulk Decoupling

0.1uFC743

PO

WE

R

U1

I

MP

C8

56

0

OV

dd

1A

E1

OV

dd

2D

1

OV

dd

3T

2

OV

dd

4N

3

OV

dd

5H

3

OV

dd

6A

H4

OV

dd

7A

D4

OV

dd

8W

4

OV

dd

9K

4

OV

dd

10

E4

OV

dd

11

AC

5

OV

dd

12

AA

5

OV

dd

13

U5

OV

dd

14

M5

OV

dd

15

AF

7

OV

dd

16

AB

7

OV

dd

17

Y7

OV

dd

18

T7

OV

dd

19

L7

OV

dd

20

AE

8

OV

dd

21

V8

OV

dd

22

AB

9

OV

dd

23

AE

10

OV

dd

24

K1

0

OV

dd

25

AC

11

OV

dd

26

AF

12

OV

dd

27

AA

12

OV

dd

28

W1

3

OV

dd

29

AE

15

OV

dd

30

AA

16

OV

dd

31

AC

17

OV

dd

32

W1

9

OV

dd

33

R1

9

OV

dd

34

AA

20

OV

dd

35

U2

0

OV

dd

36

W2

1

OV

dd

37

P2

2

OV

dd

38

Y2

3

OV

dd

39

R2

5

OV

dd

40

AB

26

OV

dd

41

U2

6

OV

dd

42

AG

27

GN

D1

AF

2

GN

D2

N2

GN

D3

C2

GN

D4

AG

3

GN

D5

AD

3

GN

D6

T3

GN

D7

E3

GN

D8

B3

GN

D9

AF

4

GN

D1

0A

B4

GN

D1

1M

4

GN

D1

2H

4

GN

D1

3C

4

GN

D1

4W

5

GN

D1

5K

5

GN

D1

6A

C6

GN

D1

7A

A6

GN

D1

8U

6

GN

D1

9L

6

GN

D2

0A

G7

GN

D2

1V

7

GN

D2

2A

D8

GN

D2

3Y

8

GN

D2

4T

8

GN

D2

5D

8

GN

D2

6A

C9

GN

D2

7K

9

GN

D2

8G

9

GN

D2

9A

F1

0

GN

D3

0V

10

GN

D3

1T

10

GN

D3

2A

B1

1

GN

D3

3F

11

GN

D3

4C

11

GN

D3

5T

12

GN

D3

6P

12

GN

D3

7M

12

GN

D3

8H

12

GN

D3

9G

12

GN

D4

0E

12

GN

D4

1A

12

GN

D4

2A

F1

3

GN

D4

3A

A1

3

GN

D4

4U

13

GN

D4

5R

13

GN

D4

6N

13

GN

D4

7T

14

GN

D4

8P

14

GN

D4

9M

14

GN

D5

0H

14

GN

D5

1B

14

GN

D5

2A

F1

5

GN

D5

3U

15

GN

D5

4R

15

GN

D5

5N

15

GN

D5

6Y

16

GN

D5

7U

16

GN

D5

8T

16

GN

D5

9P

16

GN

D6

0M

16

GN

D6

1A

D17

GN

D6

2U

17

GN

D6

3R

17

GN

D6

4N

17

GN

D6

5H

17

GN

D6

6C

17

GN

D6

7A

17

GN

D6

8W

18

GN

D6

9K

18

GN

D7

0F

18

GN

D7

1A

B1

9

GN

D7

2J1

9

GN

D7

3C

19

GN

D7

4R

20

GN

D7

5L

20

GN

D7

6H

20

GN

D7

7B

20

GN

D7

8U

21

GN

D7

9M

22

GN

D8

0H

22

GN

D8

1C

22

GN

D8

2W

23

GN

D8

3P

23

GN

D8

4K

23

GN

D8

5F

23

GN

D8

6J2

4

GN

D8

7E

24

GN

D8

8L

25

GN

D8

9G

25

GN

D9

0A

G2

6

GN

D9

1V

26

GN

D9

2R

26

GN

D9

3B

26

GN

D9

4A

F2

7

GN

D9

5M

27

GN

D9

6H

27

GN

D9

7C

27

GN

D9

8B

27

GN

D9

9K

28

0.1uFC1118

0.1uFC764

TP

18

3

10

R R2

67

+

C1088

10uF,6.3V Tants

S3

DO

57

0.1uFC758

C1128

220uF, Tants

12

0.1uFC760

0.1uFC756

0.1uFC1262

S4

DO

57

0.1uFC768

0.1uFC749

0.1uFC759

2.2uF

C311

0.1uFC1123

0.1uFC745

C1129

220uF, Tants

12

0.1uFC1263

HD

21

12

0.1uFC770

0.1uFC762

0.1uFC1122

0.1uFC744

0.1uFC755

HS

2

10

-TH

MA

-01

0.1uFC751

+

C1087

10uF,6.3V Tants

C1126

220uF, Tants

12

0.1uFC748 0.1uF

C1264

L3

1

Fe

rrite B

ea

d1

2

0.1uFC753

0.1uFC757

0.1uFC750

CO

RE

&P

LL

Su

pp

ly

U1

E

MP

C8

56

0

VD

D1

U1

2

VD

D2

R1

2

VD

D3

T1

3

VD

D4

P1

3

VD

D5

M1

3

VD

D6

U1

4

VD

D7

R1

4

VD

D8

N1

4

VD

D9

T1

5

VD

D10

P1

5

VD

D11

M1

5

VD

D12

R1

6

VD

D13

N1

6

VD

D14

T1

7

VD

D15

P1

7

VD

D16

M1

7

AV

dd

1A

H1

9

AV

dd

2A

H1

8

AV

dd

3A

H1

7

SE

NS

E_V

DD

L1

2

SE

NS

E_V

SS

K1

2

C1127

220uF, Tants

12

0.1uFC1119

2.2uF

C312

2.2uF

C314

0.1uFC761

10uF, 6.3VC957

0.1uFC765

0.1uFC1125

0.1uFC767

0.1uFC742

0.1uFC1121

10uF, 6.3V

C956

0.1uFC763

2.2uF

C310

0.1uFC766

0.1uFC747

10

R R2

68

10

R R2

69

0.1uFC752

0.1uFC769

0.1uFC1124

0.1uFC746

0.1uFC1120

2.2uF

C313

0.1uFC754

2.2uF

C315

TP

18

2



Schematics


55

44

33

22

11

DD

CC

BB

AA

Vd

d

+2

.5V

LG

PL

0

LG

PL

2

G1

TX

D[7

:4]

LC

S_

N[0

:2]

G1

TX

D[7

:4]

MS

RC

ID0

MS

RC

ID0

WP

2_

TR

ST

_N

+3

.3V

LC

S_

N[0

:2]

WP

2_

HR

ES

ET

_R

EQ

_N

+3

.3V

WP

2_

HR

ES

ET

_N

G1

GT

XC

LK

DG

ND

WP

2_

SR

ES

ET

_N

G2

TX

D[7

:2]

+2

.5V

GE

the

r

LG

PL

0WP

2_

RS

T_

CO

NF

_N

LA

LE

LW

E_

N[2

:3]

LG

PL

2

LA

LE

WP

2_

CO

P_

HR

ES

ET

_N

+1

.5V

GE

the

r

LG

PL

1

LW

E_

N[2

:3]

WP

2_

CO

P_

SR

ES

ET

_N

G2

TX

D[7

:2]

+3

.3V

LG

PL

1

WP

2_

SY

S_

CL

K

DG

ND

DG

ND

WP

2_

RT

C_

CL

K

G1

GT

XC

LK

BL

A[2

7:3

1]

BL

A[2

7:3

1]

DG

ND

+3

.3V

+3

.3V

WP

2_

CO

P_

TR

ST

_N

RIO

2_

TX

CL

K_

IN_

NR

IO2

_T

XC

LK

_IN

RIO

2_

RD

_N

[0:7

]

RIO

2_

TC

LK

RIO

2_

TD

[0:7

]

RIO

2_

TC

LK

_N

RIO

2_

TF

RA

ME

_N

RIO

2_

RD

[0:7

]

RIO

2_

RC

LK

_N

RIO

2_

RF

RA

ME

_N

RIO

2_

RC

LK

RIO

2_

RF

RA

ME

RIO

2_

TD

_N

[0:7

]

RIO

2_

TF

RA

ME

DG

ND

WP

2_

TX

DW

P2

_R

XD

+1

2V

BP

_IN

T_

N

WP

1_

INT

_N

WP

3_

INT

_N

WP

2_

INT

_N

I2C

_S

DA

I2C

_S

CL

MD

IO

MD

C

G1

_IR

Q_

N

WP

2_

G1

_R

ES

ET

_N

WP

2_

CO

P_

SR

ES

ET

_N

WP

2_

RS

T_

CO

NF

_N

DG

ND

WP

2_

HR

ES

ET

_N

DG

ND

+3

.3V

+2

.5V

GE

the

r

WP

2_

HR

ES

ET

_R

EQ

_N

Vd

d

WP

2_

CO

P_

HR

ES

ET

_N

WP

2_

CO

P_

TR

ST

_N

+3

.3V

+3

.3V

+1

.5V

GE

the

r

WP

2_

SR

ES

ET

_N

+2

.5V

WP

2_

SY

S_

CL

K

+3

.3V

WP

2_

TR

ST

_N

DG

ND

WP

2_

RT

C_

CL

K

DG

ND

+3

.3V

RIO

2_

TX

CL

K_

INR

IO2

_T

XC

LK

_IN

_N

RIO

2_

RC

LK

_N

RIO

2_

TC

LK

RIO

2_

TC

LK

_N

RIO

2_

RF

RA

ME

_N

RIO

2_

TD

[0:7

]

RIO

2_

RF

RA

ME

RIO

2_

RD

_N

[0:7

]

RIO

2_

TD

_N

[0:7

]

RIO

2_

RC

LK

RIO

2_

TF

RA

ME

RIO

2_

TF

RA

ME

_N

RIO

2_

RD

[0:7

]

DG

ND

WP

2_

RX

DW

P2

_T

XD

+1

2V

BP

_IN

T_

NW

P3

_IN

T_

N

WP

1_

INT

_N

WP

2_

INT

_N

WP

2_

G1

_R

ES

ET

_N

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 2 - T

op

Le

ve

l0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

35

72

Mo

nd

ay, S

ep

tem

be

r 08

, 20

03

Pa

ge

39

WP

2 - A

UX

WP

2_

SY

S_

CL

KW

P2

_R

TC

_C

LK

I2C

_S

DA

I2C

_S

CL

DG

ND

+3

.3V

WP

2_S

RE

SE

T_N

WP

2_H

RE

SE

T_R

EQ

_N

WP

2_H

RE

SE

T_N

WP

2_C

OP

_S

RE

SE

T_N

WP

2_

CO

P_

TR

ST

_N

WP

2_

TR

ST

_N

WP

2_C

OP

_H

RE

SE

T_N

MS

RC

ID0

G1

_IR

Q_

N

MD

C

MD

IO

BP

_IN

T_

N

WP

1_

INT

_N

WP

3_

INT

_N

WP

2_

INT

_N

Pa

ge

37

WP

2 - P

CI

Pa

ge

43

WP

2 - C

PM

WP

2_T

XD

WP

2_R

XD

Pa

ge

46

WP

2- P

ow

er

+3

.3V

Vd

d

DG

ND

+1

2V

Pa

ge

32

WP

2 - D

DR

SD

RA

M

+2

.5V

DG

ND

+3

.3V

I2C

_S

DA

I2C

_S

CL

Pa

ge

36

WP

2 - L

oca

l Bu

s

LA

LE

LG

PL

0

LG

PL

1

LW

E_

N[2

:3]

LG

PL

2

LC

S_

N[0

:2]

BL

A[2

7:3

1]

Pa

ge

35

WP

2 - T

SE

C - T

op

+2

.5V

GE

the

r

G1

TX

D[7

:4]

G2

TX

D[7

:2]

+1

.5V

GE

the

r

MD

C

WP

2_

G1

_R

ES

ET

_N

G1

GT

XC

LK

G1

_IR

Q_

N

MD

IO

DG

ND

+3

.3V

Pa

ge

45

WP

2 - C

on

fig

DG

ND

+3

.3V

LG

PL

1

G1

TX

D[7

:4]

LG

PL

0

BL

A[2

7:3

1]

LA

LE

G2

TX

D[7

:2]

MS

RC

ID0

WP

2_

RS

T_

CO

NF

_N

LC

S_

N[0

:2]

LG

PL

2

LW

E_

N[2

:3]

G1

GT

XC

LK

Pa

ge

38

WP

2 - R

IO

RIO

2_T

XC

LK

_IN

RIO

2_

TX

CL

K_

IN_

N

RIO

2_

TC

LK

RIO

2_

TC

LK

_N

RIO

2_

TF

RA

ME

_N

RIO

2_T

FR

AM

E

RIO

2_

TD

[0:7

]

RIO

2_

TD

_N

[0:7

]

RIO

2_

RC

LK

RIO

2_

RC

LK

_N

RIO

2_R

FR

AM

ER

IO2_R

FR

AM

E_N

RIO

2_R

D_N

[0:7

]

RIO

2_R

D[0

:7]




55

44

33

22

11

DD

CC

BB

AA

LG

PL

2

LW

E_

N3

LC

S_

N2

BL

A2

7

BL

A3

1

BL

A2

9

LG

PL

0

BL

A3

0

LG

PL

1

LC

S_

N0

LA

LE

LC

S_

N1

BL

A2

8

LW

E_

N2

LA

LE

BL

A[2

7:3

1]

LG

PL

0

LW

E_

N[2

:3]

LG

PL

2L

GP

L1

LC

S_

N[0

:2]

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 2 - L

oca

l Bu

s0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

36

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

TP

27

3T

P2

74

LO

CA

L B

US

U7

F

MP

C8

56

0

LA

D0

AD

26

LA

D1

AD

27

LA

D2

AD

28

LA

D3

AC

26

LA

D4

AC

27

LA

D5

AC

28

LA

D6

AA

22

LA

D7

AA

23

LA

D8

AA

26

LA

D9

Y2

1

LA

D1

0Y

22

LA

D1

1Y

26

LA

D1

2W

20

LA

D1

3W

22

LA

D1

4W

26

LA

D1

5V

19

LA

D1

6T

22

LA

D1

7R

24

LA

D1

8R

23

LA

D1

9R

22

LA

D2

0R

21

LA

D2

1R

18

LA

D2

2P

26

LA

D2

3P

25

LA

D2

4P

20

LA

D2

5P

19

LA

D2

6P

18

LA

D2

7N

22

LA

D2

8N

23

LA

D2

9N

24

LA

D3

0N

25

LA

D3

1N

26

LD

P0

AA

27

LD

P1

AA

28

LD

P2

T2

6

LD

P3

P2

1

LA

LE

V2

1

LB

CT

LV

20

LG

PL

0/L

SD

A1

0U

19

LG

PL1/L

SD

WE

U2

2

LG

PL2/L

OE

/LS

DR

AS

V2

8

LG

PL3/L

SD

CA

SV

27

LG

PL4/L

GT

A/L

UP

WA

IT/L

PB

SE

V2

3

LG

PL

5V

22

LW

E0/L

BS

0A

B2

8

LW

E1/L

BS

1A

B2

7

LW

E2/L

BS

2T

23

LW

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BS

3P

24

LA

27

U1

8

LA

28

T1

8

LA

29

T1

9

LA

30

T2

0

LA

31

T2

1

LC

S0

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7

LC

S1

Y2

8

LC

S2

W2

7

LC

S3

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8

LC

S4

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7

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S5/D

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LC

S6/D

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AC

K2

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LC

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28

LC

LK

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27

LC

LK

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28

LC

LK

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18

LC

KE

U2

3

LS

YN

C_IN

T2

7

LS

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C_O

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T2

8



Schematics


55

44

33

22

11

DD

CC

BB

AA

2M

DQ

30

2M

BA

0

2M

DQ

18

2M

DQ

23

2M

DQ

37

VR

EF

2

2M

CS

0_

N

2M

DQ

60

2M

RA

S_

N

2M

DQ

59

2M

DQ

13

2M

A1

0

2M

EC

C5

2M

DQ

25

2M

DQ

19

2M

DQ

63

2M

EC

C6

2M

CK

1

2M

DQ

53

2M

DQ

S3

2M

DQ

4

2M

DQ

49

2M

DQ

36

2M

DQ

S6

2M

DQ

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2M

DQ

12

2M

DQ

20

2M

A3

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DQ

21

2M

EC

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CK

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DQ

11

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2M

DQ

29

2M

DQ

24

2M

DQ

S2

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DQ

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DQ

8

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DQ

55

2M

DQ

40

2M

A4

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DQ

26

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DQ

34

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CA

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DQ

61

VR

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39

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DM

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2M

DQ

57

2M

DQ

50

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EC

C4

2M

DM

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A5

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46

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DQ

S4

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DQ

6

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DQ

58

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DQ

31

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DQ

17

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CK

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DQ

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CK

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27

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DM

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9

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DQ

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2M

DQ

38

2M

DQ

41

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CK

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DQ

45

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DQ

28

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DQ

62

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DQ

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DQ

14

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DQ

51

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DQ

33

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DQ

52

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DQ

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DQ

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DQ

35

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DQ

43

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DQ

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22

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DQ

54

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DQ

16

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DQ

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72

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2A

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2A

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72

DQ

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14

2A

13

2A

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92

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15

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r 26

, 20

03

PC

IX/P

CI

U7

A

MP

C8

56

0

PC

I_C

_B

E0

AC

12

PC

I_C

_B

E1

AD

11

PC

I_C

_B

E2

AB

10

PC

I_C

_B

E3

AH

8

PC

I_C

_B

E4

W1

4

PC

I_C

_B

E5

V1

4

PC

I_C

_B

E6

AH

13

PC

I_C

_B

E7

AG

13

PC

I_A

D0

AC

13

PC

I_A

D1

AB

13

PC

I_A

D2

Y1

3

PC

I_A

D3

V1

3

PC

I_A

D4

AH

12

PC

I_A

D5

AG

12

PC

I_A

D6

AE

12

PC

I_A

D7

AD

12

PC

I_A

D8

AB

12

PC

I_A

D9

Y1

2

PC

I_A

D10

W1

2

PC

I_A

D11

V1

2

PC

I_A

D12

AH

11

PC

I_A

D13

AG

11

PC

I_A

D14

AF

11

PC

I_A

D15

AE

11

PC

I_A

D16

AA

10

PC

I_A

D17

Y1

0

PC

I_A

D18

W1

0

PC

I_A

D19

AH

9

PC

I_A

D20

AG

9

PC

I_A

D21

AF

9

PC

I_A

D22

AE

9

PC

I_A

D23

AD

9

PC

I_A

D24

AG

8

PC

I_A

D25

AF

8

PC

I_A

D26

AC

8

PC

I_A

D27

AB

8

PC

I_A

D28

AH

7

PC

I_A

D29

AE

7

PC

I_A

D30

AD

7

PC

I_A

D31

AH

6

PC

I_A

D32

AF

18

PC

I_A

D33

AF

17

PC

I_A

D34

AE

17

PC

I_A

D35

AB

17

PC

I_A

D36

AA

17

PC

I_A

D37

Y1

7

PC

I_A

D38

W1

7

PC

I_A

D39

V1

7

PC

I_A

D40

AF

16

PC

I_A

D41

AE

16

PC

I_A

D42

AD

16

PC

I_A

D43

AC

16

PC

I_A

D44

AB

16

PC

I_A

D45

W1

6

PC

I_A

D46

V1

6

PC

I_A

D47

AH

15

PC

I_A

D48

AG

15

PC

I_A

D49

AD

15

PC

I_A

D50

AC

15

PC

I_A

D51

AB

15

PC

I_A

D52

AA

15

PC

I_A

D53

Y1

5

PC

I_A

D54

W1

5

PC

I_A

D55

V1

5

PC

I_A

D56

AH

14

PC

I_A

D57

AG

14

PC

I_A

D58

AF

14

PC

I_A

D59

AE

14

PC

I_A

D60

AD

14

PC

I_A

D61

AC

14

PC

I_A

D62

AB

14

PC

I_A

D63

AA

14

PC

I_P

AR

AA

11

PC

I_P

AR

64

Y1

4

PC

I_F

RA

ME

AC

10

PC

I_T

RD

YA

G1

0

PC

I_IR

DY

AD

10

PC

I_S

TO

PV

11

PC

I_D

EV

SE

LA

H1

0

PC

I_ID

SE

LA

A9

PC

I_R

EQ

64

AE

13

PC

I_A

CK

64

AD

13

PC

I_P

ER

RW

11

PC

I_S

ER

RY

11

PC

I_R

EQ

0A

F5

PC

I_R

EQ

1A

F3

PC

I_R

EQ

2A

E4

PC

I_R

EQ

3A

G4

PC

I_R

EQ

4A

E5

PC

I_G

NT

0A

E6

PC

I_G

NT

1A

G5

PC

I_G

NT

2A

H5

PC

I_G

NT

3A

F6

PC

I_G

NT

4A

G6




55

44

33

22

11

DD

CC

BB

AA

G1

CR

S

G1

RX

ER

+3

.3V

DG

ND

MG

TX

125

MD

C

G1T

XE

R

G1

CO

L

G1

GT

XC

LK

G1

TX

CL

K

MD

IOD

GN

D

G1

TX

D[7

:4]

G1T

XE

N

+2

.5V

GE

the

r

+1

.5V

GE

the

rW

P2

_G

1_

RE

SE

T_

N

G1

RX

DV

G1

TX

D[7

:0]

G2

TX

D[7

:2]

G1

RX

CL

K

G1

_IR

Q_

N

+3

.3V

G1

RX

D[7

:0]

+2

.5V

GE

the

r

G1

TX

D[7

:4]

G2

TX

D[7

:2]

+3

.3V

+1

.5V

GE

the

r

MD

C

WP

2_

G1

_R

ES

ET

_N G

1G

TX

CL

K

G1

_IR

Q_

NMD

IO

DG

ND

DG

ND

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 2 - G

iga

Byte

Eth

ern

et In

terfa

ce

- To

p0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

40

72

Mo

nd

ay, S

ep

tem

be

r 08

, 20

03

Pa

ge

42

WP

2 - T

SE

C - P

HY

G1

TX

CL

KG

1T

XE

R

MD

IO

+1

.5V

GE

the

r

G1R

XD

V

G1

RX

CL

K

G1

GT

XC

LK

G1

TX

D[7

:0]

MG

TX

12

5

+3

.3V

+2

.5V

GE

the

r

G1T

XE

N

WP

2_

G1

_R

ES

ET

_N

DG

ND

G1C

RS

G1

CO

L

G1

RX

D[7

:0]

MD

C

G1R

XE

R

G1

_IR

Q_

N

Pa

ge

41

WP

2 - T

SE

C

G1

CO

L

G1

RX

D[7

:0]

G2

TX

D[7

:2]

G1R

XD

V

MG

TX

12

5

G1C

RS

G1

TX

CL

K

DG

ND

G1

GT

XC

LK

G1R

XE

R

G1

TX

D[7

:0]

G1T

XE

R

+3

.3V

G1

RX

CL

K

G1T

XE

N



Schematics


55

44

33

22

11

DD

CC

BB

AA

G1

RX

CL

K

G1

RX

D5

G1

TX

D5

G1

RX

DV

G1

RX

D7

G2

TX

D4

G1

TX

D3

G1

RX

D2

G1

TX

D3

MG

TX

125

G1

RX

D6

G1

TX

D0

G1

TX

D6

G1T

XE

N

G1

RX

D4

G1

CO

L

G2

TX

D5

G1

RX

D0

G1

RX

D0

G1

TX

D5

G1

TX

D2

G1

TX

D1

G1

RX

D3

G1

RX

D4

G1

RX

D1

G1

TX

D7

G2

TX

D6

G1

RX

ER

G1

RX

D3

G1

CR

S

G1

TX

D7

G1

TX

D6

G1

RX

D5

G1

RX

D1

G1

TX

D4

G1

TX

D7

G1

RX

D5

G1

TX

D3

G1

RX

D2

G1

RX

D7

G1

TX

D2

G1

RX

D0

G1

TX

D1

DG

ND

G1

TX

D4

G1T

XE

R

G1

TX

D5

+3

.3V

G1

RX

D4

G1

TX

D2

G1

TX

D4

G1

TX

D0

G1

TX

D1

G1

TX

D6

G1

GT

XC

LK

G1

RX

D3

G1

RX

D6

MG

TX

12

5

G1

RX

D1

G1

RX

D[7

:0]

G1

RX

D6

G1

RX

D7

G1

TX

D[7

:0]

G1

TX

D0

G1

TX

CL

K

G1

RX

D2

G2

TX

D7

G1T

XE

R

G1

GT

XC

LK

G1T

XE

N

G1

RX

CL

KG

1C

OL

G1

RX

DV

G1

RX

ER

G1

CR

S

G1

TX

CL

K

G2

TX

D3

G2

TX

D2

G1

RX

ER

G1

RX

DV

G1

RX

D[7

:0]

G1

GT

XC

LK

+3

.3V

G1T

XE

R

G1

TX

D[7

:0]

G1

TX

CL

K

G1T

XE

N

G1

RX

CL

K

G1

CR

S

DG

ND

MG

TX

125

G1

CO

L

G2

TX

D[7

:2]

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rkP

roce

sso

r 2 - G

iga

Byte

Eth

ern

et In

terfa

ce

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

41

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

Power

Decoupling

Decoupling

100pF C879

R600330R R594330R

R5

85

22

0R

CN

16

10

0p

F, C

N

1234

8765

R5

91

22

0R

100pF C886

0.1uFC735

100pF C883

100pF C878

R592330R

RN

16

0

22

0R

, R

N

123456789 1

01

11

21

31

41

51

6

R598330R

R5

97

22

0R

R5

93

22

0R

R3

74

22

R 0

.1W

R602330R

R5

89

22

0R

100pF C884

CN

13

10

0p

F, C

N

1234

8765

RN

16

1

33

0R

, R

N

123456789 1

01

11

2

13

14

15

16

R5

95

22

0R

R590330R

R3

77

22

0R

R3

75

22

R 0

.1W

R6

01

22

0R

TS

EC

1

TS

EC

2

Gb

EC

lock

ing

U7

G

MP

C8

56

0

TS

EC

1_T

XD

0E

8

TS

EC

1_T

XD

1G

8

TS

EC

1_T

XD

2A

7

TS

EC

1_T

XD

3B

7

TS

EC

1_T

XD

4C

7

TS

EC

1_T

XD

5D

7

TS

EC

1_T

XD

6F

7

TS

EC

1_T

XD

7A

6

TS

EC

1_T

X_E

NC

8

TS

EC

1_T

X_E

RB

8

TS

EC

1_

TX

_C

LK

C6

TS

EC

1_

GT

X_

CL

KB

6

TS

EC

1_R

XD

0E

6

TS

EC

1_R

XD

1F

6

TS

EC

1_R

XD

2A

5

TS

EC

1_R

XD

3B

5

TS

EC

1_R

XD

4D

5

TS

EC

1_R

XD

5D

3

TS

EC

1_R

XD

6B

4

TS

EC

1_R

XD

7D

4

TS

EC

1_R

X_D

VD

2

TS

EC

1_R

X_E

RE

5

TS

EC

1_

RX

_C

LK

D6

TS

EC

1_C

RS

C3

TS

EC

1_

CO

LG

7

TS

EC

2_T

XD

0E

11

TS

EC

2_T

XD

1G

11

TS

EC

2_T

XD

2H

11

TS

EC

2_T

XD

3J1

1

TS

EC

2_T

XD

4K

11

TS

EC

2_T

XD

5J1

0

TS

EC

2_T

XD

6A

10

TS

EC

2_T

XD

7B

10

TS

EC

2_T

X_E

NB

11

TS

EC

2_T

X_E

RD

11

TS

EC

2_

TX

_C

LK

D1

0

TS

EC

2_

GT

X_

CL

KC

10

TS

EC

2_R

XD

0F

10

TS

EC

2_R

XD

1G

10

TS

EC

2_R

XD

2H

9

TS

EC

2_R

XD

3A

9

TS

EC

2_R

XD

4B

9

TS

EC

2_R

XD

5C

9

TS

EC

2_R

XD

6E

9

TS

EC

2_R

XD

7F

9

TS

EC

2_R

X_D

VH

8

TS

EC

2_R

X_E

RA

8

TS

EC

2_

RX

_C

LK

E1

0

TS

EC

2_C

RS

D9

TS

EC

2_

CO

LF

8

EC

_G

TX

_C

LK

12

5E

2

LV

dd

1A

4

LV

dd

2C

5

LV

dd

3E

7

LV

dd

4H

10

0.1uFC737

100pF C881

100pF C882

0.1uFC734

+

C1086

10uF,6.3V Tants

100pF C880

R5

87

22

0R

100pF C428

CN

15

10

0p

F, C

N

1234

8765

R3

76

22

R 0

.1W

100pF C885

0.1uFC736

R596330R

RN

15

82

2R

, RN

123456789 1

01

11

21

31

41

51

6

RN

16

2

33

0R

, R

N

123456789 1

01

11

2

13

14

15

16

R588330R

RN

15

9

22

0R

, R

N

123456789 1

01

11

21

31

41

51

6

R586330R

R378330R

R5

99

22

0R

CN

14

10

0p

F, C

N

1234

8765



Figure A-40. GigaByte Ethernet Interface—PHY

55

44

33

22

11

DD

CC

BB

AA

G1

TX

D1

G1

RX

D6

MG

TX

125

G1

RX

CL

K

G1

_IR

Q_

N

G1

RX

D3

G1

CR

S

G1

TX

D5

G1

RX

D1

+3

.3V

G1

TX

D4

+1

.5V

GE

the

r

G1

TX

D3

G1

RX

D2

G1

TX

CL

K

DG

ND

G1

TX

D2

G1

TX

D7

G1

RX

D7

G1

GT

XC

LK

G1

RX

ER

G1

RX

DV

G1

TX

D6

G1

RX

D5

G1AVDDH

G1T

XE

N

+2

.5V

GE

the

r

G1

RX

D0

G1

TX

D0

G1

CO

L

G1

RX

D4

WP

2_

G1

_R

ES

ET

_N

G1T

XE

R

WP

2_

PH

1_

P0

WP

2_

PH

1_

M0

WP

2_

PH

1_

P1

WP

2_

PH

1_

M1

WP

2_

PH

1_

P2

WP

2_

PH

1_

M2

WP

2_

PH

1_

P3

WP

2_

PH

1_

M3

MD

CM

DIO

G1

CO

L

MG

TX

125

G1T

XE

N

G1

RX

DV

G1

TX

CL

K

+3

.3V

MD

IO

G1

GT

XC

LK

G1

RX

ER

MD

C

DG

ND

G1

RX

CL

K

G1

RX

D[7

:0]

G1

_IR

Q_

N

WP

2_

G1

_R

ES

ET

_N

+2

.5V

GE

the

r

G1

CR

S

G1

TX

D[7

:0]

G1T

XE

R

+1

.5V

GE

the

r

+3

.3V

+1

.5V

GE

the

r

+3

.3V

+3

.3V

+2

.5V

GE

the

r

+2

.5V

GE

the

r

+1

.5V

GE

the

r

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roc

es

so

r 2 - G

iga

Byte

Eth

ern

et In

terfa

ce

- PH

Y0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

42

72

Tu

esd

ay, S

ep

tem

be

r 30

, 20

03

GR

OU

ND

Se

pa

rate

Power

must be 50

mill trace

1.5

V3

.3V

2.5

V



LED on => Link Up




LED on => Link Up



Pin


Pin


CONFIG0 0 0

0

CONFIG1 0 0

0

CONFIG2 1 1

0

CONFIG3 0 0

0

CONFIG4 1 1

1

CONFIG5 1 1

1

CONFIG6 0 0

0








VDD0 1 1 1

LED_LINK10 1 1 0

LED_LINK100 1 0 1

LED_LINK1000 1 0 0

LED_DUPLEX 0 1 1

LED_RX 0 1 0

LED_TX 0 0 1

VSS 0 0 0

Pin Bit[2:0]

Pin Setting

CONFIG0 VSS

CONFIG1 VSS

CONFIG2 LED_LINK10

CONFIG3 VSS

CONFIG4 VDDO

CONFIG5 VDDO

CONFIG6 VSS

LD26

LED_YELLOW

2 1

R4

12

22

R 0

.1W

0.01uF C485

0.1uF C481

R13440R

49

R9

R4

08

0.01uF C468

49R9R407

0.01uF C487

0.1uF C480

49

R9

R4

15

0.01uF C466

R13450R

R4

13

22

R 0

.1W

33

0R

R4

28

0.01uF C475

0.01uF C478

33

0R

R4

32

0.0

1u

F

C495

10

K

R4

24

0.0

1u

F

C493

0.01uF C467

TP145

L2

03

PIN

_F

ER

RIT

E13

2

0.01uF C477

0.1uF C492

R13460R

0.01uF C465

R4

17

22

R 0

.1W

LD28

LED_YELLOW

2 1

0.01uF C474

R13470R

R4

23

0R

0.1uF C473

0.1uF C489

0.1uF C469

0.1uF C472

49

R9

R4

14

0.1uF C479

Y1

02

5M

Hz

14

23

0.1uF C482

0.1uF C483

R4

19

22

R 0

.1W

TP146

C4

97

18

pF

R1

34

81

K

C4

98

18

pF

4K

7R

42

6

0.1uF C488

TP147

49

R9

R4

10

33

0R

R4

29

49

R9

R4

21

LD30

LED_YELLOW

2 1

0.1uF C471

R1

34

91

K4

9R

9

R4

09

0.01uF C484

R4

20

22

R 0

.1W

R13410R

33

0R

R4

30

0.1uF C491

0.0

1u

F

C494

1:1

1:1

1:1

1:1

1:1

P5

D

RJG

5-7

G0

5

9D

10

D

7D

8D

5D

6D

2D

3D

4D

1D

D1

DD

2D

D3

DD

4D

R4252K49

TP148

0.01uF C476

49

R9

R4

18

RN

16

42

2R

, RN

123456789 1

01

11

21

31

41

51

6

R13420R

49R9R406

R4

11

22

R 0

.1W

0.1uF C470

0.1uF C490

R4

22

22

R 0

.1W

0.01uF C486

U6

1

88

E1

01

1S

RX

D_2

A8

RX

D_1

B7

RX

D_0

A7

RX

_D

VA

6

RX

_C

LK

B6

VDDOC6

TX

_C

LK

B4

CO

LA

5

RX

_E

RB

5

VDDOC5

DGNDD5

DGNDD4

DGNDC4

CR

SA

4

SC

LK

_M

C3

GT

X_

CL

KB

3

TX

_E

RA

3

TX

D_

0B

2

TX

_E

NA

2

CO

MA

A1

AVDDLB1

SIN

_M

C1

SO

UT

_M

C2

SIN

_P

D1

SO

UT

_P

D2

TX

D_

6H

1

SC

LK

_P

D3

TX

D_

1E

1

CTRL_15E2

DGNDG4

DVDDLE3

DGNDE4

TX

D_

2F

1

TX

D_

3F

2

TX

D_

4G

1

DVDDHF3

DGNDF4

TX

D_

5G

2

DVDDHG3

DGNDG5

TX

D_

7H

2

DVDDLH3

DGNDH4

DGNDH5

XT

AL

2J1

XT

AL

1J2

VDDOJ3

DGNDJ4

TCKK1

RE

SE

TK

2

VS

SC

K3

DGNDK4

AVDDLL2

TMSL1

DGNDL3

TRSTM1

RSETM2

MD

I0_

PN

1

MD

I0_M

N2

AVDDLM3

MD

I1_

PN

3

DGNDL4

CTRL25M4

MD

I1_M

N4

DGNDJ5

DGNDK5

DGNDL5

HDAC_PM5

AVDDHN5

DGNDL6

HDAC_NM6

DGNDK6

MD

I2_

PN

6

MD

I2_M

N7

DGNDL7

AVDDLM7

MD

I3_

PN

8

AVDDLM8

MD

I3_M

N9

TDIM9

TDOL8

CONFIG_4L9

CONFIG_3K9

CONFIG_2K8

CONFIG_6K7

CONFIG_1J9

CONFIG_5J7

CONFIG_0J8

DGNDJ6

VDDOH7

LED_TXH9

DGNDH6

LED_RXH8

DVDDLG7

DGNDG6

LED_DPLXG9

LED_LINK1000G8

SE

L_

2_

5V

F7

LED_LINK100F9

DGNDF6

LED_LINK10F8

DGNDF5

DGNDE6

MD

CE

8

DGNDE5

VDDOE7

INT

E9

MD

IOD

9

CL

K1

25

D8

DVDDLD7

DGNDD6

DGNDC7

RX

D_6

C8

RX

D_7

C9

RX

D_3

B8

RX

D_5

B9

RX

D_4

A9

LD31

LED_RED

2 1

R130110K

0.0

1u

F

C496

R13430R

0.01uF C464

49

R9

R4

16



Schematics


55

44

33

22

11

DD

CC

BB

AA

WP

2_

RX

DW

P2

_T

XD

WP

2_

TX

DW

P2

_R

XD

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 2 - C

om

mu

nic

atio

ns P

roce

sso

r Mo

du

le0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

43

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

CP

M

Alt. DUART

A lt. DUART

Alt. 10/100 Eth.

Alt. 10/100 Eth.

U7

H

MP

C8

56

0

PA

0H

1

PA

1H

2

PA

2J1

PA

3J2

PA

4J3

PA

5J4

PA

6J5

PA

7J6

PA

8J7

PA

9J8

PA

10

K8

PA

11

K7

PA

12

K6

PA

13

K3

PA

14

K2

PA

15

K1

PA

16

L1

PA

17

L2

PA

18

L3

PA

19

L4

PA

20

L5

PA

21

L8

PA

22

L9

PA

23

L1

0

PA

24

L1

1

PA

25

M1

0

PA

26

M9

PA

27

M8

PA

28

M7

PA

29

M6

PA

30

M3

PA

31

M2

PB

4/F

EC

_T

XD

3M

1

PB

5/F

EC

_T

XD

2N

1

PB

6/F

EC

_T

XD

1N

4

PB

7/F

EC

_T

XD

0N

5

PB

8/F

EC

_R

XD

0N

6

PB

9/F

EC

_R

XD

1N

7

PB

10/F

EC

_R

XD

2N

8

PB

11/F

EC

_R

XD

3N

9

PB

12/F

EC

_C

RS

N1

0

PB

13/F

EC

_C

OL

N1

1

PB

14/F

EC

_T

X_E

NP

11

PB

15/F

EC

_T

X_E

RP

10

PB

16/F

EC

_R

X_E

RP

9

PB

17/F

EC

_R

X_D

VP

8

PB

18

P7

PB

19

P6

PB

20

P5

PB

21

P4

PB

22

P3

PB

23

P2

PB

24

P1

PB

25

R1

PB

26

R2

PB

27

R3

PB

28

R4

PB

29

R5

PB

30

R6

PB

31

R7

PC

0R

8

PC

1R

9

PC

2R

10

PC

3R

11

PC

4T

9

PC

5T

6

PC

6T

5

PC

7T

4

PC

8T

1

PC

9U

1

PC

10

U2

PC

11

U3

PC

12

U4

PC

13/U

AR

T_C

TS

1U

7

PC

14

U8

PC

15/U

AR

T_C

TS

0U

9

PC

16

U1

0

PC

17/F

EC

_R

X_C

LK

V9

PC

18

/FE

C_

TX

_C

LK

V6

PC

19

V5

PC

20

V4

PC

21

V3

PC

22

V2

PC

23

V1

PC

24

W1

PC

25

W2

PC

26

W3

PC

27

W6

PC

28

W7

PC

29

W8

PC

30

W9

PC

31

Y9

PD

4Y

1

PD

5Y

2

PD

6Y

3

PD

7Y

4

PD

8Y

5

PD

9Y

6

PD

10

AA

8

PD

11

AA

7

PD

12

AA

4

PD

13

AA

3

PD

14

AA

2

PD

15

AA

1

PD

16

AB

1

PD

17

AB

2

PD

18

AB

3

PD

19

AB

5

PD

20

AB

6

PD

21

AC

7

PD

22

AC

4

PD

23

AC

3

PD

24

AC

2

PD

25

AC

1

PD

26/U

AR

T_R

TS

1A

D1

PD

27/U

AR

T_S

OU

T1

AD

2

PD

28/U

AR

T_S

IN1

AD

5

PD

29/U

AR

T_R

TS

0A

D6

PD

30/U

AR

T_S

OU

T0

AE

3

PD

31/U

AR

T_S

IN0

AE

2




55

44

33

22

11

DD

CC

BB

AA

MD

CM

DIO

G1

_IR

Q_

N

IRQ

7_

N

MC

P_

N

TD

O

TR

IG_

OU

T

WP

2_

HR

ES

ET

_R

EQ

_N

WP

2_

CO

P_

HR

ES

ET

_N

TD

I

WP

2_

CO

P_

HR

ES

ET

_N

WP

1_

INT

_N

WP

2_

HR

ES

ET

_N

WP

2_

SY

S_

CL

K

CH

KS

TO

P_

IN_

N

WP

2_

CO

P_

SR

ES

ET

_N

IRQ

6_

N

WP

2_

CO

P_

SR

ES

ET

_N

TD

IT

CK

+3

.3V

IRQ

9_

N

TM

S

CL

K_

OU

T

WP

2_

TR

ST

_N

TC

K

IRQ

0_

N

WP

2_

CO

P_

TR

ST

_N

WP

2_

TR

ST

_N

WP

2_

SR

ES

ET

_N

BP

_IN

T_

N

CH

KS

TO

P_

IN_

N

DG

ND

AS

LE

EP

WP

2_

RT

C_

CL

K

TM

S

MS

RC

ID0

CH

KS

TO

P_

OU

T_

N

IRQ

11

_NTD

O

UD

E_

N

IRQ

10

_N

CH

KS

TO

P_

OU

T_

N

WP

2_

CO

P_

TR

ST

_N

WP

2_

SR

ES

ET

_N

WP

2_

HR

ES

ET

_R

EQ

_N

WP

2_

HR

ES

ET

_N

IRQ

5_

N

IRQ

8_

N

MD

VA

L

MS

RC

ID1

MS

RC

ID2

MS

RC

ID4

MS

RC

ID3

I2C

_S

DA

I2C

_S

CL

TH

ER

M0

TH

ER

M1

WP

2_

INT

_N

WP

3_

INT

_N

MD

IOM

DC

G1

_IR

Q_

N

I2C

_S

CL

WP

2_

HR

ES

ET

_N

WP

2_

TR

ST

_N

WP

2_

SR

ES

ET

_N

WP

2_

SY

S_

CL

K

WP

2_

CO

P_

HR

ES

ET

_N

WP

2_

CO

P_

TR

ST

_N

DG

ND

WP

2_

CO

P_

SR

ES

ET

_N

MS

RC

ID0

WP

2_

RT

C_

CL

KI2C

_S

DA

+3

.3V

WP

2_

HR

ES

ET

_R

EQ

_N

WP

3_

INT

_N

BP

_IN

T_

N

WP

2_

INT

_N

WP

1_

INT

_N

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 2 - A

uxila

ry F

un

ctio

ns

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

44

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

Power

TP

91

R2

42

4K

7

R2

38

10

K

TP

98

KEY

KEY

HD

12

2x8

He

ad

er

15

16

12

34

56

78

91

01

11

21

31

4

R2

37

10

K

R7

07

10

K

R2

35

10

K

AU

XIL

IAR

Y F

UN

CT

ION

PIC

DMA

Eth.MI

AN

AL

OG

JT

AG

DEBUG

SP

AR

ES

CL

OC

KIN

G

DFT

I2C

SY

S. C

NT

RL

PW

R M

ng

.

U7

D

MP

C8

56

0

MC

PA

G1

7

UD

EA

G1

6

IRQ

0A

A1

8

IRQ

1Y

18

IRQ

2A

B1

8

IRQ

3A

G2

4

IRQ

4A

A2

1

IRQ

5Y

19

IRQ

6A

A1

9

IRQ

7A

G2

5

IRQ

8A

B2

0

IRQ

9/D

MA

_D

RE

Q3

Y2

0

IRQ

10/D

MA

_D

AC

K3

AF

26

IRQ

11/D

MA

_D

DO

NE

3A

H2

4

IRQ

_O

UT

AB

21

DM

A_D

RE

Q0

H5

DM

A_D

RE

Q1

G4

DM

A_D

AC

K0

H6

DM

A_D

AC

K1

G5

DM

A_D

DO

NE

0H

7

DM

A_D

DO

NE

1G

6

EC

_M

DC

F1

EC

_M

DIO

E1

L1

_T

ST

CL

KA

B2

2

CLK

_O

UT

AF

22

TH

ER

M0

AG

2

TH

ER

M1

AH

3

L2

_T

ST

CL

KA

G2

2

TD

OA

F1

9

TM

SA

F2

3

TD

IA

G2

1

TC

KA

F2

1

TR

ST

AG

23

TR

IG_IN

N1

2

TR

IG_O

UT

/RE

AD

Y/Q

UIE

SC

EG

2

MS

RC

ID0

J9

MS

RC

ID1

G3

MS

RC

ID2

F3

MS

RC

ID3

F5

MS

RC

ID4

F2

MD

VA

LF

4

SP

AR

E1

T1

1

SP

AR

E2

U1

1

SP

AR

E3

AF

1

SP

AR

E4

C1

RT

CA

B2

3

SY

SC

LK

AH

21

LS

SD

_M

OD

EA

G1

9

TE

ST

_S

EL

(Dra

co

/Dra

co

m)

AH

20

AS

LE

EP

AG

18

IIC_S

CL

AH

23

IIC_S

DA

AH

22

CK

ST

P_IN

M1

1

CK

ST

P_O

UT

G1

SR

ES

ET

AF

20

HR

ES

ET

_R

EQ

AG

20

HR

ES

ET

AH

16

NC

2A

H1

NC

3A

G1

NC

4A

H2

NC

5B

1

NC

6B

2

NC

7A

2

NC

8A

3

NC

9A

H2

5

NC

10

AH

26

NC

11

AH

27

NC

12

AH

28

NC

13

AG

28

NC

14

AF

28

NC

15

AE

28

TP

90

RN

14

8

10

K, R

N

10

12346789

5

TP

93

TP

17

0T

P1

71

R6

37

0R

TP

17

2

R2

34

10

KR

23

92

K

TP

16

9T

P1

68

TP

92

RN

14

71

0K

, RN

10

12346789

5

R2

36

10

K

R6

29

4K

7

R2

40

10

KR

63

80

R

JP

37

12

R2

41

4K

7

R2

43

4K

7R

24

44

K7

R2

33

4K

7

TP

94

R6

30

4K

7



Schematics


55

44

33

22

11

DD

CC

BB

AA

+3

.3V

G2

TX

D6

G1

TX

D7

G1

TX

D6

G1

TX

D5

G2

TX

D4

G2

TX

D7

G1

TX

D4

G2

TX

D5

G2

TX

D4

G2

TX

D3

G2

TX

D2

G2

TX

D6

G2

TX

D7

G2

TX

D5

G2

TX

D2

LC

S_

N2

LC

S_

N1

G2

TX

D3

LC

S_

N0

BL

A3

1

MS

RC

ID0

LG

PL

0

BL

A2

7

LA

LE

LW

E_

N2

BL

A2

7

G1

GT

XC

LK

LG

PL

1

LG

PL

2

BL

A3

0B

LA

29

LW

E_

N3

DG

ND

BL

A2

8

DG

ND

+3

.3V

LG

PL

1

G1

TX

D[7

:4]

LG

PL

0

BL

A[2

7:3

1]

LA

LE

G2

TX

D[7

:4]

MS

RC

ID0

WP

2_

RS

T_

CO

NF

_N

LG

PL

2

LW

E_

N[2

:3]

G1

GT

XC

LK

G2

TX

D[7

:2]

LC

S_

N[0

:2]

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 2 - C

on

figu

ratio

n0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

45

72

Mo

nd

ay, S

ep

tem

be

r 08

, 20

03

Power

Pro

cesso

r

"R

OM

Lo

c.1

"

"D

ev

ice ID

4"

"D

ev

ice ID

3"

"D

ev

ice ID

0"

"R

IO C

lk 1

"

"R

OM

Lo

c.2

"

"H

ost/A

gen

t 0"

"D

ev

ice ID

7"

"D

eb

ug

En

ab

le"

"C

PU

Bo

ot"

"R

OM

Lo

c.0

"

"H

ost/A

gen

t 1"

"S

ys P

LL

0"

"S

ys P

LL

3"

"CONFIGURATION"

RIO

"D

ev

ice ID

2"

"D

ev

ice ID

6"

"S

ys P

LL

1"

"C

ore P

LL

1"

"S

ys P

LL

2"

Mem

ory

RIO

"D

ev

ice ID

5"

"C

ore P

LL

0"

"D

ev

ice ID

1"

"R

IO C

lk 0

"

PC

I/RIO

Pro

cesso

r

"T

SE

C1

Mo

de"

TS

EC

Decoupling


For Rev 2 silicon;

Remove R751,R752,R753,R754,R755

Add R749,R750

Do Not Fit

R7

54

0R

0.1uFC664

R7

55

0R

SW

9

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

SW

10

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

RN

68

10

K, R

N

10

12346789

5

R7

52

0R

RN

11

01

0K

, RN

10

12346789

5

0.1uFC663

R7

51

0R

R7

50

0R

R7

53

0R

RN

10

91

0K

, RN

10

12346789

5

R7

49

0R

U3

1

74

AL

VT

16

24

4

1A

14

7

1A

24

6

1A

34

4

1A

44

3

2A

14

1

2A

24

0

2A

33

8

2A

43

7

OE

11

OE

24

8

3A

13

6

3A

23

5

3A

33

3

3A

43

2

4A

13

0

4A

22

9

4A

32

7

4A

42

6

OE

42

4

1Y

12

1Y

23

1Y

35

1Y

46

2Y

18

2Y

29

2Y

31

1

2Y

41

2

3Y

11

3

3Y

21

4

3Y

31

6

3Y

41

7

4Y

11

9

4Y

22

0

4Y

32

2

4Y

42

3

3V37

3V318

3V331

3V342

DGND4

DGND10

DGND15

DGND21

DGND28

DGND34

DGND39

DGND45

OE

32

5

74

LV

CH

24

4

U3

2

2Y

43

2Y

35

2Y

27

2Y

19

1Y

41

21Y

31

41Y

21

61Y

11

8

2A

41

72A

31

52A

21

32A

11

1

1A

48

1A

36

1A

24

1A

12

VC

C 20

2O

E1

9

GN

D

10

1O

E1

SW

11

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9




55

44

33

22

11

DD

CC

BB

AA

Vd

d

+3

.3V

DG

ND

+1

2V

DG

ND

+3

.3V

Vd

d

+1

2V

Vd

d

Vd

d

+3

.3V

Vd

d

Vd

d

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Vd

d+

3.3

VV

dd

Vd

d

+3

.3V

+3

.3V

Vd

dV

dd

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Vd

d

+3

.3V

Vd

dV

dd

+3

.3V

Vd

d

+1

2V

+3

.3V

Vd

d

+3

.3V

+3

.3V

Vd

d

+1

2V

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 2 - P

ow

er

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

46

72

We

dn

esd

ay, O

cto

be

r 01

, 20

03

Decoupling

Decoupling

Header for

12V fan

Power

Decoupling


Bulk Decoupling

0.1uFC704

0.1uFC725

10

R R2

64

L3

2

Fe

rrite B

ea

d1

2

S5

DO

57

0.1uFC719

C1141

220uF, Tants

12

0.1uFC717

0.1uFC721

+

C1081

10uF,6.3V Tants

HD

20

12

10uF, 6.3V

C958

S6

DO

57

0.1uFC1131

0.1uFC729

0.1uFC710

0.1uFC720

TP

18

0

2.2uF

C305

0.1uFC706

0.1uFC1137

C1138

220uF, Tants

12

0.1uFC1133

0.1uFC731

0.1uFC1257

0.1uFC723

0.1uFC705

0.1uFC716

HS

7

10

-TH

MA

-01

0.1uFC712

C1139

220uF, Tants

12

0.1uFC709

CO

RE

&P

LL

Su

pp

ly

U7

E

MP

C8

56

0

VD

D1

U1

2

VD

D2

R1

2

VD

D3

T1

3

VD

D4

P1

3

VD

D5

M1

3

VD

D6

U1

4

VD

D7

R1

4

VD

D8

N1

4

VD

D9

T1

5

VD

D10

P1

5

VD

D11

M1

5

VD

D12

R1

6

VD

D13

N1

6

VD

D14

T1

7

VD

D15

P1

7

VD

D16

M1

7

AV

dd

1A

H19

AV

dd

2A

H18

AV

dd

3A

H17

SE

NS

E_V

DD

L1

2

SE

NS

E_V

SS

K1

2

0.1uFC1136

0.1uFC718

0.1uFC714

0.1uFC1132

0.1uFC711

10uF, 6.3VC959

TP

18

1

2.2uF

C306

2.2uF

C308

0.1uFC1130

0.1uFC722

0.1uFC726

0.1uFC728

0.1uFC703

0.1uFC724

2.2uF

C304

+

C1082

10uF,6.3V Tants

0.1uFC727

0.1uFC708

10

R R2

65

0.1uFC1135

10

R R2

66

0.1uFC1256

0.1uFC1258

0.1uFC713

0.1uFC730

PO

WE

R

U7

I

MP

C8

56

0

OV

dd

1A

E1

OV

dd

2D

1

OV

dd

3T

2

OV

dd

4N

3

OV

dd

5H

3

OV

dd

6A

H4

OV

dd

7A

D4

OV

dd

8W

4

OV

dd

9K

4

OV

dd

10

E4

OV

dd

11

AC

5

OV

dd

12

AA

5

OV

dd

13

U5

OV

dd

14

M5

OV

dd

15

AF

7

OV

dd

16

AB

7

OV

dd

17

Y7

OV

dd

18

T7

OV

dd

19

L7

OV

dd

20

AE

8

OV

dd

21

V8

OV

dd

22

AB

9

OV

dd

23

AE

10

OV

dd

24

K1

0

OV

dd

25

AC

11

OV

dd

26

AF

12

OV

dd

27

AA

12

OV

dd

28

W1

3

OV

dd

29

AE

15

OV

dd

30

AA

16

OV

dd

31

AC

17

OV

dd

32

W1

9

OV

dd

33

R1

9

OV

dd

34

AA

20

OV

dd

35

U2

0

OV

dd

36

W2

1

OV

dd

37

P2

2

OV

dd

38

Y2

3

OV

dd

39

R2

5

OV

dd

40

AB

26

OV

dd

41

U2

6

OV

dd

42

AG

27

GN

D1

AF

2

GN

D2

N2

GN

D3

C2

GN

D4

AG

3

GN

D5

AD

3

GN

D6

T3

GN

D7

E3

GN

D8

B3

GN

D9

AF

4

GN

D1

0A

B4

GN

D1

1M

4

GN

D1

2H

4

GN

D1

3C

4

GN

D1

4W

5

GN

D1

5K

5

GN

D1

6A

C6

GN

D1

7A

A6

GN

D1

8U

6

GN

D1

9L

6

GN

D2

0A

G7

GN

D2

1V

7

GN

D2

2A

D8

GN

D2

3Y

8

GN

D2

4T

8

GN

D2

5D

8

GN

D2

6A

C9

GN

D2

7K

9

GN

D2

8G

9

GN

D2

9A

F1

0

GN

D3

0V

10

GN

D3

1T

10

GN

D3

2A

B1

1

GN

D3

3F

11

GN

D3

4C

11

GN

D3

5T

12

GN

D3

6P

12

GN

D3

7M

12

GN

D3

8H

12

GN

D3

9G

12

GN

D4

0E

12

GN

D4

1A

12

GN

D4

2A

F1

3

GN

D4

3A

A1

3

GN

D4

4U

13

GN

D4

5R

13

GN

D4

6N

13

GN

D4

7T

14

GN

D4

8P

14

GN

D4

9M

14

GN

D5

0H

14

GN

D5

1B

14

GN

D5

2A

F1

5

GN

D5

3U

15

GN

D5

4R

15

GN

D5

5N

15

GN

D5

6Y

16

GN

D5

7U

16

GN

D5

8T

16

GN

D5

9P

16

GN

D6

0M

16

GN

D6

1A

D17

GN

D6

2U

17

GN

D6

3R

17

GN

D6

4N

17

GN

D6

5H

17

GN

D6

6C

17

GN

D6

7A

17

GN

D6

8W

18

GN

D6

9K

18

GN

D7

0F

18

GN

D7

1A

B1

9

GN

D7

2J1

9

GN

D7

3C

19

GN

D7

4R

20

GN

D7

5L

20

GN

D7

6H

20

GN

D7

7B

20

GN

D7

8U

21

GN

D7

9M

22

GN

D8

0H

22

GN

D8

1C

22

GN

D8

2W

23

GN

D8

3P

23

GN

D8

4K

23

GN

D8

5F

23

GN

D8

6J2

4

GN

D8

7E

24

GN

D8

8L

25

GN

D8

9G

25

GN

D9

0A

G2

6

GN

D9

1V

26

GN

D9

2R

26

GN

D9

3B

26

GN

D9

4A

F2

7

GN

D9

5M

27

GN

D9

6H

27

GN

D9

7C

27

GN

D9

8B

27

GN

D9

9K

28

0.1uFC707

0.1uFC1134

C1140

220uF, Tants

12

2.2uF

C307

2.2uF

C309

0.1uFC715



Schematics


55

44

33

22

11

DD

CC

BB

AA

G1

TX

D[7

:4]

+2

.5V

LG

PL

1

LG

PL

1

LW

E_

N[2

:3]

G2

TX

D[7

:2]

WP

3_

RS

T_

CO

NF

_N

LW

E_

N[2

:3]

DG

ND

+3

.3V

LG

PL

2G

1G

TX

CL

K

+3

.3V

LA

LE

LG

PL

0

BL

A[2

7:3

1]

LC

S_

N[0

:2]

DG

ND

LG

PL

0

BL

A[2

7:3

1]

LA

LE

LG

PL

2

MS

RC

ID0

LC

S_

N[0

:2]

DG

ND

+2

.5V

GE

the

r

+3

.3V

+1

.5V

GE

the

r

G1

GT

XC

LK

G2

TX

D[7

:2]

G1

TX

D[7

:4]

WP

3_

CO

P_

HR

ES

ET

_N

WP

3_

RT

C_

CL

K

WP

3_

CO

P_

SR

ES

ET

_N

WP

3_

CO

P_

TR

ST

_N

+3

.3V

WP

3_

HR

ES

ET

_R

EQ

_N

WP

3_

SR

ES

ET

_N

WP

3_

SY

S_

CL

K

DG

ND

WP

1_

TR

ST

_N

WP

3_

HR

ES

ET

_N

MS

RC

ID0

RIO

3_

TX

CL

K_

INR

IO3

_T

XC

LK

_IN

_N

RIO

3_

RF

RA

ME

RIO

3_

TC

LK

RIO

3_

TC

LK

_N

RIO

3_

TF

RA

ME

_N

RIO

3_

TD

_N

[0:7

]

RIO

3_

RD

[0:7

]

RIO

3_

TD

[0:7

]

RIO

3_

TF

RA

ME

RIO

3_

RD

_N

[0:7

]

RIO

3_

RC

LK

RIO

3_

RC

LK

_N

RIO

3_

RF

RA

ME

_N

WP

3_

RX

DW

P3

_T

XD

DG

ND

Vd

d

+3

.3V

+1

2V

WP

1_

INT

_N

WP

3_

INT

_N

WP

2_

INT

_N

BP

_IN

T_

N

I2C

_S

DA

I2C

_S

CL

MD

IO

MD

C

G1

_IR

Q_

N

CG

ND

WP

3_

G1

_R

ES

ET

_N

DG

ND

+2

.5V

+1

.5V

GE

the

r

DG

ND

DG

ND

+2

.5V

GE

the

r

WP

3_

RS

T_

CO

NF

_N

+3

.3V

+3

.3V

+3

.3V

WP

3_

CO

P_

SR

ES

ET

_N

WP

3_

SR

ES

ET

_N

WP

3_

CO

P_

HR

ES

ET

_N

WP

3_

TR

ST

_N

WP

3_

SY

S_

CL

K

WP

3_

HR

ES

ET

_R

EQ

_N

WP

3_

RT

C_

CL

K

WP

3_

CO

P_

TR

ST

_N

WP

3_

HR

ES

ET

_N

DG

ND

+3

.3V

RIO

3_

TX

CL

K_

INR

IO3

_T

XC

LK

_IN

_N

RIO

3_

RF

RA

ME

_N

RIO

3_

RC

LK

_N

RIO

3_

TC

LK

RIO

3_

RC

LK

RIO

3_

TF

RA

ME

RIO

3_

TD

[0:7

]

RIO

3_

TF

RA

ME

_N

RIO

3_

RF

RA

ME

RIO

3_

TD

_N

[0:7

]

RIO

3_

RD

_N

[0:7

]

RIO

3_

RD

[0:7

]

RIO

3_

TC

LK

_N

WP

3_

RX

DW

P3

_T

XD

Vd

d

DG

ND

+3

.3V

+1

2V

WP

1_

INT

_N

WP

2_

INT

_N

BP

_IN

T_

NW

P3

_IN

T_

N

CG

ND

WP

3_

G1

_R

ES

ET

_N

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 3 - T

op

Le

ve

l0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

47

72

Mo

nd

ay, S

ep

tem

be

r 08

, 20

03

Pa

ge

50

WP

3 - R

IO

RIO

3_T

XC

LK

_IN

RIO

3_

TX

CL

K_

IN_

N

RIO

3_

TC

LK

RIO

3_

TC

LK

_N

RIO

3_

TF

RA

ME

_N

RIO

3_T

FR

AM

E

RIO

3_

TD

[0:7

]

RIO

3_

TD

_N

[0:7

]

RIO

3_

RC

LK

RIO

3_

RC

LK

_N

RIO

3_R

FR

AM

ER

IO3_R

FR

AM

E_N

RIO

3_R

D_N

[0:7

]

RIO

3_R

D[0

:7]

Pa

ge

48

WP

3 - L

oca

l Bu

s

LA

LE

LC

S_

N[0

:2]

LG

PL

2

LG

PL

0

LW

E_

N[2

:3]

LG

PL

1

BL

A[2

7:3

1]

Pa

ge

55

WP

3 - C

PM

WP

3_R

XD

WP

3_T

XD

Pa

ge

47

WP

3 - T

SE

C - T

op

DG

ND

G1

TX

D[7

:4]

G2

TX

D[7

:2]

MD

C

MD

IO

WP

3_

G1

_R

ES

ET

_N

+2

.5V

GE

the

r

G1

GT

XC

LK

+1

.5V

GE

the

r

+3

.3V

G1

_IR

Q_

N

CG

ND

Pa

ge

57

WP

3 - C

on

fig

DG

ND

+3

.3V

LG

PL

1

G1

TX

D[7

:4]

LG

PL

0

BL

A[2

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Schematics


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24

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52

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64

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123456789 1

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123456789 1

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RIO

3_

RD

_N

0

RIO

3_

TD

2

RIO

3_

RD

_N

2

RIO

3_

TD

7

RIO

3_

RD

0

RIO

3_

TD

4

RIO

3_

TD

_N

3

RIO

3_

RF

RA

ME

RIO

3_

TD

_N

[0:7

]

RIO

3_

TX

CL

K_

IN

RIO

3_

TC

LK

RIO

3_

RF

RA

ME

_N

RIO

3_

RD

_N

[0:7

]

RIO

3_

RF

RA

ME

RIO

3_

RC

LK

RIO

3_

TD

[0:7

]

RIO

3_

TC

LK

_N

RIO

3_

TX

CL

K_

IN_

N

RIO

3_

TF

RA

ME

_N

RIO

3_

RD

[0:7

]

RIO

3_

TF

RA

ME

RIO

3_

RC

LK

_N

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 3 - R

ap

idIO

Inte

rface

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

50

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

U6

C

MP

C8

56

0

RIO

_T

CL

KA

C20

RIO

_T

CLK

-A

E2

1

RIO

_T

FR

AM

E-

AE

25

RIO

_T

FR

AM

EA

E2

4

RIO

_T

D0

AE

18

RIO

_T

D1

AC

18

RIO

_T

D2

AD

19

RIO

_T

D3

AE

20

RIO

_T

D4

AD

21

RIO

_T

D5

AE

22

RIO

_T

D6

AC

22

RIO

_T

D7

AD

23

RIO

_T

D0

-A

D1

8

RIO

_T

D1

-A

E1

9

RIO

_T

D2

-A

C1

9

RIO

_T

D3

-A

D2

0

RIO

_T

D4

-A

C2

1

RIO

_T

D5

-A

D2

2

RIO

_T

D6

-A

E2

3

RIO

_T

D7

-A

C2

3

RIO

_R

CL

KY

25

RIO

_R

CLK

-Y

24

RIO

_R

FR

AM

EA

E2

7

RIO

_R

FR

AM

E-

AE

26

RIO

_R

D0

T2

5

RIO

_R

D1

U2

5R

IO_R

D0-

T2

4

RIO

_R

D2

V2

5

RIO

_R

D3

W2

5

RIO

_R

D4

AA

25

RIO

_R

D5

AB

25

RIO

_R

D6

AC

25

RIO

_R

D7

AD

25

RIO

_R

D1-

U2

4

RIO

_R

D2-

V2

4

RIO

_R

D3-

W2

4

RIO

_R

D4-

AA

24

RIO

_R

D5-

AB

24

RIO

_R

D6-

AC

24

RIO

_R

D7-

AD

24

RIO

_T

XC

LK

_IN

AF

24

RIO

_T

XC

LK

_IN

-A

F2

5



Schematics


55

44

33

22

11

DD

CC

BB

AA

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 3 - P

CI In

terfa

ce

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

51

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

PC

IX/P

CI

U6

A

MP

C8

56

0

PC

I_C

_B

E0

AC

12

PC

I_C

_B

E1

AD

11

PC

I_C

_B

E2

AB

10

PC

I_C

_B

E3

AH

8

PC

I_C

_B

E4

W1

4

PC

I_C

_B

E5

V1

4

PC

I_C

_B

E6

AH

13

PC

I_C

_B

E7

AG

13

PC

I_A

D0

AC

13

PC

I_A

D1

AB

13

PC

I_A

D2

Y1

3

PC

I_A

D3

V1

3

PC

I_A

D4

AH

12

PC

I_A

D5

AG

12

PC

I_A

D6

AE

12

PC

I_A

D7

AD

12

PC

I_A

D8

AB

12

PC

I_A

D9

Y1

2

PC

I_A

D10

W1

2

PC

I_A

D11

V1

2

PC

I_A

D12

AH

11

PC

I_A

D13

AG

11

PC

I_A

D14

AF

11

PC

I_A

D15

AE

11

PC

I_A

D16

AA

10

PC

I_A

D17

Y1

0

PC

I_A

D18

W1

0

PC

I_A

D19

AH

9

PC

I_A

D20

AG

9

PC

I_A

D21

AF

9

PC

I_A

D22

AE

9

PC

I_A

D23

AD

9

PC

I_A

D24

AG

8

PC

I_A

D25

AF

8

PC

I_A

D26

AC

8

PC

I_A

D27

AB

8

PC

I_A

D28

AH

7

PC

I_A

D29

AE

7

PC

I_A

D30

AD

7

PC

I_A

D31

AH

6

PC

I_A

D32

AF

18

PC

I_A

D33

AF

17

PC

I_A

D34

AE

17

PC

I_A

D35

AB

17

PC

I_A

D36

AA

17

PC

I_A

D37

Y1

7

PC

I_A

D38

W1

7

PC

I_A

D39

V1

7

PC

I_A

D40

AF

16

PC

I_A

D41

AE

16

PC

I_A

D42

AD

16

PC

I_A

D43

AC

16

PC

I_A

D44

AB

16

PC

I_A

D45

W1

6

PC

I_A

D46

V1

6

PC

I_A

D47

AH

15

PC

I_A

D48

AG

15

PC

I_A

D49

AD

15

PC

I_A

D50

AC

15

PC

I_A

D51

AB

15

PC

I_A

D52

AA

15

PC

I_A

D53

Y1

5

PC

I_A

D54

W1

5

PC

I_A

D55

V1

5

PC

I_A

D56

AH

14

PC

I_A

D57

AG

14

PC

I_A

D58

AF

14

PC

I_A

D59

AE

14

PC

I_A

D60

AD

14

PC

I_A

D61

AC

14

PC

I_A

D62

AB

14

PC

I_A

D63

AA

14

PC

I_P

AR

AA

11

PC

I_P

AR

64

Y1

4

PC

I_F

RA

ME

AC

10

PC

I_T

RD

YA

G1

0

PC

I_IR

DY

AD

10

PC

I_S

TO

PV

11

PC

I_D

EV

SE

LA

H1

0

PC

I_ID

SE

LA

A9

PC

I_R

EQ

64

AE

13

PC

I_A

CK

64

AD

13

PC

I_P

ER

RW

11

PC

I_S

ER

RY

11

PC

I_R

EQ

0A

F5

PC

I_R

EQ

1A

F3

PC

I_R

EQ

2A

E4

PC

I_R

EQ

3A

G4

PC

I_R

EQ

4A

E5

PC

I_G

NT

0A

E6

PC

I_G

NT

1A

G5

PC

I_G

NT

2A

H5

PC

I_G

NT

3A

F6

PC

I_G

NT

4A

G6




55

44

33

22

11

DD

CC

BB

AA

G1

GT

XC

LK

+3

.3V

MG

TX

125

G1

TX

D[7

:0]

G1

RX

ER

G1

RX

DV

DG

ND

MD

IO

G1

CO

L

G1

_IR

Q_

N

G1T

XE

N

G1

RX

CL

K

G1

RX

D[7

:0]

+2

.5V

GE

the

r

MD

C

WP

3_

G1

_R

ES

ET

_N

G1

TX

CL

K

G1

TX

D[7

:4]

DG

ND

G1

CR

S

G2

TX

D[7

:2]

+3

.3V

G1T

XE

R

+1

.5V

GE

the

r

CG

ND

DG

ND

DG

ND

G1

TX

D[7

:4]

G2

TX

D[7

:2]

MD

CM

DIO

WP

3_

G1

_R

ES

ET

_N

+3

.3V

+2

.5V

GE

the

rG

1G

TX

CL

K

+1

.5V

GE

the

r

+3

.3V

G1

_IR

Q_

N

CG

ND

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 3 - G

iga

Byte

Eth

ern

et In

terfa

ce

- To

p0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

52

72

Mo

nd

ay, S

ep

tem

be

r 08

, 20

03

Pa

ge

54

WP

3 - T

SE

C - P

HY

G1

CO

L

G1

TX

D[7

:0]

G1

RX

D[7

:0]

+1

.5V

GE

the

r

DG

ND

MD

IO

+3

.3V

MD

C

WP

3_

G1

_R

ES

ET

_N

G1

_IR

Q_

N

G1R

XD

VG

1G

TX

CL

K

G1

RX

CL

K

+2

.5V

GE

the

rM

GT

X1

25

G1

TX

CL

K

G1T

XE

N

G1C

RS

G1T

XE

R

G1R

XE

R

CG

ND

Pa

ge

53

WP

3 - T

SE

C

G1

GT

XC

LK

G1C

RS

G1T

XE

RG

1T

XC

LK

G2

TX

D[7

:2]

+3

.3V

MG

TX

12

5

G1

RX

CL

K

G1R

XD

V

G1

CO

L

G1

TX

D[7

:0]

G1R

XE

R

G1T

XE

N

G1

RX

D[7

:0]

DG

ND



Schematics


55

44

33

22

11

DD

CC

BB

AA

G1

RX

CL

K

G1

RX

D5

+3

.3V

MG

TX

125

G1

TX

D[7

:0]M

GT

X1

25

G2

TX

D4

G1

RX

D6

G1

RX

D3

G1

RX

D7

G1

RX

D7

G1

RX

D3

G1T

XE

R

G1

RX

D5

DG

ND

G1

RX

D4

G1

RX

D1

G2

TX

D7

G1

GT

XC

LK

G1

RX

D1

G2

TX

D6

G1

TX

CL

K

G1T

XE

N

G1

RX

DV

G1

RX

D4

G1

RX

D0

G2

TX

D5

G1

CO

L

G1

RX

D2

G1

RX

D7

G1

RX

ER

G1

RX

D0

G1

RX

D2

G1

RX

D2

G1

RX

D3

G1

CR

S

G1

RX

D0

G1

RX

D5

G1

RX

D6

G1

RX

D6

G1

RX

D4

G1

RX

D1

G1

RX

D[7

:0]

G1

TX

D4

G1

TX

D2

G1

TX

D2

G1

TX

D4

G1

TX

D6

G1

TX

D0

G1

TX

D7

G1

TX

D3

G1

TX

D4

G1

TX

D5

G1

TX

D7

G1

TX

D6

G1

TX

D0

G1

TX

D3

G1

TX

D5

G1

TX

D6

G1

TX

D7

G1

TX

D1

G1

TX

D3

G1

TX

D0

G1

TX

D1

G1

TX

D2

G1

TX

D5

G1

TX

D1

G1T

XE

R

G1

GT

XC

LK

G1T

XE

N

G1

RX

CL

KG

1C

OL

G1

RX

DV

G1

RX

ER

G1

CR

S

G1

TX

CL

K

G2

TX

D3

G2

TX

D2

G1

CR

S

G2

TX

D[7

:2]

G1

RX

CL

K

G1

RX

DV

MG

TX

125

G1

TX

D[7

:0]

+3

.3V

G1

GT

XC

LK

DG

ND

G1

CO

L

G1

TX

CL

K

G1

RX

D[7

:0]

G1T

XE

N

G1

RX

ER

G1T

XE

R

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3VS

ys

tem

:

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rkP

roce

sso

r 3 - G

iga

Byte

Eth

ern

et In

terfa

ce

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

53

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

Power

Decoupling

100pF C888

R618330R R612330R

R6

03

22

0R

R6

09

22

0R C

N2

01

00

pF

, CN

1234

8765

0.1uFC839

100pF C895 100pF C892

100pF C887

R610330RR616330R

RN

16

8

22

0R

, R

N

123456789 1

01

11

21

31

41

51

6

R6

15

22

0R

R6

11

22

0R

TS

EC

1

TS

EC

2

Gb

EC

lock

ing

U6

G

MP

C8

56

0

TS

EC

1_T

XD

0E

8

TS

EC

1_T

XD

1G

8

TS

EC

1_T

XD

2A

7

TS

EC

1_T

XD

3B

7

TS

EC

1_T

XD

4C

7

TS

EC

1_T

XD

5D

7

TS

EC

1_T

XD

6F

7

TS

EC

1_T

XD

7A

6

TS

EC

1_T

X_E

NC

8

TS

EC

1_T

X_E

RB

8

TS

EC

1_

TX

_C

LK

C6

TS

EC

1_

GT

X_

CL

KB

6

TS

EC

1_R

XD

0E

6

TS

EC

1_R

XD

1F

6

TS

EC

1_R

XD

2A

5

TS

EC

1_R

XD

3B

5

TS

EC

1_R

XD

4D

5

TS

EC

1_R

XD

5D

3

TS

EC

1_R

XD

6B

4

TS

EC

1_R

XD

7D

4

TS

EC

1_R

X_D

VD

2

TS

EC

1_R

X_E

RE

5

TS

EC

1_

RX

_C

LK

D6

TS

EC

1_C

RS

C3

TS

EC

1_

CO

LG

7

TS

EC

2_T

XD

0E

11

TS

EC

2_T

XD

1G

11

TS

EC

2_T

XD

2H

11

TS

EC

2_T

XD

3J1

1

TS

EC

2_T

XD

4K

11

TS

EC

2_T

XD

5J1

0

TS

EC

2_T

XD

6A

10

TS

EC

2_T

XD

7B

10

TS

EC

2_T

X_E

NB

11

TS

EC

2_T

X_E

RD

11

TS

EC

2_

TX

_C

LK

D1

0

TS

EC

2_

GT

X_

CL

KC

10

TS

EC

2_R

XD

0F

10

TS

EC

2_R

XD

1G

10

TS

EC

2_R

XD

2H

9

TS

EC

2_R

XD

3A

9

TS

EC

2_R

XD

4B

9

TS

EC

2_R

XD

5C

9

TS

EC

2_R

XD

6E

9

TS

EC

2_R

XD

7F

9

TS

EC

2_R

X_D

VH

8

TS

EC

2_R

X_E

RA

8

TS

EC

2_

RX

_C

LK

E1

0

TS

EC

2_C

RS

D9

TS

EC

2_

CO

LF

8

EC

_G

TX

_C

LK

12

5E

2

LV

dd

1A

4

LV

dd

2C

5

LV

dd

3E

7

LV

dd

4H

10

R620330R

100pF C893

R6

07

22

0R

CN

17

10

0p

F, C

N

1234

8765

R4

60

22

R 0

.1W

RN

16

9

33

0R

, R

N

123456789 1

01

11

2

13

14

15

16

R6

13

22

0R

R608330R

R4

63

22

0R

R6

19

22

0R

0.1uFC841

100pF C890

R4

61

22

R 0

.1W

100pF C891

0.1uFC838

100pF C889

100pF C534

R6

05

22

0R

0.1uFC840

100pF C894

R614330R

RN

16

62

2R

, RN

123456789 1

01

11

21

31

41

51

6

R4

62

22

R 0

.1W

RN

17

0

33

0R

, R

N

123456789 1

01

11

2

13

14

15

16

R606330R

RN

16

7

22

0R

, R

N

123456789 1

01

11

21

31

41

51

6

CN

19

10

0p

F, C

N

1234

8765

R464330R

R604330R

R6

17

22

0R

CN

18

10

0p

F, C

N

1234

8765



Figure A-52. Work Processor 3—GigaByte Ethernet Interface—PHY

55

44

33

22

11

DD

CC

BB

AA

G1

RX

D5

MG

TX

125

G1

RX

D7

G1

TX

D5

G1

TX

CL

K

G1

RX

D1

G1

CR

S

G1

TX

D0

G1AVDDH

G1

RX

ER

Wp

3_

G1

_R

ES

ET

_N G

1T

XE

R

G1

RX

D0

G1

RX

D4

G1

TX

D6

G1

TX

D3

G1

RX

DV

G1

_IR

Q_

N

G1

TX

D4

G1

RX

D6

G1

TX

D7

G1

RX

D3

G1

TX

D2

G1T

XE

N

G1

TX

D1

G1

GT

XC

LK

G1

RX

CL

K

G1

CO

L

G1

RX

D2

CG

ND

+3

.3V

DG

ND

+2

.5V

GE

the

r

+1

.5V

GE

the

r

WP

3_

PH

1_

P0

WP

3_

PH

1_

M0

WP

3_

PH

1_

P1

WP

3_

PH

1_

M1

WP

3_

PH

1_

P2

WP

3_

PH

1_

M2

WP

3_

PH

1_

P3

WP

3_

PH

1_

M3

MD

CM

DIO

G1

TX

CL

K

G1

RX

CL

K

G1

RX

DV

MD

C

G1

RX

D[7

:0]G

1T

XE

R

G1

CR

S

G1

GT

XC

LK

MD

IO

G1

TX

D[7

:0]

MG

TX

125

G1

_IR

Q_

N

WP

3_

G1

_R

ES

ET

_N

G1

RX

ER

G1

CO

L

G1T

XE

N

CG

ND

+3

.3V

DG

ND

+2

.5V

GE

the

r

+1

.5V

GE

the

r

+1

.5V

GE

the

r

+3

.3V

+3

.3V

+3

.3V

+2

.5V

GE

the

r

+3

.3V

+3

.3V

+2

.5V

GE

the

r

+1

.5V

GE

the

r

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roc

es

so

r 3 - G

iga

Byte

Eth

ern

et In

terfa

ce

- PH

Y0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

54

72

Tu

esd

ay, S

ep

tem

be

r 30

, 20

03

GR

OU

ND

Se

pa

rate

3.3

V

must be 50

mill trace

2.5

V1

.5V



LED on => Link Up




LED on => Link Up



Power

Pin


Pin


CONFIG0 0 0

0

CONFIG1 0 0

0

CONFIG2 1 1

0

CONFIG3 0 0

0

CONFIG4 1 1

1

CONFIG5 1 1

1

CONFIG6 0 0

0








VDD0 1 1 1

LED_LINK10 1 1 0

LED_LINK100 1 0 1

LED_LINK1000 1 0 0

LED_DUPLEX 0 1 1

LED_RX 0 1 0

LED_TX 0 0 1

VSS 0 0 0

Pin Bit[2:0]

Pin Setting

CONFIG0 VSS

CONFIG1 VSS

CONFIG2 LED_LINK10

CONFIG3 VSS

CONFIG4 VDDO

CONFIG5 VDDO

CONFIG6 VSS

LD32

LED_YELLOW

2 1

0.01uF C520

0.1uF C516

R4

39

22

R 0

.1W

R130310K

49

R9

R4

35

0.01uF C503

49R9R434

R13520R

0.01uF C522

0.1uF C515

49

R9

R4

42

0.01uF C501

33

0R

R4

55

R13530R

0.01uF C513

0.01uF C510

R4

40

22

R 0

.1W

33

0R

R4

59

0.0

1u

F

C530

10

K

R4

51

0.0

1u

F

C528

0.01uF C502

TP149

L2

13

PIN

_F

ER

RIT

E13

2

0.01uF C512

0.1uF C527

R13540R

0.01uF C500

R4

44

22

R 0

.1W

LD34

LED_YELLOW

2 1

0.01uF C509

R4

50

0R

R13550R

0.1uF C524

0.1uF C504

0.1uF C508

0.1uF C507

49

R9

R4

41

0.1uF C514

R1

35

01

K

0.1uF C517

Y1

12

5M

Hz

14

23

0.1uF C518

TP150

R4

46

22

R 0

.1W

C5

32

18

pF

C5

33

18

pF

R13560R

4K

7R

45

3

0.1uF C523

TP151

49

R9

R4

37

33

0RR

45

6

R1

35

11

K

1:1

1:1

1:1

1:1

1:1

P5

E

RJG

5-7

G0

5

9E

10

E

7E

8E

5E

6E

2E

3E

4E

1E

D1

ED

2E

D3

ED

4E

11

E

49

R9

R4

48

LD36

LED_YELLOW

2 1

0.1uF C506

R13570R

49

R9

R4

36

0.01uF C519

R4

47

22

R 0

.1W

33

0R

R4

57

0.0

1u

F

C529

0.1uF C526

R4522K49

TP152

0.01uF C511

49

R9

R4

45

R13580R

RN

16

52

2R

, RN

123456789 1

01

11

21

31

41

51

6

49R9R433

R4

49

22

R 0

.1W

0.1uF C505

0.1uF C525

0.01uF C521

LD37

LED_RED

2 1

U6

2

88

E1

01

1S

RX

D_2

A8

RX

D_1

B7

RX

D_0

A7

RX

_D

VA

6

RX

_C

LK

B6

VDDOC6

TX

_C

LK

B4

CO

LA

5

RX

_E

RB

5

VDDOC5

DGNDD5

DGNDD4

DGNDC4

CR

SA

4

SC

LK

_M

C3

GT

X_

CL

KB

3

TX

_E

RA

3

TX

D_

0B

2

TX

_E

NA

2

CO

MA

A1

AVDDLB1

SIN

_M

C1

SO

UT

_M

C2

SIN

_P

D1

SO

UT

_P

D2

TX

D_

6H

1

SC

LK

_P

D3

TX

D_

1E

1

CTRL_15E2

DGNDG4

DVDDLE3

DGNDE4

TX

D_

2F

1

TX

D_

3F

2

TX

D_

4G

1

DVDDHF3

DGNDF4

TX

D_

5G

2

DVDDHG3

DGNDG5

TX

D_

7H

2

DVDDLH3

DGNDH4

DGNDH5

XT

AL

2J1

XT

AL

1J2

VDDOJ3

DGNDJ4

TCKK1

RE

SE

TK

2

VS

SC

K3

DGNDK4

AVDDLL2

TMSL1

DGNDL3

TRSTM1

RSETM2

MD

I0_

PN

1

MD

I0_M

N2

AVDDLM3

MD

I1_

PN

3

DGNDL4

CTRL25M4

MD

I1_M

N4

DGNDJ5

DGNDK5

DGNDL5

HDAC_PM5

AVDDHN5

DGNDL6

HDAC_NM6

DGNDK6

MD

I2_

PN

6

MD

I2_M

N7

DGNDL7

AVDDLM7

MD

I3_

PN

8

AVDDLM8

MD

I3_M

N9

TDIM9

TDOL8

CONFIG_4L9

CONFIG_3K9

CONFIG_2K8

CONFIG_6K7

CONFIG_1J9

CONFIG_5J7

CONFIG_0J8

DGNDJ6

VDDOH7

LED_TXH9

DGNDH6

LED_RXH8

DVDDLG7

DGNDG6

LED_DPLXG9

LED_LINK1000G8

SE

L_

2_

5V

F7

LED_LINK100F9

DGNDF6

LED_LINK10F8

DGNDF5

DGNDE6

MD

CE

8

DGNDE5

VDDOE7

INT

E9

MD

IOD

9

CL

K1

25

D8

DVDDLD7

DGNDD6

DGNDC7

RX

D_6

C8

RX

D_7

C9

RX

D_3

B8

RX

D_5

B9

RX

D_4

A9

R4

38

22

R 0

.1W

0.0

1u

F

C531

0.01uF C499

49

R9

R4

43



Schematics


55

44

33

22

11

DD

CC

BB

AA

WP

3_

RX

DW

P3

_T

XD

WP

3_

RX

DW

P3

_T

XD

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 3 - C

om

mu

nic

atio

ns P

roce

sso

r Mo

du

le0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

55

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

CP

M

Alt. DUART

A lt. DUART

Alt. 10/100 Eth.

Alt. 10/100 Eth.

U6

H

MP

C8

56

0

PA

0H

1

PA

1H

2

PA

2J1

PA

3J2

PA

4J3

PA

5J4

PA

6J5

PA

7J6

PA

8J7

PA

9J8

PA

10

K8

PA

11

K7

PA

12

K6

PA

13

K3

PA

14

K2

PA

15

K1

PA

16

L1

PA

17

L2

PA

18

L3

PA

19

L4

PA

20

L5

PA

21

L8

PA

22

L9

PA

23

L1

0

PA

24

L1

1

PA

25

M1

0

PA

26

M9

PA

27

M8

PA

28

M7

PA

29

M6

PA

30

M3

PA

31

M2

PB

4/F

EC

_T

XD

3M

1

PB

5/F

EC

_T

XD

2N

1

PB

6/F

EC

_T

XD

1N

4

PB

7/F

EC

_T

XD

0N

5

PB

8/F

EC

_R

XD

0N

6

PB

9/F

EC

_R

XD

1N

7

PB

10/F

EC

_R

XD

2N

8

PB

11/F

EC

_R

XD

3N

9

PB

12/F

EC

_C

RS

N1

0

PB

13/F

EC

_C

OL

N1

1

PB

14/F

EC

_T

X_E

NP

11

PB

15/F

EC

_T

X_E

RP

10

PB

16/F

EC

_R

X_E

RP

9

PB

17/F

EC

_R

X_D

VP

8

PB

18

P7

PB

19

P6

PB

20

P5

PB

21

P4

PB

22

P3

PB

23

P2

PB

24

P1

PB

25

R1

PB

26

R2

PB

27

R3

PB

28

R4

PB

29

R5

PB

30

R6

PB

31

R7

PC

0R

8

PC

1R

9

PC

2R

10

PC

3R

11

PC

4T

9

PC

5T

6

PC

6T

5

PC

7T

4

PC

8T

1

PC

9U

1

PC

10

U2

PC

11

U3

PC

12

U4

PC

13/U

AR

T_C

TS

1U

7

PC

14

U8

PC

15/U

AR

T_C

TS

0U

9

PC

16

U1

0

PC

17/F

EC

_R

X_C

LK

V9

PC

18

/FE

C_

TX

_C

LK

V6

PC

19

V5

PC

20

V4

PC

21

V3

PC

22

V2

PC

23

V1

PC

24

W1

PC

25

W2

PC

26

W3

PC

27

W6

PC

28

W7

PC

29

W8

PC

30

W9

PC

31

Y9

PD

4Y

1

PD

5Y

2

PD

6Y

3

PD

7Y

4

PD

8Y

5

PD

9Y

6

PD

10

AA

8

PD

11

AA

7

PD

12

AA

4

PD

13

AA

3

PD

14

AA

2

PD

15

AA

1

PD

16

AB

1

PD

17

AB

2

PD

18

AB

3

PD

19

AB

5

PD

20

AB

6

PD

21

AC

7

PD

22

AC

4

PD

23

AC

3

PD

24

AC

2

PD

25

AC

1

PD

26/U

AR

T_R

TS

1A

D1

PD

27/U

AR

T_S

OU

T1

AD

2

PD

28/U

AR

T_S

IN1

AD

5

PD

29/U

AR

T_R

TS

0A

D6

PD

30/U

AR

T_S

OU

T0

AE

3

PD

31/U

AR

T_S

IN0

AE

2




55

44

33

22

11

DD

CC

BB

AA

MD

CM

DIO

IRQ

1_

N

TD

O

UD

E_

N

BP

_IN

T_

NW

P2

_IN

T_

N

TC

K

IRQ

6_

NTC

K

WP

3_

INT

_N

CH

KS

TO

P_

IN_

N

CH

KS

TO

P_

OU

T_

N

WP

3_

HR

ES

ET

_N

TM

S

WP

3_

CO

P_

TR

ST

_N

WP

3_

TR

ST

_N

WP

3_

CO

P_

TR

ST

_N

WP

3_

SR

ES

ET

_N

WP

3_

HR

ES

ET

_N

TD

O

AS

LE

EP

TM

S

IRQ

9_

N

WP

3_

CO

P_

SR

ES

ET

_N

CH

KS

TO

P_

IN_

N

MC

P_

N

TD

I

+3

.3V

DG

ND

WP

3_

SY

S_

CL

K

WP

3_

CO

P_

SR

ES

ET

_N

WP

3_

CO

P_

HR

ES

ET

_N

WP

1_

INT

_N

MS

RC

ID0

CH

KS

TO

P_

OU

T_

N

IRQ

11

_N

IRQ

8_

N

WP

3_

HR

ES

ET

_R

EQ

_N

WP

3_

SR

ES

ET

_N

WP

3_

TR

ST

_N

CL

K_

OU

T

IRQ

0_

N

WP

3_

CO

P_

HR

ES

ET

_N

IRQ

10

_N

WP

3_

HR

ES

ET

_R

EQ

_N

TD

I

WP

3_

RT

C_

CL

K

IRQ

7_

N

MD

VA

L

MS

RC

ID1

MS

RC

ID2

MS

RC

ID4

MS

RC

ID3

I2C

_S

DA

I2C

_S

CL

TH

ER

M0

TH

ER

M1

TR

IG_

OU

T

IRQ

5_

N

MD

CM

DIO

G1

_IR

Q_

N

WP

3_

SY

S_

CL

K

DG

ND

WP

3_

CO

P_

HR

ES

ET

_N

I2C

_S

DA

WP

3_

TR

ST

_N

WP

3_

CO

P_

TR

ST

_N

WP

3_

RT

C_

CL

K

WP

3_

HR

ES

ET

_R

EQ

_N

WP

3_

CO

P_

SR

ES

ET

_N

+3

.3V

WP

3_

SR

ES

ET

_N

WP

3_

HR

ES

ET

_N

I2C

_S

CL

MS

RC

ID0

WP

1_

INT

_N

BP

_IN

T_

N

WP

3_

INT

_N

WP

2_

INT

_N

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 3 - A

uxila

ry F

un

ctio

ns

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

56

72

Frid

ay, S

ep

tem

be

r 26

, 20

03

Power

TP

82

R2

26

10

K

TP

89

KEY

KEY

HD

11

2x8

He

ad

er

15

16

12

34

56

78

91

01

11

21

31

4

R2

25

10

K

RN

14

6

10

K, R

N

10

12346789

5

R7

08

10

K

R2

23

10

K

AU

XIL

IAR

Y F

UN

CT

ION

PIC

DMA

Eth.MI

AN

AL

OG

JT

AG

DEBUG

SP

AR

ES

CL

OC

KIN

G

DFT

I2C

SY

S. C

NT

RL

PW

R M

ng

.

U6

D

MP

C8

56

0

MC

PA

G1

7

UD

EA

G1

6

IRQ

0A

A1

8

IRQ

1Y

18

IRQ

2A

B1

8

IRQ

3A

G2

4

IRQ

4A

A2

1

IRQ

5Y

19

IRQ

6A

A1

9

IRQ

7A

G2

5

IRQ

8A

B2

0

IRQ

9/D

MA

_D

RE

Q3

Y2

0

IRQ

10/D

MA

_D

AC

K3

AF

26

IRQ

11/D

MA

_D

DO

NE

3A

H2

4

IRQ

_O

UT

AB

21

DM

A_D

RE

Q0

H5

DM

A_D

RE

Q1

G4

DM

A_D

AC

K0

H6

DM

A_D

AC

K1

G5

DM

A_D

DO

NE

0H

7

DM

A_D

DO

NE

1G

6

EC

_M

DC

F1

EC

_M

DIO

E1

L1

_T

ST

CL

KA

B2

2

CLK

_O

UT

AF

22

TH

ER

M0

AG

2

TH

ER

M1

AH

3

L2

_T

ST

CL

KA

G2

2

TD

OA

F1

9

TM

SA

F2

3

TD

IA

G2

1

TC

KA

F2

1

TR

ST

AG

23

TR

IG_IN

N1

2

TR

IG_O

UT

/RE

AD

Y/Q

UIE

SC

EG

2

MS

RC

ID0

J9

MS

RC

ID1

G3

MS

RC

ID2

F3

MS

RC

ID3

F5

MS

RC

ID4

F2

MD

VA

LF

4

SP

AR

E1

T1

1

SP

AR

E2

U1

1

SP

AR

E3

AF

1

SP

AR

E4

C1

RT

CA

B2

3

SY

SC

LK

AH

21

LS

SD

_M

OD

EA

G1

9

TE

ST

_S

EL

(Dra

co

/Dra

co

m)

AH

20

AS

LE

EP

AG

18

IIC_S

CL

AH

23

IIC_S

DA

AH

22

CK

ST

P_IN

M1

1

CK

ST

P_O

UT

G1

SR

ES

ET

AF

20

HR

ES

ET

_R

EQ

AG

20

HR

ES

ET

AH

16

NC

2A

H1

NC

3A

G1

NC

4A

H2

NC

5B

1

NC

6B

2

NC

7A

2

NC

8A

3

NC

9A

H2

5

NC

10

AH

26

NC

11

AH

27

NC

12

AH

28

NC

13

AG

28

NC

14

AF

28

NC

15

AE

28

TP

81

TP

84

TP

16

5

R2

30

4K

7

TP

16

6

R6

35

0R

TP

16

7

R2

22

10

KR

22

72

K

TP

16

4

TP

83

TP

16

3

RN

14

51

0K

, RN

10

12346789

5

R2

24

10

K

R6

27

4K

7

R2

28

10

KR

63

60

R

JP

38

12

R2

29

4K

7

R2

31

4K

7R

23

24

K7

R2

21

4K

7

TP

85

R6

28

4K

7



Schematics


55

44

33

22

11

DD

CC

BB

AA

+3

.3V

DG

ND

BL

A2

7L

CS

_N

2

G2

TX

D5

G2

TX

D6

LG

PL

0

G2

TX

D4

LW

E_

N3

G2

TX

D2

BL

A2

8

MS

RC

ID0

G1

GT

XC

LK G

2T

XD

3

G1

TX

D6

LG

PL

1

BL

A3

0

G2

TX

D7

BL

A3

1

G2

TX

D5

BL

A2

9

G2

TX

D4

G2

TX

D6

LG

PL

2

G2

TX

D3

LA

LE

G2

TX

D2

G1

TX

D5

LC

S_

N1

G1

TX

D4

LC

S_

N0

BL

A2

7

LW

E_

N2

G1

TX

D7

G2

TX

D7

DG

ND

+3

.3V

WP

3_

RS

T_

CO

NF

_N

LW

E_

N[2

:3]

LG

PL

1

G1

GT

XC

LK

BL

A[2

7:3

1]

G2

TX

D[7

:4]

LG

PL

2

LC

S_

N[0

:2]

G2

TX

D[7

:2]

LG

PL

0

G1

TX

D[7

:4]

LA

LE

MS

RC

ID0

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 3 - C

on

figu

ratio

n0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

57

72

Mo

nd

ay, S

ep

tem

be

r 08

, 20

03

Power

Pro

cesso

r

"R

OM

Lo

c.1

"

"D

ev

ice ID

4"

"D

ev

ice ID

3"

"D

ev

ice ID

0"

"R

IO C

lk 1

"

"R

OM

Lo

c.2

"

"H

ost/A

gen

t 0"

"D

ev

ice ID

7"

"D

eb

ug

En

ab

le"

"C

PU

Bo

ot"

"R

OM

Lo

c.0

"

"H

ost/A

gen

t 1"

"S

ys P

LL

0"

"S

ys P

LL

3"

"CONFIGURATION"

RIO

"D

ev

ice ID

2"

"D

ev

ice ID

6"

"S

ys P

LL

1"

"C

ore P

LL

1"

"S

ys P

LL

2"

Mem

ory

RIO

"D

ev

ice ID

5"

"C

ore P

LL

0"

"D

ev

ice ID

1"

"R

IO C

lk 0

"

PC

I/RIO

Pro

cesso

r

TS

EC

"T

SE

C1

Mo

de"

Decoupling


For Rev 2 silicon;

Remove R758,R759,R760,R761,R762

Add R756,R757

Do Not Fit

R7

61

0R

0.1uFC733

R7

62

0R

SW

12

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

U3

9

74

AL

VT

16

24

4

1A

14

7

1A

24

6

1A

34

4

1A

44

3

2A

14

1

2A

24

0

2A

33

8

2A

43

7

OE

11

OE

24

8

3A

13

6

3A

23

5

3A

33

3

3A

43

2

4A

13

0

4A

22

9

4A

32

7

4A

42

6

OE

42

4

1Y

12

1Y

23

1Y

35

1Y

46

2Y

18

2Y

29

2Y

31

1

2Y

41

2

3Y

11

3

3Y

21

4

3Y

31

6

3Y

41

7

4Y

11

9

4Y

22

0

4Y

32

2

4Y

42

3

3V37

3V318

3V331

3V342

DGND4

DGND10

DGND15

DGND21

DGND28

DGND34

DGND39

DGND45

OE

32

5

SW

13

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

RN

11

11

0K

, RN

10

12346789

5

RN

14

91

0K

, RN

10

12346789

5

R7

59

0R

0.1uFC732

R7

58

0R

R7

57

0R

RN

11

21

0K

, RN

10

12346789

5

R7

60

0R

R7

56

0R

74

LV

CH

24

4

U4

0

2Y

43

2Y

35

2Y

27

2Y

19

1Y

41

21Y

31

41Y

21

61Y

11

8

2A

41

72A

31

52A

21

32A

11

1

1A

48

1A

36

1A

24

1A

12

VC

C 20

2O

E1

9

GN

D

10

1O

E1

SW

18

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9




55

44

33

22

11

DD

CC

BB

AA

DG

ND

+3

.3V

+1

2V

Vd

d

+3

.3V

Vd

d

DG

ND

+1

2V

Vd

d

+3

.3V

Vd

d

Vd

dV

dd

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Vd

dV

dd

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Vd

dV

dd

+3

.3V

Vd

d+

3.3

V

+3

.3V

Vd

d+

3.3

V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Vd

d

+3

.3V

Vd

d+

3.3

V+

3.3

V

+3

.3V

+3

.3V

+3

.3V

+1

2V

Vd

d

Vd

d

+3

.3V

+3

.3V

Vd

d

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

Vd

dV

dd

+1

2V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Wo

rk P

roce

sso

r 3 - P

ow

er

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

58

72

We

dn

esd

ay, O

cto

be

r 01

, 20

03

Decoupling

Decoupling

Header for

12V fanPower

Decoupling


Bulk Decoupling

0.1uFC635

10uF, 6.3V

C961

TP

17

9

0.1uFC656

C1143

220uF, Tants

12

10

R R2

61

+

C1079

10uF,6.3V Tants

0.1uFC650

S7

DO

57

0.1uFC648

0.1uFC652

S8

DO

57

L3

3

Fe

rrite B

ea

d1

2

0.1uFC660

0.1uFC641

0.1uFC1097

C1104

220uF, Tants

12

0.1uFC651

2.2uF

C299

0.1uFC637

0.1uFC1103

0.1uFC662

0.1uFC1099

0.1uFC654

0.1uFC636

0.1uFC1233

0.1uFC647

C1105

220uF, Tants

12

HS

4

10

-TH

MA

-01

0.1uFC643

0.1uFC640

0.1uFC649

0.1uFC645

0.1uFC1102

0.1uFC1098

0.1uFC642

2.2uF

C300

2.2uF

C302

0.1uFC653

0.1uFC1096

0.1uFC657

0.1uFC659

0.1uFC634

HD

19

12

+

C1080

10uF,6.3V Tants

0.1uFC655

TP

17

8

2.2uF

C298

0.1uFC658

0.1uFC639

10

R R2

62

10

R R2

63

0.1uFC1101

0.1uFC644

0.1uFC1232

PO

WE

R

U6

I

MP

C8

56

0

OV

dd

1A

E1

OV

dd

2D

1

OV

dd

3T

2

OV

dd

4N

3

OV

dd

5H

3

OV

dd

6A

H4

OV

dd

7A

D4

OV

dd

8W

4

OV

dd

9K

4

OV

dd

10

E4

OV

dd

11

AC

5

OV

dd

12

AA

5

OV

dd

13

U5

OV

dd

14

M5

OV

dd

15

AF

7

OV

dd

16

AB

7

OV

dd

17

Y7

OV

dd

18

T7

OV

dd

19

L7

OV

dd

20

AE

8

OV

dd

21

V8

OV

dd

22

AB

9

OV

dd

23

AE

10

OV

dd

24

K1

0

OV

dd

25

AC

11

OV

dd

26

AF

12

OV

dd

27

AA

12

OV

dd

28

W1

3

OV

dd

29

AE

15

OV

dd

30

AA

16

OV

dd

31

AC

17

OV

dd

32

W1

9

OV

dd

33

R1

9

OV

dd

34

AA

20

OV

dd

35

U2

0

OV

dd

36

W2

1

OV

dd

37

P2

2

OV

dd

38

Y2

3

OV

dd

39

R2

5

OV

dd

40

AB

26

OV

dd

41

U2

6

OV

dd

42

AG

27

GN

D1

AF

2

GN

D2

N2

GN

D3

C2

GN

D4

AG

3

GN

D5

AD

3

GN

D6

T3

GN

D7

E3

GN

D8

B3

GN

D9

AF

4

GN

D1

0A

B4

GN

D1

1M

4

GN

D1

2H

4

GN

D1

3C

4

GN

D1

4W

5

GN

D1

5K

5

GN

D1

6A

C6

GN

D1

7A

A6

GN

D1

8U

6

GN

D1

9L

6

GN

D2

0A

G7

GN

D2

1V

7

GN

D2

2A

D8

GN

D2

3Y

8

GN

D2

4T

8

GN

D2

5D

8

GN

D2

6A

C9

GN

D2

7K

9

GN

D2

8G

9

GN

D2

9A

F1

0

GN

D3

0V

10

GN

D3

1T

10

GN

D3

2A

B1

1

GN

D3

3F

11

GN

D3

4C

11

GN

D3

5T

12

GN

D3

6P

12

GN

D3

7M

12

GN

D3

8H

12

GN

D3

9G

12

GN

D4

0E

12

GN

D4

1A

12

GN

D4

2A

F1

3

GN

D4

3A

A1

3

GN

D4

4U

13

GN

D4

5R

13

GN

D4

6N

13

GN

D4

7T

14

GN

D4

8P

14

GN

D4

9M

14

GN

D5

0H

14

GN

D5

1B

14

GN

D5

2A

F1

5

GN

D5

3U

15

GN

D5

4R

15

GN

D5

5N

15

GN

D5

6Y

16

GN

D5

7U

16

GN

D5

8T

16

GN

D5

9P

16

GN

D6

0M

16

GN

D6

1A

D1

7

GN

D6

2U

17

GN

D6

3R

17

GN

D6

4N

17

GN

D6

5H

17

GN

D6

6C

17

GN

D6

7A

17

GN

D6

8W

18

GN

D6

9K

18

GN

D7

0F

18

GN

D7

1A

B1

9

GN

D7

2J1

9

GN

D7

3C

19

GN

D7

4R

20

GN

D7

5L

20

GN

D7

6H

20

GN

D7

7B

20

GN

D7

8U

21

GN

D7

9M

22

GN

D8

0H

22

GN

D8

1C

22

GN

D8

2W

23

GN

D8

3P

23

GN

D8

4K

23

GN

D8

5F

23

GN

D8

6J2

4

GN

D8

7E

24

GN

D8

8L

25

GN

D8

9G

25

GN

D9

0A

G2

6

GN

D9

1V

26

GN

D9

2R

26

GN

D9

3B

26

GN

D9

4A

F2

7

GN

D9

5M

27

GN

D9

6H

27

GN

D9

7C

27

GN

D9

8B

27

GN

D9

9K

28

0.1uFC1234

C1142

220uF, Tants

12

0.1uFC661

0.1uFC638

C960

10uF, 6.3V

0.1uFC1100

CO

RE

&P

LL

Su

pp

ly

U6

E

MP

C8

56

0

VD

D1

U1

2

VD

D2

R1

2

VD

D3

T1

3

VD

D4

P1

3

VD

D5

M1

3

VD

D6

U1

4

VD

D7

R1

4

VD

D8

N1

4

VD

D9

T1

5

VD

D10

P1

5

VD

D11

M1

5

VD

D12

R1

6

VD

D13

N1

6

VD

D14

T1

7

VD

D15

P1

7

VD

D16

M1

7

AV

dd

1A

H1

9

AV

dd

2A

H1

8

AV

dd

3A

H1

7

SE

NS

E_V

DD

L1

2

SE

NS

E_V

SS

K1

2

2.2uF

C301

0.1uFC646

2.2uF

C303



Schematics

Figure A-57. RapidIO Switch—Top Level

55

44

33

22

11

DD

CC

BB

AA

RIO

1_

TD

_N

[0:7

]

RIO

1_

RD

_N

[0:7

]

RIO

1_

TF

RA

ME

RIO

2_

RF

RA

ME

RIO

2_

TC

LK

RIO

2_

RC

LK

RIO

2_

TD

_N

[0:7

]

RIO

2_

TC

LK

_N

RIO

2_

RF

RA

ME

_N

RIO

2_

RC

LK

_N

RIO

2_

TF

RA

ME

_N

RIO

2_

TF

RA

ME

RIO

2_

TD

[0:7

]

RIO

3_

TF

RA

ME

RIO

3_

TD

_N

[0:7

]

RIO

3_

RC

LK

_N

RIO

3_

TC

LK

RIO

3_

TD

[0:7

]

RIO

3_

TF

RA

ME

_N

RIO

3_

RD

[0:7

]

RIO

3_

RD

_N

[0:7

]

RIO

3_

RF

RA

ME

_N

RIO

3_

RC

LK

RIO

3_

RF

RA

ME

RIO

3_

TC

LK

_N

DG

ND

tsi5

00

_V

DD

+2

.5V

tsi5

00

+3

.3V

DG

ND

+3

.3V

TS

I50

0_

LS

0_

CL

K

TS

I50

0_

INT

1_

NT

SI5

00

_IN

T0

_N

TS

I50

0_

HW

_R

ST

_N

TS

I50

0_

SW

_R

ST

_N

+3

.3V

DG

ND

+1

.2V

tsi5

00

+3

.3V

+1

.2V

tsi5

00

DG

ND

RIO

1_

RC

LK

RIO

1_

RF

RA

ME

RIO

1_

RC

LK

_N

RIO

0_

RF

RA

ME

_N

RIO

0_

RC

LK

_N

RIO

0_

TC

LK

RIO

0_

TF

RA

ME

_N

RIO

0_

TC

LK

_N

RIO

1_

RD

[0:7

]

RIO

1_

TD

[0:7

]

RIO

1_

TF

RA

ME

_N

RIO

0_

TD

_N

[0:7

]

RIO

1_

TC

LK

RIO

0_

RF

RA

ME

RIO

0_

RD

_N

[0:7

]

RIO

0_

RC

LK

RIO

0_

TD

[0:7

]

RIO

0_

RD

[0:7

]

RIO

1_

TC

LK

_N

RIO

0_

TF

RA

ME

RIO

1_

RF

RA

ME

_N

RIO

2_

RD

_N

[0:7

]

RIO

2_

RD

[0:7

]

TS

I50

0_

TX

CL

K_

IN_

NT

SI5

00

_T

XC

LK

_IN

+2

.5V

tsi5

00

TS

I50

0_

LS

1_

CL

K

+1

.2V

tsi5

00

DG

ND

tsi5

00

_V

DD

+2

.5V

tsi5

00

+3

.3V

+3

.3V

DG

ND

TS

I50

0_

LS

0_

CL

K

TS

I50

0_

HW

_R

ST

_N

DG

ND

+3

.3V

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+3

.3V

DG

ND

RIO

0_

TC

LK

_N

RIO

0_

TD

[0:7

]

RIO

0_

RF

RA

ME

_N

RIO

0_

RF

RA

ME

RIO

0_

TD

_N

[0:7

]

RIO

0_

RC

LK

_N

RIO

0_

TC

LK

RIO

0_

RD

_N

[0:7

]

RIO

0_

TF

RA

ME

_N

RIO

0_

RC

LK

RIO

0_

TF

RA

ME

RIO

0_

RD

[0:7

]

RIO

1_

RD

_N

[0:7

]

RIO

1_

RD

[0:7

]

RIO

1_

TD

[0:7

]

RIO

1_

TD

_N

[0:7

]

RIO

1_

TC

LK

_N

RIO

1_

TF

RA

ME

_N

RIO

1_

TC

LK

RIO

1_

TF

RA

ME

RIO

1_

RF

RA

ME

RIO

1_

RC

LK

RIO

1_

RF

RA

ME

_N

RIO

1_

RC

LK

_N

RIO

2_

RC

LK

RIO

2_

RD

_N

[0:7

]

RIO

2_

TC

LK

_N

RIO

2_

RD

[0:7

]

RIO

2_

TF

RA

ME

RIO

2_

RF

RA

ME

_N

RIO

2_

RC

LK

_N

RIO

2_

TF

RA

ME

_N

RIO

2_

TD

[0:7

]

RIO

2_

TD

_N

[0:7

]

RIO

2_

TC

LK

RIO

2_

RF

RA

ME

RIO

3_

RD

_N

[0:7

]

RIO

3_

RF

RA

ME

_N

RIO

3_

RC

LK

_N

RIO

3_

RD

[0:7

]

RIO

3_

RF

RA

ME

RIO

3_

RC

LK

RIO

3_

TC

LK

_N

RIO

3_

TD

[0:7

]

RIO

3_

TC

LK

RIO

3_

TD

_N

[0:7

]

RIO

3_

TF

RA

ME

RIO

3_

TF

RA

ME

_N

TS

I50

0_

INT

1_

NT

SI5

00

_IN

T0

_N

TS

I50

0_

SW

_R

ST

_N

TS

I50

0_

TX

CL

K_

INT

SI5

00

_T

XC

LK

_IN

_N

+2

.5V

tsi5

00

TS

I50

0_

LS

1_

CL

K

+1

.2V

tsi5

00

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Ra

pid

IO S

witc

h - T

op

Le

ve

l0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

59

72

Frid

ay, S

ep

tem

be

r 05

, 20

03

Pa

ge

63

RIO

Sw

itch

- Po

we

r

DG

ND

+3

.3V

+2

.5V

tsi5

00

tsi5

00_V

DD

Pa

ge

60

RIO

Sw

itch

- Po

rt 0 &

1

RIO

0_

TD

_N

[0:7

]

RIO

0_

TC

LK

RIO

0_R

D[0

:7]

RIO

0_

TD

[0:7

]

RIO

0_

RC

LK

_N

RIO

0_R

D_N

[0:7

]

RIO

0_

TC

LK

_N

RIO

0_

RC

LK

RIO

0_

TF

RA

ME

_N

RIO

0_T

FR

AM

E

RIO

0_R

FR

AM

ER

IO0_R

FR

AM

E_N

RIO

1_

TD

_N

[0:7

]

RIO

1_

TC

LK

RIO

1_R

D[0

:7]

RIO

1_

RC

LK

_N

RIO

1_

TD

[0:7

]

RIO

1_R

FR

AM

E_N

RIO

1_R

D_N

[0:7

]

RIO

1_

RC

LK

RIO

1_R

FR

AM

E

RIO

1_

TC

LK

_N

RIO

1_

TF

RA

ME

_N

RIO

1_T

FR

AM

E

+1

.2V

tsi5

00

+3

.3V

DG

ND

Pa

ge

62

RIO

Sw

itch

- Mis

c

TS

I50

0_

INT

1_

N

TS

I50

0_

LS

0_

CL

K

TS

I50

0_

INT

0_

N

TS

I50

0_

HW

_R

ST

_N

TS

I50

0_

SW

_R

ST

_N

+3

.3V

+1

.2V

tsi5

00

DG

ND

TS

I50

0_

TX

CL

K_

INT

SI5

00

_T

XC

LK

_IN

_N

+2

.5V

tsi5

00

TS

I50

0_

LS

1_

CL

K

Pa

ge

61

RIO

Sw

itch

- Po

rt 2 &

3

RIO

2_

TD

[0:7

]

RIO

2_

RC

LK

RIO

2_

RC

LK

_N

RIO

2_R

D[0

:7]

RIO

2_

TC

LK

_N

RIO

2_

TC

LK

RIO

2_

TD

_N

[0:7

]

RIO

2_R

D_N

[0:7

]

RIO

2_T

FR

AM

ER

IO2

_T

FR

AM

E_

N

RIO

2_R

FR

AM

ER

IO2_R

FR

AM

E_N

RIO

3_R

FR

AM

E

RIO

3_

RC

LK

RIO

3_

TD

_N

[0:7

]

RIO

3_R

FR

AM

E_N

RIO

3_

TD

[0:7

]

RIO

3_

TC

LK

_N

RIO

3_

RC

LK

_N

RIO

3_

TC

LK

RIO

3_

TF

RA

ME

_N

RIO

3_T

FR

AM

E

RIO

3_R

D[0

:7]

RIO

3_R

D_N

[0:7

]

+3

.3V

DG

ND

+1

.2V

tsi5

00



Figure A-58. RapidIO Switch—Ports 0 and 1

55

44

33

22

11

DD

CC

BB

AA

RIO

0_

RC

LK

RIO

0_

RC

LK

_N

RIO

0_

TF

RA

ME

RIO

0_

TF

RA

ME

_N

RIO

0_

TD

_N

7

RIO

0_

TD

4

RIO

0_

TD

_N

2R

IO0

_T

D2

RIO

0_

TD

_N

6

RIO

0_

TD

5R

IO0

_T

D_

N5

RIO

0_

TD

3R

IO0

_T

D_

N3

RIO

0_

TD

_N

1R

IO0

_T

D1

RIO

0_

TD

7

RIO

0_

TD

_N

4

RIO

0_

TD

6

RIO

0_

RF

RA

ME

RIO

0_

RF

RA

ME

_N

RIO

0_

RD

3

RIO

0_

RD

2

RIO

0_

RD

6

RIO

0_

RD

0

RIO

0_

RD

4R

IO0

_R

D_

N3

RIO

0_

RD

_N

5

RIO

0_

RD

_N

0

RIO

0_

RD

_N

1

RIO

0_

RD

_N

2

RIO

0_

RD

_N

6

RIO

0_

RD

1

RIO

0_

RD

5R

IO0

_R

D_

N4

RIO

1_

TD

_N

6

RIO

1_

RC

LK

RIO

1_

TD

_N

3

RIO

1_

TD

4

RIO

1_

TD

0

RIO

1_

RC

LK

_N

RIO

1_

RF

RA

ME

RIO

1_

TC

LK

RIO

1_

TD

_N

2R

IO1

_T

D_

N1

RIO

1_

TD

6

RIO

1_

TD

3

RIO

1_

TD

_N

0

RIO

1_

RF

RA

ME

_N

RIO

1_

TD

1

RIO

1_

TD

_N

4

RIO

1_

TC

LK

_N

RIO

1_

TD

_N

7

RIO

1_

TD

5

RIO

1_

TD

2

RIO

1_

TD

7

RIO

1_

TD

_N

5

RIO

1_

TF

RA

ME

RIO

1_

TF

RA

ME

_N

RIO

1_

TD

_N

1R

IO1

_T

D1

RIO

1_

TD

5

RIO

1_

TD

2

RIO

1_

TD

_N

7

RIO

1_

TD

_N

4

RIO

1_

TD

6R

IO1

_T

D_

N5

RIO

1_

TD

0

RIO

1_

TD

_N

6R

IO1

_T

D7

RIO

1_

TD

_N

0

RIO

1_

TD

4

RIO

1_

TD

3R

IO1

_T

D_

N3

RIO

1_

TD

_N

2R

IO1

_R

D2

RIO

1_

RD

_N

2

RIO

1_

RD

_N

6R

IO1

_R

D6

RIO

1_

RD

7

RIO

1_

RD

_N

0

RIO

1_

RD

4

RIO

1_

RD

0

RIO

1_

RD

_N

3

RIO

1_

RD

_N

7

RIO

1_

RD

1R

IO1

_R

D_

N1

RIO

1_

RD

_N

4

RIO

1_

RD

3

RIO

1_

RD

3

RIO

1_

RD

5

RIO

1_

RD

2

RIO

1_

RD

4

RIO

1_

RD

_N

5

RIO

1_

RD

_N

5

RIO

1_

RD

5

RIO

1_

RD

_N

1

RIO

1_

RD

1

RIO

1_

RD

_N

2R

IO1

_R

D_

N3

RIO

1_

RD

_N

4

RIO

1_

RD

_N

7

RIO

1_

RD

0

RIO

1_

RD

7

RIO

1_

RD

_N

6

RIO

1_

RD

_N

0

RIO

1_

RD

6

RIO

0_

TC

LK

_N

RIO

0_

TC

LK

+1

.2V

tsi5

00

+3

.3V

DG

ND

RIO

0_

TD

3R

IO0

_R

D4

RIO

0_

TD

_N

0

RIO

0_

RD

6R

IO0

_R

D7

RIO

0_

TD

7

RIO

0_

TD

0

RIO

0_

RD

2R

IO0

_R

D1

RIO

0_

TD

4R

IO0

_R

D3

RIO

0_

TD

5

RIO

0_

TD

2

RIO

0_

RD

0

RIO

0_

TD

6

RIO

0_

TD

1

RIO

0_

TD

0

RIO

0_

RD

5

RIO

0_

RD

_N

7

RIO

0_

RD

_N

2

RIO

0_

RD

_N

5

RIO

0_

TD

_N

7

RIO

0_

TD

_N

1

RIO

0_

TD

_N

6

RIO

0_

RD

_N

4

RIO

0_

RD

_N

7

RIO

0_

RD

_N

3

RIO

0_

RD

_N

1R

IO0

_T

D_

N0

RIO

0_

TD

_N

2

RIO

0_

TD

_N

4

RIO

0_

RD

_N

0

RIO

0_

RD

_N

6

RIO

0_

RD

7

RIO

0_

TD

_N

3

RIO

0_

TD

_N

5

RIO

0_

TD

_N

[0:7

]R

IO0

_T

CL

K

RIO

0_

RD

[0:7

]R

IO0

_T

D[0

:7]

RIO

0_

RC

LK

_N

RIO

0_

RD

_N

[0:7

]R

IO0

_T

CL

K_

NR

IO0

_R

CL

KR

IO0

_T

FR

AM

E_

NR

IO0

_T

FR

AM

ER

IO0

_R

FR

AM

ER

IO0

_R

FR

AM

E_

N

RIO

1_

TD

_N

[0:7

]R

IO1

_T

CL

K

RIO

1_

RD

[0:7

]

RIO

1_

RC

LK

_N

RIO

1_

TD

[0:7

]

RIO

1_

RF

RA

ME

_N

RIO

1_

RD

_N

[0:7

]R

IO1

_R

CL

K

RIO

1_

RF

RA

ME

RIO

1_

TC

LK

_N

RIO

1_

TF

RA

ME

_N

RIO

1_

TF

RA

ME

+1

.2V

tsi5

00

+3

.3V

DG

ND

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+1

.2V

tsi5

00

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Ra

pid

IO S

witc

h - P

ort 0

& 1

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

60

72

Tu

esd

ay, S

ep

tem

be

r 30

, 20

03

Power

Bulk Decoupling

C2

45

0.1

uF

C2

42

0.1

uF

PORT 0

TSi500

U4

A

TS

i50

0

P0

_R

FR

AM

E_

pV

2

P0

_R

FR

AM

E_

nV

3

P0

_R

CL

K_

pA

C2

P0

_R

CL

K_

nA

C3

P0

_R

D_

p(0

)A

G2

P0

_R

D_

n(0

)A

G3

P0

_R

D_

p(1

)A

F2

P0

_R

D_

n(1

)A

F3

P0

_R

D_

p(2

)A

E2

P0

_R

D_

n(2

)A

E3

P0

_R

D_

p(3

)A

D2

P0

_R

D_

n(3

)A

D3

P0

_R

D_

p(4

)A

B2

P0

_R

D_

n(4

)A

B3

P0

_R

D_

p(5

)A

A2

P0

_R

D_

n(5

)A

A3

P0

_R

D_

p(6

)Y

2

P0

_R

D_

n(6

)Y

3

P0

_R

D_

p(7

)W

2

P0

_R

D_

n(7

)W

3

P0

_T

FR

AM

E_

pU

3

P0

_T

FR

AM

E_

nU

2

P0

_T

CL

K_

pM

3

P0

_T

CL

K_

nM

2

P0

_T

D_

p(0

)H

3

P0

_T

D_

n(0

)H

2

P0

_T

D_

p(1

)J3

P0

_T

D_

n(1

)J2

P0

_T

D_

p(2

)K

3

P0

_T

D_

n(2

)K

2

P0

_T

D_

p(3

)L

3

P0

_T

D_

n(3

)L

2

P0

_T

D_

p(4

)N

3

P0

_T

D_

n(4

)N

2

P0

_T

D_

p(5

)P

3

P0

_T

D_

n(5

)P

2

P0

_T

D_

p(6

)R

3

P0

_T

D_

n(6

)R

2

P0

_T

D_

p(7

)T

3

P0

_T

D_

n(7

)T

2

P0_CLK_SEL(1)F1

P0_CLK_SEL(0)F3

P0_DVDDAJ1

P0_DVSSAL1

P0_AVDDAK1

P0_AVSSAK2

C1189

220uF, Tants

12

PORT 1

TSi500

U4

B

TS

i50

0

P1

_R

FR

AM

E_

pA

N18

P1

_R

FR

AM

E_

nA

M1

8

P1

_R

CL

K_

pA

N23

P1

_R

CL

K_

nA

M2

3

P1

_R

D_

p(0

)A

N27

P1

_R

D_

n(0

)A

M2

7

P1

_R

D_

p(1

)A

N26

P1

_R

D_

n(1

)A

M2

6

P1

_R

D_

p(2

)A

N25

P1

_R

D_

n(2

)A

M2

5

P1

_R

D_

p(3

)A

N24

P1

_R

D_

n(3

)A

M2

4

P1

_R

D_

p(4

)A

N22

P1

_R

D_

n(4

)A

M2

2

P1

_R

D_

p(5

)A

N21

P1

_R

D_

n(5

)A

M2

1

P1

_R

D_

p(6

)A

N20

P1

_R

D_

n(6

)A

M2

0

P1

_R

D_

p(7

)A

N19

P1

_R

D_

n(7

)A

M1

9

P1

_T

FR

AM

E_

pA

M1

7

P1

_T

FR

AM

E_

nA

N1

7

P1

_T

CL

K_

pA

M1

2

P1

_T

CL

K_

nA

N12

P1

_T

D_

p(0

)A

M8

P1

_T

D_

n(0

)A

N8

P1

_T

D_

p(1

)A

M9

P1

_T

D_

n(1

)A

N9

P1

_T

D_

p(2

)A

M1

0

P1

_T

D_

n(2

)A

N10

P1

_T

D_

p(3

)A

M1

1

P1

_T

D_

n(3

)A

N11

P1

_T

D_

p(4

)A

M1

3

P1

_T

D_

n(4

)A

N13

P1

_T

D_

p(5

)A

M1

4

P1

_T

D_

n(5

)A

N14

P1

_T

D_

p(6

)A

M1

5

P1

_T

D_

n(6

)A

N15

P1

_T

D_

p(7

)A

M1

6

P1

_T

D_

n(7

)A

N16

P1_CLK_SEL(1)F2

P1_CLK_SEL(0)E1

P1_DVDDAP29

P1_DVSSAP30

P1_AVDDAN29

P1_AVSSAM29

L7

47

0n

H

R2

04

0R

+C

24

31

0u

F,6

.3V

Ta

nts

JP

9

12

L8

47

0n

H

R2

08

0R

R2

05

10

K

C2

47

0.1

uF

C2

44

0.1

uF

R2

01

10

K

JP

10

12

JP

11

12

R2

06

10

K

+C

24

61

0u

F,6

.3V

Ta

nts

JP

8

12

R2

02

10

K

R2

03

2R

2

R2

07

2R

2



Schematics

Figure A-59. RapidIO Switch—Ports 2 and 3

55

44

33

22

11

DD

CC

BB

AA

RIO

2_

RC

LK

RIO

2_

TC

LK

_N

RIO

2_

RC

LK

_N

RIO

2_

TC

LK

RIO

2_

TD

2

RIO

2_

TD

3

RIO

2_

TD

_N

4R

IO2

_T

D4

RIO

2_

TD

6

RIO

2_

TD

_N

7R

IO2

_T

D7

RIO

2_

TD

_N

2

RIO

2_

TD

_N

6

RIO

2_

TD

5

RIO

2_

TD

_N

3

RIO

2_

TD

_N

5

RIO

2_

TD

_N

1

RIO

2_

TD

0

RIO

2_

RD

2R

IO2

_R

D_

N1

RIO

2_

RD

_N

4

RIO

2_

RD

6

RIO

2_

RD

_N

2

RIO

2_

RD

0

RIO

2_

RD

_N

6

RIO

2_

RD

4

RIO

2_

RD

_N

0R

IO2

_R

D1

RIO

2_

TF

RA

ME

RIO

2_

TF

RA

ME

_N

RIO

2_

TD

_N

0

RIO

2_

TD

4R

IO2

_T

D3

RIO

2_

TD

0

RIO

2_

TD

7

RIO

2_

TD

1

RIO

2_

TD

5

RIO

2_

TD

1

RIO

2_

TD

2

RIO

2_

TD

6

RIO

2_

RF

RA

ME

_N

RIO

2_

RF

RA

ME

RIO

2_

RD

_N

7R

IO2

_R

D7

RIO

3_

TD

0

RIO

3_

TD

_N

1

RIO

3_

TC

LK

RIO

3_

RF

RA

ME

RIO

3_

TD

_N

6R

IO3

_T

D_

N5

RIO

3_

RF

RA

ME

_N

RIO

3_

TD

5

RIO

3_

TD

_N

2

RIO

3_

TD

4

RIO

3_

TD

_N

4

RIO

3_

RC

LK

_N

RIO

3_

TD

1

RIO

3_

TD

7

RIO

3_

TD

2

RIO

3_

TD

_N

0

RIO

3_

TD

3

RIO

3_

RC

LK

RIO

3_

TC

LK

_N

RIO

3_

TD

_N

7

RIO

3_

TD

_N

3

RIO

3_

TD

6

RIO

3_

TD

0

RIO

3_

TD

_N

3R

IO3

_T

D4

RIO

3_

TD

_N

4

RIO

3_

TD

7

RIO

3_

TD

_N

1

RIO

3_

TD

_N

7

RIO

3_

TD

_N

0R

IO3

_T

D1

RIO

3_

TD

_N

6R

IO3

_T

D6

RIO

3_

TD

_N

2

RIO

3_

TD

5R

IO3

_T

D_

N5

RIO

3_

TD

3

RIO

3_

TD

2

RIO

3_

RD

6

RIO

3_

RD

5

RIO

3_

RD

_N

6

RIO

3_

RD

_N

1

RIO

3_

RD

_N

2

RIO

3_

RD

_N

7R

IO3

_R

D7

RIO

3_

RD

2

RIO

3_

RD

_N

0

RIO

3_

RD

3R

IO3

_R

D_

N3

RIO

3_

RD

_N

4

RIO

3_

RD

_N

5

RIO

3_

RD

4

RIO

3_

RD

1

RIO

3_

TF

RA

ME

RIO

3_

TF

RA

ME

_N

RIO

3_

RD

0

RIO

3_

RD

_N

6

RIO

3_

RD

2

RIO

3_

RD

_N

1

RIO

3_

RD

1

RIO

3_

RD

5

RIO

3_

RD

_N

5

RIO

3_

RD

7

RIO

3_

RD

_N

0

RIO

3_

RD

6

RIO

3_

RD

_N

2

RIO

3_

RD

_N

7

RIO

3_

RD

_N

3R

IO3

_R

D_

N4

RIO

3_

RD

0

RIO

3_

RD

4R

IO3

_R

D3

RIO

2_

RD

5

RIO

2_

RD

1

RIO

2_

RD

3R

IO2

_R

D2

RIO

2_

RD

7

RIO

2_

RD

0

RIO

2_

RD

4

RIO

2_

RD

6

RIO

2_

RD

_N

3R

IO2

_R

D3

+3

.3V

+1

.2V

tsi5

00

DG

ND

RIO

2_

TD

_N

5R

IO2

_R

D_

N6

RIO

2_

RD

_N

1

RIO

2_

RD

_N

7

RIO

2_

TD

_N

4

RIO

2_

TD

_N

6

RIO

2_

RD

_N

0R

IO2

_T

D_

N0

RIO

2_

RD

_N

5

RIO

2_

RD

_N

2R

IO2

_T

D_

N2

RIO

2_

TD

_N

1

RIO

2_

RD

_N

5R

IO2

_R

D5

RIO

2_

RD

_N

4R

IO2

_R

D_

N3

RIO

2_

TD

_N

7

RIO

2_

TD

_N

3

RIO

2_

TD

[0:7

]

RIO

2_

RC

LK

RIO

2_

RC

LK

_N

RIO

2_

RD

[0:7

]

RIO

2_

TC

LK

_N

RIO

2_

TC

LK

RIO

2_

TD

_N

[0:7

]R

IO2

_R

D_

N[0

:7]

RIO

2_

TF

RA

ME

RIO

2_

TF

RA

ME

_N

RIO

2_

RF

RA

ME

RIO

2_

RF

RA

ME

_N

RIO

3_

RF

RA

ME

RIO

3_

RC

LK

RIO

3_

TD

_N

[0:7

]R

IO3

_R

FR

AM

E_

N

RIO

3_

TD

[0:7

]

RIO

3_

TC

LK

_N

RIO

3_

RC

LK

_N

RIO

3_

TC

LK

RIO

3_

TF

RA

ME

_N

RIO

3_

TF

RA

ME

RIO

3_

RD

[0:7

]

RIO

3_

RD

_N

[0:7

]

+3

.3V

DG

ND

+1

.2V

tsi5

00

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+1

.2V

tsi5

00

+3

.3V

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+1

.2V

tsi5

00

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Ra

pid

IO S

witc

h - P

ort 2

& 3

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

61

72

Tu

esd

ay, S

ep

tem

be

r 30

, 20

03

Power

Bulk Decoupling

R2

3

2R

2

C9

0.1

uF

R2

11

0K

R1

9

2R

2

JP

2

12

L2

47

0n

H

R2

21

0K

+C

81

0u

F,6

.3V

Ta

nts

PORT 2

TSi500

U4

C

TS

i50

0

P2

_R

FR

AM

E_

pU

33

P2

_R

FR

AM

E_

nU

32

P2

_R

CL

K_

pM

33

P2

_R

CL

K_

nM

32

P2

_R

D_

p(0

)H

33

P2

_R

D_

n(0

)H

32

P2

_R

D_

p(1

)J3

3

P2

_R

D_

n(1

)J3

2

P2

_R

D_

p(2

)K

33

P2

_R

D_

n(2

)K

32

P2

_R

D_

p(3

)L

33

P2

_R

D_

n(3

)L

32

P2

_R

D_

p(4

)N

33

P2

_R

D_

n(4

)N

32

P2

_R

D_

p(5

)P

33

P2

_R

D_

n(5

)P

32

P2

_R

D_

p(6

)R

33

P2

_R

D_

n(6

)R

32

P2

_R

D_

p(7

)T

33

P2

_R

D_

n(7

)T

32

P2

_T

FR

AM

E_

pV

32

P2

_T

FR

AM

E_

nV

33

P2

_T

CL

K_

pA

C32

P2

_T

CL

K_

nA

C33

P2

_T

D_

p(0

)A

G3

2

P2

_T

D_

n(0

)A

G3

3

P2

_T

D_

p(1

)A

F3

2

P2

_T

D_

n(1

)A

F3

3

P2

_T

D_

p(2

)A

E3

2

P2

_T

D_

n(2

)A

E3

3

P2

_T

D_

p(3

)A

D32

P2

_T

D_

n(3

)A

D33

P2

_T

D_

p(4

)A

B3

2

P2

_T

D_

n(4

)A

B3

3

P2

_T

D_

p(5

)A

A3

2

P2

_T

D_

n(5

)A

A3

3

P2

_T

D_

p(6

)Y

32

P2

_T

D_

n(6

)Y

33

P2

_T

D_

p(7

)W

32

P2

_T

D_

n(7

)W

33

P2_CLK_SEL(1)B4

P2_CLK_SEL(0)D3

P2_DVDDF34

P2_DVSSE34

P2_AVDDF33

P2_AVSSF32

C1

0

0.1

uF

JP

1

12

JP

3

12

PORT 3

TSi500

U4

D

TS

i50

0

P3

_R

FR

AM

E_

pB

17

P3

_R

FR

AM

E_

nC

17

P3

_R

CL

K_

pB

12

P3

_R

CL

K_

nC

12

P3

_R

D_

p(0

)B

8

P3

_R

D_

n(0

)C

8

P3

_R

D_

p(1

)B

9

P3

_R

D_

n(1

)C

9

P3

_R

D_

p(2

)B

10

P3

_R

D_

n(2

)C

10

P3

_R

D_

p(3

)B

11

P3

_R

D_

n(3

)C

11

P3

_R

D_

p(4

)B

13

P3

_R

D_

n(4

)C

13

P3

_R

D_

p(5

)B

14

P3

_R

D_

n(5

)C

14

P3

_R

D_

p(6

)B

15

P3

_R

D_

n(6

)C

15

P3

_R

D_

p(7

)B

16

P3

_R

D_

n(7

)C

16

P3

_T

FR

AM

E_

pC

18

P3

_T

FR

AM

E_

nB

18

P3

_T

CL

K_

pC

23

P3

_T

CL

K_

nB

23

P3

_T

D_

p(0

)C

27

P3

_T

D_

n(0

)B

27

P3

_T

D_

p(1

)C

26

P3

_T

D_

n(1

)B

26

P3

_T

D_

p(2

)C

25

P3

_T

D_

n(2

)B

25

P3

_T

D_

p(3

)C

24

P3

_T

D_

n(3

)B

24

P3

_T

D_

p(4

)C

22

P3

_T

D_

n(4

)B

22

P3

_T

D_

p(5

)C

21

P3

_T

D_

n(5

)B

21

P3

_T

D_

p(6

)C

20

P3

_T

D_

n(6

)B

20

P3

_T

D_

p(7

)C

19

P3

_T

D_

n(7

)B

19

P3_CLK_SEL(1)A4

P3_CLK_SEL(0)B5

P3_DVDDA6

P3_DVSSA5

P3_AVDDB6

P3_AVSSC6

R1

81

0K

L1

47

0n

H

R2

4

0R

C1188

220uF, Tants

12

C1

2

0.1

uF

JP

4

12

R2

0

0R

+C

11

10

uF

,6.3

V T

an

ts

R1

71

0K

C7

0.1

uF



Figure A-60. RapidIO Switch—Misc

55

44

33

22

11

DD

CC

BB

AA

TS

I50

0_

LS

0_

CL

K

TS

I50

0_

HW

_R

ST

_N

TS

I50

0_

SW

_R

ST

_N

TS

I50

0_

INT

1_

N

TS

I50

0_

INT

0_

N

+3

.3V

DG

ND

+1

.2V

tsi5

00

TS

I50

0_

TX

CL

K_

IN_

N

TS

I50

0_

TX

CL

K_

IN

+2

.5V

tsi5

00

TS

I50

0_

LS

1_

CL

K

TS

I50

0_

INT

1_

N

TS

I50

0_

LS

0_

CL

K

TS

I50

0_

INT

0_

N

TS

I50

0_

HW

_R

ST

_N

+3

.3V

+1

.2V

tsi5

00

DG

ND

TS

I50

0_

SW

_R

ST

_N

TS

I50

0_

TX

CL

K_

IN

TS

I50

0_

TX

CL

K_

IN_

N

+2

.5V

tsi5

00

TS

I50

0_

LS

1_

CL

K

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+1

.2V

tsi5

00

+1

.2V

tsi5

00

+3

.3V

+2

.5V

tsi5

00

+2

.5V

tsi5

00

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Ra

pid

IO S

witc

h - M

isc

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

62

72

Frid

ay, S

ep

tem

be

r 05

, 20

03

Power

Do Not Fit

Interrupt pull ups on processor page.

R3

51

0K

X3

8-P

in D

IP S

ocke

t

R2

5

10

K

R2

6

10

K

R2

7

10

K

JP

6

12

TP

11

R3910K

C1

3

0.1

uF

R3674K7

R2

9

2R

2

JP

5

12H

D1

2x5

He

ad

er

13579

24681

0

L3

47

0n

H

R4010K

TSi500

Misc

U4

G

TS

i50

0

INT

(0)

E2

INT

(1)

C4

JT

_T

DI

C2

9

JT

_T

CK

B3

0

JT

_T

MS

B2

9

JT

_T

RS

T_

BA

30

JT

_T

DO

A2

9

RE

SE

RV

E1

AN

30

RE

SE

RV

E2

AM

31

RE

SE

RV

E3

AP

31

RE

SE

RV

E4

AJ3

4

RE

SE

RV

E5

AJ3

2

RE

SE

RV

E6

D3

4

BO

OT

UP

_D

ISA

BL

E_

BA

K3

3

SW

_R

ST

AJ3

3

HA

RD

_R

ST

_B

AK

34

HS

PLL_D

VD

DA

M4

HS

PLL_D

GN

DA

N4

HS

PLL_A

VD

DA

L2

HS

PLL_A

GN

DA

L3

HS

PLL_B

YP

AS

S_C

LK

_p

AJ2

HS

PLL_B

YP

AS

S_C

LK

_n

AJ3

HS

PL

L_

RA

NG

E_

SE

L(0

)A

M6

HS

PL

L_

RA

NG

E_

SE

L(1

)A

P6

LS

1_

CL

KA

P5

LS

0_

CL

KA

N6

CO

RE

_C

LK

_S

EL

(1)

AN

31

CO

RE

_C

LK

_S

EL

(0)

AL

32

TM

_D

OC

31

TM

_D

ID

32

I2C

_S

CL

KD

33

I2C

_S

DA

E3

3

C1

5

0.1

uF

R3

0

0R

+C

14

10

uF

,6.3

V T

an

ts

TP

12

R3664K7

R3

3

10

K

R3

2

10

K

C1

6

0.1

uF

R3684K7

R3

1

10

K

R2

8

10

K

U5

EE

PR

OM

GN

D4

VC

C8

A0

1A

12

A2

3

WP

7

SD

A5

SC

L6

R3

71

0K

R3810K

SW

1

SW

DIP

-4

1234

8765

R3

61

0K

R3

4

10

K



Schematics

Figure A-61. RapidIO Switch—Power

55

44

33

22

11

DD

CC

BB

AA

DG

ND

tsi5

00

_V

DD

+3

.3V

+2

.5V

tsi5

00

DG

ND

+3

.3V

+2

.5V

tsi5

00

tsi5

00

_V

DD

+2

.5V

tsi5

00

+3

.3V

tsi5

00

_V

DD

+3

.3V

+3

.3V

+2

.5V

tsi5

00

+2

.5V

tsi5

00

+2

.5V

tsi5

00

+2

.5V

tsi5

00

+2

.5V

tsi5

00

+2

.5V

tsi5

00

+2

.5V

tsi5

00+2

.5V

tsi5

00

tsi5

00

_V

DD

tsi5

00

_V

DD

tsi5

00

_V

DD

tsi5

00

_V

DD

tsi5

00

_V

DD

tsi5

00

_V

DD

+3

.3V

+3

.3V

tsi5

00

_V

DD

tsi5

00

_V

DD

+2

.5V

tsi5

00

+2

.5V

tsi5

00

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Ra

pid

IO S

witc

h - P

ow

er

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

63

72

Mo

nd

ay, S

ep

tem

be

r 29

, 20

03

Power

Decoupling

Decoupling

Bulk DecouplingBulk DecouplingBulk Decoupling

C1

58

0.0

47

uF

C1

92

22

00

pF

C1

47

0.1

uF

C1

81

22

00

pF

C1

75

22

00

pF

C1

65

22

00

pF

C2

07

0.1

uF

C1

66

22

00

pF

C1

72

22

00

pF

C2

09

0.1

uF

C2

06

0.1

uF

C1

74

22

00

pF

C1

95

22

00

pF

C2

19

0.1

uF

C1

49

0.1

uF

C2

18

0.1

uF

C1

48

0.1

uF

C2

17

0.1

uF

C1

96

22

00

pF

C1

88

0.1

uF

C1

59

0.0

47

uF

C1

87

0.1

uF

C2

01

22

00

pF

C2

14

0.1

uF

C2

22

0.1

uF

C2

21

0.1

uF

C1

85

0.1

uF

C1

77

22

00

pF

C1

80

22

00

pF

C2

27

0.1

uF

C1

55

0.1

uF

C1

83

0.1

uF

U3

4

MA

X6520

VO

UT

2

VIN

1

EN

D3

C1

60

22

00

pF

C2

04

0.1

uF

C1

54

0.1

uF

C1

69

22

00

pF

C2

29

0.1

uF

C1

90

0.1

uF

C1

71

22

00

pF

C2

26

0.1

uF

C2

32

0.1

uF

C1

73

22

00

pF

C2

30

0.1

uF

C1

63

22

00

pF

C2

28

0.1

uF

C2

13

0.1

uF

C2

36

0.1

uF

C2

16

0.1

uF

C2

15

0.1

uF

C1

67

22

00

pF

C1

56

0.0

47

uF

C1

64

22

00

pF

C2

39

0.1

uF

C2

08

0.1

uF

C1

86

0.1

uF

U3

6

MA

X6520

VO

UT

2

VIN

1

EN

D3

C2

10

0.1

uF

C2

24

0.1

uF

C2

34

0.1

uF

TSi500

IO Power

U4

F

TS

i50

0

P3_IO

_V

DD

A2

5

P3_IO

_V

DD

A2

3

P3_IO

_V

DD

A2

1

P3_IO

_V

DD

A1

9

P3_IO

_V

DD

A1

7

P3_IO

_V

DD

A1

5

P3_IO

_V

DD

A1

3

P3_IO

_V

DD

A1

1

P2_IO

_V

DD

W3

4

P2_IO

_V

DD

AA

34

P2_IO

_V

DD

AC

34

P2_IO

_V

DD

AE

34

P2_IO

_V

DD

U3

4

P2_IO

_V

DD

R3

4

P2_IO

_V

DD

N3

4

P2_IO

_V

DD

L3

4

P1_IO

_V

DD

AP

24

P1_IO

_V

DD

AP

22

P1_IO

_V

DD

AP

20

P1_IO

_V

DD

AP

18

P1_IO

_V

DD

AP

16

P1_IO

_V

DD

AP

14

P1_IO

_V

DD

AP

12

P1_IO

_V

DD

AP

10

P0_IO

_V

DD

M1

P0_IO

_V

DD

T1

P0_IO

_V

DD

V1

P0_IO

_V

DD

Y1

P0_IO

_V

DD

AB

1

P0_IO

_V

DD

AD

1

P0_IO

_V

DD

P1

P0_IO

_V

DD

K1

P3

_IO

_V

SS

D2

5

P3

_IO

_V

SS

D2

3

P3

_IO

_V

SS

D2

1

P3

_IO

_V

SS

D1

9

P3

_IO

_V

SS

D1

5

P3

_IO

_V

SS

D1

3

P3

_IO

_V

SS

D1

1

P2

_IO

_V

SS

N3

1

P2

_IO

_V

SS

L3

1

P2

_IO

_V

SS

R3

1

P2

_IO

_V

SS

AC

31

P2

_IO

_V

SS

AE

31

P2

_IO

_V

SS

AA

31

P2

_IO

_V

SS

W3

1

P1

_IO

_V

SS

AL

24

P1

_IO

_V

SS

AL

22

P1

_IO

_V

SS

AL

20

P1

_IO

_V

SS

AL

16

P1

_IO

_V

SS

AL

14

P1

_IO

_V

SS

AL

12

P1

_IO

_V

SS

AL

10

P0

_IO

_V

SS

AB

4

P0

_IO

_V

SS

AD

4

P0

_IO

_V

SS

Y4

P0

_IO

_V

SS

T4

P0

_IO

_V

SS

P4

P0

_IO

_V

SS

K4

P0

_IO

_V

SS

M4

P0_V

RE

FV

4

P1_V

RE

FA

L1

8

P2_V

RE

FU

31

P3_V

RE

FD

17

C1

44

0.1

uF

U3

7

MA

X6520

VO

UT

2

VIN

1

EN

D3

C1

82

0.1

uF

C2

35

0.1

uF

U3

5

MA

X6520

VO

UT

2

VIN

1

EN

D3

C1

45

0.1

uF

C2

05

0.1

uF

C1

89

0.1

uF

TSi500

Power and Ground

U4

E

TS

i50

0

GNDAF4

GNDAF1

GNDJ34

GNDJ31

GNDH4

GNDH1

GNDG34

GNDG31

GNDD31

GNDD27

GNDD4

GNDD9

GNDD7

GNDC34

GNDC1

GNDC3

GNDC32

GNDB34

GNDB33

GNDB2

GNDB1

GNDA34

GNDA33

GNDA32

GNDA27

GNDA9

GNDA7

GNDA3

GNDA2

GNDA1

VDDA28

VDDB3

VDDB7

VDDB28

VDDB32

VDDC2

VDDC5

VDDC7

VDDC33

VDDD5

VDDD6

VDDC28

VDDC30

VDDD28

VDDD29

VDDD30

VDDE3

VDDE4

VDDE31

VDDE32

VDDF4

VDDF31

VDDG1

VDDG2

VDDG3

VDDG4

VDDG32

VDDG33

VDDAH2

VDDAH3

VD

DA

H3

1

VD

DA

H3

2

VD

DA

H3

3

VD

DA

H3

4

VD

DA

J4

VD

DA

J3

1

VD

DA

K3

VD

DA

K3

1

VD

DA

K3

2

VD

DA

L5

VD

DA

L6

VD

DA

L7

VD

DA

L2

9

VD

DA

L3

0

VD

DA

M2

VD

DA

M5

VD

DA

M7

VD

DA

M2

8

VD

DA

M3

0

VD

DA

M3

3

VD

DA

N7

VD

DA

N2

8

VD

DA

N3

2

VD

DA

P7

VD

DA

N3

VD

DA

K4

GN

DA

G3

1

GN

DA

P3

4

GN

DA

P3

3

GN

DA

P3

2

GN

DA

P2

8

GN

DA

P2

6

GN

DA

P8

GN

DA

P3

GN

DA

P2

GN

DA

P1

GN

DA

N3

4

GN

DA

N3

3

GN

DA

N2

GN

DA

N1

GN

DA

M3

4

GN

DA

M3

2

GN

DA

M3

GN

DA

M1

GN

DA

L3

1

GN

DA

L2

8

GN

DA

L2

6

GN

DA

L8

GN

DA

L4

GN

DA

H4

GN

DA

H1

GN

DA

G3

4

VS

SO

AN

5

VS

SO

AL

34

VS

SO

B3

1

VS

SO

D1

VD

DO

AP

4

VD

DO

AL

33

VD

DO

D2

VD

DO

A3

1

C1185

220uF, Tants

12

C2

20

0.1

uF

C2

25

0.1

uF

C2

38

0.1

uF

C2

23

0.1

uF

C2

37

0.1

uF

C2

11

0.1

uF

C1

57

0.0

47

uF

C1

99

22

00

pF

C1

70

22

00

pF

C1183

220uF, Tants

12

C2

40

0.1

uF

C2

00

22

00

pF

C1

46

0.1

uF

C1181

220uF, Tants

12

C1

97

22

00

pF

C1

51

0.1

uF

C2

03

0.1

uF

C2

31

0.1

uF

C1

68

22

00

pF

C1

98

22

00

pF

C1

79

22

00

pF

C1

62

22

00

pF

C1186

220uF, Tants

12

C1

50

0.1

uF

C1184

220uF, Tants

12

C2

02

0.1

uF

C2

33

0.1

uF

C1

53

0.1

uF

C1

52

0.1

uF

C1

76

22

00

pF

C1182

220uF, Tants

12

C1

78

22

00

pF

C2

12

0.1

uF

C1

84

0.1

uF

C1

93

22

00

pF

C2

41

0.1

uF

C1

61

22

00

pF

C1

91

0.1

uF

C1

94

22

00

pF



Figure A-62. Clocking—Top Level

55

44

33

22

11

DD

CC

BB

AA

WP

1_

SY

S_

CL

K

WP

1_

RT

C_

CL

K

BP

_S

YS

_C

LK

WP

2_

RT

C_

CL

K

PC

I_C

LK

WP

3_

RT

C_

CL

K

WP

3_

SY

S_

CL

K

BP

_R

TC

_C

LK

WP

2_

SY

S_

CL

K

LA

_C

LK

DG

ND

+3

.3V

TS

I50

0_

TX

CL

K_

IN_

NT

SI5

00

_T

XC

LK

_IN

RIO

3_

TX

CL

K_

IN_

NR

IO3

_T

XC

LK

_IN

RIO

1_

TX

CL

K_

IN_

N

TS

I50

0_

LS

1_

CL

K

RIO

0_

TX

CL

K_

IN

RIO

1_

TX

CL

K_

IN

RIO

2_

TX

CL

K_

IN

TS

I50

0_

LS

0_

CL

K

RIO

2_

TX

CL

K_

IN_

N

RIO

0_

TX

CL

K_

IN_

N

+3

.3V

DG

ND

VIA

_C

LK

WP

3_

SY

S_

CL

K

WP

1_

SY

S_

CL

KW

P2

_S

YS

_C

LK

WP

2_

RT

C_

CL

K

BP

_R

TC

_C

LK

BP

_S

YS

_C

LK

WP

1_

RT

C_

CL

K

PC

I_C

LK

LA

_C

LK

WP

3_

RT

C_

CL

K

DG

ND

+3

.3V

RIO

0_

TX

CL

K_

IN_

NR

IO0

_T

XC

LK

_IN

RIO

3_

TX

CL

K_

IN

TS

I50

0_

TX

CL

K_

IN_

N

RIO

1_

TX

CL

K_

IN_

N

RIO

2_

TX

CL

K_

IN

RIO

1_

TX

CL

K_

IN

RIO

3_

TX

CL

K_

IN_

N

TS

I50

0_

TX

CL

K_

IN

RIO

2_

TX

CL

K_

IN_

N

TS

I50

0_

LS

1_

CL

KT

SI5

00

_L

S0

_C

LK

+3

.3V

DG

ND

VIA

_C

LK

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Clo

ckin

g - T

op

Le

ve

l0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

64

72

Mo

nd

ay, S

ep

tem

be

r 29

, 20

03

Pa

ge

65

Clo

ckin

g - P

roce

sso

r

BP

_S

YS

_C

LK

+3

.3V

WP

3_

RT

C_

CL

KW

P2

_R

TC

_C

LK

WP

1_

SY

S_

CL

K

WP

3_

SY

S_

CL

K

DG

ND

WP

1_

RT

C_

CL

KB

P_

RT

C_

CL

K

WP

2_

SY

S_

CL

K

LA

_C

LK

PC

I_C

LK

VIA

_C

LK

Pa

ge

66

Clo

ckin

g - R

ap

idIO

RIO

3_T

XC

LK

_IN

+3

.3V

RIO

3_

TX

CL

K_

IN_

N

RIO

2_T

XC

LK

_IN

RIO

1_

TX

CL

K_

IN_

N

RIO

2_

TX

CL

K_

IN_

N

RIO

0_

TX

CL

K_

IN_

NR

IO0_T

XC

LK

_IN

DG

ND

RIO

1_T

XC

LK

_IN

TS

I50

0_

LS

0_

CL

K

TS

I50

0_

TX

CL

K_

INT

SI5

00

_T

XC

LK

_IN

_N

TS

I50

0_

LS

1_

CL

K



Schematics

Figure A-63. Clocking—Processor

55

44

33

22

11

DD

CC

BB

AA

BP

_R

TC

_C

LK

WP

1_

RT

C_

CL

K

DG

ND

WP

2_

RT

C_

CL

K

+3

.3V

WP

3_

RT

C_

CL

K

PC

I_C

LK

LA

_C

LK

CL

K_

SE

LE

CT

WP

1_

SY

S_

CL

KB

P_

SY

S_

CL

K

WP

2_

SY

S_

CL

KW

P3

_S

YS

_C

LK

VIA

_C

LK

+3

.3V

WP

3_

RT

C_

CL

KW

P2

_R

TC

_C

LK

DG

ND

WP

1_

RT

C_

CL

KB

P_

RT

C_

CL

K

WP

2_

SY

S_

CL

KW

P1

_S

YS

_C

LK

PC

I_C

LK

BP

_S

YS

_C

LK

WP

3_

SY

S_

CL

KL

A_

CL

K

VIA

_C

LK

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Clo

ckin

g - P

roce

sso

r0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

65

72

Tu

esd

ay, S

ep

tem

be

r 30

, 20

03

Power

Processors' RTC Clocks

Decoupling

Decoupling

System Clocks

Oscillator

is

Socketted

in

Socket X4

TP

13

1

X4

8-P

in D

IP S

ocke

t

R5

11

27

R

0.1uFC626

R5

18

27

R

TP

13

0Y

8

16

MH

z

1 2

R5

12

27

RR

36

41

00

R

U5

8

MP

C9

05

VDD5

VDD9

VDD13

GND3

GND7

GND11

EN

11

5

EN

22

XT

AL_O

UT

1

XT

AL_IN

16

CLK

OU

T0

4

CLK

OU

T1

6

CLK

OU

T2

8

CLK

OU

T3

10

CLK

OU

T4

14

CLK

OU

T5

12

C4

16

10

pF

CLK

OUT

Vdd

gnd

Y1

5

33

.3M

Hz, O

sc

84

5123

67

R36110K

TP

14

0

R5

14

27

R

R5

13

27

R

TP

13

9

R7

10

27

R

R1

35

9

4K

7

0.1uFC629

TP

17

3

R36210K

TP

17

4

R5

15

27

R

0.1uFC628

FA

NO

UT

BU

FF

ER

0...3

50

MH

z

U5

9

MP

C9

44

8F

A

PC

LK

3

PC

LK

4

CC

LK

2

CLK

_S

EL

1C

LK

_S

TO

P5

OE

6

Q0

31

Q1

29

Q2

27

Q3

25

Q4

23

Q5

21

Q6

19

Q7

17

Q8

15

Q9

13

Q1

01

1

Q1

19

VCC17

VCC210

VCC314

VCC418

VCC522

VCC626

VCC730

GND18

GND212

GND316

GND420

GND524

GND628

GND732

C4

13

16

pF

R5

16

27

R

0.1uFC627

0.1uFC625

TP

13

8R

13

81

27

R

R6

61

27

R

R5

10

27

R

R5

17

27

R



Figure A-64. Clocking—RapidIO

55

44

33

22

11

DD

CC

BB

AA

RIO

_N

1

RIO

_M

1

RIO

_P

_L

OA

D

RIO

_M

3R

IO_

M2

RIO

_M

0

RIO

3_

TX

CL

K_

IN

RIO

2_

TX

CL

K_

IN

RIO

_M

5R

IO_

M4

RIO

2_

TX

CL

K_

IN_

N

+3

.3V

RIO

_N

0

RIO

0_

TX

CL

K_

IN

TS

I50

0_

TX

CL

K_

IN_

N

FB

F0

3D

S0

1D

S1

3D

S1

FB

DS

1

FS

TS

I50

0_

LS

0_

CL

K

1D

S0

FB

DS

0

1F

1

3F

0

FS

MO

DE

3F

1

MO

DE

INV

3

FB

F0

1F

0

FB

DS

0

3D

S0

3F

1F

BD

S1

3F

0

INV

33

DS

11

F0

1F

1

1D

S1

1D

S0

TS

I50

0_

LS

1_

CL

K

DG

ND

RIO

_T

XC

LK

_IN

_N

RIO

3_

TX

CL

K_

IN_

N

RIO

0_

TX

CL

K_

IN_

N

TS

I50

0_

TX

CL

K_

IN

RIO

1_

TX

CL

K_

INR

IO1

_T

XC

LK

_IN

_N

RIO

_T

XC

LK

_IN

_P

RIO

_M

7R

IO_

M6

RIO

_M

8

RIO

3_

TX

CL

K_

IN

+3

.3V

RIO

3_

TX

CL

K_

IN_

N

RIO

2_

TX

CL

K_

IN

RIO

1_

TX

CL

K_

IN_

N

RIO

2_

TX

CL

K_

IN_

N

RIO

0_

TX

CL

K_

IN_

NR

IO0

_T

XC

LK

_IN

DG

ND

RIO

1_

TX

CL

K_

IN

TS

I50

0_

TX

CL

K_

INT

SI5

00

_T

XC

LK

_IN

_NTS

I50

0_

LS

0_

CL

K

TS

I50

0_

LS

1_

CL

K

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V +3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Clo

ckin

g - R

ap

idIO

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

66

72

We

dn

esd

ay, O

cto

be

r 01

, 20

03

RapidIO Clocks

Power

Trst~150mS

Decoupling

Decoupling

RapidIO Switch Clocks

Decoupling

SW

4

SW

DIP

-6

1234567 8 1

21

11

09

SW

28

SW

DIP

-6

1234567 8 1

21

11

09

Y1

25

MH

z

14

23

0.1uFC624

JP

34

13

2

0.1uFC912

+

C25

10uF,6.3V Tants

12

TP

25

9

22

0p

F

C9

26

TP

24

8

R7

11

51

R

TP

25

7

TP

26

6

22

0p

F

C9

29

JP

27

13

2

U1

1

ICS

85

16

VDD1

nQ

52

Q5

3

nQ

44

Q4

5

VDD6

GND7

nQ

38

Q3

9

nQ

21

0Q

21

1

VDD12

nQ

11

3Q

11

4

nQ

01

5Q

01

6

GND17

nC

LK

18

CL

K1

9

GND20

Q1

52

1

nQ

15

22

Q1

42

3

nQ

14

24

VDD36

nQ

10

35

Q1

03

4

nQ

11

33

Q1

13

2

VDD31

GND30

nQ

12

29

Q1

22

8

nQ

13

27

Q1

32

6

VDD25

Q6

48

nQ

64

7

Q7

46

nQ

74

5

GND44

OE

14

3

OE

24

2

GND41

nQ

84

0Q

83

9

nQ

93

8Q

93

7

0.1uFC916

U1

0

ICS

84

42

M5

1

M6

2

M7

3

M8

4

N0

5

N1

6

nc

7

GN

D8

TE

ST

9

VD

D1

0

FO

UT

11

1

nF

OU

T1

12

VD

D1

3

FO

UT

01

4

nF

OU

T0

15

GN

D1

6

MR

17

S_C

LO

CK

18

S_D

AT

A1

9

S_

LO

AD

20

VD

DA

21

nX

TA

L_S

EL

22

T_

CL

K2

3

XT

AL

12

4

M4

32

M3

31

M2

30

M1

29

M0

28

VC

O_S

EL

27

nP

_L

OA

D2

6

XT

AL

22

5

R7

24

51

R

TP

10

8

TP

25

6

TP

26

5

22

0p

F

C9

33

TP

11

0

R6

67

27

R

C9

73

18

pF

0.1uFC909

0.1uFC969

TP

11

2T

P1

11

TP

25

1

JP

25

13

2

22

0p

F

C9

25

R7

25

51

R

TP

10

9

R7144K7

R7

17

4K

7

0.1uFC968

JP

32

13

2

0.1uFC622

JP

35

13

2

R6

66

27

R

TP

25

2

0.1uFC918

0.1uFC920

JP

31

13

2

R7134K7

R7

27

51

R

JP

26

13

2

U9

DS

18

18

R-1

0/T

&R

RS

T1

VC

C2

DG

ND

3

R7

23

51

R

TP

10

7

22

0p

F

C9

23

0.1uFC910

0.1uFC915

TP

25

3

JP

33

13

2

C9

72

22

pF

R7

20

4K

7

R7

26

51

R

R7

16

51

R

0.1uFC971

0.1uFC914

JP

30

13

2

R6

68

27

R

22

0p

F

C9

34

TP

25

4

R1

36

00

R

22

0p

F

C9

24

CLK

OUT

Vdd

gnd

Y2

25

MH

z, O

sc

42

31

R7

19

51

RR

71

85

1R

0.1uFC621

0.1uFC966

0.1uFC970

TP

24

22

0p

F

C9

31

0.1uFC967

JP

24

13

2

R7

15

10

R

JP

23

13

2

0.01uF C23

22

0p

F

C9

32

TP

25

5

0.1uFC911

22

0p

F

C9

27

0.1uFC935

JP

36

13

2

R7

22

51

R

0.1uFC919

R7

21

51

R

JP

29

13

2

R7

12

51

R

22

0p

F

C9

30

SW

3

Pu

sh

-to-M

ake

1234

U7

7

CY

7B

99

4V

GND1

3F

12

4F

13

3F

04

4F

05

4D

S1

6

3D

S1

7

GND8

4Q

B1

9

VCCN10

4Q

B0

11

GND12

GND13

4Q

A1

14

VCCN15

4Q

A0

16

GND17

2D

S1

18

1D

S1

19

VCCQ20

4D

S0

21

3D

S0

22

2D

S0

23

1D

S0

24

GND25

GND26

GND27

GND28

VCCQ29

VCCQ30

2F

13

1

1F

13

2

DIS

13

3

DIS

23

4

GND35

3Q

A0

36

VCCN37

3Q

A1

38

GND39

GND40

3Q

B0

41

VCCN42

3Q

B1

43

GND44

VCCQ45

INV

34

6

GND47

OU

TP

UT

_M

OD

E4

8

VCCQ49

GND50

DIS

35

1

DIS

45

2

FB

DIS

53

VCCQ54

GND55

1F

05

6

FB

F0

57

GND58

2Q

B1

59

VCCN60

2Q

B0

61

GND62

GND63

2Q

A1

64

VCCN65

2Q

A0

66

GND67

FS

68

2F

06

9

RE

FB

+7

0

RE

FB

-7

1

RE

FS

EL

72

RE

FA

-7

3R

EF

A+

74

VCCQ75

VCCQ76

FB

KA

+7

7

FB

KA

-7

8

FB

SE

L7

9F

BK

B-

80

FB

KB

+8

1

GND82

GND83

QF

A1

84

VCCN85

QF

A0

86

GND87

GND88

1Q

A0

89

VCCN90

1Q

A1

91

GND92

GND93 1

QB

09

4

VCCN95

1Q

B1

96

GND97

FB

DS

09

8

FB

DS

19

9LOCK

100

0.1uFC917

22

0p

F

C9

28

JP

28

13

2

22

0p

F

C9

22

TP

25

0

TP

26

0

0.1uFC913

22

0p

F

C9

21



Schematics

Figure A-65. Reset Control

55

44

33

22

11

DD

CC

BB

AA

FP

_R

ES

ET

US

R5

WP

1_

CO

P_

HR

ES

ET

_N

DL

AL

E

PO

RS

T

DD

R_

Po

we

r_G

oo

d

WP

2_

TR

ST

_N

WP

3_

CO

P_

SR

ES

ET

_N

WP

3_

HR

ES

ET

_R

EQ

_N

BP

_S

RE

SE

T_

N

Co

re_

Po

we

r_O

n

ID0

Co

re_

Po

we

r_G

oo

d

WP

1_

CO

P_

SR

ES

ET

_N

DD

R_

Po

we

r_G

oo

d

WP

1_

TR

ST

_N

LE

D_

N6

WP

1_

CO

P_

TR

ST

_N

Co

re_

Po

we

r_O

n

BP

_H

RE

SE

T_

RE

Q_

N

WP

3_

HR

ES

ET

_N

BP

_H

RE

SE

T_

N

US

R2

BP

_C

OP

_T

RS

T_

N

TS

I50

0_

SW

_R

ST

_N

SH

UT

DO

WN

BP

_C

OP

_H

RE

SE

T_

N

BP

_H

RE

SE

T_

RE

Q_

N

LE

D_

N5

TE

ST

LE

D_

N4

US

R3

5V

_P

ow

er_

On

5V

_P

ow

er_

On

5V

_P

ow

er_

Go

od

ID0

FP

_R

ES

ET

SY

S_

RE

SE

T_

NL

AL

E

3.3

V_

Po

we

r_O

n

FP

_R

ES

ET

FP

_P

OW

ER

_O

N

WP

1_

HR

ES

ET

_N

PL

D_

CL

K

US

R6

DE

BU

G0

PW

R_

OK

IO_

LV

_P

ow

er_

On

WP

3_

TR

ST

_N

PS

_O

N

ON

_O

FF

WP

3_

SR

ES

ET

_N

AD

S_

HR

ES

ET

_N

LE

D_

N0

BP

_T

RS

T_

N

FP

_P

OW

ER

_O

N

3.3

V_

Po

we

r_G

oo

d

ID1

FP

_P

OW

ER

_O

N

BP

_S

RE

SE

T_

N

WP

2_

RE

SE

T_

N

WP

1_

SR

ES

ET

_N

TE

ST

LE

D_

N1

+5

VS

B

WP

2_

HR

ES

ET

_R

EQ

_N

WP

2_

HR

ES

ET

_N

ID0

3.3

V_

Po

we

r_O

n3

.3V

_P

ow

er_

Go

od

SY

S_

RE

SE

T_

N

DE

BU

G0

US

R4

WP

3_

CO

P_

HR

ES

ET

_N

BP

_C

OP

_S

RE

SE

T_

N

BP

_C

OP

_S

RE

SE

T_

N

TS

I50

0_

SW

_R

ST

_N

DE

BU

G1

PB

_R

ES

ET

_N

ON

_O

FF

PL

D_

CL

K

BP

_R

ST

_C

ON

F_

N

LE

D_

N6

PL

D_

LA

_C

LK

LE

D_

N7

TS

I50

0_

HW

_R

ST

_N

LE

D_

N4

ID2

WP

3_

CO

P_

TR

ST

_N

US

R5

BP

_R

ST

_C

ON

F_

N

WP

1_

RS

T_

CO

NF

_N

DD

R_

Po

we

r_G

oo

d

LE

D_

N3

IO_

LV

_P

ow

er_

On

ID2

BP

_C

OP

_H

RE

SE

T_

N

LE

D_

N0

PC

I_R

ST

_N

TS

I50

0_

HW

_R

ST

_N

SY

ST

EM

_R

ES

ET

_N

US

R1

DE

BU

G1

5V

_P

ow

er_

Go

od

Co

re_

Po

we

r_G

oo

d

DG

ND

VIA

_R

ES

ET

_R

EQ

_N

DE

BU

G2

BP

_T

RS

T_

N

US

R6

ID1

TD

O

WP

2_

RS

T_

CO

NF

_N

WP

1_

RE

SE

T_

N

TC

K

5V

_P

ow

er_

Go

od

WP

2_

CO

P_

HR

ES

ET

_N

AD

S_

HR

ES

ET

_N

BP

_C

OP

_T

RS

T_

N

LE

D_

N1

PC

I_R

ST

_N

TD

O

US

R2

BP

_H

RE

SE

T_

N

LE

D_

N2

PW

R_

OK

PO

RS

T

WP

2_

CO

P_

TR

ST

_N

LE

D_

N2

VIA

_R

ES

ET

_N

ID1

PB

_R

ES

ET

_N

US

R7

WP

1_

HR

ES

ET

_R

EQ

_N

WP

3_

RS

T_

CO

NF

_N

WP

3_

RE

SE

T_

N

DD

R_

Po

we

r_O

n

DE

BU

G2

TM

S

PS

_O

N

US

R3

ID2

TD

IO

N_

OF

F

PL

D_

LA

_C

LK

WP

2_

CO

P_

SR

ES

ET

_N

3.3

V_

Po

we

r_G

oo

d

TM

S

LE

D_

N5

TC

K

PC

I_IN

TA

_N

LE

D_

N3

LE

D_

N7

US

R1

AT

X_

BP

VIA

_O

NA

TX

_B

P

US

R4

Co

re_

Po

we

r_G

oo

d

US

R0

DD

R_

Po

we

r_O

n

US

R7

US

R0

ID3

WP

2_

SR

ES

ET

_N

ID3

TD

I

PS

_O

N

PB

_R

ES

ET

_N

ID3

WP

1_

RE

SE

T_

NW

P2

_R

ES

ET

_N

WP

3_

RE

SE

T_

N

BP

_G

2_

RE

SE

T_

NB

P_

G1

_R

ES

ET

_N

WP

1_

G1

_R

ES

ET

_N

WP

2_

G1

_R

ES

ET

_N

WP

3_

G1

_R

ES

ET

_N

VIA

_IN

T

FP

_L

ED

_N

FP

_L

ED

_N

SP

EA

KE

R

SP

EA

KE

R

LA

8F

LA

8

WP

1_

CO

P_

SR

ES

ET

_N

WP

2_

CO

P_

HR

ES

ET

_N

AT

X_

BP

+5

VS

B

BP

_C

OP

_S

RE

SE

T_

N

WP

2_

HR

ES

ET

_R

EQ

_N

WP

3_

SR

ES

ET

_N

WP

3_

TR

ST

_N

WP

1_

CO

P_

TR

ST

_N

DD

R_

Po

we

r_G

oo

d

VIA

_IN

T

WP

1_

SR

ES

ET

_N

WP

2_

CO

P_

TR

ST

_N

WP

3_

CO

P_

HR

ES

ET

_N

VIA

_R

ES

ET

_R

EQ

_N

BP

_H

RE

SE

T_

N

DG

ND

SY

S_

RE

SE

T_

N

VIA

_R

ES

ET

_N

WP

3_

HR

ES

ET

_R

EQ

_N

PC

I_R

ST

_N

BP

_T

RS

T_

N

SH

UT

DO

WN

IO_

LV

_P

ow

er_

On

LA

LE

WP

2_

RE

SE

T_

N

DL

AL

E

5V

_P

ow

er_

On

WP

2_

RS

T_

CO

NF

_N

PC

I_IN

TA

_N

WP

1_

HR

ES

ET

_N

Co

re_

Po

we

r_G

oo

d

WP

2_

CO

P_

SR

ES

ET

_N

WP

1_

HR

ES

ET

_R

EQ

_N

TS

I50

0_

HW

_R

ST

_N

BP

_C

OP

_T

RS

T_

N

SY

ST

EM

_R

ES

ET

_N

WP

2_

SR

ES

ET

_N

WP

3_

RE

SE

T_

N

TS

I50

0_

SW

_R

ST

_N

WP

2_

HR

ES

ET

_N

WP

1_

RE

SE

T_

N

BP

_S

RE

SE

T_

N

PW

R_

OK

PS

_O

N

WP

3_

RS

T_

CO

NF

_N

WP

3_

CO

P_

SR

ES

ET

_N

3.3

V_

Po

we

r_G

oo

d

Co

re_

Po

we

r_O

n

WP

1_

RS

T_

CO

NF

_N

BP

_C

OP

_H

RE

SE

T_

N

BP

_H

RE

SE

T_

RE

Q_

N

WP

1_

CO

P_

HR

ES

ET

_N

WP

3_

HR

ES

ET

_N

5V

_P

ow

er_

Go

od

3.3

V_

Po

we

r_O

n

WP

1_

TR

ST

_N

WP

3_

CO

P_

TR

ST

_N

VIA

_O

N

AD

S_

HR

ES

ET

_N

BP

_R

ST

_C

ON

F_

N

DD

R_

Po

we

r_O

n

WP

2_

TR

ST

_N

ID[3

:0]

BP

_G

1_

RE

SE

T_

NB

P_

G2

_R

ES

ET

_N

WP

1_

G1

_R

ES

ET

_N

WP

2_

G1

_R

ES

ET

_N

WP

3_

G1

_R

ES

ET

_N

LA

8F

LA

8

US

R4

+3

.3V

CP

LD

+5

VS

B+

3.3

VC

PL

D

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+5

VS

B

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

+3

.3V

CP

LD

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Re

se

t Co

ntro

l0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

67

72

We

dn

esd

ay, O

cto

be

r 01

, 20

03

2uH, 3A

3.3V

@ 1A

"P

WR

_O

N/O

FF

"

Decoupling

Reset - Front

Panel

Connection

Power On - Front

Panel Connection

"C

PL

DR

ES

ET

"

Note :- Key for Switches

Switch Controls

USR0 BP Reset

USR1 WP1 Reset

USR2 WP2 Reset

USR3 WP3 Reset

USR4 Switch Flash Bank

USR5 Reserved

USR6 Reserved

USR7 Reserved

"S

yste

m R

ES

ET

"

Power

Note :- Key for LEDs

LED Indicates

LD13 +5VSB_ATX is on

LD14 ATX Power Supply is on

LD15 +5V Power is Good

LD16 +3.3V Power is Good

LD17 Core Power is Good

LD18 DDR Power is Good

LD19 Low Voltage IO Power is On

LD20 "Heart Beat"

Power Indicator -

Front Panel Connection

Speaker header

33

0R

R1

36

8

TP

30

6

U2

9

isp

MA

CH

42

56

NC

81

GND2

TD

I3

VCCO_BANK04

C1

45

C1

26

C1

07

C8

8C

69

C4

10

C2

11

C0

12

GND_BANK013

D1

41

4D

12

15

D1

01

6D

81

7D

61

8D

41

9D

22

0D

02

1

VCCO_BANK022

E0

23

E2

24

E4

25

E6

26

E8

27

E1

02

8

E1

22

9

E1

43

0

GND_BANK031

F0

32

F2

33

F4

34

F6

35

F8

36

F1

03

7

F1

23

8

F1

43

9

VCCO_BANK040

TC

K4

1

VCC42

NC

54

3

NC

64

4

NC

74

5

GND46

G1

44

7G

12

48

G1

04

9G

85

0G

65

1G

45

2G

25

3G

05

4

GND_BANK055

VCCO_BANK056

H1

45

7H

12

58

H1

05

9H

86

0H

66

1H

46

2H

26

3H

06

4

GND65

CL

K_

1_

I6

6

GND_BANK167

CL

K_

2_

I6

8

VCC69

I27

1I4

72

I67

3I8

74

I10

75

I12

76

I14

77

VCC0_BANK178

GND_BANK179

J0

80

J2

81

J4

82

J6

83

J8

84

J1

08

5J1

28

6J1

48

7

VCC88

NC

48

9

GND90

TM

S9

1

VCCO_BANK192

K1

49

3

K1

29

4

K1

09

5

K8

96

K6

97

K4

98

K2

99

K0

10

0

GND_BANK1101

L1

41

02

L1

21

03

L1

01

04

L8

10

5

L6

10

6

L4

10

7

L2

10

8

L0

10

9

VCCO_BANK1110

M0

11

1M

21

12

M4

11

3M

61

14

M8

11

5M

10

11

6M

12

11

7M

14

11

8

GND_BANK1119

N0

12

0N

21

21

N4

12

2N

61

23

N8

12

4N

10

12

5N

12

12

6N

14

12

7

VCCO_BANK1128

TD

O1

29

VCC130

NC

11

31

NC

21

32

NC

31

33

GND134

O1

41

35

O1

21

36

O1

01

37

O8

13

8

O6

13

9

O4

14

0

O2

14

1

O0

14

2

GND_BANK1143

VCCO_BANK1144

P1

41

45

P1

21

46

P1

01

47

P8

14

8

P6

14

9

P4

15

0

P2

_G

OE

11

51

P0

15

2

GND153

CL

K_

3_

I1

54

GND_BANK0155

CL

K_

0_

I1

56

VCC157

A0

15

8

A2

_G

OE

01

59

A4

16

0

A6

16

1

A8

16

2

A1

01

63

A1

21

64

A1

41

65

VCCO_BANK0166

GND_BANK0167

B0

16

8

B2

16

9

B4

17

0

B6

17

1

B8

17

2

B1

01

73

B1

21

74

B1

41

75

VCC176

I07

0

TP

30

7

TP

28

4

TP

28

9

TP

32

7

D1

1M

BR

S1

30

L

2 1

0.1uFC739

HD

9

2x5

He

ad

er

13579

246810

33

0R

R1

36

9

LE

D_

YE

LL

OW

LD

15

21

TP

30

3

U4

5

MA

X811

VC

C4

RE

SE

T2

GN

D1

MR

3

LE

D_

YE

LL

OW

LD

18

21

TP

28

5

L1

7C

DR

H6

D2

8-3

R0

12

TP

28

8

TP

32

6

33

0R

R1

36

4

C410

2.2uF

C4

11

47

0p

F

TP

28

1

TP

32

1

R2744K7

RN

21

21

0K

, RN

10

12346789

5

33

0R

R1

36

5

R3

65

10

K

R3

41

84

K5

, 1%

R1941K

HD

24

12

TP

27

5

TP

31

1

LE

D_

YE

LL

OW

LD

14

21

+C

40

8

12

0u

F,4

V T

an

ts

TP

27

7

LE

D_

YE

LL

OW

LD

17

21

TP

31

5

LE

D_

YE

LL

OW

LD

19

21

TP

32

0

TP

29

3

HD

25

12

R7

78

27

R

33

0R

R1

37

0

TP

27

6

33

0R

R1

36

2

SW

23

Pu

sh

-to-M

ake

1234

TP

31

2

R13821K

LE

D_

YE

LL

OW

LD

16

21

TP

31

6

TP

28

3

0.1uFC741

TP

33

0

R70310K

TP

32

3

RN

20

71

0K

, RN

10

12346789

5

R13614K7

0.1uFC738

SW

19

Pu

sh

-to-M

ake

1234

LE

D_

YE

LL

OW

LD

13

21

33

0R

R1

36

6

TP

31

7

TP

28

2

R1924K7

TP

31

8

TP

29

1

0.1uFC740

TP

32

9

TP

32

4

R3

40

10

R

U5

5

MA

X1831

FB

8

IN1

2LX

11

IN2

4

TO

FF

7

SH

DN

5

LX

23

CO

MP

6

GN

D9

RE

F1

0

FB

SE

L1

1

VC

C1

2P

GN

D1

3

LX

31

4

PG

ND

15

LX

41

6

CLK

OUT

Vdd

gnd

Y6

66

MH

z

42

31

HD

30

132

R7

65

27

R

SW

27

Pu

sh

-to-M

ake

1234

GND

39

40

41

42

43

P2

0

MIC

TO

R 3

8 S

OC

KE

T

5V

1S

CL

2

GN

D3

SD

A4

CLK

A5

CLK

B6

D1

5A

7D

15

B8

D1

4A

9D

14

B1

0

D1

3A

11

D1

3B

12

D1

2A

13

D1

2B

14

D1

1A

15

D1

1B

16

D1

0A

17

D1

0B

18

D9

A1

9D

9B

20

D8

A2

1D

8B

22

D7

A2

3D

7B

24

D6

A2

5D

6B

26

D5

A2

7D

5B

28

D4

A2

9D

4B

30

D3

A3

1D

3B

32

D2

A3

3D

2B

34

D1

A3

5D

1B

36

D0

A3

7D

0B

38

33

0R

R1

36

7

C4

09

22

uF

,6.3

V

TP

31

3

HD

32

HE

AD

ER

4x1

13 24

LE

D_

GR

EE

NL

D3

92

1

TP

32

8

SW

25

SW

DIP

-8

12345678

16

15

14

13

12

11

10

9

C4

12

1u

F,1

0V

TP

32

5

33

0R

R1

36

3

RN

21

41

0K

, RN

10

12346789

5



Figure A-66. Power Supply—Top Level

55

44

33

22

11

DD

CC

BB

AA

+2

.5V

tsi5

00

IO_

LV

_P

ow

er_

On

Vd

d

tsi5

00

_V

DD

+1

.5V

GE

the

r

+1

2V

+2

.5V

DD

R_

Po

we

r_G

oo

d

DD

R_

Po

we

r_O

n

DG

ND

+2

.5V

GE

the

r

Co

re_

Po

we

r_O

n

Co

re_

Po

we

r_G

oo

d

+5

V

DG

ND

SE

NS

E_

VD

D

SE

NS

E_

VS

S

+3

.3V

_B

P

+5

V_

BP

+5

VS

B_

BP

PW

R_

OK

+1

2V

5V

_P

ow

er_

On

DG

ND +5

VS

B

+3

.3V

3.3

V_

Po

we

r_O

n

+5

V

CG

ND

5V

_P

ow

er_

Go

od

PS

_O

N

3.3

V_

Po

we

r_G

oo

d

+1

.2V

tsi5

00

-12

V

+1

2V

+3

.3V

Co

re_

Po

we

r_G

oo

d

DD

R_

Po

we

r_G

oo

d

IO_

LV

_P

ow

er_

On

DG

ND

tsi5

00

_V

DD

+1

2V

+2

.5V

tsi5

00

Vd

d

3.3

V_

Po

we

r_O

n

Co

re_

Po

we

r_O

n

5V

_P

ow

er_

On

PW

R_

OK

3.3

V_

Po

we

r_G

oo

d

5V

_P

ow

er_

Go

od

+2

.5V

GE

the

r

+2

.5V

+1

.5V

GE

the

r

PS

_O

N

+5

V

DD

R_

Po

we

r_O

n

DG

ND

SE

NS

E_

VD

D

SE

NS

E_

VS

S

+1

2V

+3

.3V

+3

.3V

_B

P

+5

VS

B_

BP

+5

V_

BP

+5

VS

B

DG

ND

CG

ND

+5

V

+1

.2V

tsi5

00

-12

V

+1

2V

+3

.3V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Po

we

r Su

pp

ly - T

op

Le

ve

l0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

68

72

Th

urs

da

y, S

ep

tem

be

r 25

, 20

03

Pa

ge

71

PS

- Po

we

r Su

pp

ly

+5V

SB

CG

ND

PS

_O

N

PW

R_O

K

DG

ND

3.3

V_

Po

we

r_G

oo

d

3.3

V_

Po

we

r_O

n

5V

_P

ow

er_

Go

od

5V

_P

ow

er_

On

+5

V

+3

.3V

+5

V_

BP

+3

.3V

_B

P

+5V

SB

_B

P

+1

2V

-12

V

Pa

ge

69

PS

- Co

re

DG

ND

Vd

d

+1

2V

Co

re_

Po

we

r_O

n

Co

re_

Po

we

r_G

oo

d

SE

NS

E_V

SS

SE

NS

E_V

DD

+3

.3V

Pa

ge

70

PS

- IO

tsi5

00_V

DD

+2

.5V

+2

.5V

GE

the

r

DG

ND

+2

.5V

tsi5

00

+5

V

+1

.5V

GE

the

r

DD

R_

Po

we

r_G

oo

d

IO_

LV

_P

ow

er_

On

DD

R_

Po

we

r_O

n

+1

.2V

tsi5

00

+1

2V



Schematics

Figure A-67. Power Supply—Core Voltage

55

44

33

22

11

DD

CC

BB

AA

+1

2V

Vd

d

VID

0

VID

4

SE

NS

E_

VD

D

SE

NS

E_

VS

S

VID

3V

ID1

Co

re_

Po

we

r_G

oo

d

VID

4V

ID2

VID

0

Co

re_

Po

we

r_O

n

VID

1V

ID2

VID

3

Vo

_S

en

ce

-

Vo

_S

en

ce

+

Vo

_S

en

ce

+

Vo

_S

en

ce

-

+3

.3VDG

ND

DG

ND

+1

2V

Co

re_

Po

we

r_O

n

Vd

d

Co

re_

Po

we

r_G

oo

d

SE

NS

E_

VD

D

SE

NS

E_

VS

S

+3

.3V

+3

.3V

+1

2V

Vd

d

Vd

d

+1

2V

+1

2V

+3

.3V

Vd

d

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Po

we

r Su

pp

ly - C

ore

Vo

ltag

e0

.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

69

72

We

dn

esd

ay, O

cto

be

r 29

, 20

03

Power

This sets 1.2V

Processor Core

1.1V to 1.85V

@ 81A with

25mV step Size

Note :- Default settings for Switches

VID4 VID3 VID2

VID1 VID0

1 1 0

1 0

Do Not Fit

R6

42

0R

SW

20

SW

DIP

-6

1234567 8 1

21

11

09

4.7uF, 6.3C1152

4.7uF, 6.3C1158

P3

6

VR

M 9

.0 C

on

ne

cto

r

Vin

+_

11

Vin

+_

22

Vin

+_

33

Vin

+_

44

Re

se

rve

d_

15

VID

37

VID

18

Re

se

rve

d_

29

PW

RG

D1

0

Vo

Se

n-

11

Re

se

rve

d_

31

2

Vo

-_1

13

Vo

+_

11

4

Vo

-_2

15

Vo

+_

21

6

Vo

-_3

17

Vo

+_

31

8

Vo

-_4

19

Vo

+_

42

0

Vo

-_5

21

Vo

+_

52

2

Vo

-_6

23

Vo

+_

62

4

Vo

-_7

25

Vo

+_

72

6

Vo

-_8

27

Vo

+_

82

8

Vo

-_9

29

Vo

+_

93

0

Vo

-_1

03

1V

o-_

11

32

Vo

+_

10

33

Vo

-_1

23

4V

o+

_1

13

5V

o-_

13

36

Vo

+_

12

37

Vo

-_1

43

8V

o+

39

Vo

-_1

54

0V

o+

_1

34

1V

o-_

16

42

Vo

+_

14

43

Vo

-_1

74

4V

o+

_1

54

5V

o-_

18

46

Vo

+_

16

47

Vo

-_1

94

8V

o+

_1

74

9V

o+

_1

85

0R

ese

rve

d_

45

1V

o S

en

+5

2O

UT

EN

53

Ish

are

54

VID

05

5V

ID2

56

VID

45

7V

RM

-pre

s5

8V

in-_

15

9V

in-_

26

0V

in-_

36

1V

in-_

46

2

R6

41

0R

+

C1150

560uF, 6.3V, OSCON

12

R3

18

10

K

1(62)

11(52)

12(51)

31(32)

NXI100 Module

A2N

XI1

00

R2

88

10

K

+

C1146

560uF, 6.3V, OSCON

12

4.7uF, 6.3C1153

4.7uF, 6.3C1159

TP

12

1

+

C1151

560uF, 6.3V, OSCON

12

4.7uF, 6.3C1154

4.7uF, 6.3C1160

+

C1147

560uF, 6.3V, OSCON

12

R2

89

10

K

4.7uF, 6.3C1155

4.7uF, 6.3C1161

+

C1187

680uF, 16V, Aluminium Electrolytic

12

+

C1148

560uF, 6.3V, OSCON

12

R2

91

10

K

4.7uF, 6.3C1156

R6

40

0R

+

C1144

560uF, 6.3V, OSCON

12

R3

19

10

K

+

C1149

560uF, 6.3V, OSCON

12

4.7uF, 6.3C1157

R2

90

10

K

+

C1145

560uF, 6.3V, OSCON

12

R6

39

0R



Figure A-68. Power Supply—IO Voltages

55

44

33

22

11

DD

CC

BB

AA

IO_

LV

_P

ow

er_

On

IO_

LV

_P

ow

er_

On

+1

.5V

GE

the

r

+2

.5V

tsi5

00

IO_

LV

_P

ow

er_

On

+2

.5V

+5

V

IO_

LV

_P

ow

er_

On

tsi5

00

_V

DD

+2

.5V

GE

the

r

DD

R_

Po

we

r_G

oo

dD

DR

_P

ow

er_

On

IO_

LV

_P

ow

er_

On

+1

.2V

tsi5

00

DG

ND

Vd

d_

Se

nse

-V

dd

_S

en

se

+

Vd

d_

Se

nse

-

Vd

d_

Se

nse

+

+1

2V

tsi5

00

_V

DD

DG

ND

+5

V

IO_

LV

_P

ow

er_

On

+2

.5V

tsi5

00

IO_

LV

_P

ow

er_

On

IO_

LV

_P

ow

er_

On

+1

.5V

GE

the

r

+2

.5V

IO_

LV

_P

ow

er_

On

+2

.5V

GE

the

r

DD

R_

Po

we

r_G

oo

dD

DR

_P

ow

er_

On

IO_

LV

_P

ow

er_

On

+1

.2V

tsi5

00

+1

2V

+2

.5V

GE

the

r

+5

V

+1

.5V

GE

the

r

tsi5

00

_V

DD

+2

.5V

tsi5

00

+2

.5V

tsi5

00

+2

.5V

GE

the

r

+5

V

+2

.5V

+5

V

+1

.5V

GE

the

r

+5

V

tsi5

00

_V

DD

+5

V

+2

.5V

+1

2V

+5

V+

5V

+5

V+

5V

+5

V+

1.2

Vts

i50

0

+1

.2V

tsi5

00

+5

V

+1

2V

+2

.5V

+2

.5V

+1

2V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Po

we

r Su

pp

ly - IO

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

70

72

We

dn

esd

ay, O

cto

be

r 29

, 20

03

2.5V @

1.5A

1.5V @

2.5A

10uH, 6A

Power

Gigabyte

Ethernet

DDR SDRAM

1.3V

@ 2A

Check resistor vlaues for 1.2V o/p

2.5V

@ 2A

RapidIO

Switch

2.5V @ 25A

Decoupling

Decoupling

235mA x 5

= 1.175A.

(typical)

340mA x 5

= 1.7A.

(typical)

1.518A.

(typical)

896mA + 83mA

= 979mA.

(typical)

10uH, 6A

10uH, 6A

10uH, 6A

10uH, 6A

1.518A.

(typical)

1.2V

@ 2A

C3

26

22

uF

,6.3

V

U4

8

MA

X1831

FB

8

IN1

2LX

11

IN2

4

TO

FF

7

SH

DN

5

LX

23

CO

MP

6

GN

D9

RE

F1

0

FB

SE

L1

1

VC

C1

2P

GN

D1

3

LX

31

4

PG

ND

15

LX

41

6

C9

37

22

uF

,6.3

V

R6

83

10

K, 1

/8W

A1

DD

R1

2

Po

we

r Go

od

J1

-1

Ou

tpu

t En

ab

leJ1

-2

Gro

un

d_

1J1

-3

Gro

un

d_

2J1

-4

+1

2V

_1

J1

-5

+1

2V

_2

J1

-6

+1

2V

_3

J1

-7

Vtt R

ef

J2

-1

Vtt_

1J2

-2

Vtt_

2J2

-3

Gro

un

d_

3J2

-4

Gro

un

d_

4J2

-5

Gro

un

d_

5J2

-6

Gro

un

d_

6J2

-7

Gro

un

d_

7J2

-8

Vd

d S

en

se

-J2

-9

Vd

d S

en

se

+J2

-10

Vd

d_

1J2

-11

Vd

d_

2J2

-12

Vd

d_

3J2

-13

Vd

d_

5J2

-15

Vd

d_

4J2

-14

+

C1166

270uF, 16V

12

C335

2.2uF

C3

42

1u

F,1

0V

C9

38

47

0p

F

R2

86

18

2K

, 1%

C3

34

22

uF

,6.3

V

C345

2.2uF

R2

79

10

R

R2

85

10

K, 1

/8W

0.1uFC847

R1

37

68

2R

L9

DO

50

10

P-1

03

HC

12

R2

83

10

R

C3

37

1u

F,1

0V

R6

82

90

0R

D3

MB

RS

13

0L

2 1

+

C1165

270uF, 16V

12

U5

0

MA

X1831

FB

8

IN1

2LX

11

IN2

4

TO

FF

7

SH

DN

5

LX

23

CO

MP

6

GN

D9

RE

F1

0

FB

SE

L1

1

VC

C1

2P

GN

D1

3

LX

31

4

PG

ND

15

LX

41

6

C3

28

47

0p

F

C3

36

47

0p

F

L2

6D

O5

01

0P

-10

3H

C

12

L1

1D

O5

01

0P

-10

3H

C

12

+

C1163

680uF, 6.3V

12

C3

44

22

uF

,6.3

V

0.1uFC846

+C

32

5

47

uF

, Ta

nts

D4

MB

RS

13

0L

2 1

R2

81

10

R

U4

6

MA

X1831

FB

8

IN1

2LX

11

IN2

4

TO

FF

7

SH

DN

5

LX

23

CO

MP

6

GN

D9

RE

F1

0

FB

SE

L1

1

VC

C1

2P

GN

D1

3

LX

31

4

PG

ND

15

LX

41

6

+

C369

220uF, Tants

D1

4M

BR

S1

30

L

2 1

L1

3D

O5

01

0P

-10

3H

C

12

+

C1164

680uF, 6.3V

12

C3

47

1u

F,1

0V

0.1uFC845

+C

93

6

47

uF

, Ta

nts

R2

80

18

2K

, 1%

C3

41

47

0p

F

R1

37

30

R

C3

30

1u

F,1

0V

D5

MB

RS

13

0L

2 1

0.1uFC941

R1

37

40

R

C9

40

1u

F,1

0V

+C

33

3

47

uF

, Ta

nts

R6

81

10

R

C340

2.2uF

R2

78

10

0K

.0

.5%

U4

9

MA

X1831

FB

8

IN1

2LX

11

IN2

4

TO

FF

7

SH

DN

5

LX

23

CO

MP

6

GN

D9

RE

F1

0

FB

SE

L1

1

VC

C1

2P

GN

D1

3

LX

31

4

PG

ND

15

LX

41

6

U7

8

MA

X1831

FB

8

IN1

2LX

11

IN2

4

TO

FF

7

SH

DN

5

LX

23

CO

MP

6

GN

D9

RE

F1

0

FB

SE

L1

1

VC

C1

2P

GN

D1

3

LX

31

4

PG

ND

15

LX

41

6

C3

46

47

0p

F

R2

76

10

R

+

C1162

680uF, 6.3V

12

R6

84

18

2K

, 1%

+C

34

3

47

uF

, Ta

nts

R1

37

23

K3

C3

39

22

uF

,6.3

V

+

C896

220uF, Tants

C939

2.2uF

+C

33

8

47

uF

, Ta

nts

C327

2.2uF

L1

2D

O5

01

0P

-10

3H

C

12

R1

37

51

0R

D2

MB

RS

13

0L

2 1

0.1uFC848

R2

82

10

0K

.0

.5%



Schematics

Figure A-69. Power Supply—Supplied Power

55

44

33

22

11

DD

CC

BB

AA

PS

_O

N

5V

_P

ow

er_

Go

od

+3

.3V

DG

ND

3.3

V_

Po

we

r_G

oo

d

+5

VS

B_

BP

CG

ND

3.3

V_

Po

we

r_O

n

5V

_P

ow

er_

On

+5

V

+3

.3V

_B

P

+5

V_

BP

+5

VS

B

+1

2V

-12

V

+5

VS

B_

BP

5V

_P

ow

er_

Go

od

+5

V

+3

.3V

3.3

V_

Po

we

r_O

n

3.3

V_

Po

we

r_G

oo

d

PW

R_

OK

PS

_O

N

5V

_P

ow

er_

On

DG

ND

CG

ND

+5

V_

BP

+3

.3V

_B

P

+5

VS

B

+1

2V

-12

V

+3

.3V

+5V

SB

_A

TX

+5

V+

5V

_A

TX

+5

VS

B_

BP

+3.3

V_

AT

X

+5

V

+3

.3V

_A

TX

+5V

_A

TX

+3

.3V

+1

2V

+3.3

V_

AT

X-1

2V

_A

TX

+5V

_A

TX

+3

.3V

+3

.3V

+5

V_

BP

+3

.3V

_B

P

+5

V_

BP

+3

.3V

_B

P

+5V

SB

_A

TX

+5

VS

B_

BP

+5

VS

B

+5

VS

B

+5

V

+1

2V

+3

.3V

+3

.3V

+5

V+

5V

-12V

_A

TX

-12

V

-12

V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+1

2V

Sy

ste

m :

Siz

eP

ag

e T

itle :

Re

v

Da

te:

Sh

ee

to

f

Po

we

r Su

pp

ly - S

up

plie

d P

ow

er

0.6

To

rrido

n - R

ap

idIO

En

ab

led

Mu

lti-Pro

ce

ssin

g S

yste

m

En

gin

ee

r : Ro

d W

att, N

CS

G P

latfo

rms G

rou

p, M

oto

rola

Ltd

.,Ea

st K

ilbrid

e

C

71

72

Frid

ay, O

cto

be

r 24

, 20

03

Power

Decoupling

Mou

ntin

g H

oles

+5V Stand By comes from

either the ATX power

supply or the backplane

Power Indicator -

Front Panel Connection

Short pins 3 & 4 close to U53

Short pins 53 & 54 close to U53

Do Not Fit

Bulk Decoupling

33

0R

R1

37

1

MH

3M

H5

MH

1

0.1uFC666

10uF, 6.3VC962

+

C1179

10uF,6.3V Tants

12

20K. 1%R337

10

0K

.0

.5%

R3

33

C4

07

0.1

uF U

53

MA

X591

8

MO

N1

8

TIM2

PG

OO

D1

1

SENSE14

LIM17

GATE15

IN13

GN

D6

MO

N2

9

LIM210

ON

11

1

GATE212

SENSE213

IN214

ON

21

5

PG

OO

D2

16

20K. 1%R338

TP

33

4

C4

04

0.1

uF

MH

6

+

C1175

10uF,6.3V Tants

12

8K

06

. 1%

R5

09

Q8

FD

B7

04

5L

1

23

+

C1180

10uF,6.3V Tants

12+

C4

05

10

00

uF

,16

V E

lecto

lytic

+C

29

33

30

uF

, Ta

nts

10uF, 6.3VC965

+C

12

86

33

0u

F, T

an

ts

+C

29

53

30

uF

, Ta

nts

MH

2

+C

29

73

30

uF

, Ta

nts

+

C1176

10uF,6.3V Tants

12

44

2K

.0

.5%

R3

34

+C

12

87

33

0u

F, T

an

ts

+C

29

43

30

uF

, Ta

nts

10uF, 6.3VC964

Q7

FD

B7

04

5L

1

23

MH

4

0.1uFC665

20K. 1%R336

+

C2

96

33

0u

F, T

an

ts

+

C1177

10uF,6.3V Tants

12

HD

26

13

2

+C

12

88

33

0u

F, T

an

ts

P3

7

AT

X_

12

V_

PW

R_

CO

NN

GN

D1

GN

D2

12

V3

12

V4

1K

R3

35

71

5K

.0

.5%

R3

31

+

C1178

10uF,6.3V Tants

12

+

C2

92

33

0u

F, T

an

ts

10

0K

.0

.5%

R3

32

10uF, 6.3VC963

P9

AT

X_

PW

R_

CO

NN

3.3

V1

1

-12

V1

2

GN

D1

3

PS

-ON

14

GN

D1

5

GN

D1

6

GN

D1

7

-5V

18

5V

19

5V

20

3.3

V1

3.3

V2

GN

D3

5V

4

GN

D5

5V

6

GN

D7

PW

-OK

8

5V

SB

9

12

V1

0

+C

12

89

33

0u

F, T

an

ts

+C4

06

10

00

uF

,16

V E

lecto

lytic



Figure A-70. WP—Debug Ports

55

44

33

22

11

DD

CC

BB

AA

DG

ND

+3

.3V

WP

3_

TX

D

WP

2_

RX

D

WP

1_

TX

DW

P2

_T

XD

WP

3_

RX

D

WP

1_

RX

D

+3

.3V

DG

ND

WP

1_

TX

D

WP

3_

TX

D

WP

1_

RX

D

WP

3_

RX

DW

P2

_R

XD

WP

2_

TX

D

+3

.3V

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Schematics


Freescale Semiconductor B-1PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Appendix B Revision History

Table B-1. Revision History

Revision Release Date Changes

0.1 12/2004 Modified footer on front cover

0 11/2004 Initial release


B-2 Freescale SemiconductorPRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Revision History

MPC8560 PowerQUICC III Torridon User's Guide - NXP

Documents