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Date: 6/23/2015

Revision: 1.0

Motorola MC68332 Reference Design

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Table of Contents Theory of Operation...................................................................................................................................... 3

Hardware Design ....................................................................................................................................... 3

Simulation ................................................................................................................................................. 3

MC68332 to Qsys ...................................................................................................................................... 3

Creating the Hardware .................................................................................................................................. 5

Creating the Software ................................................................................................................................... 7

Simulating ................................................................................................................................................... 10

MC68332 Replacement Components ......................................................................................................... 16

PWM Component Example ..................................................................................................................... 17

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Theory of Operation This reference design was created to demonstrate a strategy for replacing a Motorola MC68332

microcontroller with an Altera MAX10 FPGA utilizing the Nios II soft controller. While there are

challenges associated with directly replacing the MC68332, most of the basic functionality is available

with a Nios II solution.

Hardware Design This design focuses on three of the MC68332’s primary elements, the System Integration Module (SIM),

The Time Processor Unit (TPU), and the Queued Serial Module (QSM).

The QSM replacement peripherals include a SPI (3 Wire Serial), UART and 8 bit PIO input register. The

SIM replacement peripherals include an Avalon slave peripheral (memory interface) and several GPIO

including PIO substitutions for PORT C, PORT E and PORT F. The MC68332’s TPU is a timing module used

for sampling and pulse generation functions. While no QSYS peripherals are direct replacements for the

TPU functions, a custom PWM peripheral was created and included in the reference design. The PWM

peripheral was created using the QSYS custom component editor. This peripheral operates in a similar

fashion to the TPU’s Pulse Width Modulation function. The component was added to demonstrate how

most of the MC68332’s functionality could be replicated using a Nios II based solution.

The top level of this Verilog design is top.v. The Nios II controller and peripherals are instantiated in the

design as the component (MC68332).

Simulation The simulation tool used for this design is ModelSim Altera Starter Edition. Because this design is

primarily a QSYS implementation, the simulation for this design is run from the Eclipse IDE. A small

portion of software is used to generate the stimulus for the design.

The same procedure found in Altera Application Note 351 (AN-351) was followed in order to generate

and view the results of the simulation.

The time required to run a simulation can be lengthy, so only a few software commands are included to

demonstrate the basic operation of the peripherals.

MC68332 to Qsys The Nios II controller was created using Altera’s system integration tool (Qsys). The scope of the

reference design was limited to using existing Qsys peripherals. The table on the next page identifies the

MC68332 peripherals and possible Qsys replacements.

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MC68332 Qsys

Central Processor Unit (CPU32) Nios II Processor:altera_nios2_gen2

System Integration Module (SIM)

System Configuration and Protection

System Configuration Altera: On chip configuration Flash

System Protection Control Register no "off the shelf" equivalent NIOS function

Module Configuration and Test no "off the shelf" equivalent NIOS function

Bus Monitor equivalent debug features use Eclipse

Halt Monitor equivalent debug features use Eclipse

Spurious Interrupt Monitor equivalent NIOS feature

Software Watchdog Timer Qsys: Interval Timer

Periodic Interrupt Timer Qsys: Interval Timer

System Clock

Clock Sources Altera PLL (25MHz)

Clock Synthesizer Operation Altera PLL (25MHz)

Clock Control Altera PLL (25MHz)

External Bus Interface

Qsys: Avalon-MM simple slave with interrupt. Note: The MC68332 Memory Interface could be implemented with a custom IP block.

Bus Control Signals

Function Codes

Address Bus

Address Strobe

Data Bus

Data Strobe

Bus Cycle Termination Signals

Data Transfer Mechanism

Dynamic Bus Sizing

Operand Alignment

Misaligned Operands

Operand Transfer Cases

General Purpose Input/Output Qsys: PIO for port f,e,c

Resets Qsys:Clock and Reset

Interrupts Qsys: Interrupt Controller

Queued Serial Module (QSM)

QSPI Qsys: Serial:SPI

SCI Qsys: UART

Time Processor Unit (TPU)

MC68332 and MC68332A Time Functions

Discrete Input/Output (DIO) Qsys: PIO

Input Capture/Input Transition Counter (ITC) no equivalent "off the shelf" IP available

Output Compare (OC) no equivalent "off the shelf" IP available

Pulse Width Modulation (PWM) Custom PWM IP function included

Synchronized Pulse-Width Modulation (PWM) no equivalent "off the shelf" IP available

Period Measurement with Additional Transition Detect (PMA) no equivalent "off the shelf" IP available

Period Measurement with Missing Transition Detect (PMM) no equivalent "off the shelf" IP available

Position-Synchronized Pulse Generator (PSP) no equivalent "off the shelf" IP available

Stepper Motor (SM) no equivalent "off the shelf" IP available

Period/Pulse-Width Accumulator (PPWA) no equivalent "off the shelf" IP available

Quadrature Decode (QDEC) no equivalent "off the shelf" IP available

Static RAM Module with TPU Emulation Capability (TPURAM)

2-Kbyte array of fast static RAM Configurable 32768 memory

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Creating the Hardware Please perform the following steps:

Setting up the files

1. Copy the MC68332_REF design and then extract the design to a working directory.

2. Start the Quartus II software

3. Browse to the directory where you extracted the design.

4. Select top.qpf

5. Click open

6. On the tools menu of the Quartus II window, click Qsys.

7. Open the mc68332.qsys file.

Generating the Qsys design

You should now see a window like the one below.

1. At the bottom of the QSYS window press the Generate HDL button.

2. Fill out the dialog window like the one shown below:

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3. Now press generate

4. Once Generate completes, close the Generate Completed dialog box.

Creating the testbench

5. Under the Generate tab at the top left of the QSYS tool page, select “Generate Testbench

System”. This will open the testbench generation tool. Please fill out the dialog box like the one

shown below:

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6. Click Generate

7. Once completed, press Finish on the lower right corner of the Qsys tool.

At this point, all of the steps necessary to simulate the Nios II design have been completed. There is

“NO” need to compile the design in the Quartus II tool.

Creating the Software This reference design uses software as input stimulus for the testbench. All of the included peripherals

can be exercised in this manner. This design only exercises the output ports of the design, thus four

peripherals will be exercised. These peripherals include a SPI interface, UART, PIO and custom PWM

module.

The software projects are located in software directory of your project directory.

1. Open the Nios II 15.0 Software Build Tools for Eclipse from your Altera Nios II EDS installation

directory.

2. Select your workspace to be the software directory where the MC68332 reference design is

located.

3. The Eclipse IDE should open without any projects visible. See window below:

4. Under the File tab, select import. This will open the Import dialog box.

5. In the Import dialog box select General and Existing Projects into workspace.

6. Click “Next”

7. Browse to the location of the Software directory located in the MC68332 reference design.

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8. Two directories should be visible in the Import dialog box. Click “Finish”.

9. Your Eclipse IDE should now show MC68332_software and MC68332_software_bsp under the

Project Explorer window. See below:

10. Because we re-generated the QSYS design, it is necessary to update the existing BSP.

11. Right click the BSP project. Scroll down to the NIOS II, open the sub menu and Click Generate

BSP. This will refresh the BSP with the updated Qsys generation. See Below:

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12. Once the BSP generation is complete. Right click the “mc68332_software” project and select

build project. See below:

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The software portion of the design has now been completed.

Simulating Before beginning verify that you have installed the ModelSim tool. The ModelSim tool should be located

in your Quartus II install directory.

1. Right click the “mc68332_software” project and expand the “Run As” menu. Click Nios II

ModelSim. See below:

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This should begin execution of the ModelSim tool. If you encounter a problem, using the same

procedure above, select Run Configurations. Configure your window like the one shown below. Pay

careful attention to the ModelSim path and the Qsys Testbench Simulation Package Descriptor File

name. See below:

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Once the ModelSim tool opens the default window should look like the one shown below:

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1. Begin by executing the wave.do file located in the simulation directory of the MC68332

reference design directory. To do this Click the File tab at the top of the ModelSim tool, Click

Load, and then Click Macro File. Now browse to the simulation directory located in MC68332

project directory. See below:

2. Select the wave.do file.

3. The wave window should now be populated with the target signals. See below

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4. We can now begin the simulation by typing “run 1ms” at the VSIM > prompt. See below:

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5. The simulation will begin and your ModelSim transcript window should look like the one below:

6. The wave window will begin displaying signals. This simulation takes 10 to 20 minutes to run.

You can zoom in and out of the wave by Left clicking anywhere in the wave window and then

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use the “I” key (zoom in), ‘o’ key (zoom out) or “c” key (zoom around cursor). The cursor is the

yellow time bar.

The following peripherals can be viewed in ModelSim waveform viewer: PWM, PIO, SPI and JTAG UART.

A value of “F’ is written to the PWM period register and a value of “7” is written to the PWM High

register. The result is a pulse train like the one shown below (zoom in to see this).

The value “101010: is written out to the PORT C output bus.

The value “5A” is written out on the MOSI pin of the SPI interface. You can see that 5A is written out

consecutively using all 4 chip selects.

The UART output “Hello from Nios II!” can be viewed ModelSim transcript window at the end of the

simulation.

MC68332 Replacement Components While the Qsys IP catalog contains a number of components that can be used to create an equivalent

MC68332 system, there are a number of MC68332 components that are not available. The Qsys

Component Editor allows users to develop their own custom components that can be seamlessly

mapped to the Avalon system bus. Thus, equivalent MC68332 functions can be developed and added to

the Qsys IP library.

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PWM Component Example The MC68332 Time Processor Unit (TPU) is a 16 channel configurable module that provides a number of

preprogrammed timing functions. One of the TPU’s functions is Pulse Width Modulation (PWM). The

PWM function can generate a pulse width modulation waveform within the resolution capability of the

MC68332’s system clock (approximately 20 MHz). Configuring the PWM is achieved by writing two

parameters to the PWM module. These parameters determine the period and high time of the PWM

waveform. Both parameters are supplied to the module as 16 bit values.

A similar architecture was selected for the custom PWM module provided in the design. The PWM

module is configured by writing a single 32bit value to the module. The lower 16 bits determine the

period, while the upper 16 bits determine the waveforms high time. The custom module was developed

and mapped on to the Avalon system bus using the Qsys Component Editor. The example below is one

approach for creating a PWM component that can be used in the Qsys environment:

First, Develop a Pulse-Width Modulation RTL Module with Avalon Interface. The interface to the PWM

module must match the Avalon Slave timing to operate properly. A timing waveform for the Avalon

slave interface can be viewed in the component editor, once a Avalon slave interface template is

selected.

Second, create a testbench and verify the design using Modelsim. Verification of the PWM module

should be done at the module level to insure functionality and performance prior to building the

component.

clk

writedata

readdata

write

read

t0 t1 t2 t3 t4 t5

Avalon Slave Timing PWM Interface

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Third, create a component with the Qsys Component Editor.

The name, version, and group can be tracked by entering the information in the ‘Component Type’ tab.

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The source files for synthesis and simulations are both required to complete a component. You can use

the same source file for both the Synthesis and simulation entries. It is also important to specify the

‘attributes’ for the target simulation vendor. For example, if you are going to use ModelSim for

simulation then select Mentor specific in the attributes field of verilog simulation files.

The top level signal types must be specified in order for Qsys to recognize the difference between the

Avalon slave interface, clock, reset, and any external conduits. The conduits are used to identify any

signals not specifically identified by the Avalon slave interface.

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You can refer to the following files included in this reference design (in the pwm_files folder):

Files Description

pwm.v verilog module

pwm_tb.v verilog test bench

pwm.do modelsim do file

pwm_hw.tcl component definition file