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MOS VLSI DESIGN

KAUSHIK ROY EDWARD G. TIEDEMANN JR. DISTINGUISHED PROFESSOR

ECE, PURDUE UNIVERSITY

Prof. Kaushik Roy

@ Purdue Univ.

Grading Policy

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Mid-terms + quizzes + hw will account for 75% of the grade – 3 mid-terms – Mandatory and has to be taken on the scheduled day of the exam.

• Project will account for 25% of the grade. Late projects will not be accepted.

• You are guaranteed an A if your weighted average score over exams, quizzes, and projects is 90 or above.

• Any form of cheating will be heavily penalized and reported to the Dean of students and may result in a failing grade.

• Instructor reserves right to change project requirements.

Text and References

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Text: – Digital Integrated Circuits: A Design Perspective,

J. Rabaey et. al., Prentice Hall, Second edition

• References: – Principles of CMOS VLSI Design: A Systems Perspective,

2nd Ed., N. H. E. Weste and K. Eshraghian, Addison Wesley

– Circuits, Interconnects, and Packaging for VLSI, H. Bakoglu, Addison Wesley

• Class Notes: – http://www.ece.purdue.edu/~vlsi/ee559/2013

Conferences & Journals

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• IEEE Transactions on VLSI Systems • IEEE Transactions on Electron Devices • Electron Device Letters • IEEE Transactions on nanotechnology • IEEE Transactions on CAD of IC’s • IEEE Journal of Solid State Circuits • IEEE VLSI Circuits Symposium • Journal of Electronic Testing • ACM Design Automation Conference • IEEE International Conference on CAD • IEEE Solid State Circuits Conference • International symposium on Low-Power Electronics & Design • IEEE Conference on Computer Design • IEEE International Test Conference

Course Outline

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Introduction: Historical perspective and Future Trend • Semiconductor Devices – On-current, Off-current, Short-channel

effects and how it impacts design, transistor parameter variations; technology directions (Bulk, Multi-gate transistors)

• CMOS Logic: Basic CMOS logic gates and different logic styles (Ratioed logic, Standard CMOS, Domino, DCVS, ..); Inverter transfer characteristics, static and dynamic behavior, power and energy consumption of static MOS inverters; scaling implications; designing for low-leakage; Implications of different transistor technologies (Bulk, SOI, double/tri-gates) on circuit design

Course Outline (Cont’d)

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Low Voltage Low Power Logic – Near-threshold logic operation, designing for low-leakage current

• On-chip memory design in scaled technologies: Different FF’s, 6-T SRAM bit-cells (stability analysis: read, write, hold, access under parameter variations), robust design of 6-T SRAMs, Bit-cells for low voltage and low-leakage (6-T, 8-T configurations and analysis); technology considerations (Bulk versus Multi-gate)

• Technology directions – high density on-chip magnetic memories

• Interconnect and timing issues • Design of circuits in CMOS and other emerging technologies

and circuit evaluation using PETE (in the nanohub)

VLSI CAD Lab and TA

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• VLSI CAD Lab located in 360 Potter – SUN workstations running Cadence and Synopsys tools – Courtesy key for after-hour access can be obtained from

front desk in Potter Engineering Library – Additional workstations in MSEE 186

• Lab TA: – Facilitates the use of lab design tools. – Office hours: TBA – Lab Orientation will be held in the second week

• Lab URL – http://min.ecn.purdue.edu/~mgcdevel/ee559_lab.html

Course Project

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Complete design of a functional logic block or system – Complexity of 5000+ transistors – Design using the CADENCE tools and HSPICE

• Design your own library from scratch – Functionality to be verified – Critical path timing should be verified using HSPICE – Project report due the last day of class – Project presentation by each group in the last week of class – Work in a group of 2 will be allowed in special cases – Start early! – Emphasis on power dissipation, performance, reconfigurability, low

voltage design

A Historical Perspective and Future Trends

Prof. Kaushik Roy

@ Purdue Univ.

References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey © UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

The First Computer

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• The Babbage Differential Engine (1834)

• 25,000 mechanical parts • Cost £17,470

Digital Electronic Computing

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Started with the introduction of vacuum tube • ENIAC for computing artillery firing tables in 1946 • Integration density

– 80 feet long, 8.5 feet high, and several feet wide – 18,000 vacuum tubes

• Reliability issues and excessive power consumption • Did not go far until the invention of the transistor at

Bell Lab in 1947

HISTORY

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• MOS field-effect transistor: Lilienfeld (1925), Heil (1935)

• Bipolar transistors: Bardeen (1947), Schockley (1949)

• First Bipolar digital logic: Harris (1956) – IC Logic family:

• Transistor-Transistor Logic (TTL) (1962)

• Emitter-Coupled Logic (ECL) (1971)

• Integrated Injection Logic (I2L) (1972)

• PMOS and NMOS transistors on the same substrate: Weimer (1962), Wanlass (1965)

• PMOS-only logic until 1971 when NMOS technology emerged • NMOS-only logic until late 1970s, when CMOS technology took

over • Later developments: BiCMOS, GaAs, low-temperator CMOS,

super-conducting technologies, Nano-electronic

Chip Complexity

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Clock Frequency

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Core Count

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Total Die on Cache

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Intel 4004 Microprocessor

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Intel Pentium (II) Microprocessor

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Technology Scaling

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Technology scaling improves: Transistor & interconnect performance Transistor density Energy consumed per switching transition

0.7X scaling factor (30% scaling) results in: 30% gate delay reduction (43% freq. ↑ ) 2X transistor density increase (49% area ↓ ) Energy per transition reduction

Technology Scaling

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

22 7.0

reduction)delay (30% 7.07.0

7.07.0 )(

,,7.0

β

ββ

ββ

ββ

→=

=×

→=

=× →−=

→ → →

scalesdd

scalesdd

scalestdd

scalest

scalesdd

scale

CVE

ICV

D

VVTkWI

VVDimensions

ox

Exponential Increase in Leakage

Prof. Kaushik Roy

@ Purdue Univ.

Non-Silicon Technology

Silicon Micro- electronics

Silicon Nano- electronics

1970 1980 2000 2010 2020

Junction leakage

Gate Source

n+ n+

Bulk

Drain

Subthreshold Leakage

Gate Leakage

A. Grove, IEDM 2002

Lea

kage

Pow

er (%

of T

otal

)

0%

10%

20%

30%

40%

50%

1.5 0.7 0.35 0.18 0.09 0.05

Must stop at 50%

610ON

OFF

II

= 310ON

OFF

II

= 2~6~ 10ON

OFF

II

1 µm 100 nm 10 nm 5 µm

Technology Trend

Prof. Kaushik Roy

@ Purdue Univ.

Buried Oxide (BOX)Substrate

Fully-depleted body

Gate

VG

VS VD

DrainSource

Vback

Buried Oxide (BOX)Substrate

Fully-depleted body

Gate

VG

VS VD

DrainSource

Vback

Bulk-CMOS

FD/SOI

Nano devices Carbon nanotube Graphene TFETs III-V devices Spintronics

Single gate device

2009 2020

DGMOS

FinFET Trigate

Multi-gate devices

Buried Oxide (BOX)

Substrate

Source Floating Body Drain

GateVS

VG

VD

Buried Oxide (BOX)

Substrate

Source Floating Body Drain

GateVS

VG

VD

PD/SOI

Design methods to exploit the advantages of technology innovations

Variation in Process Parameters

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Inter and Intra-die Variations

Device parameters are no longer deterministic

Device 1 Device 2

Channel length Delay and Leakage Spread

10

100

1000

10000

1000 500 250 130 65 32 Technology Node (nm)

# do

pant

ato

ms Source: Intel

Random dopant fluctuation

Reliability

Prof. Kaushik Roy

@ Purdue Univ.

Temporal degradation of performance: NBTI, HCI, TDDB

Tech. generation

Failu

re p

roba

bilit

y

Time

Defects Life time degradation

Power & Power Density

Prof. Kaushik Roy

@ Purdue Univ.

Year

Pow

er (W

atts

)

P6 Pentium ® proc

486

386

286 8086

8085 8080

8008 4004

0.1

1

10

100

1971 1974 1978 1985 1992 2000 Po

wer

Den

sity

(W/c

m2 )

Year

Increased Average Power • Battery Life • Cooling Cost

Increased Power Density • Reliability

Source: Intel

Supply Voltage & Transistor Threshold Voltage

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

1.4 1.0 0.8 0.6 .35 .25 .18Technology Generation (µm)

0

1

2

3

4

5

0 1 2 3 4 5 6 7

VC

C o

r VT (V

)

VT=.45V

VCC=1.8V

VCC

VT

(VCC- VT)Gate over drive

V CC o

r V T

(V)

5

4

3

2

1

0

Voltage scaling is good for controlling IC’s active power, but it requires aggressive VT scaling for high performance

Barriers to Voltage Scaling

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Technology Generation

Subt

hres

hold

Lea

kage

1

10

100

1000

0.25um 0.18um 0.13um 0.09um

constrained Ioff maintain Vcc/Vt

Leakage power Short-channel effects Soft error

Delay

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

2 W W

1 . τ =

− +

CL T ox

V DD V T

V DD n p

0 5 0 5

0 3 0 9 1 3

2 . .

. ( . ) . ( ) [1]

[1] C. Hu, “Low Power Design Methodologies,” Kluwer Academic Publishers, p. 25.

D

DDLd I

VC=τ

2)1()2

(DD

TDDox

Ld

VVVC

LW

C

−=

µτ

)1(DD

TSATox

Ld

VVWC

C

−=

υτ

Long Channel MOSFET

Short Channel MOSFET

Performance significantly degrades when VDD approaches 3VT.

VT Scaling: VT and IOFF Trade-off

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

As VT decreases, sub-threshold leakage increases Leakage is a barrier to voltage scaling

Performance vs Leakage:

VT ↓ IOFF ↑ ID(SAT) ↑ Low VT

High VT

VG VTL VTH

I D

S

IOFFL

IOFFH

VD = VDD fixed Tox

ID(SAT)

)()( 3 TGSSAToxeffD VVCWKSATI −∝ υ

22 )()( TGS

eff

effD VVK

LW

SATI −∝

)(1

TGS VV

eff

effsubthOFF eK

LW

II −∝∝

Why Excessive leakage an Issue?

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Leakage component to active power becomes significant % of total power

• ~10% in 0.18 µm technology

• Acceptable limit less than ~10%, implies serious challenge in VT scaling!

1.0 0.8 0.6 .35 .25 .18

100

10

1

10-1

10-2

10-3

10-4

10-5

10-61.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

0 1 2 3 4 5 6 7

Active Power

Standby power (component Transistor

Leakage T=110C)

486DX CPU

Pentium Processor386

Pentium Pro Processor

R

R

Technology Generation (µm)

101

101

100

10-1

10-2

10-3

10-4

10-5

10-6

Pow

er

(W)

Trends in Microelectronics

Source: Intel30

Prof. Kaushik Roy

@ Purdue Univ.

• Improvement in device technology – Smaller circuits – Faster circuits – More circuits on a chip

• Higher Integration – More complex systems – Lower cost of computation – Higher reliability

• Limitations – Intrinsic device scaling limits – Cost of fabrication – Interconnect limitation – Large scale design management

Issues/Considerations

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Design Cost: – design time – fabrication time – impossibility to repair – reduce design cost to be competitive in price

• Marketing Issues: – use most recent technologies to stay competitive in

performance – volume production is inexpensive – time-to-market is critical – evolving market

• Solution: – Hierarchical and abstraction – Different design styles – Computer-Aided-Design

Circuit and System Representations

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• 3 design domains – Behavioral

• specifies what a particular system does – Structural

• how entities are connected together to effect the prescribed manner

– Physical • how to actually build a structure that has the required

connectivity to implement the prescribed behavior

Complex digital system Component gates +

Memory systems

Design Abstraction Levels

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

For a Digital Design

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Architecture • Algorithm • Module or Functional Block • logical • Switch • Circuit • Layout

Behavioral Representation Domain

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• Hardware description language – VHDL, Verilog

• Boolean equation • Within this domain, there are various level of

abstraction – Algorithm – Register transfer level (communication between registers)

– Boolean equations CO = A.B + A.C + B.C

carry

Acc ← Acc + R1

Behavioral Representation Domain - cont.

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

output co input a, b, c

MODULE carry (co, a,b,c)

ENDMODULE

can include speed info assign co = (a&b)|(a&c)|(b&c);

• Algorithm level (Verilog)

Structural Domain

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

input a, b, c; output co;

MODULE carry (co, a, b, c)

wire x, y, z AND g1 (x, a, b) AND g2 (y, a, c) AND g3 (z, b, c) OR g4 (co, x, y, z);

ENDMODULE

• The levels of abstraction include – module – gate – switch – circuit

Structural Domain- cont.

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

a b

a c

x b c

z

y x y

co

g3

g4 g2

g1

z

Transistor Level

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

input a, b, c; output co;

MODULE carry (co, a, b, c)

wire i1, i2, i3, i4, cn;

ENDMODULE

NMOS n1(i1, vss, a) NMOS n2(i1, vss, b)

PMOS p1(i3, vdd, b); PMOS p2(cn, i3, a);

. . .

. .

.

Physical Representation

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Input a, b, c; output co;

MODULE carry ;

boundary [0, 0, 100, 400] port a aluminum width = 1 origin = [0,2] port b aluminum width = 1 origin = [0,7]

ENDMODULE

.

. port

Port ci polysilicon ……. .

CMOS Logic

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

Consider them as switches

s = 0

s = 1

a

a

b

b

s = 0

a

a

b s = 0

a

b

a b

s = 1

a

b

s = 1 a b b

a a

NMOS transistor PMOS transistor b

s s

b

Inverter (A)

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

- Low power dissipation

VDD

B A

Particle Location is an Indicator of State

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

1 1 0 0 1 0

A physical system as a computing medium

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• We need to create a bit first. Information processing always requires physical carrier, which are material particles.

• First requirement to physical realization of a bit implies creating distinguishable states within a system of such material particles.

• The second requirement is conditional change of state.

• The properties of distinguishability and conditional change of state are two fundamental properties of a material subsystem to represent information. These properties can be obtained by creating energy barriers in a material system.

Kroemer’s Lemma of Proven Ignorance

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

• If in discussing a semiconductor problem, you cannot

draw an Energy-Band-Diagram, this shows that you don’t know what are you talking about

• If you can draw one, but don’t, then your audience won’t know what are you talking about

Barrier engineering in semiconductors

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.

n n

p

By doping, it is possible to create a built-in field and energy barriers of controllable height and length within semiconductor. It allows one to achieve conditional complex electron transport between different energy states inside semiconductors that is needed in the physical realization of devices for information processing.