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Sheet
1 of 14
MOS Differential LNA Design Tutorial J P Silver
E-mail: [email protected]
1 ABSTRACT
This tutorial describes the theory and design on a MOS
Differential Low noise amplifier using source de-generation. A
worked example is given together with the associated Agilent ADS
simulation circuits and plots.
2 INTRODUCTION The MOS LNA Design tutorial describes the design
of a single stage LNA using source degeneration technique to
provide a good noise match. A cascade output stage was added to the
source degenerated stage provide improved gain & reverse
isolation. This tutorial describes the design of a differential LNA
using the same design specification and device models. There are
several advantages in using a differential de-sign. Firstly, the
virtual ground formed at the ‘tail’ re-moves the sensitivity to
parasitic ground inductances, which makes the real part of the
input impedance purely controlled by the source degeneration
inductance (Ls). Secondly the differential amplification of the
signal en-sures attenuation of the common mode signal, in most
systems this common mode signal will be noise! Thirdly, the use of
Gilbert mixers and image rejection schemes require to be fed from a
differential source.
3 LNA SINGLE-STAGE DESIGN The design equations are the same as
for the single stage LNA design and are summarized below:
[ ]gs
msCGSLS
gss
gs
ms
C.gL
Ra WhereX-Xj Ra Rg Rin
as written-re be Can ωC
1ωLj C.gL
Rg Rin
=++=
⎟⎟⎠
⎞⎜⎜⎝
⎛−++=
Therefore, the impedance of the MOSFET without feed-back is:
CGSCGS jX RinjX Rg Rin −=→−=
Adding series feedback adds the following term to the original
input impedance:
jX Ra LS+
Additionally, another inductor is added in series with the gate
Lg that is selected to resonate with the Cgs Capacitor. What we are
trying to achieve is:
0ωC
1ωLj
ie Cgs out cancels it frequency resonant the at that so designed
is Lg
ohms. 50say bemay Rin WhereC.gL
Rin
gss
gs
ms
=⎟⎟⎠
⎞⎜⎜⎝
⎛−
=
In most LNA designs the value of Ls is picked and the values of
gm and Cgs are calculated to give the required Rin.
4 DESIGN EXAMPLE The aim of this example is to design
step-by-step a nar-row band LNA (Low noise amplifier) to work over
the Bluetooth frequency band. A summary of the required
specification for the LNA is given in Table 1. Parameter
Specification Units Frequency 2.45 to 2.85 GHz Noise Figure 20 dB
Power Gain >10 dB Power consumption
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Sheet
2 of 14
Rs = 50Ω
Lg
M1 Using Agilent
CMOS14 process
Vbias
Ls
Lbias
Vcc +1.5V
Figure 1 Initial single-stage LNA schematic
4.1 STARTING VALUE OF DE-GENERATION INDUCTOR LS. The value of
this inductor is fairly arbitrary but is ulti-mately limited on the
maximum size of inductance al-lowed by the technology, which is
typically about 10nH (anything bigger would probably be too big to
be put on the chip). For this example we will pick a value of
1.0nH. We now find the cut-off frequency defined as:
16GHz)(~rad/sec 1E 0.5E
50 LsRs ω 119-T ==== Cgs
gm
4.2 OPTIMAL Q OF INDUCTOR Optimal Q is given by:
.γδ.α5
p Where
p11QL
2
=
+=
The parameters for p are dependant on the CMOS tech-nology but
typically
0.9) be to (take 1-0.8 be to assumed is α4)(normally of value
the times 3-2 to set is δ
2)(normally 3 - 2 between set is γ
γ
2.67 0.162
11QL
0.162 45
)9.0(4 p2
=+=
==.
.
4.3 EVALUATION OF LG
7.52nH 1E-1.665E2.67.50 Lg
rad/sec 1.665E 2.65E2
frequency centreω Where
Ls-ω.RsQ Lg
9-10
109
o
o
L
==
=
==
=
π.
4.4 FIND CGS (GATE-SOURCE CAPACITANCE)
( )
( ) ( )pF45.0
E5.07.52E1.665E
1Cgs
LsLgω1Cgs
99210
2o
=+
=
+=
−−
4.5 FIND W
330umW
330 .0.63.419E
0.45.23 W
pF/um3.419E 1.01E
8.854E x 3.9 ToxεoxCox
F/cm8.854E space free for constant dielectric εoand 3.9 silicon
for constant dielectric εs
Where
εo .εox εox
m1.01E Tox m;0.6E Lmin
Cox.LCgs
23 W
ie Wget to rearrange Cox.W.L32 Cgs
3-
23-8-
14-
14-
8-6-
min
min
=
==
===
==
==
=
==
=
=
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Sheet
3 of 14
4.6 CALCULATE GM
0.045A/V .0.45E1Egm
.Cgsωgm
12-11
T
==
=
4.7 V EFFECTIVE
gate the toV 16.1 0.5)(0.67
apply to need weTherefore,
0.67V VTWith
0.5V 164.330
45000.0.6Veff
:gives units Converting433cm/V mobility deviceu
.Cox.Wugm.L
)V(VgsVeff
n
n
minT
=+
=
==
==
=−=
4.8 BIAS CURRENT ID
mA11.0.5045.0.21 gm.V.
21 Id eff ===
(9) Estimated Optimum Noise Figure
( )
[ ]( )
3.26dB )10log(2.12 2.12Fopt
162.01162.04.0162.05E
1.665E0.941
Fopt4.0c Take
1cωω
α2γ1Fopt
10
10
T
o
===
+++⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
=
+++⎟⎟⎠
⎞⎜⎜⎝
⎛+= ppp
To complete the design another N-type is added as the cascode
stage with the same W/L ratio as the LNA device. The cascode stage
is connected at a iode ie the gate is DC connected to the drain to
en-sure the device is in saturation. Finally it is as-sumed that
on-chip spiral inductors will be used in the design, which will
have a typical loaded Q of 6.
5 DIFFERENTIAL LNA DESIGN The basic circuit of the differential
LNA is shown in Figure 2. As can be seen each half of the
differ-
ential amplifier is in fact the single LNA designed earlier in
this tutorial (ie with a 50ohm input im-pedance set by making gm =
20mS), with the de-generating inductors (Ls) connected together at
the ‘virtual earth’. At this point the a current source is
connected to the negative supply set to give twice the current
flowing down one of the LNA sections. The ADS schematic showing the
differential LNA is shown in Figure 3. Note to supply a
differential signal to each LNA input, an ‘ideal’ balun (bal-anced
to unbalanced) transformer has been used (We could also use two AC
sources each set to 0.5V and opposite polarity). In addition
another balun is used on the amplifier output to re-combine the
signal to allow the voltage gain to be simulated.
Rs = 50Ω
Lg
All devices use Agilent
CMOS14 process
Vout1
Ls
Lbias
Vcc +2.5V
Vin1
Ls Rs = 50Ω
Lg
Vin2
Vout2
Lbias
Vee -2.5V
‘Tail’ current bias
M5 ‘Virtual’ Ground
11mA
M1
22mA
M2
M3 M4
Figure 2 Schematic of the differential amplifier LNA using two
single stage LNA’s from the previous tutorials. Circuit values are
Lg = 7.52nH ; Ls = 1nH; M1,M2,M3 & M4 W/L = 330 (Lmin =
0.5um).
Calculation of Load Inductor:
10nH 0.4E
E5.2.21
C
o.21
L
L then 0.4pF of capacitor load a Assumimg
.LC21o
12-
2
9
out
2
LOAD
Load
Loadout
=⎟⎠⎞
⎜⎝⎛
=⎟⎠⎞
⎜⎝⎛
=
=
=
πfπ
πf
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Sheet
4 of 14
vg
v2v1
Balun3PortCMP1
V_ACSRC6
Freq=freqVac=polar(1,0) V
INDQL4
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Lg nH
CC5C=10 pF
VARVAR4
Lg=5.5Load=7.5Ls=0.5
EqnVar
CC4C=0.4 pFC
C3C=0.4 pF
INDQL5
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Load nH
VARVAR3Ibias=22
EqnVar
RR2R=10k
MOSFET_NMOSMOSFET4
Width=W umLength=L umModel=cmosn
vee
MOSFET_NMOSMOSFET6
Width=W umLength=L umModel=cmosn
vee
INDQL6
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Ls nH
DCDC1
DC
BSIM3_Modelcmosn
Xl=-1e-7Xw=0Em=4.1e7Kt2=0.022Kt1=-0.11Uc1=-5.6e-11
Ub1=-7.61e-18Ua1=4.31e-9At=3.3e4Ute=-1.5Pvag=0.1945781Pscbe2=5e-10Pscbe1=2.541131e10Pdiblcb=-0.5Pdiblc2=9.723614e-4Pdiblc1=2.091364e-3Pclm=0.7319137Drout=0.0428851Dsub=0.751089Etab=2.603903e-3Eta0=0.1178659
Cit=0Cdscd=0Cdscb=0Cdsc=2.4e-4Nfactor=1.2410485Voff=-0.0850186B1=5e-6B0=1.648829e-6Pags=0.0968Ags=0.1450882Wketa=-5.792854e-3Lketa=-0.0143698Keta=3.997018e-3A0=0.9059229Vsat=1.174604e5
Prwb=-0.0586598Prwg=0.0182608Prdsw=-33.9337286Rdsw=1.28604e3Delta=0.01Uc=1.831708e-11Ub=1.582544e-18Ua=1e-12Dvt2=-0.1427458Dvt1=0.9107896Dvt0=6.5803089Nlx=5.28517e-8W0=1e-5K3b=1.252205K3=68.279056
Pk2=9.631217e-3K2=-0.0316751K1=0.825917Pvth0=8.691731e-3Vth0=0.6701079U0=433.6065339Xj=1.5e-7Vbm=-3.0Nch=1.7e17Dwb=1.238214e-8Dwg=-7.483283e-9Xpart=0.5Cgbo=2e-9Cgdo=2.79e-10Cgso=2.79e-10
Pbswg=0.99Mjswg=0.1Cjswg=2.2346e-10Pbsw=0.99Pb=0.99Mjsw=0.1Cjsw=4.437149e-10Mj=0.7549569Cj=5.067009e-4Tox=1.01e-8Tnom=27Wwl=0Wwn=1Ww=0Wln=1
Wl=0Wint=2.277646e-7Lwl=0Lwn=1Lw=0Lln=1Ll=0Lint=1.097132e-7Js=0Rsh=2.8Capmod=2Mobmod=1Version=3.1Idsmod=8NMOS=yes
RR1R=10k
VARVAR1
W=330L=0.6
EqnVar
V_DCSRC1Vdc=2.5 V
I_ProbeID
INDQL1
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Lg nH
MOSFET_NMOSMOSFET1
Width=W umLength=L umModel=cmosn
vee
CC2C=10 pF
MOSFET_NMOSMOSFET3
Width=W umLength=L umModel=cmosn
vee
INDQL3
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Load nH
INDQL7
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Ls nH
ACAC1
Step=Stop=3.0 GHzStart=2.0 GHz
AC
I_DCSRC5Idc=Ibias mA
V_DCSRC4Vdc=-2.5 V
Figure 3 ADS schematic of the Common-source Differential LNA.
The differential input voltage is supplied vai the balun
transformer (CMP1). An ideal current source has been added at this
stage on the ‘tail’ set to 22mA so that 11mA will flow down each
‘arm’ of the LNA. The 0.4pF load capacitors (representing a typical
load of say a gilbert mixer) have been added to each of the two
output nodes V1 & V2.
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Sheet
5 of 14
vg
v2v1
CC5C=22 pF
CC2C=22 pF
VARVAR3Ibias=22
EqnVar
DCDC1
DC
VARVAR4
Lg=5.5Load=7.0Ls=0.4
EqnVar
VARVAR1
W2=330W1=330L=0.6
EqnVarS_Param
SP1
Step=Stop=3 GHzStart=2 GHz
S-PARAMETERS
TermTerm1
Z=50 OhmNum=1
Balun3PortCMP1
V_DCSRC1Vdc=2.5 V
RR2R=5 kOhm
RR1R=5 kOhm
MOSFET_NMOSMOSFET6
Width=W1 umLength=L umModel=cmosn
vee
MOSFET_NMOSMOSFET4
Width=W2 umLength=L umModel=cmosn
vee
MOSFET_NMOSMOSFET3
Width=W2 umLength=L umModel=cmosn
vee
MOSFET_NMOSMOSFET1
Width=W1 umLength=L umModel=cmosn
vee
TermTerm2
Z=50 OhmNum=2Term
Term3
Z=50 OhmNum=3
DC_BlockDC_Block2
DC_BlockDC_Block1
INDQL4
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Lg nH
INDQL5
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Load nH
INDQL6
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Ls nH
BSIM3_Modelcmosn
Xl=-1e-7Xw=0Em=4.1e7Kt2=0.022Kt1=-0.11Uc1=-5.6e-11
Ub1=-7.61e-18Ua1=4.31e-9At=3.3e4Ute=-1.5Pvag=0.1945781Pscbe2=5e-10Pscbe1=2.541131e10Pdiblcb=-0.5Pdiblc2=9.723614e-4Pdiblc1=2.091364e-3Pclm=0.7319137Drout=0.0428851Dsub=0.751089Etab=2.603903e-3Eta0=0.1178659
Cit=0Cdscd=0Cdscb=0Cdsc=2.4e-4Nfactor=1.2410485Voff=-0.0850186B1=5e-6B0=1.648829e-6Pags=0.0968Ags=0.1450882Wketa=-5.792854e-3Lketa=-0.0143698Keta=3.997018e-3A0=0.9059229Vsat=1.174604e5
Prwb=-0.0586598Prwg=0.0182608Prdsw=-33.9337286Rdsw=1.28604e3Delta=0.01Uc=1.831708e-11Ub=1.582544e-18Ua=1e-12Dvt2=-0.1427458Dvt1=0.9107896Dvt0=6.5803089Nlx=5.28517e-8W0=1e-5K3b=1.252205K3=68.279056
Pk2=9.631217e-3K2=-0.0316751K1=0.825917Pvth0=8.691731e-3Vth0=0.6701079U0=433.6065339Xj=1.5e-7Vbm=-3.0Nch=1.7e17Dwb=1.238214e-8Dwg=-7.483283e-9Xpart=0.5Cgbo=2e-9Cgdo=2.79e-10Cgso=2.79e-10
Pbswg=0.99Mjswg=0.1Cjswg=2.2346e-10Pbsw=0.99Pb=0.99Mjsw=0.1Cjsw=4.437149e-10Mj=0.7549569Cj=5.067009e-4Tox=1.01e-8Tnom=27Wwl=0Wwn=1Ww=0Wln=1
Wl=0Wint=2.277646e-7Lwl=0Lwn=1Lw=0Lln=1Ll=0Lint=1.097132e-7Js=0Rsh=2.8Capmod=2Mobmod=1Version=3.1Idsmod=8NMOS=yes
I_ProbeID
INDQL1
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Lg nH
INDQL3
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Load nH
INDQL7
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Ls nH
I_DCSRC5Idc=Ibias mA
V_DCSRC4Vdc=-2.5 V
Figure 4 ADS schematic of the Common-source Differential LNA.
The small signal input power is supplied via the balun transformer
(CMP1). An ideal current source has been added at this stage on the
‘tail’ set to 22mA so that 11mA will flow down each ‘arm’ of the
LNA. The two output nodes V1 & V2 are now terminated in 50-ohm
loads – Note the DC blocks to ensure that the DC bias condition, is
not upset by the loads.
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Sheet
6 of 14
5.1 ESTIMATION OF DIFFERENTIAL GAIN
32dB20log(41)(dB)A
412.5E x 2π x 0.4E
6 x 0.043 Co.2πo.2gm.Q
A
0.043 E11 0.6300.170E x 2 gm
I.LW2.Kp. gm
LNA
912-LOAD
LNA
36-
DS
==
===
==
==
−x
This gain is for one C-S stage and as the output are not
combined the gain of the differential amplifier will be half that
for a single stage ie 3dB less. This will make the predicted gain
of our example 29dB. Note to centre the gain response the load
inductors were reduced to 7nH.
m1 freq=2.493GHz dB(AC.vout1)=27.176
2.2 2.4 2.6 2.8 2.0 3.0
16 18 20 22 24 26
14
28
freq, GHz
dB(AC.vout1) m1
DC.ID.i 11.00mA
Figure 5 Simulation result of the ADS schematic shown in Figure
3. The predicted voltage gain is 29dB, which is pretty close to the
simulated re-sult and much greater than the specification of 20dB.
Note to centre the gain response, the load inductors were reduced
from 10nH to 7nH.
5.2 S-PARAMETERS The differential voltage gain is predicted to
be ~29dB exceeding our specification for voltage gain, but power
gain requirement has to met too. To check the power gain ie S21 we
need to configure the ADS schematic of the LNA with an S-Parameter
simulator. This is show in Figure 4 with the resulting simulation
result shown in Figure 6.
DC.ID.i11.00mA
m1 freq=2.513GHzdB(S(2,1))=8.315
2.2 2.4 2.6 2.8 2.0 3.0
6.5
7.0
7.5
8.0
8.5
6.0
9.0
freq, GHz
dB(S(2,1))
m1
m2 freq=2.503GHznf(2)=2.877
2.2 2.4 2.6 2.8 2.0 3.0
2.7
2.8
2.9
3.0
3.1
3.2
2.6
3.3
freq, GHz nf(2)
m2
Figure 6 Simulation of power gain (S21) and noise figure of the
LNA using the setup shown in Figure 4.
The simulation plot of Figure 6, shows the classic gain/noise
trade-off of LNA design. To peak the gain at 2.5GHz we need to
increase the gate inductance (Lg), to peak the noise we need to
decrease the noise figure. The noise specification for this LNA
is
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Sheet
7 of 14
DC.ID.i 11.00mA
m1 freq=2.513GHz dB(S(2,1))=9.271
2.2 2.4 2.6 2.8 2.0 3.0
8.0
8.5
9.0
7.5
9.5
freq, GHz
dB(S(2,1)) m1
m2freq=2.503GHz nf(2)=3.135
2.2 2.4 2.6 2.8 2.0 3.0
3.2
3.3
3.4
3.1
3.5
freq, GHz
nf(2)
m2
Figure 7 ADS simulation of the circuit shown in Figure 4 with
each Lgate increased to 7nH to cen-ter the gain response at 2.5GHz.
Note that the noise figure has now degraded to 3.1dB. Further
optimization is required to increase S21 to > 10dB.
DC.ID.i 20.00mA
m1 freq=2.513GHz dB(S(2,1))=10.883
2.2 2.4 2.6 2.8 2.0 3.0
10.0 10.2 10.4 10.6 10.8
9.8
11.0
freq, GHz
dB(S(2,1)) m1
m2freq=2.503GHz nf(2)=2.397
2.2 2.4 2.6 2.8 2.0 3.0
2.40 2.45 2.50 2.55
2.35
2.60
freq, GHz
nf(2)
m2
Figure 8 ADS simulation of the circuit shown in Figure 4 with Lg
decreased to 4.5nH, Ls reduced to 0.35nH, Cascode width increased
to 660um, Input device width increased to 530um and the current
through each arm increased to 20mA .
Although the specification for power gain is now met, a 1.8dB
margin might be unacceptable when taking into account process and
temperature varia-tions. Therefore, the final design gain is
increased by adding simple C-S stages with inductive loads and
decoupled on the output by small value capaci-tor. This output
stage is DC coupled to the output of the first ‘cascode’ stage so
that is receives a cor-rect bias to be in saturation. The increased
gain will greatly improve the noise figure of the receiver as the
noise figure of the second stage (most likely the mixer) will be
reduced by ~1/gain_LNA. The modified circuit and increased gain
responses are shown in Figure 9 and Figure 10.
DC.ID.i11.00mA
m1freq=2.490GHz dB(S(2,1))=24.145
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.41.4 3.6
16
18
20
22
24
14
26
freq, GHz
dB(S(2,1))
m1
m2freq=2.498GHz nf(2)=2.936
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.41.4 3.6
3.0
3.5
4.0
2.5
4.5
freq, GHz
nf(2)
m2
Figure 9 Gain & noise plots from the differential LNA with
added C-S stage on the output (with a tuned inductive load).
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Sheet
8 of 14
v2
vg
v1
INDQL9
Rdc=0.0 OhmMode=proportional to F=2400.0 MHzQ=6L=Load
MOSFET_NMOSMOSFET7
Width=330 umLength=L Model=cmos
CC3C=0.4 pF
Term Term1 Z=50 Ohm Num=1
TermTerm2
Z=50 OhmNum=2
S_ParamSP1
Step=Stop=3.5 GHzStart=1.5 GHz
S-PARAMETERS
CC6C=10 pF
INDQ L8
Rdc=0.0 OhmMode=proportional to F=2400.0 MHzQ=6 L=1 nH
MOSFET_NMOS MOSFET4
Width=W um Length=L Model=cmos
vee
VARVAR4
Lg=5.5Load=7.0Ls=0.5
EqnVar
Balun3PorCMP1
INDQL4
Rdc=0.0 Ohm Mode=proportional to F=2400.0 MHz Q=6L=Lg nH CC5
C=10 pF
INDQL5
Rdc=0.0 Ohm Mode=proportional to F=2400.0 MHz Q=6L=Load
VARVAR3Ibias=22
EqnVar
R R2 R=10k
MOSFET_NMOS MOSFET6
Width=W um Length=L Model=cmos
vee
INDQL6
Rdc=0.0 OhmMode=proportional to F=2400.0 MHzQ=6L=Ls nH
DC DC1
DC
BSIM3_Modecmosn
Xl=-1e-7 Xw=0 Em=4.1e7Kt2=0.022Kt1=-0.11Uc1=-5.6e-
Ub1=-7.61e-Ua1=4.31e-At=3.3e4 Ute=-1.5
Pvag=0.194578Pscbe2=5e-Pscbe1=2.541131ePdiblcb=-Pdiblc2=9.723614ePdiblc1=2.091364ePclm=0.731913Drout=0.042885Dsub=0.75108Etab=2.603903e-Eta0=0.117865
Cit=0Cdscd=0Cdscb=0Cdsc=2.4e-4Nfactor=1.241048Voff=-B1=5e-6B0=1.648829e-Pags=0.096Ags=0.145088Wketa=-5.792854e-Lketa=-Keta=3.997018e-A0=0.905922Vsat=1.174604e
Prwb=-Prwg=0.018260Prdsw=-Rdsw=1.28604eDelta=0.01Uc=1.831708e-Ub=1.582544e-Ua=1e-12Dvt2=-Dvt1=0.910789Dvt0=6.580308Nlx=5.28517e-W0=1e-5K3b=1.25220K3=68.27905
Pk2=9.631217e-K2=-K1=0.82591Pvth0=8.691731e-Vth0=0.670107U0=433.606533Xj=1.5e-7Vbm=-3.0Nch=1.7e1Dwb=1.238214e-Dwg=-7.483283e-Xpart=0.5Cgbo=2e-Cgdo=2.79e-Cgso=2.79e-
Pbswg=0.99Mjswg=0.1 Cjswg=2.2346e-Pbsw=0.99 Pb=0.99 Mjsw=0.1
Cjsw=4.437149e-Mj=0.754956Cj=5.067009e-Tox=1.01e-8 Tnom=27
Wwl=0Wwn=1 Ww=0Wln=1
Wl=0 Wint=2.277646e-Lwl=0 Lwn=1 Lw=0 Lln=1 Ll=0
Lint=1.097132e-Js=0 Rsh=2.8 Capmod=Mobmod=1 Version=3.1Idsmod=8
NMOS=yes
R R1 R=10k
VARVAR1
W=330L=0.6
EqnVar
V_DCSRC1Vdc=2.5 V
I_Probe ID
INDQ L1
Rdc=0.0 OhmMode=proportional to F=2400.0 MHzQ=6 L=Lg nH
MOSFET_NMOS MOSFET1
Width=W um Length=L Model=cmos
vee
C C2 C=10 pF
MOSFET_NMOSMOSFET3
Width=W um Length=L Model=cmos
vee
INDQL3
Rdc=0.0 OhmMode=proportional to F=2400.0 MHzQ=6L=Load
INDQL7
Rdc=0.0 OhmMode=proportional to F=2400.0 MHzQ=6L=Ls nH
I_DCSRC5Idc=Ibias mA
V_DCSRC4Vdc=-2.5 V
Figure 10 ADS schematic of the differential LNA with a C-S stage
added to the cascode output. Note for clar-ity only one extra C-S
stage has been added, normally another stage would be added to M1.
To complete the design a current mirror (and associated bias
network) will replace the ideal 11mA current source (SRC5).
6 LINEARITY This final section deals with estimating the 1dB
gain compression point and IM3 (3rd order inter-modulation
products). If an amplifier is driven hard enough the output power
will begin to roll off re-sulting in a drop of gain known as gain
compres-sion. The measurement of gain compression, is given by the
1dB gain compression point. This pa-rameter in another measure of
the linearity of a de-vice and is defined as the input power that
causes a 1dB drop in the linear gain due to device saturation. An
example of the 1dB compression point is shown in Figure 11.
We can get a rough estimate of the gain compres-sion of the LNA
a non-linear expression of the in-put and output parameters can be
expanded using Taylor’s theorem. This results in the following
equations for 1dB gain compression point and IM3 [3].
-
Sheet
9 of 14
1dB Compression Point 20dBm
0
5
10
15
20
25
30
-10 -5 0 5 10Pin (dBm)
Pout (dBm)
1dB gain change
Saturated Output Power 21dBm
Figure 11 Compression point plot. The red curve is the gain
compression characteristic of a 15dB gain amplifier. The parallel
black line is 1dB be-low and represents a gain of 14dB. The input
power where the amplifier gain crosses the 1dB down line is know as
the 1dB input compression point.
od.V1eff Where
eff
sat2V satE
by given strength field saturation Velocity satE
and Vt- Vgs overdrive Voltage odV
With
.LsatEodV
2odV.ox.CvsatWDSATI
ϑ+==
=
==
+=
oµµµ
(1) - .2
.11.4
.11.1
.29.0~2
1 ⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟
⎟⎠
⎞⎜⎜⎝
⎛+
LV
Vµ
LV
VµV
RsµLVP
sat
od
sat
odod
satdB
to convert to dBm = 10 log (1000*P1dB)
Vsat.L2oµ1µ
(2) - .L2V
.V1µ1.L4V
.V1µ1V.Rs1µ
.LV38~
2
sat
od
sat
od
odsat
IIP3
ϑ+≅
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛+
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛+P
Example Running the simulation shown in Figure 10, the values of
Vgs = 1.26V. Using the spice model data for the Agilent CMOS14
0.5um we have: L = 0.6um, µ0 = 433 cm^2/(V*s), θ = 0.1, Rs = 50
ohms, VT = 0.67V Vsat = 1.73E5 m/s First convert numbers to metre
format: µ0 = 433 cm^2/(V*s), = 0.433 m^2/(V*s L = 0.6um, =
0.6E-6m.
0.59V 0.67-1.26 TV-gs VodV ===
453 .0.6EE2x0.1x1.730.4331
65 =+≅ −µ
Feeding these values into equations 1 & 2 yields P1dB =
9.39dBm and IIM3 = 19.02dBm. The equations 1 & 2 were entered
into a spread-sheet, along with a range of Vod from 0.01 to 5V. The
table of results is shown in Table 2.
Vod (V) Input 1dB Comp IIMP3 (dBm) (dBm)
0.01 -10.05 -0.41 0.5 8.42 18.05 0.59 9.39 19.02
1 12.77 22.40 1.5 15.74 25.37 2 18.09 27.72
2.5 20.07 29.70 3 21.80 31.43
3.5 23.34 32.97 4 24.73 34.37
4.5 26.01 35.64 5 27.19 36.82
Table 2 Calculated 1dB compression point & 3rd order
intercept point.
-
Sheet
10 of 14
The following two graphs show the plotted data of the data shown
in Table 2. 1dB compression point is shown in & 3rd order
in-tercept point is shown in Figure 12 and Figure 13
respectively.
Input referred 1dB compression point vs Vod
-15
-10
-5
0
5
10
15
20
25
30
0 1 2 3 4 5
Vod = Vgs-Vt (Volts)
Inpu
t 1dB
com
p (d
Bm
)
Figure 12 Referred to input 1dB compression point plot using the
CMOS 14 Spice data
Input referred 3rd Order Intercept Point vs Vod
-5
0
5
10
15
20
25
30
35
40
0 1 2 3 4 5
Vod = Vgs-Vt (Volts)
Inpu
t 1dB
com
p (d
Bm
)
Figure 13 Referred to 3rd Order Intercept point (IIMP3) plot
using the CMOS 14 Spice data
Figure 14 shows the ADS simulation setup to al-low the 1dB
compression point to be simulated. The sub-circuit Diff_MOS_LNA is
shown in Figure 15. The resulting plots are shown in Figure 16
(harmonic spec-trum) and Figure 17 (gain compression plot).
Vout
Diff_MOS_LNAX1
SweepPlanPlan1
Reverse=noSweepPlan=UseSweepPlan=Start=-40.0 Stop=10 Step=0.5
Lin=
SWEEP PLAN
TermTerm2
Z=50 OhmNum=2
P_1TonePORT1
Freq=RFfreqP=dbmtow(Pin)Z=50 OhmNum=1
VARVAR1
Pin=-5RFfreq=2.5 GHz
EqnVar
XDBHB2
GC_MaxInputPower=100GC_OutputPowerTol=1e-3GC_InputPowerTol=1e-3GC_OutputFreq=2.5
GHzGC_InputFreq=2.5
GHzGC_OutputPort=2GC_InputPort=1GC_XdB=1Order[1]=5Freq[1]=RFfreq
GAIN COMPRESSIONHarmonicBalanceHB1
SweepPlan="Plan1"SweepVar="Pin"Order[1]=5Freq[1]=RFfreq
HARMONIC BALANCE
Figure 14 ADS simulation setup to measure the 1dB compression
point of the LNA. The sweep plan sets the input power sweep. The
harmonic balance allows the LNA harmonics to be plotted and the
gain compression block allows a pin vs pout plot to be
generated.
-
Sheet
11 of 14
vg
v2v1
PortP1Num=1
CC3C=0.4 pF
PortP2Num=2
Balun3PortCMP2
Balun3PortCMP1
VARVAR4
Lg=5.5Load=7.0Ls=0.5
EqnVar
INDQL4
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Lg nH
CC5C=10 pF
CC4C=0.4 pF
INDQL5
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Load nH
VARVAR3Ibias=22
EqnVar
RR2R=10k
vee
MOSFET_NMOSMOSFET4
Width=W umLength=L umModel=cmosn
vee
MOSFET_NMOSMOSFET6
Width=W umLength=L umModel=cmosn
INDQL6
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Ls nH
BSIM3_Modelcmosn
Xl=-1e-7Xw=0Em=4.1e7Kt2=0.022Kt1=-0.11Uc1=-5.6e-11
Ub1=-7.61e-18Ua1=4.31e-9At=3.3e4Ute=-1.5Pvag=0.1945781Pscbe2=5e-10Pscbe1=2.541131e10Pdiblcb=-0.5Pdiblc2=9.723614e-4Pdiblc1=2.091364e-3Pclm=0.7319137Drout=0.0428851Dsub=0.751089Etab=2.603903e-3Eta0=0.1178659
Cit=0Cdscd=0Cdscb=0Cdsc=2.4e-4Nfactor=1.2410485Voff=-0.0850186B1=5e-6B0=1.648829e-6Pags=0.0968Ags=0.1450882Wketa=-5.792854e-3Lketa=-0.0143698Keta=3.997018e-3A0=0.9059229Vsat=1.174604e5
Prwb=-0.0586598Prwg=0.0182608Prdsw=-33.9337286Rdsw=1.28604e3Delta=0.01Uc=1.831708e-11Ub=1.582544e-18Ua=1e-12Dvt2=-0.1427458Dvt1=0.9107896Dvt0=6.5803089Nlx=5.28517e-8W0=1e-5K3b=1.252205K3=68.279056
Pk2=9.631217e-3K2=-0.0316751K1=0.825917Pvth0=8.691731e-3Vth0=0.6701079U0=433.6065339Xj=1.5e-7Vbm=-3.0Nch=1.7e17Dwb=1.238214e-8Dwg=-7.483283e-9Xpart=0.5Cgbo=2e-9Cgdo=2.79e-10Cgso=2.79e-10
Pbswg=0.99Mjswg=0.1Cjswg=2.2346e-10Pbsw=0.99Pb=0.99Mjsw=0.1Cjsw=4.437149e-10Mj=0.7549569Cj=5.067009e-4Tox=1.01e-8Tnom=27Wwl=0Wwn=1Ww=0Wln=1
Wl=0Wint=2.277646e-7Lwl=0Lwn=1Lw=0Lln=1Ll=0Lint=1.097132e-7Js=0Rsh=2.8Capmod=2Mobmod=1Version=3.1Idsmod=8NMOS=yes
RR1R=10k
VARVAR1
W=330L=0.6
EqnVar
V_DCSRC1Vdc=2.5 V
I_ProbeID
INDQL1
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Lg nH
vee
MOSFET_NMOSMOSFET1
Width=W umLength=L umModel=cmosn
CC2C=10 pF
vee
MOSFET_NMOSMOSFET3
Width=W umLength=L umModel=cmosn
INDQL3
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Load nH
INDQL7
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Ls nH
I_DCSRC5Idc=Ibias mA
V_DCSRC4Vdc=-2.5 V
Figure 15 Addition of Baluns on the Differential amplifier to
allow gain compression simulation. Note the polarity of signals on
the output balun.
-
Sheet
12 of 14
Eqn Gain=dBm(HB1.HB.Vout[1])-HB1.HB.Pin
Eqn linear=Gain[0]+HB1.HB.Pin
1 2 3 4 5 6 7 8 90 10
-300
-250
-200
-150
-100
-50
0
-350
50
freq, GHz
dBm
(HB2
.HB
.Vou
t)
Output Spectrum at 1 dB Gain Compression Point
Input and Output Powers at 1 dB Compression Point
inpwr[1]-2.271
outpwr[1]5.070
1dB Compression Characteristic of MOS LNA
Figure 16 Harmonic spectrum of the MOS LNA with a prediction of
the 1dB compression point of +5.-7dBm (-4dBm input referred). The
gain compression calculation agrees with the simulation value to
within 1dB at 7.5dBm (Simula-tion value calculated at 6.5dBm).
Finally, to increase the gain margin of the LNA another C-S stage
could be added to the ’cascode’ output. This output stage is DC
coupled to the out-put of the first ‘cascode’ stage so that is
receives a correct bias to be in saturation. The increased gain
will greatly improve the noise figure of the receiver as the noise
figure of the second stage (most likely the mixer) will be reduced
by ~1/gain_LNA.
Eqn compression=m1-m2
m1indep(m1)=plot_vs(dBm(HB1.HB.Vout[1]), HB1.HB.Pin)=5.179
-2.000
m2Pin=linear=6.341
-2.000
m1indep(m1)=plot_vs(dBm(HB1.HB.Vout[1]), HB1.HB.Pin)=5.179
-2.000
m2Pin=linear=6.341
-2.000
-30 -20 -10 0-40 10
-30
-20
-10
0
10
-40
20
HB1.HB.Pin
dBm
(HB1
.HB.
Vout
[1]) m1
Pin
linea
r
m2
compression-1.162
Figure 17 Gain compression plot of the MOS LNA. The markers m1
and m2 are adjusted to give a compression of 1dB, giving an output
1dB compression point of +6.3dBm. We could combine the outputs of
the LNA by add-ing a current mirror to the cascode stages as shown
in Figure 18. Note care has to be taken as the addi-tional current
mirror will drop voltage and it may be necessary to raise the
supply rail slightly. Alter-natively, the cascaded LNA could feed a
second stage differential amplifier stage. This amplifier could
then be loaded with a current mirror to sum the outputs.
-
Sheet
13 of 14
vout
v2v1
vg
V_DCSRC1Vdc=2.5 V
INDQL8
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Load nH
INDQL3
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Load nH
vee
MOSFET_NMOSMOSFET4
Width=W umLength=L umModel=cmosnvee
MOSFET_NMOSMOSFET3
Width=W umLength=L umModel=cmosn
ACAC1
Step=Stop=3.0 GHzStart=2.0 GHz
AC
DCDC1
DCV_ACSRC6
Freq=freqVac=polar(1,0) V
vee
MOSFET_NMOSMOSFET8
Width=W umLength=L umModel=cmosn vee
MOSFET_NMOSMOSFET7
Width=W umLength=L umModel=cmosn
I_ProbeID
CC4C=0.4 pF
VARVAR4
Lg=5.5Load=7.0Ls=0.5
EqnVar
Balun3PortCMP1
INDQL4
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Lg nH
CC5C=10 pF
VARVAR3Ibias=22
EqnVar
RR2R=10k
vee
MOSFET_NMOSMOSFET6
Width=W umLength=L umModel=cmosn
INDQL6
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Ls nH
BSIM3_Modelcmosn
Xl=-1e-7Xw=0Em=4.1e7Kt2=0.022Kt1=-0.11Uc1=-5.6e-11
Ub1=-7.61e-18Ua1=4.31e-9At=3.3e4Ute=-1.5Pvag=0.1945781Pscbe2=5e-10Pscbe1=2.541131e10Pdiblcb=-0.5Pdiblc2=9.723614e-4Pdiblc1=2.091364e-3Pclm=0.7319137Drout=0.0428851Dsub=0.751089Etab=2.603903e-3Eta0=0.1178659
Cit=0Cdscd=0Cdscb=0Cdsc=2.4e-4Nfactor=1.2410485Voff=-0.0850186B1=5e-6B0=1.648829e-6Pags=0.0968Ags=0.1450882Wketa=-5.792854e-3Lketa=-0.0143698Keta=3.997018e-3A0=0.9059229Vsat=1.174604e5
Prwb=-0.0586598Prwg=0.0182608Prdsw=-33.9337286Rdsw=1.28604e3Delta=0.01Uc=1.831708e-11Ub=1.582544e-18Ua=1e-12Dvt2=-0.1427458Dvt1=0.9107896Dvt0=6.5803089Nlx=5.28517e-8W0=1e-5K3b=1.252205K3=68.279056
Pk2=9.631217e-3K2=-0.0316751K1=0.825917Pvth0=8.691731e-3Vth0=0.6701079U0=433.6065339Xj=1.5e-7Vbm=-3.0Nch=1.7e17Dwb=1.238214e-8Dwg=-7.483283e-9Xpart=0.5Cgbo=2e-9Cgdo=2.79e-10Cgso=2.79e-10
Pbswg=0.99Mjswg=0.1Cjswg=2.2346e-10Pbsw=0.99Pb=0.99Mjsw=0.1Cjsw=4.437149e-10Mj=0.7549569Cj=5.067009e-4Tox=1.01e-8Tnom=27Wwl=0Wwn=1Ww=0Wln=1
Wl=0Wint=2.277646e-7Lwl=0Lwn=1Lw=0Lln=1Ll=0Lint=1.097132e-7Js=0Rsh=2.8Capmod=2Mobmod=1Version=3.1Idsmod=8NMOS=yes
RR1R=10k
VARVAR1
W=330L=0.6
EqnVar
INDQL1
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Lg nH
vee
MOSFET_NMOSMOSFET1
Width=W umLength=L umModel=cmosn
CC2C=10 pF
INDQL7
Rdc=0.0 OhmMode=proportional to freqF=2400.0 MHzQ=6L=Ls nH
I_DCSRC5Idc=Ibias mA
V_DCSRC4Vdc=-2.5 V
Figure 18 Addition of a current mirror to the LNA to combine the
differential outputs to a single output. Note care has to be taken
as the additional current mirror will drop voltage and it may be
necessary to raise the supply rail. Alternatively the cascaded LNA
could feed a second stage differential amplifier (with current
mir-ror to sum the outputs) where the differential signal could be
combined.
-
Sheet
14 of 14
7 SUMMARY This tutorial gave the design equations to design a
dif-ferential LNA using shunt feedback realized with on-chip
inductors. A design example of a ‘bluetooth’ LNA was given, with
the associated step-by-step design proc-ess to meet a given
specification. ADS simulations have been given to predict the
various circuit parameters of gain, noise figure and power
consumption, all summa-rized in Table 3. Further discussions,
described how the power gain could be further increased by adding
another C-S stage to each ‘cascode’ stage output. This increased
the power gain to >20dB and would greatly improve the noise
figure of the receiver, as the noise figure contribution of the
following mixer stage would be reduced by a 1/gain_LNA. Parameter
Specifica-
tion Prediction Units
Frequency 2.45 to 2.85 2.45 to 2.85 GHz Noise Figure 20 27 dB
Power Gain >10-15 11.4* dB Power con-sumption
20dB with another C-S stage added. ** Including ‘tail’ current
mirror network not shown in the simulation schematics.
Table 3 Summary of simulated device per-formance.
Finally the definition of linearity was given, to-gether with
the associated equations for the calcula-tion of 1dB gain
compression point and 3rd Order Intercept point. A worked example
was given, together with ADS Simulations showing close agreement
with the hand calculations and the ADS simulations.
8 REFERENCES [1] T.H Lee, “The Design of CMOS Radio Fre-quency
Integrated Circuits”, Cambridge University Press, ISBN 0 521 63922
0, Chapter 2. [2] C.S Kim, M Park, C-H Kim, Y C Hyeon, H K Yu, K
Lee, K S Nam, “A fully integrated 1.9GHz
CMOS Low-noise amplifier” in IEE Microwave and guided wave
letters, Vol 8, No 8 August 1998. [3] T Soorapanth, T.H Lee, “RF
Linearity of Short-Channel MOSFETs”, IEEE Journal of Solid State
Circuits, vol. 32, no. 5, May 1997
/ColorImageDict > /JPEG2000ColorACSImageDict >
/JPEG2000ColorImageDict > /AntiAliasGrayImages false
/DownsampleGrayImages true /GrayImageDownsampleType /Bicubic
/GrayImageResolution 300 /GrayImageDepth -1
/GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true
/GrayImageFilter /DCTEncode /AutoFilterGrayImages true
/GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict >
/GrayImageDict > /JPEG2000GrayACSImageDict >
/JPEG2000GrayImageDict > /AntiAliasMonoImages false
/DownsampleMonoImages true /MonoImageDownsampleType /Bicubic
/MonoImageResolution 1200 /MonoImageDepth -1
/MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true
/MonoImageFilter /CCITTFaxEncode /MonoImageDict >
/AllowPSXObjects false /PDFX1aCheck false /PDFX3Check false
/PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true
/PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ]
/PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [
0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile ()
/PDFXOutputCondition () /PDFXRegistryName (http://www.color.org)
/PDFXTrapped /Unknown
/Description >>> setdistillerparams>
setpagedevice