MOS Capacitances

MOSFET CapacitancesMOSFET Capacitances97.477 Lecture97.477 Lecture

January 13, 2003January 13, 2003

Why this lecture is important.Why this lecture is important.

We will use MOSFETs to design our circuits.We will use MOSFETs to design our circuits.MOSFET capacitances tend to limit the MOSFET capacitances tend to limit the frequency response of circuits.frequency response of circuits.nn In order to predict the circuit frequency response, we In order to predict the circuit frequency response, we

need to estimate the circuit capacitance.need to estimate the circuit capacitance.

We may use the MOSFET capacitance to our We may use the MOSFET capacitance to our advantage, by intentionally implementing advantage, by intentionally implementing capacitors using MOSFETs.capacitors using MOSFETs.

EXAMPLE PROBLEM:EXAMPLE PROBLEM:Differential Pair 3dBDifferential Pair 3dB--Down FrequencyDown Frequency

Find the 3dBFind the 3dB--down down frequency (include the frequency (include the MOSFET capacitances).MOSFET capacitances).Ignore the sidewall Ignore the sidewall capacitances.capacitances.Assume the drain implant Assume the drain implant region length is 6region length is 6µµm and m and the width equals the the width equals the device width.device width.

In order to solve this problem, we must find the total In order to solve this problem, we must find the total capacitance present at the output of the amplifier.capacitance present at the output of the amplifier.The capacitance is a combination of the load capacitance and The capacitance is a combination of the load capacitance and the MOSFET capacitances.the MOSFET capacitances.

Extrinsic Versus IntrinsicExtrinsic Versus IntrinsicMOSFET parasitic capacitances are subdivided into two MOSFET parasitic capacitances are subdivided into two general categories: general categories: nn extrinsic capacitancesextrinsic capacitancesnn intrinsic capacitances.intrinsic capacitances.

Extrinsic capacitances are associated with regions of the Extrinsic capacitances are associated with regions of the transistor outside the dashed line.transistor outside the dashed line.Intrinsic capacitances are all those capacitances located Intrinsic capacitances are all those capacitances located within the boxed region.within the boxed region.

G DSB

n+p+ n+

p-sub

intrinsic region

EXTRINSIC CAPACITANCESEXTRINSIC CAPACITANCES

Extrinsic capacitances are Extrinsic capacitances are modeled by using lumped modeled by using lumped capacitances, each of which capacitances, each of which is associated with a region is associated with a region of the transistor’s geometry.of the transistor’s geometry.One capacitor is used One capacitor is used between each pair of between each pair of transistor terminals, plus an transistor terminals, plus an additional capacitor between additional capacitor between the well and the bulk if the the well and the bulk if the transistor is fabricated in a transistor is fabricated in a well.well.

G

D

S

B W

Intrinsic Model

CGD,e CSD,e

CDB,e

CGB,e

CBW,e

CGS,eCSB,e

Extrinsic Capacitance TypesExtrinsic Capacitance Types

Overlap capacitancesOverlap capacitances that are mostly that are mostly dependent on geometry.dependent on geometry.Junction capacitancesJunction capacitances that are that are dependent on geometry and on bias.dependent on geometry and on bias.

Gate Overlap CapacitancesGate Overlap CapacitancesThere is some overlap between the gate There is some overlap between the gate and the source and the gate and the drain. and the source and the gate and the drain. This overlap area gives rise to the gate This overlap area gives rise to the gate overlap capacitances.overlap capacitances.

GateGate--Source/Drain Overlap CapacitancesSource/Drain Overlap CapacitancesThe overlap between the gate The overlap between the gate and the source and the gate and the source and the gate and the drain gives rise to the and the drain gives rise to the gate overlap capacitances gate overlap capacitances denoted by denoted by CCGSOGSO and and CCGDOGDO for for the gatethe gate--toto--source overlap source overlap capacitance and the gatecapacitance and the gate--toto--drain overlap capacitance drain overlap capacitance respectively.respectively.

The overlap capacitances The overlap capacitances CCGSOGSO

and and CCGDOGDO are proportional to are proportional to the width, the width, WW, of the device and , of the device and the amount that the gate the amount that the gate overlaps the source and the overlaps the source and the drain, typically denoted as “LD” drain, typically denoted as “LD” in SPICE parameter files.in SPICE parameter files.

The overlap capacitances of the The overlap capacitances of the source and the drain are often source and the drain are often modeled as linear parallelmodeled as linear parallel--plate plate capacitors, since the high dopant capacitors, since the high dopant concentration in the source and concentration in the source and drain regions and the gate material drain regions and the gate material implies that the resulting implies that the resulting capacitance is largely bias capacitance is largely bias independent.independent.

GateGate--Source/Drain Overlap CapacitancesSource/Drain Overlap CapacitancesFor MOSFETs constructed with a lightlyFor MOSFETs constructed with a lightly--dopeddoped--drain drain (LDD(LDD--MOSFET), the overlap capacitances can be MOSFET), the overlap capacitances can be highly bias dependent and therefore nonhighly bias dependent and therefore non--linear. For linear. For a treatment of overlap capacitances in LDDa treatment of overlap capacitances in LDD--MOSFETs, refer to Klein, P., “A CompactMOSFETs, refer to Klein, P., “A Compact--Charge Charge LDDLDD--MOSFET Model”, MOSFET Model”, IEEE Transactions on IEEE Transactions on Electron DevicesElectron Devices, vol. 44, pp. 1483, vol. 44, pp. 1483--1490, Sep, 1490, Sep, 1997.1997.For nonFor non--LDD MOSFETs, the gateLDD MOSFETs, the gate--drain and gatedrain and gate--source overlap capacitances can be source overlap capacitances can be approximatedapproximatedby the expression by the expression CCGSOGSO = = CCGDOGDO = = W LD CW LD Coxox, where , where CCoxoxis the thinis the thin--oxide fieldoxide field--capacitance per unit area capacitance per unit area under the gate region.under the gate region.

GateGate--Source/Drain Overlap CapacitancesSource/Drain Overlap Capacitances

It turns out that fringing field lines add It turns out that fringing field lines add significantly to the total capacitance.significantly to the total capacitance.Estimates of the fringing field capacitances Estimates of the fringing field capacitances based on measurements are normally used.based on measurements are normally used.The gateThe gate--toto--drain overlap capacitances are drain overlap capacitances are generally given as measured parameters in the generally given as measured parameters in the MOSFET model files.MOSFET model files.There are values for NMOS MOSFETs and There are values for NMOS MOSFETs and PMOS MOSFETs.PMOS MOSFETs.The values are “perThe values are “per--width” values.width” values.

GateGate--Source/Drain Overlap Source/Drain Overlap Capacitances From Model FilesCapacitances From Model Files

.MODEL CMOSN NMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 + VTO=0.6684 DELTA=1.0700E+00 LD=4.2030E-08 KP=1.7748E-04 + UO=493.4 THETA=1.8120E-01 RSH=1.6680E+01 GAMMA=0.5382 + NSUB=1.1290E+17 NFS=7.1500E+11 VMAX=2.7900E+05 ETA=1.8690E-02 + KAPPA=1.6100E-01 CGDO=4.0920E-10 CGSO=4.0920E-10 + CGBO=3.7765E-10 CJ=5.9000E-04 MJ=0.76700 CJSW=2.0000E-11 + MJSW=0.71000 PB=0.9900000

.MODEL CMOSP PMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1 + VTO=-0.9352 DELTA=1.2380E-02 LD=5.2440E-08 KP=4.4927E-05 + UO=124.9 THETA=5.7490E-02 RSH=1.1660E+00 GAMMA=0.4551 + NSUB=8.0710E+16 NFS=5.9080E+11 VMAX=2.2960E+05 ETA=2.1930E-02 + KAPPA=9.3660E+00 CGDO=2.1260E-10 CGSO=2.1260E-10 + CGBO=3.6890E-10 CJ=9.3400E-04 MJ=0.48300 CJSW=2.5100E-10 + MJSW=0.21200 PB=0.930000

GateGate--toto--Bulk Overlap CapacitanceBulk Overlap Capacitance

There is a gateThere is a gate--toto--bulk overlap capacitance caused by bulk overlap capacitance caused by imperfect processing of the MOSFET.imperfect processing of the MOSFET.

The parasitic gateThe parasitic gate--bulk capacitance, bulk capacitance, CCjGB,ejGB,e , is located in , is located in the overlap region between the gate and the substrate the overlap region between the gate and the substrate (or well) material outside the channel region.(or well) material outside the channel region.The parasitic extrinsic gateThe parasitic extrinsic gate--bulk capacitance is bulk capacitance is extremely small in comparison to the other parasitic extremely small in comparison to the other parasitic capacitances. In particular, it is negligible in comparison capacitances. In particular, it is negligible in comparison to the intrinsic gateto the intrinsic gate--bulk capacitance. The parasitic bulk capacitance. The parasitic extrinsic gateextrinsic gate--bulk capacitance has little effect on the bulk capacitance has little effect on the gate input impedance and is therefore often ignored.gate input impedance and is therefore often ignored.

SourceSource--Drain CapacitanceDrain CapacitanceAccurate models of Accurate models of short channel devicesshort channel devices may may include the capacitance that exists between the include the capacitance that exists between the source and drain region of the MOSFET. The source and drain region of the MOSFET. The

sourcesource--drain capacitance is denoted as drain capacitance is denoted as CCSD,eSD,e..

SourceSource--Drain CapacitanceDrain Capacitance

Although the sourceAlthough the source--drain capacitance originates drain capacitance originates in the region normally associated with intrinsic in the region normally associated with intrinsic capacitance, it is still referred to as an extrinsic capacitance, it is still referred to as an extrinsic capacitance.capacitance.The value of this capacitance is difficult to The value of this capacitance is difficult to calculate because its value is highly dependent calculate because its value is highly dependent upon the source and drain geometries. For upon the source and drain geometries. For longer channel devices, longer channel devices, CCSD,eSD,e is very small in is very small in comparison to the other extrinsic capacitances, comparison to the other extrinsic capacitances, and is therefore normally ignored.and is therefore normally ignored.

Refresher: Diode CapacitanceRefresher: Diode CapacitanceWhen a reverse voltage is applied to a PN junction , the When a reverse voltage is applied to a PN junction , the holes in the pholes in the p--region are attracted to the anode terminal region are attracted to the anode terminal and electrons in the nand electrons in the n--region are attracted to the cathode region are attracted to the cathode terminal.terminal.The resulting region contains almost no carriers, and is The resulting region contains almost no carriers, and is called the depletion region.called the depletion region.The depletion region acts similarly to the dielectric of a The depletion region acts similarly to the dielectric of a capacitor.capacitor.The depletion region increases in width as the reverse The depletion region increases in width as the reverse voltage across it increases.voltage across it increases.If we imagine that the diode capacitance can be likened If we imagine that the diode capacitance can be likened to a parallel plate capacitor, then as the plate spacing to a parallel plate capacitor, then as the plate spacing (i.e. the depletion region width) increases, the (i.e. the depletion region width) increases, the capacitance should decrease.capacitance should decrease.Increasing the reverse bias voltage across the PN Increasing the reverse bias voltage across the PN junction therefore decreases the diode capacitance.junction therefore decreases the diode capacitance.

Source/DrainSource/Drain--Bulk Junction Bulk Junction CapacitancesCapacitances

At the source region there is a sourceAt the source region there is a source--toto--bulk junction capacitance, bulk junction capacitance, CCjBS,ejBS,e, and at , and at the drain region there is a drainthe drain region there is a drain--toto--bulk bulk junction capacitance, junction capacitance, CCjBD,ejBD,e..

Source/DrainSource/Drain--Bulk Junction Bulk Junction CapacitancesCapacitances

The junction capacitances can be calculated by The junction capacitances can be calculated by splitting the drain and source regions into a splitting the drain and source regions into a “side“side--wall” portion and a “bottomwall” portion and a “bottom--wall” portion.wall” portion.

nn The capacitance associated with the side wall The capacitance associated with the side wall portion is found by multiplying the length of portion is found by multiplying the length of the sidethe side--wall perimeter (excluding the side wall perimeter (excluding the side contacting the channel) by the effective sidecontacting the channel) by the effective side--wall capacitance per unit length.wall capacitance per unit length.

nn The capacitance for the bottomThe capacitance for the bottom--wall portion is wall portion is found by multiplying the area of the bottomfound by multiplying the area of the bottom--wall by the bottomwall by the bottom--wall capacitance per unit wall capacitance per unit area.area.

WellWell--Bulk Junction CapacitanceBulk Junction CapacitanceIf the MOSFET is in a well, a wellIf the MOSFET is in a well, a well--toto--bulk junction bulk junction capacitance, capacitance, CCjBW,ejBW,e, must be added. The well, must be added. The well--bulk junction bulk junction capacitance is calculated similarly to the source and drain capacitance is calculated similarly to the source and drain junction capacitances, by dividing the total welljunction capacitances, by dividing the total well--bulk junction bulk junction capacitance into sidecapacitance into side--wall and bottomwall and bottom--wall components. If wall components. If more than one transistor is placed in a well, the wellmore than one transistor is placed in a well, the well--bulk bulk junction capacitance should only be included once in the junction capacitance should only be included once in the total model.total model.

Junction Capacitance EquationsJunction Capacitance Equations

A Note on EstimationA Note on Estimation

If you are estimating a worst case delay, then If you are estimating a worst case delay, then you should generally use a worst case you should generally use a worst case capacitance.capacitance.Both the effective sideBoth the effective side--wall capacitance and the wall capacitance and the effective bottomeffective bottom--wall capacitance are bias wall capacitance are bias dependent.dependent.The zeroThe zero--bias sidebias side--wall capacitance and the per wall capacitance and the per unit area zerounit area zero--bias bottombias bottom--wall capacitance wall capacitance give the worst case (largest) capacitance.give the worst case (largest) capacitance.

Junction Capacitances From Model FilesJunction Capacitances From Model Files

The junction capacitances can be calculated The junction capacitances can be calculated from parameters given in the MOSFET model from parameters given in the MOSFET model files. There are values for NMOS MOSFETs files. There are values for NMOS MOSFETs and PMOS MOSFETs.and PMOS MOSFETs.

.MODEL CMOSN NMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 + VTO=0.6684 DELTA=1.0700E+00 LD=4.2030E-08 KP=1.7748E-04 + UO=493.4 THETA=1.8120E-01 RSH=1.6680E+01 GAMMA=0.5382 + NSUB=1.1290E+17 NFS=7.1500E+11 VMAX=2.7900E+05 ETA=1.8690E-02 + KAPPA=1.6100E-01 CGDO=4.0920E-10 CGSO=4.0920E-10 + CGBO=3.7765E-10 CJ=5.9000E-04 MJ=0.76700 CJSW=2.0000E-11 MJSW=0.71000 PB=0.9900000

.MODEL CMOSP PMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1 + VTO=-0.9352 DELTA=1.2380E-02 LD=5.2440E-08 KP=4.4927E-05 + UO=124.9 THETA=5.7490E-02 RSH=1.1660E+00 GAMMA=0.4551 + NSUB=8.0710E+16 NFS=5.9080E+11 VMAX=2.2960E+05 ETA=2.1930E-02 + KAPPA=9.3660E+00 CGDO=2.1260E-10 CGSO=2.1260E-10 + CGBO=3.6890E-10 CJ=9.3400E-04 MJ=0.48300 CJSW=2.5100E-10 MJSW=0.21200 PB=0.930000

MODEL EXAMPLEMODEL EXAMPLE.MODEL CMOSN NMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 + VTO=0.6684 DELTA=1.0700E+00 LD=4.2030E-08 KP=1.7748E-04 + UO=493.4 THETA=1.8120E-01 RSH=1.6680E+01 GAMMA=0.5382 + NSUB=1.1290E+17 NFS=7.1500E+11 VMAX=2.7900E+05 ETA=1.8690E-02 + KAPPA=1.6100E-01 CGDO=4.0920E-10 CGSO=4.0920E-10 + CGBO=3.7765E-10 CJ=5.9000E-04 MJ=0.76700 CJSW=2.0000E-11 MJSW=0.71000 PB=0.9900000

0 0

perimeter area

1 1j MJSW MJ

d d

CJSW CJC

v vφ φ

× ×= +

− −