Monolithic Silicon Waveguides in Standard Silicon

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MONOLITHIC SILICON WAVEGUIDESIN STANDARD SILICON

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A METHODOLOGY ALLOWS FABRICATION OF SILICON-PHOTONIC DEVICES IN STANDARD

SILICON WAFERS, ELIMINATING THE NEED FOR SILICON-ON-INSULATOR (SOI) WAFERS.

USING THIS TECHNOLOGY, THE AUTHORS DEMONSTRATE LOW-LOSS SILICON WAVE-

GUIDES (2.34 DB/CM), COMPARABLE TO CONVENTIONAL SOI CHANNEL WAVEGUIDES.

THE EASE AND FLEXIBILITY OF THIS FABRICATION METHOD SIMPLIFY INTEGRATION OF

ELECTRONICS AND PHOTONICS AND MAKE IT A POSSIBLE ALTERNATIVE TO SOI-BASED

TECHNOLOGY FOR IMPLEMENTATION OF SILICON-PHOTONIC DEVICES AND SYSTEMS.

......The demand for higher data ratesand increases in clock speed and wiring den-sity have made electrical interconnects thelimiting factor in system performance, andresearchers have proposed optical intercon-nects as a promising solution to the intercon-nect bottleneck.1 This technology offersseveral advantages, such as higher bandwidthand density and lower power consumption,significantly improving system performance.

Silicon photonics plays an essential role inoptical interconnects because of its compatibil-ity with electronics and its potential for impor-tant applications, such as data transport andsignal processing.2-4 A key building block insilicon photonics is the optical waveguide,which usually consists of a silicon (n ¼ 3.5)core and a silicon dioxide (n ¼ 1.5) clad-ding. This waveguide configuration offersseveral advantages. Owing to the largeindex contrast between the core and clad-ding layers, light can be strongly confinedinside the waveguides, resulting in compactwaveguide sizes and low bending losses.Manufacturers can fabricate these wave-guides by leveraging well-developed

CMOS and microelectromechanical systems(MEMS) technologies, which give siliconphotonics the potential to integrate electron-ics and photonics.

Two waveguide structures commonlyused in silicon photonics are channel wave-guides and ridge waveguides. These wave-guides are usually implemented using thesilicon-on-insulator (SOI) platform, becausethe buried oxide (BOX) layers of SOI waferscan provide field confinement to avoid leak-age from the silicon waveguides to the siliconsubstrates.5 However, SOI technology hasseveral limitations. Monolithic integrationof electronics and photonics is challengingdue to BOX layer mismatch, becauseSOI electronics requires a thin BOX layer(< 100 nm) for thermal conduction,6,7 andSOI photonics usually consists of a thickBOX layer (> 1 mm) for field confinement.5

Another limitation is that SOI is not stan-dard CMOS technology, resulting in higherprocess cost. Furthermore, owing to theSOI wafer manufacturing, the device siliconlayer might not be uniform across eachwafer and could have residual stress,

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Chia-Ming Chang

Olav Solgaard

Stanford University

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32 Published by the IEEE Computer Society 0272-1732/13/$31.00 �c 2013 IEEE

potentially generating yield issues. Therefore,it is desired to use low-cost standard silicontechnology.

Eliminating SOI and its associated prob-lems requires finding another way to estab-lish field confinement and solve theproblem of coupling between the siliconwaveguides and the substrate. One approachis to create an air-cladding layer by undercut-ting the region between the waveguides andthe substrates.8-10 Researchers have used pol-ysilicon waveguides with a localized substrateremoval technique to fabricate photonic de-vices from standard silicon wafers.8 How-ever, the polysilicon’s grain boundariestypically increase the scattering loss of thewaveguides. Another approach is to locallyoxidize the region between the waveguidesand the substrates.11,12 Researchers have pro-posed using oxidized SOI from bulk siliconto tackle the field confinement issue.11 How-ever, the oxidation time is long (> 9 hours),and the resultant oxide layer is thick (> 3 mm),making it difficult to fabricate photonic de-vices close to one another.

We’ve demonstrated single crystallineridge waveguides and waveguide Braggreflectors by creating air cladding in standardsilicon wafers. Our ridge waveguides andBragg reflectors are well-suited for opticalmodulators and optical sensors.9,10 In thisarticle, we present a method for fabricationof low-loss optical waveguides in standardsilicon wafers.12 The basic idea is to firstuse an isotropic silicon etch to thin the re-gion between the waveguides and the sub-strates, and then use thermal oxidation tolocally oxidize the thinned region. Thismethodology substantially reduces the oxi-dation time (< 1 hr), resulting in a reason-able oxide thickness for photonicapplications. In addition to traditionalCMOS-compatible processes such as lithog-raphy, oxidation, and etching, the fabrica-tion of low-loss guides requires a hydrogenannealing step that significantly reducesscattering loss.

Device fabricationWe divide the fabrication of our devices

into two parts: fabrication of waveguidesand air-claddings, followed by sidewallsmoothing using hydrogen annealing.

Waveguide fabrication: The Gopher processWe fabricated silicon waveguides using

the Generation of Photonic Elements by Re-active Ion Etching (Gopher) process.9,10,12-14

Figure 1 shows the schematics of the processflow for our silicon waveguides. Startingwith a bare silicon wafer, a 300-nm thick ther-mal oxide was grown at 1,050�C to serve asthe hard mask for the waveguide structures,followed by coating a SPR955 0.7-mm pho-toresist. We patterned the wafer using a 5�reduction ASM-L i-line stepper, and the wave-guide structures were transferred to the oxidehard mask via anisotropic oxide etching.With the oxide hard mask, we created thewaveguide structures by etching directionallyinto silicon, as Figure 1a shows. Next, to pro-tect the sidewalls, we grew another thin oxidelayer (50 nm) thermally, and applied a direc-tional oxide etch until the bottom oxide wasremoved (Figure 1b). We conducted a secondanisotropic silicon etch, shown in Figure 1c,to etch further into the substrate in order toprovide spacing between the silicon wave-guides and the substrate. We then thinnedthe spacer via an isotropic silicon plasmaetch using SF6 (sulfur hexafluoride; seeFigure 1d).

Figure 2a shows a scanning electron mi-croscope (SEM) image of the resulting struc-ture after the isotropic silicon etch; thesidewalls are rough, owing to the isotropicdry etch. This sidewall roughness increasesscattering loss, thus resulting in higher prop-agation loss of the waveguides.

Sidewall smoothing: Hydrogen annealingTo smooth the sidewalls and reduce prop-

agation loss, we first removed the oxide capin 6:1 buffered oxide etch (Figure 1e), andthen hydrogen annealed the waveguides ata high temperature (Figure 1f). To investi-gate the effects of hydrogen annealing onsidewall smoothing, we adjusted three im-portant parameters: pressure, temperature,and time. We fixed the pressure to 10 torrin our experiment so that the annealingtime could be shorter than 10 minutes.15,16

We then annealed the test wafers in temper-atures varying from 930�C to 1,100�C forseveral minutes. Figures 2b, 2c, and 2dshow SEM images of waveguides at 930�Cfor 5 minutes, 1,000�C for 3 minutes, and

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1,100�C for 5 minutes, respectively. At930�C, the effects of hydrogen annealingwere weak, so sidewalls were still roughafter annealing for 5 minutes. On the otherhand, after annealing at 1,100�C for5 minutes, the hydrogen annealing had pro-ceeded too far, so the waveguide structureslost the spacer because of silicon reflow.Annealing at 1,000�C for 3 minutes resultedin smooth sidewalls and rounded corners,while maintaining a well-defined spacer. Fi-nally, the waveguide structures were com-pleted by thermal oxidation at 1,050�C for45 minutes (Figure 1g). Figure 3 shows anSEM image of the fabricated waveguide.

Fabricated waveguidesBecause of the shape transformation

in hydrogen annealing and the final

thermal-oxidation step, our silicon wave-guides fabricated by the Gopher process pos-sess an oval cross section, which is differentfrom the traditional channel waveguide.The longest waveguide width and heightmeasure at 360 nm and 630 nm, respec-tively, and the oxide cladding thickness isabout 500 nm. Light confinement at the bot-tom of the waveguide is provided by oxida-tion of the spacer (about 1 mm) betweenthe silicon waveguides and the substrate.We can create waveguides of different sizesand cross-sectional shapes by changing themask layout and silicon etching recipe (forexample, time). By using wider mask layoutand a different etching recipe, for example,we can fabricate waveguides with appropriateaspect ratios (width to height) for variousphotonic applications.

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silicon

(g)

(a) (c)(b)

(d) (f)(e)

oxide

Figure 1. Schematics of the Generation of Photonic Elements by Reactive Ion Etching (Gopher) process for low-loss silicon

waveguides: anisotropic silicon etching to define the waveguide (a); thermal oxidation to protect the waveguide’s sidewalls,

followed by directional oxide removal (b); anisotropic silicon etching to open the region for isotropic silicon etching (c);

isotropic silicon etching to thin the spacer (d); oxide cap removal for hydrogen annealing (e); hydrogen annealing to

smoothen the sidewalls (f); and final oxidation for field confinement (g).

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(a)

(c)

(b)

(d)

Figure 2. Scanning electron microscope (SEM) images of silicon waveguides smoothed

using different hydrogen annealing recipes: as fabricated (before hydrogen annealing) (a);

annealed at 930�C for 5 minutes (b); annealed at 1,000�C for 3 minutes (c); and annealed at

1,100�C for 5 minutes (d).

(a)

HV3.00 kV

spot3.0

HFW4.23 µm

WD5.0 µm Stanford Nova NanoSEM 450

1 µmmag30 000 ×

(b)

Figure 3. SEM images of fabricated monolithic silicon waveguides. Our silicon waveguide has an oval shape with the

waveguide width and height of 360 nm and 630 nm, respectively.

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Device characterizationBecause our silicon waveguide has an oval

cross section that differs from the traditionalwaveguides, we characterize our waveguidesby first analyzing the single mode conditionsand mode profiles numerically. We then testour waveguides and determine two impor-tant figures of merit: propagation loss andbending loss.

Single-mode simulationsWe simulated mode profiles of the trans-

verse electric (TE) and transverse magnetic(TM) polarizations using the alternating-direction implicit (ADI) beam propagationmethod (BPM) in OptiFDTD, a commer-cial mode solver (www.optiwave.com).According to the numerical simulation, our360 nm � 630 nm oval waveguide supportssingle-mode propagation for both the TEand TM polarizations. We then analyzedsingle-mode conditions by varying the wave-guide width (W) and fixing the waveguideheight (H) at 630 nm. Figure 4 plots the cal-culated effective indices as a function ofwaveguide width for both the TE and TMpolarizations. For the TE polarization, thewaveguide shows single-mode operationwhen the waveguide width is less than520 nm, whereas for the TM polarization,the waveguide is still in single mode whenthe waveguide width is increased to 600 nm.

Figure 5 shows the mode profiles of the360 nm � 630 nm waveguide at 1,559 nm.Compared to conventional SOI channelwaveguides with a rectangular cross section,our waveguides possess different mode pro-files, owing to the oval cross section. Thebottom two interfaces of the waveguides,which are created by isotropic etching, arenot orthogonal to either the horizontal elec-tric fields or the perpendicular electric fields.The interactions of both polarizations withthe interfaces create additional field disconti-nuities at the interfaces. These interactionscould increase the scattering loss of the wave-guides if the bottom two surfaces are rough.As a result, hydrogen annealing for sidewallsmoothness is a key step to achieving low-loss waveguides.

The electric-field distributions along thedashed lines in Figures 5a and 5c are plottedin Figures 5b and 5c for the TE and TMpolarizations, respectively. The field discon-tinuities at the interface of the core and clad-ding show, as expected, that the normalcomponent of the electric field is not contin-uous at the dielectric boundary, with higherfield amplitude in the low index side (clad-ding). Furthermore, Figure 5 shows thatthe TM mode is strongly confined with aneffective index of 2.79, whereas the TEmode is somewhat more loosely confined

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3.0

Effective ind

ex

1.8

2.0

2.2

2.4

2.6

2.8

300 350 400 450 500 550

Waveguide width (µm)

Single mode

Fundamental mode

Higher-order mode

600

(b)

(a)

2.90

Effective ind

ex

2.70300 350 400 450 500 550

Waveguide width (µm)

Single mode

600

2.72

2.74

2.76

2.78

2.80

2.82

2.84

2.86

2.88Fundamental mode

Figure 4. Calculated effective index as a function of waveguide width for

single-mode analysis. Transverse electric (TE) polarization (a) and transverse

magnetic (TM) polarization (b). The waveguide height is fixed at 630 nm.

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with an effective index of 2.63. The differen-ces in mode confinement and effective indexresult from our waveguide geometry and as-pect ratio, which can be controlled by thewaveguide design and fabrication.

Measurements of propagation and bending lossWe conducted propagation-loss measure-

ments of the silicon waveguides using thecutback method. Light from a laser source(1,559 nm) is coupled through a polarizationcontroller into a lensed fiber (www.ozoptics.com) that is edge coupled to the waveguides

under test. The transmitted power is col-lected by another lensed fiber at the wave-guide’s output facet. Figure 6 shows therelationship between the power transmis-sion and the waveguide lengths for TEand TM polarizations. The propagationlosses extracted from the figure are5.52 dB/cm and 2.34 dB/cm for the TEand TM polarization, respectively. Thiswaveguide loss is comparable to the existinglow-loss SOI channel waveguides that usu-ally have losses of 2 to 3 dB/cm,5 indicatingthat our waveguides fabricated in standard

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1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

TE

y

x

0.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Fie

ld a

mp

litud

e

0–800 –600

TE

–200–400

X (nm)

Y cut

8000 200 400 600

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Fie

ld a

mp

litud

e

0–800 –600

TM

–200–400

Y (nm)

X cut

8000 200 400 600

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1TM

y

x

(a) (b)

(c) (d)

Figure 5. Mode profiles calculated using OptiFDTD, a commercial mode solver. Ex (x, y) of the TE polarization (a),

electric-field distribution along the line shown in Figure 5a (b), Ey (x, y) of the TM polarization (c), and electric-field

distribution along the line shown in Figure 5c (d).

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wafers are well-suited for silicon photonicapplications.

As Figure 6 shows, the TE polarizationshows higher propagation loss than the TMpolarization. The difference in propagation

loss is likely due to the difference in modeconfinement and scattering loss of two polar-izations. As Figure 5 shows, the TE polariza-tion reveals a much higher electric field atthe interfaces. Thus, owing to mode confine-ment and field distribution, the interactionof the field and the waveguide sidewall isstronger for the TE polarization, leading toa larger propagation loss.

To characterize the waveguide bends, wemeasured waveguide bending losses withradii of R ¼ 5 mm and 1 mm for three setsof 90� waveguide bends: eight bends, 16bends, and 24 bends. Figure 7 shows thepower transmission as a function of thenumbers of 90� waveguide bends for TEand TM polarizations. The bending lossesfor the TE polarizations extracted from thefigure are 0.26 dB/90� and 0.074 dB/90�

for the 1 mm and 5 mm bends, respectively.For the TM polarization, the bending lossesare 0.23 dB/90� and 0.064 dB/90� for the1 mm and 5 mm bends, respectively. Thiswaveguide bending loss is comparable tothe existing SOI channel waveguides,which have a loss of about 0.1 dB/90� fora 1-mm bend.5

I n addition to straight waveguides andwaveguide bends, other passive devices

such as Y-splitters and ring resonators canbe fabricated using our processes. Becausethe Y-splitter is composed of straightwaveguides, a Y-junction, and waveguidebends, it can be implemented via thecombination of anisotropic etching, isotro-pic etching, annealing, and oxidation. Forthe ring resonators with narrow couplinggap between the waveguide and the ring,the fabrication of the devices could requiretwo lithography steps, because the gap’setching condition could be different fromthat of the straight waveguides.

Due to the waveguide geometry and lackof areas for electrical contact, it is challengingto fabricate active devices such as modulatorsusing this process. However, active devicescan be fabricated using our air-claddingprocess,9,10 which is well-suited for creatingridge waveguides. Combining these two pro-cesses, which both use the same sequence ofanisotropic etching, isotropic etching, andoxidation, makes it possible to construct

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–31

Tra

nsm

issio

n (

dB

)

–36

–35

–34

–33

–32

0.6 0.7 0.8 0.9 1.0 1.1 1.2

Waveguide length (cm)

Propagation loss = 2.34 dB/cm

1.3

(b)

–31

Tra

nsm

issio

n (

dB

)

–36

–35

–34

–33

–32

0.6 0.7 0.8 0.9 1.0 1.1 1.2

Waveguide length (cm)

Propagation loss = 5.52 dB/cm

1.3

(a)

Figure 6. Waveguide propagation loss measurement at 1,559 nm for TE

polarization (a) and TM polarization (b). The TM polarization shows lower

propagation than the TE polarization because of less scattering loss at

the interfaces. Propagation loss was 5.52 dB/cm for TE polarization and

2.34 dB/cm for TM polarization.

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low-loss silicon waveguides for propagation,and active devices for modulation andphoto detection in standard silicon. M I C RO

....................................................................References

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Optics (CLEO), IEEE, 2012, no. JW4A.76.

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Tra

nsm

issio

n (

dB

)

–24

–22

0 8 16 24

Number of 90-degree bend(b)

–20

Tra

nsm

issio

n (

dB

)

–28

–26

–24

–22

0

Number of 90 degree bend

1-µm bending lossTE: 0.26 dB/90°TM: 0.23 dB/90°

5-µm bending loss

TE: 0.074 dB/90°

TM: 0.064 dB/90°

24168

(a)

TE

TM

TE

TM

Figure 7. Waveguide bending-loss measurement for 1-mm bends (a) and

5-mm bends (b). The bending loss of our silicon waveguides is comparable

to the existing SOI channel waveguides.

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JANUARY/FEBRUARY 2013 39

14. S. Hadzialic et al., ‘‘Two-Dimensional Photonic

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Chia-Ming Chang is a PhD candidate in theDepartment of Electrical Engineering atStanford University. His research interestsinclude silicon photonics, optical intercon-nects, and optical sensing applications, andthe design and construction of waveguidedevices, gratings, and photonic crystals.Chang has an MS in electronics engineeringfrom National Tsing Hua University, Tai-wan. He is an Intel PhD Fellow.

Olav Solgaard is a professor in the Depart-ment of Electrical Engineering and thedirector of the Edward L. Ginzton Labora-tory at Stanford University. He is thecofounder of Silicon Light Machines. Hisresearch interests include optical MEMS,photonic crystals, atomic force microscopy,and solar-energy conversion. Solgaard has aPhD in electrical engineering from StanfordUniversity. He is a fellow of the OpticalSociety of America, the Royal NorwegianSociety of Sciences and Letters, and theNorwegian Academy of TechnologicalSciences.

Direct questions and comments aboutthis article to Chia-Ming Chang, 348 ViaPueblo Mall, Room 033, Stanford, CA94305; [email protected].

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