STD6, Carmel, CA, Sept. 11-15, 2006 Monolithic Integration of Detectors and Transistors on High-Resistivity Silicon G.-F. Dalla Betta 1 , G. Batignani 2 , L. Bosisio 3 , M. Boscardin 4 , P. Gregori 4 , C. Piemonte 4 , L. Ratti 5 , G. Verzellesi 6 , N. Zorzi 4 1 INFN Trento and University of Trento,Italy 2 INFN Pisa and University of Pisa, Italy 3 INFN Trieste and University of Trieste, Italy 4 ITC-irst,Trento, Italy 5 INFN Pavia and University of Pavia, Italy 6 INFN Trento and University of Modena/Reggio Emilia, Italy
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Monolithic Integration of Detectors and Transistors on High-Resistivity Silicon
Monolithic Integration of Detectors and Transistors on High-Resistivity Silicon. G.-F. Dalla Betta 1 , G. Batignani 2 , L. Bosisio 3 , M. Boscardin 4 , P. Gregori 4 , C. Piemonte 4 , L. Ratti 5 , G. Verzellesi 6 , N. Zorzi 4. 1 INFN Trento and University of Trento,Italy - PowerPoint PPT Presentation
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STD6, Carmel, CA, Sept. 11-15, 2006
Monolithic Integration of Detectors and Transistors on High-Resistivity Silicon
G.-F. Dalla Betta1, G. Batignani2, L. Bosisio3, M. Boscardin4, P. Gregori4, C. Piemonte4,
L. Ratti5, G. Verzellesi6, N. Zorzi4
1 INFN Trento and University of Trento,Italy2 INFN Pisa and University of Pisa, Italy3 INFN Trieste and University of Trieste, Italy4 ITC-irst,Trento, Italy5 INFN Pavia and University of Pavia, Italy6 INFN Trento and University of Modena/Reggio Emilia, Italy
STD6, Carmel, CA, Sept. 11-15, 2006
Outline
• Introduction
• Process development at ITC-irst
• Transistor description:
• Experimental results
• Conclusions
n-JFET (tetrode, triode)
n-MOSFET
npn BJT
STD6, Carmel, CA, Sept. 11-15, 2006
Introduction
• Front-end electronics embedded on the detector substrate
can provide better noise performance and easier assembly,
at the expense of process complexity and cost
• Normally worth for low capacitance detectors only
• Pioneering work in this field dates back to late 80’s:
MPI Munich & BNL (for drift detectors),
LBNL (detector compatible CMOS process for pixels)
• Most successful developments: fully depleted CCDs and
DEPFET DEPFET talk by J.Velthiustalk by J.Velthius
STD6, Carmel, CA, Sept. 11-15, 2006
Process development at ITC-irst
• It all started as a major technological challenge: first step
toward becoming a primary technological partner for INFN
• The process development went on in the framework of few
national projects (INFN and MIUR), mainly device oriented
• When device performance improved, we could start to
detection with a simple setup (load resistor only) …
Current gain ()
… but it needs bias to obtain a time constant of ~ 10s of s.
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0E+00 1E-04 2E-04 3E-04Time (s)
Em
itter
vol
tage
(V
)
Iem=150nA
Iem=3uA
Iem=7uA
Iem=18uA
Lbcbebcbe
E
RCrCC
tQI
exp0
Transient response
Without bias
STD6, Carmel, CA, Sept. 11-15, 2006
particle counter
Rpoly~100M(must be rbe
0
20
40
60
80
100
120
0 100 200 300
time [us]
Sig
na
l [m
V]
80V from top 9V from top 80V from bottom
particles from 239Pu source (with 150 k Rload)
Interesting for Radon monitoring with anextremely simple setup
E
C
P
B
RpolyNPN
scope
RL
Vbias
STD6, Carmel, CA, Sept. 11-15, 2006
Conclusions• We have reported on recent results from the development of detector-compatible transistors at ITC-irst• Devices feature good characteristics that are promising in view of full detector system implementations• With last batch, we have started to focus on some applications• The prototype functional tests are under way• The technology is available to interested application-oriented partners
STD6, Carmel, CA, Sept. 11-15, 2006
Additional slides
STD6, Carmel, CA, Sept. 11-15, 2006
Radiation damage effects
Gate current (Vgs=0, Vds=3V)
Noise spectrum(Id=250A, Vds=3V)
10-11
10-10
10-9
10-8
10-7
0 20 40 60 80 100
Substrate voltage, Vsub (V)
Gat
e cu
rre
nt, I
g(A
)
Before irradiation
After 1×1012 n/cm2
After 9×1012 n/cm2
10-11
10-10
10-9
10-8
10-7
0 20 40 60 80 100
Substrate voltage, Vsub (V)
Gat
e cu
rre
nt, I
g(A
)
Before irradiation
After 1×1012 n/cm2
After 9×1012 n/cm2
Before irradiation
After 1×1012 n/cm2
After 9×1012 n/cm2
Single JFETs (1000/4) irradiated with neutrons
102 103 104 105 106
frequency (Hz)
Noi
se v
olta
ge
spec
trum
(n
V/H
z0.5
)
1
10
100
After 1×1012 n/cm2
After 9×1012 n/cm2
Before irradiation
Increase of gate current (proportional to fluence)Lorentzian noise contributions appear
STD6, Carmel, CA, Sept. 11-15, 2006
Irradiated CSA: ENC prediction
400
600
800
1000
1200
1400
0 4 8 12 16 20 24
Peaking time (s)
Equ
ival
ent N
oise
Cha
rge
(e-rm
s)
Before irradiation, sim.Before irradiation, exp.
After 1×1012 n/cm2, sim.
After 9×1012 n/cm2, sim.
400
600
800
1000
1200
1400
0 4 8 12 16 20 24
Peaking time (s)
Equ
ival
ent N
oise
Cha
rge
(e-rm
s)
Before irradiation, sim.Before irradiation, exp.
After 1×1012 n/cm2, sim.
After 9×1012 n/cm2, sim.
RF=10M
400
500
600
700
800
900
1000
1 10
Eq
uiv
ale
nt
no
ise
char
ge
[e- r
ms]
Peaking time [s]
High fluence
Low fluence
w Lorentzian contribution
w/o Lorentzian contribution
Based on input JFET characteristics (1000/4)
Minor effect of Lorentzian noiseLarge effect of gate current increase and related need of lower RF value
Should be better with tetrode JFET (lower current from top-gate alone)