MonolithIC 3D ICs

MonolithIC 3D Inc. , Patents Pending

MonolithIC 3D ICs

October 2012

1MonolithIC 3D Inc. , Patents Pending

The Monolithic 3D Innovation

Utilize Ion-Cut (‘Smart-Cut’) to transfer a thin (<100nm) single crystal layer on top of the bottom (base) wafer Form the cut at less than 400ºC *

Use co-implant Use mechanically assisted cleaving

Form the bonding at less than 400ºC ** See details at: Low Temperature Cleaving, Low Temperature Wafer

Direct Bonding

Split the transistor processing to two portions High temperature process portion (ion implant and activation) to be

done before the Ion-Cut Low temperature (<400°C) process portion (etch and deposition) to be

done after layer transferSee details in the following slides:

Monolithic 3D ICs

Using SmartCut technology - the ion cutting process that Soitec uses to make SOI wafers for AMD and IBM (millions of wafers had utilized the process over the last 20 years) - to stack up consecutive layers of active silicon (bond first and then cut). Soitec’s Smart Cut Patented* Flow:

MonolithIC 3D Inc. , Patents Pending 3

*Soitec’s fundamental patent US 5,374,564 expired Sep. 15, 2012

Monolithic 3D ICs

Ion cutting: the key idea is that if you implant a thin layer of H+ ions into a single crystal of silicon, the ions will weaken the bonds between the neighboring silicon atoms, creating a fracture plane (Figure 3). Judicious force will then precisely break the wafer at the plane of the H+ implant, allowing you to in-effect peel off very thin layer. This technique is currently being used to produce the most advanced transistors (Fully Depleted SOI, UTBB transistors – Ultra Thin Body and BOX), forming monocrystalline silicon layers that are less than 10nm thick.


Figure 3Using ion-cutting to place a thin layer of monocrystalline silicon

above a processed (transistors and metallization) base wafer


p- Si

Oxide

p- Si

OxideH

Top layer

Bottom layer

Oxide

Hydrogen implant

of top layerFlip top layer and

bond to bottom layer

Oxide

p- Si

Oxide

H

Cleave using <400oC

anneal or sideways

mechanical force.

CMP.

OxideOxide

Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today

p- Si

MonolithIC 3D Inc. Patents Pending 6

Chapter 3Monolithic 3D HKMG


The monolithic 3D IC technology is applied to produce monolithically stacked high performance High-k Metal Gate (HKMG) devices, the world’s most advanced production transistors.

3D Monolithic State-of-the-Art transistors are formed with ion-cut applied to a gate-last process, combined with a low temperature face-up layer transfer, repeating layouts, and an innovative inter-layer via (ILV) alignment scheme.

Monolithic 3D IC provides a path to reduce logic, SOC, and memory costs without investing in expensive scaling down.

Technology


~700µm Donor Wafer

On the donor wafer, fabricate standard dummy gates with oxide and poly-Si; >900ºC OK

PMOSNMOS

Silicon

PolyOxide


~700µm Donor Wafer

Form transistor source/drain

PMOSNMOS

Silicon

PolyOxide


~700µm Donor Wafer

PMOSNMOS

Silicon

Form inter layer dielectric (ILD), S/D implants and high temp anneals, CMP to transistor tops

CMP to top of dummy gatesILDS/D Implant


~700µm Donor Wafer

PMOSNMOS

Silicon

Implant hydrogen to generate cleave plane


~700µm Donor Wafer

PMOSNMOS

Silicon



~700µm Donor Wafer

PMOSNMOS

Silicon


H+


~700µm Donor Wafer

Silicon

Bond donor wafer to carrier wafer

H+

~700µm Carrier Wafer


~700µm Donor Wafer

Cleave to remove bulk of donor wafer

H+


Transferred Donor Layer

Silicon

Silicon


CMP to STI


STITransferred

Donor Layer


Deposit oxide, ox-ox bond carrier structure to base wafer that has transistors & circuits


STI

Oxide-oxide bond

PMOSNMOS


Base Wafer

18

Remove carrier wafer

Oxide-oxide bond



MonolithIC 3D Inc. Patents Pending

PMOSNMOSBase Wafer

19

Carrier wafer had been removed

Oxide-oxide bond



PMOSNMOSBase Wafer

20

Replace dummy gate stacks with Hafnium Oxide & metal at low temp

Oxide-oxide bond



PMOSNMOSBase Wafer

Note: Replacing oxide and gate result in oxide and gate that were not damaged by the H+ implant

21

Form inter layer via through oxide only (similar to standard via)

Oxide-oxide bond



PMOSNMOSBase Wafer

Note: The second mono-crystal layer is very thin (<100nm) and via through it, is similar to other vias in the metal stack


Form top layer interconnect and connect layers with inter layer via

Oxide-oxide bond



PMOSNMOSBase Wafer

ILV


Novel Alignment Scheme using Repeating Layouts

Even if misalignment occurs during bonding repeating layouts allow correct connections.

Above representation simplistic (high area penalty).

Bottom layerlayout

Top layerlayout

Landing pad

Through-layer connection

Oxide


Smart Alignment Scheme

Bottom layerlayout

Top layerlayout

Landing pad

Through-layer connection

Oxide

MonolithIC 3D ICs

Documents

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d hkmgmonolithic

d icsion

d icsoctober

patents pendingthe monolithic

patents pendingfigure

d innovationutilize

d ic technology