Monitoring Programmable Logic Controllers - ULisboa · PLC programmers develop programs using Ladder Logic, that makes a situation with a very large number of logical inputs and logical

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Monitoring Programmable Logic ControllersHenrique Goncalves, Jose Gaspar

Instituto Superior Tecnico / Universidade de Lisboa, [email protected], [email protected]

Abstract—Discrete Event Systems (DES) are ubiquitous inindustrial applications. Programmable Logic Controllers (PLC)are commonly used to implement DES. Designing a DES andimplementing in a PLC is a lengthy process typically requiringmultiple verifications and an end process validation.

Our approach to design a DES involves using Petri Nets (PN).Then we propose an automatic conversion of the PN to StructuredText (ST) code, a standard PLC programming language. Withthe objective of verifying that the PLC program fulfills designspecifications we develop a PLC monitoring system.

Construction of a hardware PLC Signal Acquirer, able tomonitor PLC inputs and outputs, is detailed in this work. Cost iskept low by using the affordable microcontroller board ArduinoMega. Development of additional hardware is also detailed,having the purpose of interconnecting the monitor with the PLCand the controlled plant.

With our hardware developed and DES implemented we showcharacteristics of the PLC behavior, as the variability of the scancycle time, and validate the DES implementation of a keyboardreading case study.

Keywords: Signal Acquirer, Discrete Event Systems, Pro-grammable Logic Controllers, Arduino, Petri Net, StructuredText.

I. I NTRODUCTION

In industrial applications Discrete Event Systems (DES)are ubiquitous, from telecommunications to flexible manu-facturing. Programmable Logic Controllers (PLC) are usedto implement DES. With the objective of verifying that aPLC program fulfills design specifications we develop a PLCmonitoring system. To achieve our objective we detail the useof Petri Nets (PN) to create a DES, and develop a programthat from PN characteristics is able to create Structured Text(ST) code, a PLC programming language, to be implementedin a PLC. Construction of an hardware PLC Signal Acquirer,able to monitor PLC programs, will be detailed using theaffordable microcontroller board Arduino Mega. Developmentof additional hardware will be explained, in order to make con-nections possible between the Arduino a PLC and a controlledplant. With our hardware developed and DES implemented wethen are able to observe the PLC behavior, and try to validatethe DES implementation.

A. Related Work

Petri net theory was continually developed since its be-ginnings with Dr. Petri’s 1962 Ph.D. Dissertation[13]. Butit was not until 1981, that Peterson [12] wrote the bookthat presented all the development work scattered amongmany sources in a coherent and consistent manner. In 1967Naylor and Finger [10], proposed a multistage process of

validation. This validation method consists of (1) developingthe model on theory, observations, and general knowledge;(2) validating the model’s assumptions where possible byempirically testing them; and (3) comparing (testing) theinput-output relationships of the model to the real system.In 1979 Schlesinger [14], defined Model validation to mean”substantiation that a computerized model within its domainof applicability possesses a satisfactory range of accuracyconsistent with the intended application of the model”. In1992 [2], Cutts and Rattigan addressed the fact that mostPLC programmers develop programs using Ladder Logic,that makes a situation with a very large number of logicalinputs and logical combinations, very hard to control.As asolution to this problem, Cutts and Rattigan [2], proposed touse software based on Petri nets. In 2004 conformance test,testing a PLC system seen as a black-box (its internal structureis unknown) with observable inputs/outputs, is advocated bycertification bodies and standards [7]. In 2011 Sargent [8],made a study of the several validation techniques and testscommonly used in model validation, and purposed a model forseveral steps for validation of simulation models, in whichit isnecessary to make comparisons between the simulation modeland system behavior data for at least a few sets of experimentalconditions, and preferably for several sets. In 2013 Vargas,Mellado and Lesage [4] [3], developed a software tool forbuilding automatically interpreted Petri net models from anobserved system’s input/output sequence.

B. Objectives and Challenges

In this thesis we develop PLC monitoring with the objectiveof verifying that a PLC program fulfills the design specifica-tions. In other words, we want a design validation procedureapplicable to a discrete event system (DES) implemented ina PLC. We assume that the input and output events duringa finite amount of time are enough to characterize the DES.Hence, our validation procedure will be based in observinginput and output signals (events) of the DES.

Our approach for building and debugging a DES imple-mented with a PLC is the following: (i) Design one PN solvingthe same problem that the DES will solve. In this step weavoid some problems by design, e.g. not using unobservabletransitions, preventing deadlocks, etc. (ii) Simulating the PNand saving input and output signals. (iii) Encode the PN intoa PLC language. (iv) Compare simulation with real run.

In this work is proposed the construction of an hardwarePLC Signal Acquirer, able to monitor analyze and validatePLC programs.

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II. D ISCRETEEVENT SYSTEMS

In this chapter we introduce Discrete Event Systems (DES).The structure of the introduction is based in the course Indus-trial Processes Automation by Professor Paulo Oliveira [11]1

and in books [12], [9], [1].A DES can be characterized by a discrete state space whose

state transitions happen at discrete points in time due toevents [1]. In generic terms one PLC is composed of tree majorparts, namely inputs, outputs and a control processor. Whenan input changes, the control processor responds by changingan output. This can be compared to the the state change thatleads to an event occurrence in a DES.

Petri nets allow representing general DES, whose operationdepends on potentially complex control schemes. In Petri nets,events change in accordance to a set of rules. Graphicallyrepresentation of Petri nets, result in Petri net graphs that areintuitive and capture a lot of structural information aboutthesystem.

A Petri net is represented graphically by transitions, eventsthat can or not happen (graphically represented by bars);places, conditions represented by circles; oriented arcs joiningthe circles and bars, conditions that lead to events.An arccan only connect transitions to places and vice-verse. Eachplace is associated with a natural number of marks. The initialstate representation, evolves according to a labeling transitionfunction.

A. Petri Net Definition

A Petri net is a quintuplet, defined by parameters theparameters(P, T,A,W, x), whereP is a finite set of places,T is a finite set of transitions,A are arcs that connect places totransitions and transitions to places,W is the weight functionof the arches, andx represents the marking of places.

B. State Evolution

The state evolution of a Petri net can be described as thefollowing matrix function,

µ(k + 1) = µ(k) +D ∗ q(k). (1)

whereµ(k) represents the present marking,µ(k + 1) is themarking we want to achieve,q(k) represents the triggeringvector needed to go from the markingµ(k) to µ(k + 1) andD is the incidence matrix that accounts the balance of tokens(giving the transitions fired).

A transition tj ∈ T is active if x(pi) ≥ w(pi, tj) for allpi ∈ I(tj). That is,tj transition is enabled when the numberof marks onpi is at least as great as the weight arc connectingpi to tj for all pathspi that are inputs to the transitiontj .

The implementation of a transitiont is accomplished byremoving each place of assemblyL, I(L, t) marks. After this,O(P, t) marks are set in each place of assembly P.

1https://fenix.tecnico.ulisboa.pt/disciplinas/APInd/2010-2011/1-semestre

C. Properties

Petri net properties provide us a way to characterize andstudy discrete event systems.

Property 1. Reachability, a configuration of the marks overplaces M (marking), given a Petri netN , is reachable ifM ∈R(N), whereR(N) is the group of all the possible markingsof N.

Property 2. Boundness, it is the property that verifies if thenumber of marks for all the places is limited. A place in aPetri net is k−bounded if it does not contain more thankmarks in all reachable markings.

Property 3. Safeness, a Petri net is safe if for every possiblemarking, there isn’t more then one mark for each place. ASafe Petri net is 1-bounded.

Property 4. Conservation. A Petri net is strictly conservative,when for every marking the total number of marks remainsthe same. A Petri net is strictly conservative if for everyµ ∈R(C, µ):

∑

pi∈P

µ′(pi) =∑

pi∈P

µ(pi)

Property 5. Liveness. This property is associated, with thepossibility that a Petri net has of running continuously withoutreaching a deadlock. A Petri net is alive if for all the possiblemarkings, there’s a trigger for another marking.

Property 6. Coverability. Given a Petri net with initial mark-ing u0, the stateu′ ∈ R(C, u) is covered ifu′(i) ≤ u(i), forall placespi ∈ P .

D. Supervision based on Linear Constraints

A supervisor is a discrete event system that is used tomonitor and control another discrete event system, satisfyinga specification. In a Petri net, a supervisor restricts transitionsthat may trigger at a given state of the Petri net, so that thespecification is satisfied. We desire a supervisor to preventthesystem from reaching markings which do not satisfy,

Lµp ≤ b (2)

WhereL is an integernc × n matrix (nc is the number ofconstraints, n is the number of places of the given Petri net),b is an integer column vector, andµ is the Petri net marking.µc is a vector ofnc non-negative slack variables, defined as,

µc = b− Lµ (3)

After introduction of slack variables, (2) becomes,

Lµp + µc ≤ b (4)

With µc0 as the initial marking of the Petri net supervisor,

µc0 = b− Lµ0 . (5)

Let Dp be the Petri net incidence matrix, the supervisor withincidence matrix beDc = −LDp,

D = [DTp, D

Tc]T , (6)

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If,Lµp0 − b ≤ 0, (7)

Then a Petri net supervisor enforces the constraint (2) whenincluded in the closed-loop system. If (7) is not true, theconstraints cannot be enforced.

III. PLC DATA ACQUISITION

This section details first the hardware already available forPLC interaction, and then the hardware used and developedfor signal acquisition.

A. Hardware Setup

Figure 1 shows the system architecture in which we basedourselves to fulfill this thesis, composed of four elements:the controlled plant, the programmable logic controller (PLC),the signal acquirer and a personal computer (PC). The signalacquirer and PC form the monitoring hardware. The PLCprovides all the information necessary for the plant to operate,the monitoring hardware is responsible for monitoring thesystem, while it is also able to control the plant (referencegenerator).

PC

Signal

Acquirer

PLC Plant

Fig. 1. Generic setup block diagram.

(a) Power supply. (b) PLC. (c) Terminal.

Fig. 2. 24 volt DC power supply (a). Modicon PLC (b). Terminal with twelvekey numbered keyboard (c).

B. PLC Input and Output Connections

The used controlled plant, our terminal, is a twelve keykeyboard, seen in Figure 2 (c).

To facilitate connections between the difference hardwarecomponents, several printed circuit boards were designed(PCBs), that would allows us to forty pin IDC cables andcables that have a forty pin IDC connection on one end andtwo twenty pin IDC connection connections on the other,Figure3.

(a) Final PLC PCB. (b) Final terminal PCB.

Fig. 3. Assembled printed circuit boards, for PLC (a), and forterminal (b).

Figure 4 shows the full hardware setup with the developedinput and output connections PCBs already assembled.

Fig. 4. PLC to terminal connections using final PCBs manufactured atEurocircuits [5].

C. PLC Input and Output Monitor

Monitoring the PLC will provide a way to keep a log ofall signals that go from/to the PLC to/from the terminal, aswell as communicate with the PLC (acting as a if it was theterminal), and communicate the acquired data with a PC.

I O

PLC

Arduino IO Shield

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4 5 6

7 8 9

0 #*Arduino Mega

INOUT

USB Connection

24V

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ArduinoIn

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Fig. 5. Arduino based pass through logic observer and reference generator

In figure 5 a design for an Arduino based monitoringhardware is shown. The signal acquirer/monitor, composed bythe Arduino and Arduino shield, is the center piece of thesystem, everything connects to it.

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The design of our signal acquirer was done with an ArduinoMega as it main processing unit, because of its characteristics,ease of use, and low cost.

The designed shield provides three forty pin IDC cableconnection, there are two possible connection configurationsthat can the used. The first one for use as a data logger, in theother configuration the Arduino can be configured so that itsinputs/outputs mimics an hardwired connection and also, andto act as a terminal, sending desired signals to the PLC.

The last problem that our Arduino shield solves is theproblem of the Arduino and the PLC’s inputs/outputs workingin different potential differences, using voltage dividers andhex buffer/driver integrated circuits.

USB connection

to PC

Generate andmonitor signalsto/from the PLC

Arduidoto PLC adapter

Arduino Mega

(a) Shield PCB. (b) Signal Acquirer.

Fig. 6. Designed Arduino Mega shield PCB (a). Signal monitor composedby Arduino Mega and Arduino shield (b).

Fig. 7. Generic setup with signal monitor assembled.

1) Arduino Monitoring Program:The main function pro-gram that runs constantly in loop works withFLAG system.The different start with aFALSE value. Inside the mainfunction there is a switch statement that, if there is anyserial communication done with the Ardunio, changes theFLAGS value to TRUE, depending on serial communicationreceived. The fact that aFLAGS hasTRUE value, makes theprogram run extra functions in the next program loop, eachone of this functions represents a command given by serialcommunication.

2) PC Monitoring Program:On the side of the PC the USBconnection allows serial communication. A Matlab script wasdeveloped to do this communication. The script allows a serialconnection to be established with the Arduino, commands tobe send to the Arduino, storage of log data sent from theArduino, ending the serial connection, and drawing differenttype of graphs depending on the information received fromthe Arduino.

IV. PLC PROGRAM DEVELOPMENT AND MONITORING

In this chapter we explain our approach to designing adiscrete event system (DES) problem solution and implemen-tation based in Petri net theory.

A. Petri net Simulation

With a 3x4 keyboard in mind, a Petri net, describing theevents and the state evolution of the key reading system, wasdeveloped to model the process of reading one keyboard keyas a DES, this subject is focus of chapter V. Its analysis isdone resorting to the Petri net simulator PM Editeur[6] andthe Matlab Petri Net toolbox[15], that allows us to generatePetri net’s incidence matrix and initial marking matrix. UsingMatlab functions, combined with the tools mentioned above,we are able to simulate the Petri net’s behavior.

The Matlab simulator works by receiving a structure forPetri net’s characteristics and running a loop, for which eachiteration corresponds to ten milliseconds. The loop’s functionsreceive as inputs the Petri net’s characteristics, and has thefollowing sequence:PN_s2act, for each loop iteration, thisfunction returns an array with the active keyboard columnfor that iteration;PN_tfire, this function returns the Petrinet’s transitions that can be activated at the current time thatthe function is called;filter_possible_firings, thisfunction compares the result fromPN_tfire with the markedplaces from the previous loop iteration or from initial marking,the function returns an array with the possible transition to betriggered, the program can now reassign the marked placesarray with the marked places result for this loop iteration;PN_s2yout, this function checks the marked places arrayand returns the key pressed for this loop iteration.

B. Petri net to PLC Conversion

The approach chosen is using PLC programming languageStructured Text (ST), as the pure text content allows an easiertransfer from the Petri net to the PLC integrated develop-ment environment. ST allows to describe the behavior ofa control function according to the information it receives.Its understanding is simple for users familiar with high-levelprogramming languages.

1) Petri net to Structured Text Compiler:The method cho-sen to transcribe Petri net to ST, creating a PLC program froma Petri Net and IO mapping, uses three auxiliary functions tothat prepare a problem’s specific data, like timed transitionsand physical inputs or outputs, to be used straightforward bythe main script. After having the information provided byour auxiliary functions, we are able to create a PLC programfrom a Petri Net and IO mapping using the functions brieflydescribed:

• plc_map_inputs(inp_bits_lst,trans_lst, options), input is a List of mappedtransitions, outputis ST code with list of transitions andtheir respective input. Allocates one memory position foreach transition. Each transition is represented by memoryposition that is the sum of%MW100 plus its transitionnumber (transition four is%MW104). Establishes causal

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effect relation between PLC inputs and memory positionsthat define transitions.

• plc_timed_transitions(t_trans_place_lst),inputs are a list of timed transitions, time out time,list of places; output is ST code with one timer foreach timed transition. Creates one timer for each timedtransition. The activation of the timer is controlled by aplace being marked, after the timer reaches timeout timethe transition is triggered. Each of this timed transitionsare allocated to one memory position.

• plc_encode_petri_net(pre, pos, mu0,tprio, options), input is loaded Petri net, outputis ST code for memory initialization and logicalconditions between memory positions. To set the initialcondition of the program (initial marking in the Petrinet) it is necessary to create a statement that will beexecuted only once by the PLC. The program representseach place by a memory position that is the sum of%MW200 plus its place number (place four is%MW204).It verifies if initialization command is received, and ifso, all the variables associated to places are set to theirinitial marking value.Defines cause and effect relations between memory posi-tions that define places and memory positions that definetransitions, by usingif statements that check if thememory position for a transition has a value different thanone, and that the memory positions for the places thatneed to be marked for the transition’s firing are marked,if these two conditions are met, the memory positionvalues are decremented and the memory positions for theplaces that receive a mark from the referred transition areincremented.

• plc_output_if_any_place(places_lst_main,outp_bit_main), input is list of mapped places,output is ST code with list of places and their respectiveoutput. The value of auxiliary variable associated witheach place is assigned to its respective output variable,using if statements. Various places can be associatedwith the same PLC output, usingor statements.

• plc_encode_places(places_lst,outp_bits_lst), input is list of places, outputis ST code to output debug/monitor info. Creates PLCcode to output debug / monitor info. Receives a list ofplaces. Usingif, establishes relation between thoseplaces being marked and a variable (output). It alsocreates aflag to check if more then on of the places inthe list e marked. Using bit logic bit logic, and the valuefrom the variableoutput, a bit signal representing themarked place is sent using four outputs.

V. CASE STUDY: KEYBOARD READING

The physical system’s process consists of reading onekeyboard key with a PLC implementing the DES. This sectiondescribes the synthesis of the DES for keyboard reading, tak-ing into account modeling and analysis properties. Synthesiswill be based on supervised control.

A. Proposed Petri Net Model

Modeling the process of reading one keyboard key as aDES, is done by developing a Petri Net that describes theevents and the state evolution of the key reading system. Thedeveloped system can be divided into tree main blocks. Eachblock represents one of the tree keyboard columns. In eachof the three blocks there is a wait state, waiting for a keyin their column to be pressed. If a key is pressed the systemevolves to a state waiting for the key to be released, and thenthe system evolves to the first state, of waiting for a key to bepressed (same column). The wait for a key to be pressed stateis timed (fifty milliseconds), if a key is not pressed the systemevolves to a wait state for keys from the second column. Ifagain a key is not pressed, after fifty milliseconds the systemevolves to a state of waiting for a key to be pressed on thethird column, if another fifty milliseconds go by, the systemevolves again to the first state. A timed transition (T1, T11 andT2) is used for each of the tree wait states. The activation ofdifferent columns is represented by the marking of one placeconnected that connect to one of these transitions (P1, P2 adP3). If a key is pressed transitions are activated, depending onthe key, that pass the mark to a new place representing thepressed key. A transition connected to each place representinga pressed key, sends the mark to the wait timed place when akey is released. From the event evolution the incident matrixcan be obtained. The resulting Petri net is shown in Figure 8.

P1

P6 P7

T9

T1

P5 P4

T10 T7 T8

T4 T5 T6 T3

P2

P9 P8

T16

T2

T11

T17 T18 T19

T12 T13 T14 T15

P10 P11

P3

P13 P12

T24 T25 T26 T27

T20 T21 T22 T23

P14 P15

Fig. 8. Developed Petri net.

B. Properties

From equation 1, it is known that for in order there needsto exist a triggering vectorq(k) to go from the markingµ(k)to µ(k + 1), in order µ(k + 1) be reachable. By analyzing

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the Reachability Tree, with initial stateµ0 = (1, 0, ..., 0)(corresponding to the beginning column scanning in column1), it is verified that the reachability setR(N) is finite and thatall other system states are reachable. From the ReachabilityTree we can observe that there are sixteen different possiblemarkings. From a direct analysis, we observe that for eachmarking, it is always possible to define a triggering sequencethat will enable any other transition. From this we can con-clude all transitions are live, and from every state you canreach every state, no deadlock occurs. All the transitions arelive of level four. A Petri net is k-bounded if all its placesare k-bounded. A place is k-bounded if for all possible states,the number of marks is less than or equal to a integer k. Thedeveloped Petri net is conservative, the total number of marksremains constant, which ensures that all states have the samenumber of marks that the initial state. As the initial state hasa mark in place one (scanning starts in column one), and zeromarks in the other places, after each transition, only one ofthe places will have a mark and all other places will have zeromarks. Therefore, all places are one bounded and as such, thePetri net is one bounded. It is observable that the Petri net issafe, since by definition, a Petri net is safe if all its placesareone bounded.

C. Supervisor

In order to eliminate failure in the designed system, due tomore than one key being pressed simultaneously, designingand implementation of a supervisor, that detects the multiplekeys pressed error and resumes the normal operation of thesystem, is done by applying Supervisory Control theory.

Using only two transitions and two places, we can informthe system of triggering of multiple keys at the same time,taking the system to a error state. Place seventeen is usedas a flag, that when marked indicates multiple keys arebeing triggered. In order to trigger transition twenty eight,the triggering of multiple keys must be detected, leading tothe marking of place seventeen. When a non-error state isagain reached transition twenty nine is triggered and placesixteen is marked. On Figure 9 the Petri net way of workingis shown. To integrate theflag Petri net, with the Petri net

P17

T28

T29

P16

T28

T29Multiple

keys Pressed

Fig. 9. Flag Petri net method of operation.

described in section V-A, and this way creating a controllertohandle the multiple keys pressed error, linear constraintsmustbe implemented. The linear constraints imposed are relatedto key validation places and the place that is used as a errorflag not being able to be marked simultaneously. This isrepresented by, ifµk is the number of marks in placek:

µ17 + µk ≤ 1, k ∈ {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} (8)

From the linear constraints and using controller synthesisdescribed in section II-D, the relation 9 allows us to obtainthe matrices forL andb.

Lµp ≤ b (9)

The next step in controller synthesis based on linear constraintsis verifying b− Lµp0 ≥ 0, which is true given that the resultof b− Lµp0 is b. It is relevant to note thatµp0 represents theinitial markings of the combined Petri nets, it is an one columnmatrix with one row per Petri net place, seventeen in total,with all values zero except for the first and sixteenth values,which are one. The first value represents the first state of thekeyboard Petri net, waiting for a key to be pressed for fiftymilliseconds, and sixteenth value represents theFlag Petri netstate of multiple keys not being pressed at the same time. Thesupervisor incidence matrix (Dc) and initial markings (µc0)are determined by the relations 10 and 11, respectively.Dp

represents the incidence matrix of the combined Petri nets.

Dc = −LDp (10)

µc0 = b− Lµp0 (11)

The finale incidence matrix of the supervised system (D) isconstituted by the incidence matrix for the Petri net used forkey detection from section V-A, the incidence matrix for thePetri net used to detect pressing of multiple keys, the incidencematrix for the system that combines the last two referredPetri nets (Dp), and the supervisor controller incidence matrixsynthesized based on linear constraints (Dc). The supervisedsystem resulting Petri net is shown in Figure 10.

Fig. 10. Petri net developed for keyboard control, with supervisor.

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D. Implementation

Using the ST compiler detailed in IV-B1, we are able toimplement the Petri net for our case study in the PLC asST code. With the results from the auxiliary functions, ourcompiler is then able to create ST code to run in loop in thePLC, that simulates the work-flow of the developed Petri Net,taking into account the inputs and outputs received by thePLC. The ST program generate is comprised of five cyclicoperations:Petri net initialization To set the initial conditionof the program (initial marking in our Petri net) it is necessaryto create a statement that will be executed only when anspecific input is received by the PLC. If this condition ismet, the valueHIGH must be assigned to all the auxiliaryvariables corresponding to the places initially marked, andthe valueLOW must be assigned to all the auxiliary variablescorresponding to the places with no initial marking. Thiscorrelates to our case study keyboard being in the state of nokeys pressed and with the column one being the first one to bechecked. Tomap PLC inputs For each input (that represents atransition) there are two variables, one to represent theHIGHstate of the input and one to represent theLOW state. Thevariables also takes into consideration if the output that allowsthe change of state of an input isHIGH or LOW. This part ofthe program checks for keys being pressed or released, and setsthe appropriate value to a variable that represents those actionstransition. Controlling oftimed transitions is done with threetimers which consecutively, for fifty milliseconds, set thevalueof one variable corresponding to a Petri net place toHIGHstate. This are the same transitions used in our Petri net towait for a key to be pressed for fifty milliseconds for eachcolumn. ThePetri net loop does PLC variables verification.For each scancycle, checks which places should be markedor unmarked. For this, a logical combination (AND) of twoconditions must be performed: (a) input variables associatedwith the transition are satisfied (HIGH); (b) existence of tokensin places (auxiliary variables areHIGH). If a transition toanother PN state is possible, the value of place variables isdecreased, and the value of the variable representing the nextPlace is increased.Setting PLC outputs is done by checkingthe values of the created variables and variables that representPN Places directly dependent on the first referred variables. Itthen sets one of three PLC outputs to aHIGH or LOW level,making possible the interaction of the terminal with the PLC.Encoding of placeschecks the value of the PLC variablesthat represent PN Places are marked depending on the PLCinput, and then outputs a four bit signal depending on whichPN Place is marked or if more then one Place is marked (errorcase).

VI. EXPERIMENTS

This chapter describes the experiments performed to vali-date the methodologies presented and introduced in previouschapters.

A. PLC Characterization

PLC’s operate by continually scanning programs and read-ing inputs and outputs. One iteration of this process is called

I O

PLC

Arduino based

monitor

(a) Setup. (b) Monitored signal.

%q0 . 3 . 1 6 := NOT(%q0 . 3 . 1 6 ) ;

(c) PLC program

Fig. 11. Experimental setup for PLC characterization (a). Signal flow diagramfor the first experiment (b). PLC square wave generation program (c).

scan cycle. The scan cycle consists of three steps: determinestatus of inputs, interpret logic of programs, and update outputstatus. Knowing the scan cycle allows us to know smallesttime period possible for the PLC to detect two consecutivekey triggers. In our experiments the PLC’s scan cycle wasfixed to ten milliseconds, this value was chosen to have a morestable scan cycle, as experiments will show, and because in theimplemented Petri net the minimum value of scan cycle neededfor correct operation is fifty milliseconds. It is also a unrealisticto experiment terminal key pressing for time differences solow. The used experimental setup for this section is shownin Figure 11 (a). Figure 11 (b) shows the block diagramrepresentation of the system used for the PLC’s scan cyclecharacterization. The structured text program implemented inthe PLC in order to monitor the scan cycle is shown inFigure 11 (c). By running this program the PLC is setting itsfirst output (%q0.3.16) to zero volts or twenty four volts,its output is a square wave. Figure 12 shows the results of

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(c) Scan cycle times. (d) Histogram.

Fig. 12. PLC output captured by the Arduino based monitor, multipleexperiments, 5 scan cycles window, first rising edge in each window shiftedto t = 0 (a). All rising edges shifted tot = 0 (b). Observed scan cycle timesalong 8 seconds (c). Histogram of observed scan cycle times (d).

monitoring the PLC’s square wave for eight seconds. In (a)and (b) we overlap the results of the monitored scan cyclesrising edge’s shifted totime = 0s. In (a) the overlapping is

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done in groups of five scan cycles, and in (b) all the monitoredscan cycles are overlapped. In (c)Each of the blue circlesrepresents the time difference between a monitoring a digitalTRUE value and a digitalFALSE value PLC output (half theperiod of the square wave the PLC sending as output) along theeight seconds of monitoring, each value represents a differenttime of scan cycle. (d) is a graphical representation of thedistribution of the scan cycle time value, histogram. Fromthe results shown in Figure 12 it is observable that the PLCdoes not have an exact time value between occurrences, thistime varies roughly between nine point five milliseconds andten point five milliseconds. In the context of our case study,keyboard reading, the interpretation of these results leads usto acknowledge that a key should not be pressed for less thenten point five milliseconds, or it might not be detected by thePLC. This is of course also valid for any input we wish thePLC to read. In this next experiment the PLC structured text

%q0 . 3 . 1 6 := %i 0 . 3 . 0 ;

(a) PLC program.

I O

PLC

50ms

100ms

10Hz

Time difference of

rising and falling edges

0 1 2 3 4 5 6 7 8

40

42

44

46

48

50

52

54

56

58

60

time [s]

half

perio

d [m

s]

(b)IO signals. (c) Input Detection.

Fig. 13. Observing the time for 100ms period square signal detection. PLCtest code. (a) Connections diagram (b). Observed PLC time of signal detectionalong 8 seconds (c).

program in Figure 13 (a) was implemented in PLC. In thiscase, the monitoring system is not only monitoring the PLC’sinputs and outputs, but it is also generating a square wavesignal with a period of one hundred milliseconds. The PLCshould set its output according to the value it is receiving inits input (digitalTRUE or FALSE), the received square wavevalue. In Figure 13 (b) a block diagram for this experiment isshown. From the results shown in Figure 13 (c) we observethat the monitoring system detected the PLC output changein the expected time instances, fifty milliseconds apart (halfthe period time). We can also observe that time of inputdetection is not exact. The results also show some increasein input detection, of almost ten milliseconds. This happenswhen the PLC fails to detect an input change, and onlydetects it in its next scan cycle, thus the increase of tenmilliseconds. The forty milliseconds time change shown inthe results, happens because an input was detected late bythe PLC, so the time difference of the next correctly detectedinput should be detected ten milliseconds earlier. The factthatthere are two input detections at sixty milliseconds since thelast inputs, but only one forty milliseconds input detectionsince the last input, can be attributed to two straight inputdetection delays by the PLC. In the context of our case study,keyboard reading, the interpretation of previous results leadsus to acknowledge that the PLC set to a ten millisecond time of

0 1 2 3 4

x 10−3

0

5

10

15

20

25

time [s]

PLC

out

[V]

0 1 2 3 4

x 10−3

0

5

10

15

20

25

time [s]

PLC

out

[V]

(a) Minimum time observed. (b) Maximum time observed.

Fig. 14. Varying scan cycle time. Minimum scan cycle time observedexperimentally (a). Maximum scan cycle time observed experimentally (b).

scan cycle has an accuracy with an error of plus and minus tenmilliseconds. Figure 14 shows the minimum (a) and maximum(b), time difference between rising edges, of monitoring timeof scan cycle, as it was done in the first experiment (resultsshown in Figure 12), but with the difference that this resultswere obtained without a PLC fixed scan cycle time of tenmilliseconds. As shown in Figure 14, the PLC can have ascan cycle of less then one millisecond, but the variation oftime of scan cycle increases greatly, leading to detected changein scan cycle time of around three milliseconds. Since thereis no need in our case study, to have a scan cycle lower thanten milliseconds, and since not assigning a fixed value to thePLC’s time of scan cycle leads to a more unstable scan cycletime, the ten milliseconds time of scan cycle was sustained inexperiments done in the next sections.

B. Key detection

This experiment carried out a sequential triggering and re-lease of all the keys, without conflicts. The used experimentalsetup for this section is the same shown in Figure 7. The key

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]

Time Key Inputs Expected Result0 - -1 1 12 - -3 2 24 2 25 3 36 - -7 4 48 5 59 6 610 7 711 - -12 8 813 9 914 10 1015 11 1116 - -17 12 12

(a) Input data, pressed keys.(b) Expected results given the input

data.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Errors

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Errors

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]

(c) Expected output, MatLab sim-

ulation.(d) Monitoring experiment results.

Fig. 15. PLC output captured by the Arduino based monitor, input datakey sequence (a). Input data, sequence of keys (b). Expectedoutput, MatLabSimulation (c). PLC output observed with the developed monitor (d).

sequence used, during a time period of eighteen seconds (inputdata), is shown in Figure 15 (a). In Table (b), besides the keysequence used, also includes the period of time in which thekeys are triggered and the expected results the PLC should

9

output. Figure 15 (c) shows the Matlab simulation results usingthe input data for this experiment. Figure 15 (d) shows the PLCmonitoring results for the same input data. The experimentalresults are consistent with the Matlab simulation results,aswell as with the expected results. This experiment shows thatthe correct validation of key triggering and release of all thekeys, without conflicts, is correctly done by the the Petri netimplemented in the PLC.

C. Initial Marking Effect

Initial marking of the implemented Petri net is expectedto have an effect to our system in the way it validates oneof multiple keys triggered at the same time from differenceterminal keyboard columns. The key sequence used for all the

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

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key 12

time[s]0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

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key 12

time[s]

(a) Input data.

µ0 =[

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1]T

(b) Initial marking.

(c) MatLab Simulation. (d) PLC output.

Fig. 16. PLC output captured by the Arduino based monitor, input datakey sequence (a). Initial marking of Petri net (b). Expected output, MatLabSimulation (c). PLC output observed with the developed monitor (d).

experiments in this section, during a time period of eighteenseconds (input data), is shown in Figure 16 (a). In (b) isshown the first used initial marking matrix. Figure 16(c) showsthe Matlab simulation results using the input data for thisexperiment. Figure 16(d) shows the PLC monitoring results forthe same input data. The experimental results are consistentwith the Matlab simulation results. As expected, the resultsshow that in the first time instance of pressed keys, the keyvalidated is the one that belongs to the initial marked column(first column), key one. In Figure 17(a) is shown the initialmarking matrix used for this section’s second experiment.With this initial marking, when the Petri net is initialized,the place in which the the system waits for a key to bepressed on the third column for fifty milliseconds is marked.Figure 17(c) shows the Matlab simulation results using theinput data for this experiment. Figure 17(d) shows the PLCmonitoring results for the same input data. The experimentalresults are consistent with the Matlab simulation results.Asexpected, the results show that in the first time instance of

µ0 =[

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1]T

(a) Initial marking.

(b) MatLab Simulation. (c) PLC output.(c) PLC output.

Fig. 17. PLC output captured by the Arduino based monitor, initial markingof Petri net (a). Expected output, MatLab Simulation (b). PLCoutput observedwith the developed monitor (c).

pressed keys, the key validated is the one that belongs to theinitial marked column (third column), key three. Comparingthese results with the ones on the last experiment we alsoobserve that the rest of the validated keys does not match, thisis also expected, since the fact that the initialization is donein different columns, with the passage of time, the columnactivation for each column will be done in different timeinstances.

D. Supervisory Control

In this section we present the results concerning the imple-mentation, to the design Petri net, of a supervisor based inlinear constraints, done in section V-C, in order to preventfailure in the designed system, due to more than one keybeing pressed simultaneously. Figure 18 (a) shows the key

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

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key 12

time[s]

Time Key Inputs Expected Result0 1 11 - -2 - -3 - -4 - -5 - -6 - -7 - -8 2, 8 Error9 - -10 - -11 - -12 - -13 5 514 - -15 - -16 - -17 - -

(a) Input data, pressed keys.(b) Expected results given the input

data.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Errors

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Errors

key 1

key 2

key 3

key 4

key 5

key 6

key 7

key 8

key 9

key 10

key 11

key 12

time[s]

(c) Expected output for supervisor

experiments, MatLab simulation.

(d) Monitoring supervisor experi-

ment results.

Fig. 18. PLC output captured by the Arduino based monitor, input datakey sequence (a). Input data, sequence of keys (b). Expectedoutput, MatLabSimulation (c). PLC output observed with the developed monitor (d).

combinations being pressed and released by the developedmonitoring system, during a time period of eighteen seconds(input data). The table (b) in the same Figure shows the

10

expected results for each time instant. Figure 18 (c) showsthe Matlab simulation results from the input data mentionedabove. Figure 18 (d) shows the PLC monitoring results for thesame input data. Both results are consistent with the expectedresults, and with each other. The supervisor detects triggeringof multiple keys and does not validate any of them. In theMatlab simulation that single keys being pressed during thetime of experiment are validated, but when the system receivesmultiple keys from the same column, eight seconds time mark,no key is validated. In the monitoring results, no key validatedin the eight seconds time instance, and we can also observethat the PLC outputs the error bit sequence as mentioned insection V-D. This error sequence is received multiple timesduring the referred time instance, this is due to the fact that thePLC keeps receiving, from the monitoring system, the samekey triggering information for every scan cycle it does duringthe said time period.

VII. C ONCLUSION AND FUTURE WORK

The work described in this thesis aimed at verifying thata PLC program fulfills design specifications, from the dataacquired by a developed signal acquirer for PLC signal inputsand outputs. The main objective of developing this device istobe able obtain information about a DES PLC implementationthat could lead to the validation of the implementation.

We first presented a form of DES representation, Petri nets,a intuitive method that captures structural information aboutthe system and has mathematical analysis techniques welldeveloped. This proved to be a way to represent our case study.We were able to create the intended system as a Petri net, andusing matrix techniques, we were able to solve the problemof multiple keys being triggered at the same time.

We have developed a signal acquirer, based in the low-cost microcontroller-based board Arduino Mega, that canobserve and save in memory signals going from and to a PLCconnected to a terminal, and at the same time is able to connectto a PC for further data processing. The signal acquirer is alsoable to act as the terminal, mimicking its behavior by sendingsignals to the PLC. In order to achieve this we developedan Arduino shield that was able to ensure the connectionsbetween the Arduino, the PLC and the terminal.

To implement a DES in a PLC, in a the form of Petrinet representation, we chose to do it building a program thatproduces structured text code, a form of PLC programming,based on receiving a Petri net characteristics. Implementinga Petri net in a device usually requires discrete events, butmay also require timed events. To develop the conversionprogram we add to take into consideration not only the Petrinet relationships between places and transitions, but we hadto take into consideration the assurance of having a way toinitialize the implemented Petri net in the desired configura-tion. We had to define connections between signal inputs andoutputs with the various PLC memory positions attributed tothe Petri net places and transitions. In the end, besides onefunction that creates code from a Petri net structure, four otherfunctions had to be created. This points are also valid for thePetri net simulator used to obtain results about the Petri netdevelopment along a time period.

The case studied in chapter V showed that, although a Petrinet being good way to represent a DES, it does not take intoconsideration some. One of those aspects is that a PLC isbased in scan cycles, as shown in the experiments section,which constrain the activation speed of transitions. We alsoobserved, in the experiments, that a PLC is also subject todelay of signal change detection, which is another aspect thata Petri net does not take into consideration.

The Petri net modeling proved to be effective. We were ableto obtain a working system for the proposed case study. Thesupervisor implementation was also successful, in the sensethat applied the desired constraints. However, even thought wewere able to predict to a large extent the experimental results,the experiment consisting of changing the initial marking ofa Petri net, proved that a DES implementation into a realworld situation has more details that have to be taken intoto consideration than those presented by a Petri net.

Future work should focus on further development of theArduino based shield. Ways to not bind each of the Arduino’sinputs and outputs to one signal can be implemented using IC’sthat can send send signals to multiple lines at the same time,by only receiving signal from one source. This would makeit possible to use a even lower-cost version of the Arduinoboard.

Another aspect that should be developed, is the DES repre-sentation. The use of a more advanced Petri net representation,I/O Petri net, can lead to a more detailed DES representation,with fewer aspects that affect its implementation.

REFERENCES

[1] Christos G. Cassandras and Stephane Lafortune.Introduction to discreteevent systems. Springer Science+Business Media, New York, N.Y, 2008.

[2] Geoff Cutts and Shaun Rattigan. Using Petri nets to develop programsfor PLC systems. InApplication and Theory of Petri Nets 1992, pages368–372. Springer, 1992.

[3] Ana Paula Estrada-Vargas, Ernesto Lopez-Mellado, and Jean-JacquesLesage. Automated modelling of reactive discrete event systems fromexternal behavioural data. InElectronics, Communications and Comput-ing (CONIELECOMP), 2013 International Conference on, pages 120–125. IEEE, 2013.

[4] Ana Paula Estrada-Vargas, Ernesto Lopez-Mellado, and Jean-JacquesLesage. Identification of partially observable discrete event manufactur-ing systems. InEmerging Technologies & Factory Automation (ETFA),2013 IEEE 18th Conference on, pages 1–7. IEEE, 2013.

[5] Eurocircuits. Online pcb prototype and small series specialist.http://www.eurocircuits.com/, 2015.

[6] A. Gordon, F. Bousseau, and N. Dangoumau. PM Editor.[7] Tao Huang and Anthony Chung. Communication networks and systems

in substations. 2004.[8] S. Jain, R. R. Creasey, J. Himmelspach, K. P. White, and M. Fu.

VERIFICATION AND VALIDATION OF SIMULATION MODELS.[9] John O. Moody and Panos J. Antsaklis.Supervisory Theory of DES

Using Petri Nets. Kluwer Academic Publishers, Notre Dame, 1998.[10] Thomas H. Naylor, J. M. Finger, James L. McKenney, WilliamE.

Schrank, and Charles C. Holt. Verification of computer simulationmodels.Management Science, 14(2):pp. B92–B106, 1967.

[11] Paulo Oliveira. Industrial processes automation (course IST/MEEC).https: //fenix.tecnico.ulisboa.pt /disciplinas /APInd /2010-2011 /1-semestre, 2010.

[12] James L. Peterson.Petri Net Theory and the Modeling of Systems.Pretice-Hall, Austin, Texas, 1981.

[13] Carl Petri. Communication With Automata. PhD thesis, DarmstadtUniversity of Technology, 1962.

[14] S. Schlesinger.Terminology for model credibility. 1979.[15] Martina Svadova and Zdenek Hanzalek. Matlab toolbox for petri nets.

In 22nd International conference ICATPN 2001, pages 32–36, 2001.