VHDL : Part 1 of 3 Page 1 of 12 Module 6: VHSIC Hardware Description Language VHDL stands for VHSIC (very high-speed integrated circuit) hardware description language. Process of bringing number of circuits into single chip. It is a programming language used to design or simulate a digital system. This language was first introduced in 1981 for the department of Defense (DoD) under the VHSIC program. Do we really need VHDL? There are other conventional options to describe or design system. They are 1. Boolean Equations By creating Boolean equations & using different minimization techniques e.g. K map, Quine MC Cluskey, for required digital system, one can design system. But if system is very big which contains millions of gates, then this method is impractical. If we know how system behaves but don‟t know it‟s equation then also we can not design digital system using this method. 2. Schematic based design method It uses CAD tools. This method also have drawbacks. It is time consuming to design large systems which contains millions of gates. This method can not built system by only describing functional behavior of system. All above drawbacks are get overcome by using VHDL. Why VHDL is most Universal?/ What are advantages of VHDL? 1. VHDL is most popular HDL language wordwide. In North America and Europe more than 50% design engineers use VHDL. 2. Flexible:- Simply by editing source code easy modification possible in circuit. 3. No limit on size of circuit for implementation. 4. Less time to market:- Once coding is ready, system can be built on FPGA/CPLD in no time. Hence prototyping is possible. 5. System can be specified in structural and/or behavioral ways at different levels. It does not restrict user for one type of description only. Even VHDL can used at different complexity levels, i.e. from single transistors to complete systems.
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Module 6: VHSIC Hardware Description Language€¦ · VHDL : Part 1 of 3 Page 1 of 12 Module 6: VHSIC Hardware Description Language VHDL stands for VHSIC (very high-speed integrated
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Process of bringing number of circuits into single chip.
It is a programming language used to design or simulate a digital system. This language was first
introduced in 1981 for the department of Defense (DoD) under the VHSIC program.
Do we really need VHDL? There are other conventional options to describe or design system. They are
1. Boolean Equations
By creating Boolean equations & using different minimization techniques e.g. K map, Quine
MC Cluskey, for required digital system, one can design system.
But if system is very big which contains millions of gates, then this method is
impractical.
If we know how system behaves but don‟t know it‟s equation then also we can not
design digital system using this method.
2. Schematic based design method
It uses CAD tools. This method also have drawbacks. It is time consuming to design large
systems which contains millions of gates. This method can not built system by only
describing functional behavior of system.
All above drawbacks are get overcome by using VHDL.
Why VHDL is most Universal?/ What are advantages of VHDL? 1. VHDL is most popular HDL language wordwide. In North America and Europe more than 50%
design engineers use VHDL.
2. Flexible:- Simply by editing source code easy modification possible in circuit.
3. No limit on size of circuit for implementation.
4. Less time to market:- Once coding is ready, system can be built on FPGA/CPLD in no time.
Hence prototyping is possible.
5. System can be specified in structural and/or behavioral ways at different levels. It does not
restrict user for one type of description only. Even VHDL can used at different complexity
levels, i.e. from single transistors to complete systems.
VHDL : Part 1 of 3
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6. VHDL is not only restricted to electronics system. It has been used for modeling & simulation of
electromechanical, hydraulic, chemical and other systems.
7. VHDL based simulation tools are available easily. Simulation means applying inputs to system
through software and checking output again on software. Simulation is used to check whether
system is working asper desire. Output is in form of timing waveforms. No hardware come into
picture. Modelsim and Synplify Pro are the most popularly used simulation tools.
8. Many vendors offer synthesis tools. Synthesis means conversion of design at gate level circuit.
Commonly Used VHDL tools
Vendor Simulator Synthesizer
Altera Modelsim- Altera Edition Altera Quartus
Xilinx ISE Simulator XST
Actel Modelsim-Actel Edition Synplify
Mentor Modelsim PE Leonardo Spectrum
Some terms in VHDL:-
Netlist:- It is textual representation of circuit in terms of components and nets that are connecting the
components.
RTL:- It is level of description of a digital circuit in which operation is spread over several clock cycles
describes circuit behavior as a flow of data between registers.
History of VHDL:- DoD need VHSIC chips. At that time, most of companies were using different HDL to describe or
develop VHSIC, because of that different vendors could not exchange designs to one another. Each
Vendor provide its design to DoD in different HDL. Hence it is difficult to combine this all. Therefore
need of standardization come forward. In 1981, DoD has given responsibility to 3 companies, IBM,
Texas Instruments & Intermetrics of developing common standard language for design. These
companies were developed VHDL version 7.2 in 1985. Joint efforts by universities, Industry & DoDs
make language standardize by IEEE in 1987. After 5 years IEEE standard need to be rebooted.
Features of VHDL/ Capabilities of VHDL:- 1. It supports hierarchy – Digital system can be modeled as set of interconnected components.
Again each component can be modeled as set of interconnected subcomponets.
Consider example of a Full-adder which is the top-level module, being composed of
three lower level modules i.e. Half-Adder and OR gate.
Example:
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2. VHDL is not case sensitive language
3. VHDL is not restricted to electronics only. It has been used for modeling & simulation of
electromechanical, hydraulic, chemical and other systems.
4. It is synthesizable language.
5. Along with functionality, area and speed can be identified.
6. Large designs can be modeled using VHDL. There is no limitation on size of design.
7. It contains elements which makes Large Scale design easy. e.g. components, procedures,
functions, packages.
8. Language is not technology specific:- As technology independent same model can be
synthesized into different vendor libraries. E.g. same design can be synthesized on 65 nm
technology, 90 nm technology, 45 nm technology,
9. Support for Test & simulation:- To ensure that design is correct as per the specifications, the
designer has to write another program known as “TEST BENCH”. It generates a set of test
vectors and sends them to the design under test(DUT). Also gives the responses made by the
DUT against a specifications for correct results to ensure the functionality. Test benches can be
written using same language to test other VHDL modules.
10. System can be explained in VHDL by three different ways. They are called as modeling styles.
E.g. Dataflow modeling, Behavioral modeling and structural modeling.
11. It supports flexible design methodologies: Top down, Bottom-up, Mixed.
12. Concurrency:- VHDL is a concurrent language. It supports concurrent statements, means
statements executing in parallel. HDL differs with Software languages with respect to
Concurrency only. VHDL executes statements at the same time in parallel (concurrently), as in
Hardware.
13. VHDL supports sequential statements also, it executes one statement at a time in sequence
only. As the case with any conventional languages.
example:
if a=„1‟ then
y<=„0‟;
else
y<=„1‟;
end if ;
14. Strongly typed language:-
VHDL allows LHS & RHS operators of same type. Different types in LHS & RHS is illegal in
VHDL. Allows different type assignment by conversion.
example:
A : in std_logic_vector(3 downto 0).
B : out std_logic_vector(3 downto 0).
C : in bit_vector(3 downto 0).
B <= A; --perfect.
B <= C; --type miss match, syntax error
Basic Elements in VHDL file:- Identifiers
Data objects
Data Types
Operators
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Basic Structure of VHDL file/ VHDL code:- Library
Package
Configuration
Entity
Functions
Procedures
Architecture
VHDL code for full adder:- Step1:
Draw IC layout for full adder. Full adder adds 3 bit
of data and gives output in form of sum & Carry.
Decide name of IC.
Decide input and output pins.
Name each pin.
Fulladder
Step2:
Decide in which modeling style program to be
written.
Here dataflow modeling style is selected.
Before writing program using dataflow modeling
programmer should know either logic equations of
digital system or Truth table of system.
For full adder equations of system are:
Sum = A B Cin
Cout = AB + ACin + BCin
These equations are represented in architecture body of VHDL code using VHDL operators.
_ _Full adder VHDL Program
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Fulladder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC); end Fulladder;
architecture dataflow of Fulladder is begin Sum <= A XOR B XOR Cin; Cout <= (A AND B) or (A AND Cin) or (B AND Cin);
end dataflow;
………………………………………………..
In above program words written in bold
are called „keywords‟. (Keywords are
reserved words in language. They have
specific meaning & task assigned
which is known by language. They can
not be used as basic identifiers.)
Remaining words are called
„Identifiers‟. These are names given by
programmer.
Description of VHDL program:
VHDL source code(program) has two main parts: „Entity‟, which describes input ,output pins of
system and „Architecture‟ which gives entire function of circuit. Refer above VHDL code while
reading following description.
Comment:- comment in VHDL is denoted by “--”( Two consecutive dashes). Everything after the
“--” to the end of the line is considered as comment. Whatever typed after -- in same line is not
considered for compilation.
Optional
Called as subprograms and they are optional
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Library:- Library statements usually located at the top of a file. Library contains number of
packages. IEEE is name of library. It contains standard modules, all inbuilt defined constructs like
all basic gates, operators, packages etc. In most vhdl programs you have already seen examples of
packages and libraries. Here are two:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
The packages are "std_logic_1164" and "std_logic_signed" and the library is "ieee". Since the
"scope" of the library statement extends over the entire file, it is not necessary to repeat that. The
VHDL datatype „std_logic‟ is declared in „ieee.std_logic_1164‟, and so a use word at the top of the
file makes the datatype visible for later reuse. Above the „use’ word, we need a „library’ word so
that the compile would know that the word ieee is a library name.
There are two types of libraries in VHDL: System library and User library. User library is not
needed. If required we can include it. But system library is compulsory to use in any vhdl code.
Syntax of system Library:-
library library_name; use library_name.Package_name.ALL;
Example of system library:-
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
Syntax of work Library:-
library work; use work.user_Package_name.ALL;
A signal declared in a package can be used by any design entity that access the package. Such
signals are similar in concept to global variables used in computer programming languages.
Entity:-
Entity specify external view of system. Entity does not specify circuit functionality. It only explains
input ,output pins of system, names of that pins and their data type. „port‟ means pins of system.
Direction of port means direction of pins. It is also called „modes‟ for signals. Datatype informs
about type of data, the pin can accept or give out e.g. binary, decimal etc.
Syntax of entity:-
entity entity_name is
port(port_name:direction_of_port_pin datatype;
port_name: direction_of_port_pin datatype;
………..);
end entity_name;
Example of entity:-
Fulladder
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entity Fulladder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC); end Fulladder;
Mode/Direction Purpose Diagrammatic View
IN Used for signal that is an input to a system
OUT Used for signal that is an output to a system.
INOUT Used for signal that is both input & output to a
system.
BUFFER Used for a signal that is output from system.
But signal can go in both directions, either in
or out inside the components. The value of
signal can be read by component.
Identifiers:- Identifiers are used as names for VHDL entities, architectures, objects, procedures,
functions, processes etc., and as reserved words. There are two classes of identifiers: basic
identifiers and extended identifiers.
I. Basic Identifier (naming) rules:
Can consist of alphabet characters [an upper-case letter (A... Z), or a lower-case letter (a. ..