MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17 Dept. of Computer Science And Applications, SJCET, Palai Page 19 2.1 INTRODUCTION Instruction: - An instruction is a binary pattern designed inside a microprocessor to perform a specific function. 8086 instruction size varies from one to six bytes Fig 1. 8086 General Machine language instruction format of 8086 Byte 1 information: • Opcode field (6-bits)—specifies the operation to be performed by the instruction • D (1-bit)—register direction: tells whether the register which is selected by the REG field in the second byte is the source or destination D = 0 source operand D= 1 destination operand • W (1-bit)—data size word/byte for all registers Byte = 0 Word =1 Byte 2 information: • MOD (2-bit mode field)—specifies the type of the second operand Memory mode: 00, 01,10—Register to memory move operation Register mode: 11—register to register move operation • REG (3-bit register field)—selects the register for a first operand, which may be the source or destination
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MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
Dept. of Computer Science And Applications, SJCET, Palai Page 19
2.1 INTRODUCTION
Instruction: - An instruction is a binary pattern designed inside a microprocessor to perform a
specific function.
8086 instruction size varies from one to six bytes
Fig 1. 8086 General Machine language instruction format of 8086
Byte 1 information:
• Opcode field (6-bits)—specifies the operation to be performed by the instruction
• D (1-bit)—register direction: tells whether the register which is selected by the REG field in the
second byte is the source or destination
D = 0 source operand
D= 1 destination operand
• W (1-bit)—data size word/byte for all registers
Byte = 0
Word =1
Byte 2 information:
• MOD (2-bit mode field)—specifies the type of the second operand
Memory mode: 00, 01,10—Register to memory move operation
Register mode: 11—register to register move operation
• REG (3-bit register field)—selects the register for a first operand, which may be the source or
destination
MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
Dept. of Computer Science And Applications, SJCET, Palai Page 20
• R/M (3-bit register/memory field)—specifies the second operand as a register or a storage location
in memory
2.2 INSTRUCTION FORMATS
In 8086 six types of instruction formats.
1. 1-Byte instruction
2. Register to register
3. Register to/from memory with no displacement
4. Register to/from memory with displacement
5. Immediate operand to register
6. Immediate operand to memory with 16-Bit displacement.
1. 1-Byte instruction
The instruction is 1-byte long in size.
It May contain implied data or register operands (data).
The least significant 3 bits of the opcode are used for specifying the register operand, if any.
Otherwise all the 8 bits form an opcode
MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
Dept. of Computer Science And Applications, SJCET, Palai Page 21
2. Register to Register
The instruction is 2-byte long in size.
First byte of code denotes opcode, direction & width of operand.
Second byte denotes register operands & R/M field.
REG field denotes type of register used.
R/M field denotes register or memory location used.
The register specified by REG is a source operand if D = 0 , else it is a destination operand.
10001000 11 000 001
REG =000 indicates Register AL
R/M =001 indicates Register CL
3. Register to/from memory with no Displacement
The instruction is 2-byte long in size.
First byte of code denotes opcode & width of operand.
Second byte denotes mod, register operands & R/M field.
MOD field denotes type of addressing mode used.
The instruction 10001011 00 000 111 indicates the operation MOV AX, [BX]
4. Register to/from memory with Displacement
The instruction is 4-byte long in size.
First byte of code denotes opcode.
Second byte denotes register mod, register operands & R/M field.
Third byte denotes lower byte of displacement.
MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
Dept. of Computer Science And Applications, SJCET, Palai Page 22
fourth byte denotes higher byte of displacement
5. Immediate operand to register
The instruction is 4-byte long in size.
The first byte as well as the 3 bits from the second byte which are used for REG field in case of
register to register format is used for opcode.
Second byte denotes opcode, R/M field.
Third byte denotes lower byte of data.
Fourth byte denotes higher byte of data.
6. Immediate operand to memory with 16-bit displacement
The instruction is 5 or 6-byte long in size.
First byte of code denotes opcode.
Second byte denotes register mod, opcode & R/M field.
Third byte and fourth byte denotes lower byte and higher byte of displacement.
2.3 INSTRUCTION SET OF 8086
The entire group of instructions that a microprocessor supports is called Instruction Set.
Classification
1. Data Transfer instructions.
2. Arithmetic & Logical instructions.
3. Branch instructions.
4. Loop instructions.
5. Machine Control instructions.
6. Flag Manipulation instructions.
7. Shift & Rotate instructions.
8. String instructions.
1. Data Transfer Instructions
These instructions are used to transfer data from source to destination.
The operand can be a constant, memory location, register or I/O port address.
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i. MOV Destination, Source;
Source can be register, memory location, immediate data and port address.
Destination can be register or memory location.
Both Source and Destination cannot be memory location or segment registers at the same time.
They must both be of the same type (bytes or words).
Does not affect any flag.
Examples
MOV CX, 037AH Put immediate number 037AH to CX
MOV AX, BX Copy content of register BX to AX
MOV DL, [BX] Copy byte from memory at [BX] to DL
MOV DS, BX Copy word from BX to DS register
ii. Push Source;
Source can be register, segment register or memory.
This instruction pushes the contents of specified source on to the stack.
In this stack pointer is decremented by 2.
The higher byte data is pushed first.
Then lower byte data is pushed.
iii. POP Destination;
Destination can be register, segment register or memory.
This instruction pops (takes) the contents of stack to the specified destination.
In this stack pointer is incremented by 2.
The lower byte data is popped first.
Then higher byte data is popped.
E.g.
POP AX;
POP DS;
POP [5000H];
MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
Dept. of Computer Science And Applications, SJCET, Palai Page 24
iv. XCHG Destination, source;
This instruction exchanges contents of Source with destination.
It cannot exchange two memory locations directly.
The source and destination are of equal types.
E.g.
XCHG BX, AX;
XCHG [5000H], AX;
v. IN AL/AX, 8-bit/16-bit port address
It reads from the specified port address.
It copies data to accumulator from a port with 8-bit or 16-bit address.
DX is the only register is allowed to carry port address.
E.g.
IN AL, 80H;
IN AX, DX; //DX contains address of 16-bit port.
vi. OUT 8-bit/16-bit port address, AL/AX;
It writes to the specified port address.
It copies contents of accumulator to the port with 8-bit or 16-bit address.
DX is the only register is allowed to carry port address.
E.g.
OUT 80H, AL;
OUT DX, AX; //DX contains address of 16-bit port.
vii. LEA 16-bit register, address
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LEA also known as Load Effective Address (LEA).
It loads a 16-bit register with the offset address of the data specified by the Src.
Does not affect any flag.
E.g.
LEA BX, [DI]: This instruction loads the contents of DI (offset) into the BX register.
viii. LDS 16-bit register, address
LDS Also known as Load Data Segment (LDS).
Loads new values into the specified register and into the DS register from four successive memory
locations.
The word from two memory locations is copied into the specified register and the word from the
next two memory locations is copied into the DS registers.
LDS does not affect any flag.
Ex: LDS BX,5000H;
ix. LES 16-bit register, address
LES Also known as Load Extra Segment (LES).
This instruction loads new values into the specified register and into the ES register from four
successive memory locations.
The word from the first two memory locations is copied into the specified register, and the word
from the next two memory locations is copied into the ES register.
LES does not affect any flag.
Ex
LES BX, 5000H;
x. LAHF
This instruction loads the AH register from the contents of lower byte of the flag register.
This command is used to observe the status of the all conditional flags (except over flow) of flag
register.
E.g. LAHF;
xi. SAHF
This instruction sets or resets all conditional flags (except over flow) of flag register with respect to
the corresponding bit positions.
If bit position in AH is 1 then related flag is set otherwise flag will be reset.
MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
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E.g. SAHF;
xii. PUSH F
It copies contents of flag register to the stack
This instruction decrements the stack pointer by 2.
E.g. PUSH F
xiii. POP F
It copies contents of memory location pointed by stack pointer to the flag register.
This instruction increments the stack pointer by 2.
E.g. POP F
2. Arithmetic Instructions
These instructions perform the operations like: Addition, Subtraction, Increment, Decrement,
Compare etc
i. ADD/ADC destination, source;
ADD instruction adds the contents of source operand with the contents of destination operand.
ADC instruction adds the contents of source operand with the contents of destination operand with
carry flag bit.
The source may be immediate data, memory location or register.
The destination may be memory location or register.
The result is stored in destination operand. AX is the default destination register.
The source and the destination in an instruction cannot both be memory locations.
The source and the destination must be of the same type (bytes or words).
Flags affected: AF, CF, OF, SF, ZF.
E.g. ADD AX,2020H;
ADD AX, BX;
E.g. ADC AX,2020H;
ADC AX, BX;
ii. INC source
This instruction increases the contents of source operand by 1.
The source may be memory location or register.
The source cannot be immediate data.
The result is stored in the same place.
E.g. INC AX;
INC [5000H];
MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
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iii. DEC source
This instruction decreases the contents of source operand by 1.
The source may be memory location or register.
The source cannot be immediate data.
The result is stored in the same place.
E.g. DEC AX;
DEC [5000H];
iv. SUB/SBB destination, source
SUB instruction subtracts the contents of source operand from contents of destination.
A SBB instruction subtracts the contents of source operand & borrows from contents of destination
operand.
The source may be immediate data, memory location or register.
The destination may be memory location or register.
The result is stored in the destination place.
E.g. SUB AX,1000H;
SUB AX, BX;
E.g. SBB AX,1000H;
SBB AX, BX;
v. CMP destination, source
Also known as Compare.
This instruction compares the contents of source operand with the contents of destination operands.
The source may be immediate data, memory location or register.
The destination may be memory location or register.
Result is, carry & zero flag will be set or reset.
E.g. CMP AX,1000H;
CMP AX, BX;
D=S: CY=0,Z=1
D>S: CY=0,Z=0
D<S: CY=1,Z=0
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vi. AAA
Also known as ASCII Adjust After Addition
Corrects result in AH and AL after addition when working with BCD values.
does not have any operand and affects AF and CF flags
Is executed after ADD instruction.
Example:
MOV AH,0 ; Clear AH for MSD
MOV AL,6 ; BCD 6 in AL
ADD AL,5 ; Add BCD 5 to digit in AL
AAA ; AH=1, AL=1 representing BCD 11
vii. AAS
Known as ASCII Adjust After Subtraction.
This instruction is executed after SUB instruction.
Affects Z and C flags
If low nibble of AL > 9 or AF = 1 then:
AL = AL - 6
AH = AH – 1
AF =CF = 1
Else
AF = CF = 0
In both cases: clear the high nibble of AL.
Example;
AL =0011 1001 =ASCII 9
BL=0011 0101 =ASCII 5
SUB AL, BL; (9 - 5) Result: AL = 00000100,CF = 0
If low nibble of AL > 9 or AF = 1 then:
AL = AL + 6
AH = AH + 1
AF = 1 and CF = 1
Else
AF = 0 and CF = 0
In both cases: Clear the high nibble of AL.
MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
Dept. of Computer Science And Applications, SJCET, Palai Page 29
AAS; Result: AL=00000100; CF = 0
viii. MUL operand
Unsigned Multiplication.
Operand contents are positively signed.
Operand may be general purpose register or memory location.
If operand is of 8-bit then multiply it with contents of AL.
If operand is of 16-bit then multiply it with contents of AX.
Result is stored in accumulator (AX).
Flags Affected: OF, CF
Ex
MUL BH // AX= AL*BH; // (+3) * (+4) = +12.
MUL CX // AX=AX*CX;
ix. DIV operand
Unsigned Division.
Operand may be register or memory.
Operand contents are positively signed.
AL=AX/Operand (8-bit/16-bit) & AH=Remainder.
E.g. MOV AX, 0203 // AX=0203
MOV BL, 04 // BL=04
DIV BL // AL=0203/04=50 (i.e. AL=50 & AH=03)
x. AAM
Also known as ASCII Adjust after Multiplication.
This instruction is executed after MUL instruction.
Corrects the result of multiplication of two BCD values.
does not work with imul instruction
Then AH=AL/10 & AL=Remainder.
updates P, S and Z flags
Example:
MOV AL, 5
MOV BL, 7
MUL BL ; Multiply AL by BL , result in AX
AAM ; After AAM, AX =0305h
xi. AAD;
Also known as ASCII Adjust before Division.
MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17
Dept. of Computer Science And Applications, SJCET, Palai Page 30
converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL .