MODULE I PROCESS STEPS IN IC FABRICATION INTRODUCTION The monolithic IC is one in which all circuit components are fabricated into or top of a block of silicon which is referred to as chip (or dies). Interconnections between the components within the chip are made by means of metallization patterns, and the individual components are not separable from the circuit. The processing steps used to fabricate various silicon devices, such as diodes, transistors, and integrated circuits are as follows: 1. Refining and growth of Silicon Crystals 2. Si Wafer preparation 3. Diffusion (and ion implantation) of dopant impurities 4. Oxidation 5. Photolithography 6. Chemical vapour deposition (including epitaxy) 7. Metallization. 8. Testing and chip separation 9. Packaging The fabrication of devices starts with single-crystal silicon wafers. Then the processes listed above can be used to produce discrete devices (i.e., individual diodes and transistors) and ICs. These devices or ICs will be in wafer form with tens, hundreds, or even thousands of discrete devices or ICs on the same silicon wafer. The wafer is then divided up to obtain the individual dice or chips. These chips are then encapsulated or packaged, with a wide variety of packages and packaging methods being possible.
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MODULE I
PROCESS STEPS IN IC FABRICATION
INTRODUCTION
The monolithic IC is one in which all circuit components are fabricated into or top of a block of silicon
which is referred to as chip (or dies). Interconnections between the components within the chip
are made by means of metallization patterns, and the individual components are not separable
from the circuit.
The processing steps used to fabricate various silicon devices, such as diodes, transistors, and integrated
circuits are as follows:
1. Refining and growth of Silicon Crystals
2. Si Wafer preparation
3. Diffusion (and ion implantation) of dopant impurities
4. Oxidation
5. Photolithography
6. Chemical vapour deposition (including epitaxy)
7. Metallization.
8. Testing and chip separation
9. Packaging
The fabrication of devices starts with single-crystal silicon wafers. Then the processes listed above can
be used to produce discrete devices (i.e., individual diodes and transistors) and ICs. These devices or
ICs will be in wafer form with tens, hundreds, or even thousands of discrete devices or ICs on the same
silicon wafer. The wafer is then divided up to obtain the individual dice or chips. These chips are then
encapsulated or packaged, with a wide variety of packages and packaging methods being possible.
Packaging provides
encapsulation of the chip for protection of the environmental effects, and
Easy access to the various parts of the chip by means of a lead or pin structure such that
the device may be conveniently plugged into or attached to the rest of the system.
The process steps for wafer fabrication are generally applied a number of times in succession, especially
in the case of ICs, where as many as 10 repetitions of the photolithography, oxidation, and
diffusion steps may be used.
REFINING AND GROWTH OF SILICON CRYSTALS
The most commonly available natural sources of silicon are silica and silicates. At present, silicon-made
devices constitute over 95% of all semiconductor devices.
The reasons for using silicon as a suitable material for IC fabrication are:
1. Silicon devices can operate up to 150˚C versus 100˚C for Germanium.
2. Silicon grows a stable oxide (SiO2), which is one of the very important process steps in the
fabrication of ICs. Germanium oxides are unsuited for devices applications.
3. The intrinsic (Undoped) resistivity of Ge is about 47Ω-cm, which precludes the fabrication of
rectifying devices with high breakdown voltages. The intrinsic resistivity of Si is 23x104Ω-cm,
thus high rectifying devices are practical with Si.
4. Electronic graded Ge is more costly than Si.
Production of Electronic Grade Silicon (EGS)
The raw material for the preparation of single-crystal silicon is the electronic-grade silicon (EGS) which
is a polycrystalline material of high purity. The major impurities in the EGS are boron, carbon, and
residual donors. Pure EGS should have doping elements in the parts per billion (ppb) range, and carbon
less than, 2 parts per million (ppm). Production of EGS is a multistep process as shown in Fig.1.
A metallurgical-grade silicon (MGS) is produced in an arc furnace, which is charged with
quartzite, a relatively pure form of sand (SiO2), and carbon in the form of coal, coke, and wood
chips. The MGS is drawn off and solidified at a purity of 98%. This is still not suitable for
manufacturing semiconductor devices. The overall reaction in the furnace being
SiC+Si02 Si + SiO+ CO
(Solid) (Solid) (Liquid) (Gas) (Gas)
The MGS is pulverized mechanically and reacted with anhydrous hydrogen chloride (HCl) to
form Trichlorosilane (SiHCl3), according to the reaction :
Si + 3 HC1 SiHCl3+H2
(Solid) (Gas) (Gas) (Gas)
The reaction takes place at a nominal temperature of 300°C using a catalyst. Here silicon
tetrachloride (SiCI4) and the chlorides of impurities are formed. At this point the purification
process occurs. Trichlorosilane is a liquid at room temperature, because its boiling point is
32°C. Therefore purification is done by fractional distillation. The purified SiHCl3 is subjected
to chemical vapour deposition (CVD) to be discussed later. The chemical reaction is a
hydrogen reduction of SiHCl3.
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2SiHC13+ 2H2 2Si+ 6HCl
The reaction takes place in a CVD reactor in which a resistance-heated Si-rod (4-mm diameter),
called a "slim-rod", serves as the nucleation point for the deposition of silicon. The process results in
rods of EGS which are up to 0.2 m (or more) in diameter and several meters in length. EGS can be cut
from these rods as single chunks or crushed into nuggets. To achieve high overall efficiency of the
process, feedback or recycling of reaction byproducts is used as shown in Fig.1.
There is also another process of producing EGS in which silane (SiH4) is subjected to
pyrolysis.
SiH4+heat Si + 2H2
(Gas) (Solid) (Gas)
In this process the CVD reactor is operated at about 900°C and supplied with silane instead of
Trichlorosilane. The advantages of producing EGS from silane are lower cost and less harmful
reaction byproducts.
Crystal Structure and Growing
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Crystal structure: Though EGS is highly refined, it is not suitable for manufacturing ICs because IC
components are formed in a single crystal silicon wafer. The silicon wafer must be single crystal, but it
does not represent an ideal crystal due to following reasons:
The wafer has finite boundaries; thus, atoms at the surfaces are incompletely bonded as against
those in the bulk of the wafer material.
The atoms are displaced from their ideal locations by thermal agitation.
Real crystals have defects which are mainly classified into four types :
o point defect,
o line defect (dislocation),
o area or planar defect, and
o Volume defect.
The crystal defects influence the optical, electrical, and mechanical properties of silicon.
Point defect refers to following forms of defect:
A nonsilicon atom incorporated into the lattice at either a substitutional or interstitial site: The
former refers to site produced by replacing a parent silicon atom and the latter refers to existing
site between silicon atoms. The nonsilicon atom may be an intentional dopant as introduced
by diffusion process (to be discussed) or an unintentional impurity.
A vacancy in the lattice created due to missing atom: this is also known as a Schottky defect.
A silicon atom in an interstitial lattice site with an associated vacancy: this is also known as a
Frenkel defect.
Chemicalvapour deposition (including epitaxy)
Metallization
Vacancies and interstitials have equilibrium concentrations that depend on temperature. Point defects
are important in the kinetics of diffusion and oxidation. The diffusion of many impurities depends on
the vacancy concentration, as does the oxidation rate of silicon.
Dislocations second class of defects. There may be edge (line) dislocation or screw dislocation. The
edge dislocation in a cubic lattice may be created by an extra plane of atoms. Crystals for IC usage
are generally grown free of edge dislocations, but may contain small dislocation loops from excess
point-defect considerations. These defects act as nuclei for the precipitation of impurities such as
oxygen and are responsible for a swirl pattern seen in wafers. Dislocations in devices are generally
undesirable, because they act as sinks for metallic impurities and alter diffusion profiles.
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Area defects represent a large area discontinuity in the lattice. The crystal on either side of the dis-
continuity may be otherwise perfect. Two typical area defects are twin and grain boundaries.
Twinning represents a change in the crystal orientation across a twin plane, such that certain
symmetry, such as mirror image, exists across that plane. In silicon the twin plane is 111). A grain
boundary represents a transition between crystals having no particular orientation relationship to one
another. Grain boundaries separate grains of single crystal in polycrystalline silicon. Crystals having
such area defects are not used for IC manufacture.
Volume Defects Precipitates of impurity or dopant atoms constitute the volume defects. Every impurity
introduced into the lattice has a solubility; that is, a concentration that the parent lattice can accept in a
solid solution of itself and the impurity. If an impurity is introduced (at a temperature T1 at the
maximum concentration allowed by its solubility, add the crystal is then cooled to a lower temperature
(say T2), a supersaturated condition is said to exist. The crystal achieves an equilibrium state by
precipitating the impurity atoms in excess of the solubility level as a second phase which is being a
material of different composition and structure. For example, excess metallic impurities can react with
silicon and form silicides within the parent lattice. Precipitates are generally undesirable because they
act as sites for dislocation generation.
Crystal Growing: Growing crystals involves a phase change from solid, liquid, or gas phases to
crystalline solid phase. Czochralski growth is the process used to grow most of the crystals from
which silicon wafers are produced. The silicon crystal growth is a liquid-solid mono component
growth system. The growth of a Czochralski (CZ) crystal, involves the solidification of atoms from a
liquid phase at an interface. The speed of the growth is determined by the number of sites on the face
of the crystal and the specifics of heat transfer at the interface. Fig.2 shows the transport process and
temperature gradients involved.
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The heat transfer condition about the interface can be modeled by the following equation
H dm/dt + σl dT/dxM AM = σs dT/dxN AN……………………………. (1)
where H is the latent heat of fusion, dm/dt: is the mass solidification rate, T is the temperature, σl and
σs are the thermal conductivities of the liquid and solid respectively, dT/dxM and dT/dxN are the thermal
gradients at point M and N which are near the interface in the liquid and solid, respectively, and AM
and AN are the areas of the isotherms at positions M and N respectively. From Eq. (1) the maximum pull
rate of a crystal under the condition of zero thermal gradients in the melt, i.e., dT/dxM = 0, can be
obtained. The maximum pull rate is given by
Pmax = σs dT/Hd dxN ……………………………. (2)
Pmax is the maximum pull rate or pull speed and d is the density of solid silicon.
The pull rate affects the impurities going into the crystal during growth and decides the defects
generated. Generally, when the temperature gradient in the melt is small, the heat transferred to the
crystal is the latent heat of fusion. Therefore, the pull rate generally varies inversely with the diameter.
In practice the pull rates obtained are 30 to 50% slower than the maximum theoretical values.
The growth rate or growth velocity of the crystal is very important growth parameter, and is the
instantaneous solidification rate. We should note that pull rate is the macroscopic indication of net
solidification rate. These two rates differ because of temperature fluctuations near the interface. The
growth rate can be more than the pull rate or even be negative at a given time. When the growth rate is
negative, remelting occurs. That is, the crystal dissolves back into the melt. Remelting must be
eliminated to remove crystal defects. This elimination also results in more uniformly doped crystal.
The growth rate affects the defect structure and dopant distribution in the crystal on a macroscopic
scale.
Every impurity has a solid solubility in silicon. The impurity has different equilibrium solubility in the
melt. The equilibrium segregation coefficient (ratio of equilibrium concentrations in solid to that in
liquid) of the impurity or dopant atoms is below unity; this holds good for commonly found impurities,
and commonly used dopants in silicon. Therefore during growth, the impurities at the interface are left
in the liquid (melt). Thus, as the crystal grows, the melt becomes progressively enriched with
impurity, i.e., extremely small impurities are incorporated in the grown crystal.
The boundary layer thickness is a function of the convection conditions in the melt. Rotation of a
crystal in a melt (forced convection) produces a boundary layer. In large melts the convection forced
by rotation is often secondary to the thermal convection caused by temperature gradients in the crucible.
Because the thermal convection is a random process, the thickness of the boundary layer fluctuates with
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time, resulting in a variable value for boundary layer thickness. The net result of thermal convection
effects is an inhomogeneous distribution of dopant in the crystal on a microscale. The pull speed is
also a factor in determining the shape of the growing interface. A proper choice of these conditions is
needed to ensure the stability of the growth process. The crystal planes decide the processing
characteristics and some material properties of silicon wafers. The 111 planes have the highest
density of atoms on the surface, so crystal grow most easily on these planes.
Mechanical properties such as tensile strength are highest for <111> directions. The moduli of
elasticity also shows an orientation dependence. Processing characteristics such as thermal oxidation
are similarly orientation dependent. For example, 111 planes oxidize faster than 100 planes,
because they have more atoms per unit surface area available for the oxidation reaction to occur.
Historically, bipolar transistor devices have preferred <111> oriented material and MOS devices
<100>. There are, of course, exceptions.
Crystal Growth Apparatus
The highly refined silicon (EGS) though free from impurities, is still polycrystalline. Hence it is to be
processed to become single crystal. The Czochralski crystal growth process shown in Fig.3, is the one
most often used for producing single-crystal silicon ingots.
Since monolithic ICs are usually fabricated on a substrate which is doped with impurity, the poly-
crystalline silicon with an appropriate amount of dopant is put into a quartz crucible, which is then
placed inside a crystal growth furnace. The material is then heated to a temperature that is slightly in
excess of the silicon melting point of 1420°C. A small single crystal rod of silicon called a seed crystal
is then dipped into the silicon melt. The conduction of heat up the seed crystal will produce a reduction
in the temperature of the melt in contact with the seed crystal to slightly below the silicon melting
point. The silicon will therefore freeze onto the end of the seed crystal, and as the seed crystal is slowly
pulled up out of the melt it will pull up with it a solidified mass of silicon that will be a crystallographic
continuation of the seed crystal. Both the seed crystal and the crucible are rotated but in opposite
directions during the crystal pulling process in order to produce crystalline ingots of circular cross
section. If the temperature and pulling rate are correctly chosen, the liquid solid interface remains
near to the surface of the melt and long single crystal silicon is pulled from it. The diameter of the ingot
is controlled by the pulling rate and the melt temperature, with ingot diameters of about 100 to 150
mm (4 to 6 inches) being the most common. The ingot length will generally be of the order of 3
meter, and several hours are required for the "pulling" of a complete ingot. The crystal pulling is done
in an inert-gas atmosphere (usually argon or helium), and sometimes a vacuum is used. This is done to
prevent oxidation. The pull-rate is closely related to the heat input and losses, crystal properties and
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dimensions. The conditions for crystal pulling are, therefore, carefully controlled. For example, the
melt temperature is monitored with a thermocouple and feedback controller. Longer diameter crystals
have commercial advantages and can be grown. However, difficulties may be encountered because of
resistivity gradient across finished slices.
The crystal growth apparatus in Fig.3, basically, consists of
(i) Furnace,
(ii) Crystal pulling mechanism
(iii) Ambient control facility, and
(iv) Control system circuitry.
(i) The furnace consists of crucible, susceptor (crucible support) and rotational mechanism, heating
element and power supply, and chamber. The crucible is the most important component of the growth
apparatus, since it contains the melt. The crucible material should be chemically unreactive with
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molten silicon. Also, the material should have high melting point, thermal stability, and hardness. The
materials for crucible, which satisfy these properties, are silicon nitride (Si3N4) and fused silica (SiO2).
The latter is in exclusive use. Fused silica, however, reacts with silicon, releasing silicon and oxygen
into the melt. In this process the crucible undergoes erosion. Crystals grown with this crucible also
contain substantial amounts of interstitial oxygen that can be either beneficial or deterimental. Also, the
purity of the silica of crucible itself affects the crystal purity. The susceptor is used to support the silica
crucible. It also provides for better thermal conditions. Graphite is the material of choice because of its
high-temperature properties. The graphite should be pure to prevent contamination of the crystal from
impurities that would be volatilized from the graphite at the temperature involved. The susceptor rests
on a pedestal whose shaft is connected to a motor that provides rotation. The whole assembly can
usually be raised and lowered to keep the melt level equidistant from a fixed reference point, which is
needed for automatic diameter control.
The chamber housing the furnace must provide easy access to the furnace components to facilitate
maintenance and cleaning. The furnace structure must be airtight to prevent contamination from the
atmosphere, and have a specific design that does not allow any part of the chamber to become so hot that
its vapour pressure would be a factor in contaminating the crystal. Hottest parts of the apparatus are
water cooled. Insulation is usually provided between the heater and the chamber wall. To melt the
charge, RF (induction) heating or resistance heating are used. RF heating is useful for small melt
sizes, but resistance heating is used exclusively in large crystal pullers.
(ii) The crystal-pulling mechanism consists of seed shaft or chain, rotation mechanism, and seed
chuck. The mechanism controls two parameters of the growth process: pull rate and crystal rotation.
Also, the pulling mechanism must have minimum vibration and great precision. The seed holder and
pulling mechanism must maintain precise orientation perpendicular to the melt surface. As shown in
Fig. 3, the crystal leaves the furnace through a purge tube, where ambient gas, if present, is directed
along the surface of the crystal to cool it. From the purge tube, the crystal enters an upper chamber,
which is usually separated from the furnace by an isolation valve.
(iii) The ambient control for the crystal growth apparatus consists of gas source, flow control, purge
tube, and exhaust or vacuum system. The crystal growth must be conducted in an inert gas or
vacuum as stated earlier. This is necessary because
the hot graphite parts must be protected from oxygen to prevent erosion and
The gas around the process should not react with the molten silicon.
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Growth in vacuum meets these requirements. Growth in a gaseous atmosphere, generally used on large
growers, must use an inert gas such as helium or argon. The inert gas may be at atmospheric pressure
or at reduced pressure.
(iv) The control system for crystal growing may consist of micro process, sensors, and outputs and
provides control of process parameters such as temperature, crystal diameter, pull rate, and rotation
speed. The use of digital or microprocessor-based systems for control is more common because these
rely less on operator intervention and have many parts of the process preprogrammed.
Effects of Unintentional Impurities on Silicon Crystal Properties
Oxygen and carbon are the more common undesired impurities incorporated during silicon crystal
growth. Oxygen in silicon arises from the dissolution of the crucible during growth. Carbon in silicon
arises due to its transportation from the graphite parts in the furnace to the melt.
As an impurity, oxygen has three effects on silicon crystal: donor formation, yield strength
improvement and defect generation by oxygen precipitation. The donor affects the resistivity of the
crystal. Improvement in yield strength due to oxygen impurity is a beneficial effect. A variety of crystal
defects are associated with oxygen precipitate formation. These defects attract fast-diffusing metallic
species, which give rise to large junction leakage currents. The ability of defects to capture harmful
impurities is referred to as gettering. This effect can be used beneficially. Carbon impurity is another
undesirable impurity which aids in the formation of defects.
After silicon crystal (also called ingots or boules) growth, it is usually weighed, then inspected visually.
Gross crystalline imperfections such as twinning are removed by cutting. Also, the irregularly shaped
or undersized sections of boule are cut. Total silicon loss can equal 50% at this step. Next the butt (or
tang) end of the ingot (or a slice cut from that position) is preferentially etched to reveal defects. A
common etchant is a one: one mixture of HF acid (49%) and five-molar chromic acid. This etchant is
also used on polished and processed wafers to delineate other types of micro defects or impurity
precipitates. Cracks can be detected using ultrasonic technique. Resistivity measurements are made on
the flat ends of the crystal by the four-point probe method to be described later. Boron (p-type)-doped
CZ silicon is available in resistivity from 0.0005 to 50 ohm-cm. Arsenic-and phosphorus (n-type)-
doped silicon crystal is available in the range 0.005 to 40 ohm-cm. Arsenic is preferred in the lower
resistivity ranges. Antimony is also used in 0.01 ohm-cm range. This dopant is suitable for growing
epitaxial substrates.
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SI-WAFER PREPARATION
Ingot Trimming and Slicing
Once the crystal ingot is obtained using above process, the extreme top and bottom portions of the ingot
are cut off and the ingot surface is ground to produce a constant and exact diameter which is usually
100, 125, or 150mm. A crystallographic orientation flat is also ground along the length of the ingot.
The ingot is then sliced using a large-diameter stainless steel saw blade with industrial diamonds
embedded into the inner-diameter cutting edge. This will produce circular slices or wafers that are
about 600 to 1000 μm thick, as shown in Fig.4. The orientation flat serves as a useful reference plane
for various device processes. Correct orientation of the surface of the wafers with respect to the crystal
planes is important for successful epitaxial layer growth.
Wafer Polishing and Cleaning
While slicing the wafer, its surface is heavily damaged. Therefore, the wafers undergo a number of
polishing steps for the following reasons:
1. To remove the damaged silicon from the sawn surface.
2. To produce a highly planar or flat surface that will be required for the photo-lithographic
process especially when fine-line geometries are involved.
3. To improve the parallel.
As discussed above, the sliced wafer is 0.6 to 1mm thick. This is quite rough. Hence it is to be lapped
to remove saw marks and to produce a flat surface. The raw wafer may have a surface damage
(including micro cracks) of the order of 75 μm. After lapping, still there exists a surface damage to a
depth of around 15 μm. It is removed with a chemical etch employing an acid mixture consisting of
nitric acid to oxidize the surface and hydrofluoric acid to dissolve the oxide. The wafer is then
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polished mechanically on a wheel to mirror like finish, using aluminium abrasive powders of
decreasing grit size (down to a final 1 μm diameter). There still exits a surface damage of around 2 μm
deep. Finally it is removed by an additional chemical etching stage, which can be sometimes being
simultaneous with the final polishing stage.
Usually, only one side of the wafer is given the final mirror smooth highly polished finish, the other
side (i.e. the back side) being given just a lapping operation to ensure an acceptable degree of flatness
and parallelism. After the wafer polishing operations are completed, the wafers are thoroughly cleaned,
and dried, and they are now ready to be used for the various processing steps described in the
following sections.
Wafer Processing Considerations
Chemical Cleaning. After polishing, the wafers are thoroughly cleaned to remove organic films,
heavy metals, and particulates. Commonly used are aqueous mixtures of NH2OH–H2O2, HC1–H202,
and H2SO4–H2O2. All of the solutions are efficient in removing metallic impurities, but the HCl– H202
mixture is the best. The ammonium hydroxide and sulfuric acid based mixtures will also remove
organic contaminants, but the latter is better in this regard. A typical cleaning sequence would be
sulfuric acid-hydrogen peroxide clean followed by the hydrofluoric acid dip, with deionized water
rinses following each acid step.
Gettering Treatments. Metallic impurities, such as transition group elements, are located at interstitial
or substitutional lattice sites and act as generation-recombination centers for carriers. The precipitated
forms of these impurities are usually silicides, which am electrically conductive. These effects
deteriorate the performance of VLSI circuits, such as, dynamic random access memories (which
require low junction leakage currents) and narrow-base bipolar transistors, which are sensitive to
conductive impurity precipitates. To remove impurities, as above, "gettering treatment" is carried out.
Gettering is a process that removes harmful impurities or defects from the regions in a wafer where
devices are fabricated. Pregettering refers to gettering treatment provided to silicon wafers prior to IC
processing. Pregettering provides a wafer with sinks that can absorb impurities as they are introduced
during device processing. There are number of techniques for gettering treatment as follows:
Intentionally damaging the back surface of the wafer using mechanical abrasion methods, such
as, lapping or sand blasting.
Damage created in wafer using focused heat beam obtained from a Q-pulsed, Nd : YAG laser-
The laser beam is rastered along the back surface to create dislocations in the wafer which
become favorable trapping sites for fast-diffusing species.
Intrinsic gettering — impurity oxygen causes defect generation by its precipitation. This was
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stated earlier. The defects generated by oxygen precipitation are useful as trapping sites. High
temperature cycle (over 1050°C in N2) is employed to lower the oxygen content near the surface
of the wafer to make it defect-free (denuded) zone which is used for device fabrication.
Additional thermal cycles am added to promote the formation of oxygen precipitates and defects
in the interior of the wafer (hence the name intrinsic gettering).
Intrinsic gettering is very useful-because it fills the volume of the water with trapping sites. Otherwise,
the bulk of the wafer serves-no useful function beyond mechanically supporting the thin layer where
the device is formed. All above methods are employed to improve junction leakage currents. However it
is found that gettering is also useful to improve gate-oxide quality in MOSFET and thus to reduce
leakage. For this a gettering technique is to deposit 1 μm of poly-silicon, after the chemical etching of
the wafer prior to polishing. After polishing, the polysilicon is resident on the rear surface. The grain
boundaries in the polysilicon readily retain process-induced metallic contamination.
Thermal Stress Minimization. In practice wafers experience thermal stresses as they are subjected to
high temperature furnace. If these stresses exceed the yield strength of the material, dislocations in
wafer will form. To minimize the thermal stresses, wafers are withdrawn slowly from the furnace.
This minimizes the temperature gradient. Alternatively, furnace temperature may be lowered prior to
removing the wafers. Oxygen in interstitial lattice site acts to increase the yield strength of silicon
earlier. However this beneficial effect increases with concentration until the oxygen begins to
precipitate. Therefore, oxygen precipitates used for gettering can have negative effects on the yield
strength.
DIFFUSION OF DOPANT IMPURITIES
The process of junction formation, i.e., transition from p to n type or vice versa, is typically
accomplished by the process of diffusing the appropriate dopant impurities in a high temperature
furnace. Impurity atoms are introduced onto the surface of a silicon wafer and diffuse into the lattice
because of their tendency to move from regions of high to low concentration. Diffusion of impurity
atoms into silicon crystal takes place only at elevated temperature, typically 900 to 1100°C.Although
these are rather high temperatures, they are still well below the melting point of silicon, which is at
1420°C. The rate at which the various impurities diffuse into silicon will be of the order of 1 μm /hr at a
temperature range stated above, and the penetration depth that are involved in most diffusion processes
will be of the order of 0.3 to 30 μm. At room temperature the diffusion process will be so extremely
slow such that the impurities can be considered to be essentially "frozen" in place.
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A method of pn junction formation which was popular in the early days is the grown junction
technique. In this method the dopant is abruptly changed in the melt during the process of crystal
growth.
A convenient technique for making pn junction is the alloying of a metal containing doping atoms on a
semiconductor with the opposite type of dopant. This is called the alloyed junction technique.
The pn junction using epitaxial growth is widely used in ICs. An epitaxial grown junction is a sharp
junction.
In terms of volume of production, the most common technique for forming pn junctions is the impurity
diffusion process. This produces diffused junction. Along with diffusion process the use of selective
masking to control junction geometry, makes possible the wide variety of devices available in the form
of ICs. Selective diffusion is an important technique in its controllability, accuracy and versatility.
The Nature of Impurity Diffusion
The diffusion of impurities into a solid is basically the same type of process as occurs when excess
carriers are created non-uniformly in a semiconductor which cause carrier gradient. In each case, the
diffusion is a result of random motion, and particles diffuse in the direction of decreasing concentration
gradient. The random motion of impurity atoms in a solid is, of course, rather limited unless the
temperature is high. Thus diffusion of doping impurities into silicon is accomplished at high
temperature as stated above.
There are mainly two types of physical mechanisms by which the impurities can diffusion into lattice.
They are: (i) Substitutional diffusion and (ii) Interstitial diffusion.
Substitutional Diffusion. At high temperature many atoms in the semiconductor move out of their
lattice site, leaving vacancies into which impurity atoms can move. The impurities, thus, diffuse by this
type of vacancy motion and occupy lattice position in the crystal after it is cooled. Thus,
substitutional diffusion takes place by replacing the silicon atoms of parent crystal by impurity
atom. In other words, impurity atoms diffuse by moving from a lattice site to a neighbouring one by
substituting for a silicon atom which has vacated a usually occupied site as shown in Fig. 5.
Substitutional diffusion mechanism is applicable to the most common diffusants, such as boron,
phosphorus, and arsenic. These dopants atoms are too big to fit into the interstices or voids, so the only
way they can enter the silicon crystal is to substitute for silicon atom. In order for such an impurity
atom to move to a neighbouring vacant site, it has to overcome energy barrier which is due to the
breaking of covalent bonds. The probability of its having enough thermal energy to do this is
proportional to an exponential function of temperature. Also, whether it is able to move is also
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dependent on the availability of a vacant neighbouring site, and since an adjacent site is vacated by a
silicon atom due to thermal fluctuation of the lattice, the probability of such an event is again an
exponential function of temperature.
The jump rate of impurity atoms at ordinary temperatures is very slow, for example about 1 jump per
1050 years at room temperature. However, the diffusion rate can be speeded up by an increase in
temperature. At a temperature of the order 1000°C, substitutional diffusion of impurities is practically
realized in sensible time scales.
Interstitial Diffusion. In such, diffusion type, the impurity atom does not replace the silicon atom,
but instead moves into the interstitial voids in the lattice. The main type at impurities diffusing by
such mechanism is Gold, copper, and nickel. Gold, particularly, is introduced into silicon to reduce
carrier life time and hence useful to increase speed at digital ICs.Figure does not show five voids in
the lattice due to two-dimensional representation.
Because of the large size of such metal atoms, they do not usually substitute in the silicon lattice.
To understand interstitial diffusion, let us consider a unit cell of the diamond lattice of the silicon
which has five interstitial voids. Each of the void is big enough to contain an impurity atom. An
impurity atom located in one such void can move to a neighbouring void, as shown in Fig.6. In
doing so it again has to surmount a potential barrier due to the lattice. This time, most neighbouring
interstitial sites are vacant, so the frequency of movement is reduced. Again, the diffusion rate due
to this process is very slow at room temperature but becomes practically acceptable at normal
operating temperature of around 1000°C. It will be noticed that the diffusion rate due to interstitial
movement is much greater than for substitutional movement. This is possible because interstitial
15
diffusants can fit in the voids between silicon atoms. For example, lithium acts as a donor impurity in
silicon, it is not normally used because it will still move around even at temperatures near room
temperature, and thus will not be "frozen" in place. This is true of most other interstitial diffusions, so
long term device stability cannot be assured with this type of impurity.
Fick's Laws Governing Diffusion Process
The diffusion rate of impurities into semiconductor lattice depends on the following :
1. Mechanism of diffusion,
2. Temperature,
3. Physical properties of impurity,
4. The properties of the lattice environment,
5. The concentration gradient of impurities, and
6. The geometry of the parent semiconductor.
The behaviour of diffusion particles, is governed by Fick's Law, which when solved for appropriate
boundary conditions, gives rise to various dopant distributions, called profiles, which are
approximated during actual diffusion processes. In 1855, Fick drew analogy between material
transfer in a solution and heat transfer by conduction. Fick assumed that in a dilute liquid or gaseous
solution, in the absence of convection, the transfer of solute atoms per unit area in a one dimensional
flow can be described by the following equation
F = - D ∂N(x,t)/ ∂x (3)
where F is the rate of transfer of solute atoms per unit area or the diffusion flux density (atoms/cm2-
sec), N is the concentration of solute atoms (number of atoms per unit volume, atoms/cm), and x is
16
the axis in the direction of solute flow. (Here N is assumed to be a function of x and t only), t is the
diffusion time, and D is the diffusion constant (also referred to as diffusion coefficient or diffusivity)
and has units of cm2/sec. Eq. (3) is called Fick's First law of diffusion
Fick's First law of diffusion states that the local rate of transfer (local diffusion rate) of solute per unit
area per unit time is proportional to the concentration gradient of the solute, and defines the
proportionality constant as the diffusion constant of the solute. The negative sign appears due to
opposite direction of matter flow and concentration gradient; i.e., the matter flows in the direction of
decreasing solute concentration. Fick's first law is applicable to dopant impurities used in silicon. In
general the dopant impurities are not charged, nor do they move in an electric field, so the usual drift
mobility term (as applied to electrons and holes under the influence of electric field) associated with
Eq. (3) can be omitted. In this equation N is in general function of x, y, z and t.
Fick's second Law of diffusion.
The change of solute concentration with time must be the same as the local decrease of the diffusion
flux, in the absence of a source or a sink. This follows from the law of conservation of matter.
Therefore we can write down the following equation
∂N(x,t)/ ∂t = - ∂F(x,t)/ ∂x………………….………………………..(4)
Substituting Eq. (4) into Eq. (3), yields
∂N(x,t)/ ∂t = ∂/ ∂x( D ∂N(x,t)/ ∂x)……………………………….(5)
When the concentration of the solute is low, the diffusion constant at a given temperature can be
considered as a constant, and Eq. (5) becomes
∂N(x,t)/ ∂t = D ∂2 N(x,t)/ ∂x2)……………………………….(6)
Eq. (4.6) is often referred to as Fick's second Law of diffusion.
The solution of this equation gives the impurity concentration, N, at some distance x from the origin,
usually the surface of the semiconductor, as shown in Fig. 7. Since, in all diffusion problems, we are
interested in the variation of impurity concentration with distance. Eq. (6) is useful partial differential
equation. Depending on boundary conditions Eq. (6) has two types of solution. These solutions
provide two types of impurity distribution namely (1) constant source diffusion following
complementary error function (erfc) and (ii) limited source diffusion following Gaussian
distribution function. These names are the result of the mathematical description of the distribution
function and are often referred to as the one step (erfc) and the two step (Gaussian).
17
Diffusion Profiles
Constant Source (erfc) Diffusion. In such type of impurity distribution, the impurity concentration at
the semiconductor surface is maintained at a constant level throughout the diffusion cycle, i.e.
N (o, t) = constant = Ns
The solution to the diffusion equation which is applicable in this situation is most easily obtained by
first considering diffusion totally inside a material in which the initial concentration changes abruptly
in same plane at x = 0, from NS to zero. The constant source diffusion process can be described by the
solution of Eq. (6) satisfying the boundary conditions :
N(o,t ) = Ns = constant and N(x,t)=0
The resulting particular solution of Eq. (6) can be expressed as
N(x,t)=Ns [ (1- 2/√π ∫0 x/2√Dt е- λ2 δ λ] (7)
where λ is an integration variable. The portion of the solution inside the bracket is a well defined and
tabulated function of its argument, and is known as the complementary error function (erfc). Thus, the
resulting concentration at any given point within the silicon material can be written as
N(x, t )=N serfc(x/2√Dt) .(8)
A graph of the complementary error function is shown in Fig. (8), for a range of values of its argument.
18
The change in concentration of impurities with time, as described by the Eq. (8), is then shown in Fig.
9. The surface concentration is always held at Ns, falling to some lower value away from the surface.
If a sufficiently long time is allowed to elapse, it is possible for the entire slice to acquire a dopant
level of Ns per m3. Normalized design chart, shown by Fig.8, allows Eq. (8) to be solved graphically,
so that the impurity profile can be deduced for any particular diffusion time and under particular
condition of temperature, which affects diffusion coefficient D, and surface concentration Ns. If the
diffused impurity type is different from the resistivity type of the substrate material, a junction is
formed at the points where the diffused impurity concentration is equal to the background
concentration already present in the substrate. These junction depths are shown as points x1, x2, x3,
and x4, respectively for the diffusion profiles of Fig. 9.
In the fabrication of monolithic ICs, constant source diffusion is commonly used for the isolation and the
emitter diffusion because it maintains a high surface concentration by a continuous introduction of
dopant. There is an upper limit to the concentration of any impurity that can be accommodated in the
semiconductor wafer at some temperature. This maximum concentration which determines the
surface concentration in constant source diffusion is called the solid solubility of the impurity. Values
of the solid solubility, which are commonly tabulated as function of temperature, are typically of
order 1027 per m3 for the common diffusants in silicon, i.e., boron, phosphorus, and arsenic, under
normal operating temperatures. These are substitutional diffusants. The value for the interstitial
dopant gold is much smaller being typically in the range 1022 to 1023 per m3. The Eq. (8) can be solved
graphically, using the chart shown in Fig. 8. But before this it is necessary to know the diffusion coefficient D,
19
of the particular dopant in the material in which it is diffusing, at a diffusion temperature. Such information is
obtained in graphical form, as shown in Fig.10. Similar information is available for the interstitial dopants,
which have much greater diffusion coefficients.
Limited Source Diffusion (Gaussian Diffusion). Here a predetermined amount of impurity is introduced into
the crystal unlike constant source diffusion. The diffusion takes place in two steps :
1. Predepostion step. In this step a fixed number of impurity atoms are deposited on the silicon wafer
during a short time.
2. Drive-in-step. Here the impurity source is turned off and the amount of impurities already
deposited during step (1) are allowed to diffuse into silicon wafer.
With this type of diffusion, the depth of penetration of impurities during the predeposition step is assumed to be
negligible as compared with the final junction depth achieved after "drive cycle". Thus, the initial impurity
distribution (x, o) is assumed to be a delta function on the semiconductor surface. Then the basic diffusion Eq.
(6) is solved with appropriate boundary condition.
20
∫0 α N(x,t)dx = Q/A = constant
The corresponding solution is N(x, t )= (Q/A /√πDt) е- x2/ 4Dt ……………………………..(9)
Where Q/A is the initial deposited quantity of impurity expressed as atoms/cm2. The impurity profile given
by Eq. (9) is known as the distribution is shown in Fig. 11. Impurity profiles as a function of time can be
deduced from Eq. (9) and are of the general form shown in Fig. 12 for increasing values of time.
The essential difference between the two types of diffusion technique is as follows. Whereas the
surface concentration is held constant for an error function diffusion, it decays with time for the
Gaussian type owing to the fixed available dopant concentration Q. For the case of modeling the
depletion layer of a pn junction, the erfc is modeled as a step junction and the Gaussian as a linear
graded junction. In case of the erfc, the surface concentration is constant, typically the maximum
solute concentration at that temperature or solid solubility limit as shown in Fig. 13.The Gaussian
distribution is used when moderately high sheet resistivity is desired or when multiple diffusions arc
needed. Transistor bases are made by this type of distribution.
Parameters which affect diffusion profile
1. Solid solubility. In deciding which of the available impurities can be used, it is essential to
know the number of atoms per unit volume required by the specific profile is less than the
diffusant's solid solubility
2. Diffusion temperature. Higher temperatures give more thermal energy and thus higher
velocities, to the diffused impurities. It is found that the diffusion coefficient critically depends
upon temperature. Therefore, the temperature profile of diffusion furnace must have higher
tolerance of temperature variation over its entire area.
3. Diffusion time. Increases of diffusion time, t, or diffusion coefficient D have similar effects
21
on junction depth as can be seen from the equations of limited and constant source diffusions.
For Gaussian distribution, the net concentration will decrease due to impurity compensation,
and can approach zero with increasing diffusion times. For constant source diffusion, the net
impurity concentration on the diffused side of the pn junction shows a steady increase with
time.
4. Surface cleanliness and defects in silicon crystal. The silicon surface must be prevented
against contaminants during diffusion which may interfere seriously with the uniformity of the
diffusion profile. The crystal defects such as dislocation or stacking faults may produce localized
impurity concentration. This results in the degradation of junction characteristics. Hence silicon
crystal must be highly perfect.
Basic Properties of the Diffusion Process. Following properties could be considered for designing
and laying out ICs.
1. When calculating the total effective diffusion time for given impurity profile, one must
consider the effects of subsequent diffusion cycles. The effects of the subsequent diffusions on a
given impurity profile can be estimated by defining an effective (Dt) product for the particular
impurity profile as
(Dt)eff = D1t1+D2t2+ D3t3+ ... ...(10)
where t1, t2, t3 etc. are the different diffusion times and D1,D2, D3 etc. are the corresponding diffusion
coefficients as determined by the respective temperatures of the diffusion cycles.
2. The erfc and Gaussian functions show that the diffusion profiles are functions of (x/ √Dt).
Hence, for a given surface and background concentration, the junction depth x1, and x2 associated
with the two separate diffusions having different times and temperature, can be expressed as
x1 / x2 = √ D1t1 / √D2t2 ...(11)
3. Lateral Diffusion Effects. The diffusions proceed sideways from a diffusion window as well
as downward. In both types of distribution function, the side diffusion is about 75 to 80 per cent
of the vertical diffusion.
Dopants and their Characteristics
The dopant selection affects IC characteristics. Boron and phosphorus are the basic dopants of most
ICs. Arsenic and antimony, which are highly soluble in silicon and diffuse slowly, are used before
epitaxial processing or as a second diffusion. Gold and silver diffuse rapidly. They act as
recombination centres and thus reduce carrier life time. Boron is almost an exclusive choice as an
acceptor impurity in silicon since other p-type impurities have limitations as follows :
22
Gallium has relatively large diffusion coefficient in SiO2, and the usual oxide window-
opening technique for locating diffusion would be inoperative.
Indium is of little interest because of its high acceptor level of 0.16 eV, compared with 0.01
eV for boron, which indicates that not all such acceptors would be ionized at room
temperature to produce a hole. Aluminium reacts strongly with any oxygen that is present in
the silicon lattice.
The choice of a particular n-type dopant is not so limited as for p-type materials. The n-type impurities,
such as phosphorus, antimony and arsenic, can be used at different stages of IC processing. The
diffusion constant of phosphorus is much greater than for Sb and As, being comparable to that for
boron, which leads to economies resulting from shorter diffusion times.
Dopants in VLSI Technology. The common dopants in VLSI circuit fabrication are boron,
phosphorus, and arsenic. Phosphorus is useful not only as an emitter and base dopant, but also far
gettering fast-diffusing metallic contaminants, such as Cu and Au, which cause junction leakage
current problems. Thus, phosphorus is indispensable in VLSI technology. However, npn transistors
made with arsenic-diffused emitters have better low-current gain characteristics and better control of
narrow base widths than those made with phosphorus diffused emitters. Therefore, in VLSI, the use
of phosphorus as an active dopant in small, shallow junctions and low-temperature processing will be
limited to its use as the base dopant of pnp device and as a gettering agent. Arsenic is the most
frequently used dopant for the source and drain regions in n-channel MOSFETs. In the following
section, now, we will discuss some typical diffusion system. The dopant source material may be
solid, liquid or gaseous.
DIFFUSION SYSTEMS
Impurities are diffused from their compound sources as mentioned above. The method of impurity
delivery to wafer is determined by the nature of impurity source. Two-step diffusion is widely used
technique. Using this technique, the impurity concentration and profiles can be carefully controlled.
The type of impurity distribution (erfc or Gaussian) is determined by the choice of operating
conditions. The two-step diffusion consists of a deposition step and drive-in step. In the former step, a
constant source diffusion is carried out for a short time, usually at a relatively low temperatures, say,
1000°C. In the later step, the impurity supply is shutoff and the existing dopant is allowed to diffuse
into the body of the semiconductor, which is now held at a different temperature, say 1200°C, in an
oxidizing atmosphere. The oxide layer, which forms on the surface of the wafer during this step,
prevents further impurities from entering, or those already deposited, from diffusing out. The final
impurity profile is a function of diffusion conditions, such as temperature, time, and diffusion
23
coefficients, for each step.
Diffusion Furnace
For the various types of diffusion (and also oxidation) processes a resistance-heated tube furnace is
usually used. A tube furnace has a long (about 2 to 3 m) hollow opening into which a quartz tube
about 100,150 mm in diameter is placed as shown in Fig.14. The temperature of the furnace is kept
about 1000°C. The temperature within the quartz furnace tube can be controlled very accurately such
that a temperature within 1/2°C of the set-point temperature can be maintained uniformly over a "hot
zone" about 1m in length. This is achieved by three individually controlled adjacent resistance
elements. The silicon wafers to be processed are stacked up vertically into slots in a quartz carrier or
"boat" and inserted into the furnace tube.
Diffusion of p-Type Impurity
Boron is an almost exclusive choice as an acceptor impurity in silicon. It has a moderate diffusion
coefficient, typically of order 10-16m2/sec at 1150°C which is convenient for precisely controlled
diffusion. It has a solid solubility limit of around 5 x 1026 atoms/m3, so that surface concentration can
be widely varied, but most reproducible results are obtained when the concentration is approximately
1024/m3, which is typical for transistor base diffusions.
Boron Diffusion using B2H6 (Diborane) Source. This is a gaseous source for boron. This can he
directly introduced into the diffusion furnace. A number of other gases are metered into the furnace.
The principal gas flow in the furnace will be nitrogen (N2) which acts as a relatively inert gas and is
used as a carrier gas to be a dilutent for the other more reactive gases. The N2, carrier gas will generally
make up some 90 to 99 percent of the total gas flow. A small amount of oxygen and very small amount
24
of a source of boron will make up the rest of the gas flow. This is shown in Fig.15(a). The following
reactions will be occurring simultaneously at the surface of the silicon wafers :
S i+0 2 Si0 2, (silica glass)
2B2H6+ 302 B2O3 (boron glass) +6H2
This process is the chemical vapour deposition (CVD) of a glassy layer on the silicon surface which is a
mixture of silica glass (SiO2) and boron glass (B203) is called borosilica glass (BSG). The BSG glassy
layer, shown in Fig. 16, is a viscous liquid at the diffusion temperatures and the boron atoms can move
around relatively easily. Furthermore, the boron concentration in the BSG is such that the silicon
surface will be saturated with boron at the solid solubility limit throughout the time of the diffusion
process as long as BSG remains present. This is a constant source (erfc) diffusion. It is often called a
deposition diffusion. This diffusion step is referred as predeposition step in which the dopant atoms
deposit into the surface regions (say 0.3 μm depth) of the silicon wafers. The BSG is preferable
because it protects the silicon atoms from pitting or evaporating and acts as a "getter" for undesirable
impurities in the silicon. It is etched off before next diffusion as discussed below.
The predeposition step, is followed by a second diffusion process in which the external dopant source
(BSG) is removed such that no additional dopants enter the silicon. During this diffusion process the
dopants that are already in the silicon move further in and are thus redistributed. The junction depth
increases, and at the same time the surface concentration decreases. This type of diffusion is called
drive-in, or redistribution, or limited-source (Gaussian diffusion). The impurity profile for such type of
diffusion is already discussed.
The two-step diffusion combination of deposition diffusion (predeposition step) followed by a drive-in
diffusion is often used to produce the base region of transistors.
Boron Diffusion using BBr3 (Boron Tribromide) Source. This is a liquid source of boron. In this
case a controlled flow of carrier gas (N2) is bubbled through boron tribromido, as shown in Fig. 15 (b),
which with oxygen again produces boron trioxide (BSG) at the surface of the wafers as per following
reaction : 4BBr3+302 B2O 3+2Br2 Thereafter the reaction is as discussed above.
Diffusion of n-Type Impurity
For phosphorus diffusion such compounds as PH3 (phosphine) and POCl3 (phosphorus oxychloride)
can be used. In the case of a diffusion using POC13 the reactions occurring at the silicon wafer
surfaces will be: S i+0 2 SiO2 (silica glass)
4 POCl3 + 3 0 2 2P205 + 6Cl2(Phosphorus glass)
This will result in the production of a glassy layer on the silicon wafers that is a mixture of phosphorus
25
glass and silica glass called phosphorosilicaglass (PSG), which is a viscous liquid at the diffusion
temperatures. The mobility of the phosphorus atoms in this glassy layer and the phosphorus
concentration is such that the phosphorus concentration at the silicon surface will be maintained at the
solid solubility limit throughout the time of the diffusion process (similar processes occur with other
dopants, such as the case of arsenic, in which arsenosilica glass is formed on the silicon surface).The
rest of the process for phosphorus diffusion is similar to boron diffusion, i.e., after predeposition step,
drive-in diffusion is carried out. P205 is a solid source for phosphorus impurity and can be used in
place of POCl3. However, POCl3 offers certain advantages over P2O5. Such as, easier source
handling, simple furnace requirements, similar glassware for low and high surface
concentrations and better control of impurity density from wafer to wafer and from run to run.
The phosphine as a gaseous source for phosphorus can be used. But it is toxic and explosive, thus,
needs some care in handling.
Other common n-type dopants are antimony and arsenic. These dopants have low diffusion constants.
Therefore, they are useful materials for the earlier diffusion stages such as for n+ buried layers, since
once introduced they do not migrate during subsequent diffusion processes. Antimony is sometimes
preferred because it is less toxic but arsenic has a higher solid solubility limit and can provide bigger
surface concentrations of dopants.
Interstitial Dopants. Gold diffuses into silicon as an interstitial dopant. As we know, gold diffuses
very rapidly, it is often the last wafer processing step and takes place at a relatively reduced
temperature. Gold diffusion is required in silicon circuits which should operate at high speed. Gold
atoms enhance the recombination rate and so increase the switching speed. Because of the difficulty
in controlling the gold impurity profile, it is usual to coat the back of the entire wafer, using vacuum
evaporation technique, and to diffuse the impurity throughout the whole wafer to a uniform level.
Characterization of Diffused Layers
The diffused layers are characterized by two principal parameters : sheet resistance,R s, and junction
depth. Rs is expressed in ohms per square. The sheet resistance of thin layers including diffused
layers, can be conveniently measured using a four-point probe apparatus, as shown in Fig. 17. A
fixed, measured current, typically 1 mA is passed between the two outer probes and the voltage, V1,
is measured, using a high-input impedance voltmeter between the two inner probes. Current flow is
restricted to the conductivity type of the substrate. If the conditions are satisfied that the layer
thickness T is small compared to the probe spacing such that T << S, and that the edge of the layer be
relatively remote from the probe array, the sheet resistance will given approximately by Rs =(π /
log2)V/I = 4.5324. V/I
26
As a result of having separate pairs of probes for supplying the current and measuring the voltage drop,
the probe contact resistance will not influence the measurement of sheet resistance. The four point
probe can be used to measure the sheet resistance of various types of diffused layers, epitaxial layers
and that of silicon wafers for the measurement of the resistivity. The sheet resistance values of
diffused layers generally fall in the range from 1ohm/square upto about 1000 ohm/square. The
transistor base diffused layer has a sheet resistance of 200 ohm/square, and the n+ emitter diffused
layer has down the range of around 2 ohm/square.
27
ION IMPLANTATION
Ion implantation is an alternative to deposition diffusion and is used to produce a shallow surface
region of dopant atoms deposited into a silicon wafer. In this process a beam of impurity ions is
accelerated to kinetic energies in the range of several tens of kV and is directed to the surface of the
silicon. As the impurity atoms enter the crystal, they give up their energy to the lattice in collisions
and finally come to rest at some average penetration depth, called the projected range expressed in
μm. Depending on the impurity and its implantation energy, the range in a given semiconductor may
vary from a few hundred angstroms to about 1 μm. Typical distribution of impurity about the
projected range is approximately Gaussian. By performing several implantations at different energies,
it is possible to synthesize a desired impurity distribution, uniformly doped region.
Ion Implantation System
A typical ion implantation system is shown in Fig. 18.
A gas containing the desired impurity is ionized within the ion source. The ions are generated and
repelled from their source in a diverging beam that is focused before it passes through a mass
28
separator that directs only the ions of the desired speed through a narrow aperture. A second lens
focuses this resolved beam which then passes through an accelerator that brings the ions to their
required energy before they strike the target and become implanted in the exposed areas of the silicon
wafers. The accelerating voltages may be from 20 kV to as much as 250 kV. In some ion implanters,
the mass separation occurs after the ions are accelerated to high energy. Because the ion beam is small,
means are provided for scanning it uniformly across the wafers. For this purpose the focused ion beam
is scanned electro statically over the surface of the wafer in the target chamber. Repetitive scanning in
a raster pattern provides exception uniform doping of the wafer surface. The target chamber commonly
includes automatic wafer handling facilities to speed up the process of implanting many wafers per
hour.
Annealing after Implantation.
After the ions have been implanted they are lodged principally in interstitial positions in the silicon
crystal structure, and the surface region into which the implantation has taken place will be heavily
damaged by the impact of the high energy ions. The disarray of silicon atoms in the surface region is
often to the extent that this region is no longer crystalline in structure but, rather, amorphous. To
restore this surface region back to a well ordered crystalline state and to allow the implanted ions to go
into substitutional sites in the crystal structure, the wafer must be subjected to an annealing process.
The annealing process usually involves the heating of the wafers to some elevated temperature, often
in the range of 1000°C for a suitable length of time such as 30 minutes. Laser beam and electron
beam annealing are also employed. In such annealing techniques only the surface region of the wafer
is heated and recrystallized. An ion implantation process is often followed by a conventional type
drive-in diffusion, in which case the annealing process will occur as part of the drive-in diffusion. Ion
implantation is a substantially more expensive process than conventional deposition diffusion, both in
terms of the cost of the equipment and the throughput.
High-Current High-Energy Implantation Machines
The ion-implantation apparatus, discussed above, has limits to energy range. The minimum
implantation energy is usually set by the extraction voltage, i.e., the voltage causing the ions to move
out of the ion source into the mass separator. This voltage (which is typically 20 KeV) cannot be
reduced too far without drastically reducing beam current. The maximum implantation energy is set by
the design of the high voltage equipment. The only way to circumvent this is to implant multiply
charged ions. For example, instead of implanting B+(boron ion), we can implant B++ . The B++ion would
receive twice the energy of B+ from the same accelerating potential, effectively doubling the energy of
29
the machines. The price paid is a reduced beam current since the number of B++ ions in the source
plasma is much smaller.
It is advantageous to increase beam current since it improves implanter throughput by reducing the
time for each implantation step. High-current machines can deliver at least 5 mA ion-beam currents, so
that 150 mm wafers can be given a dose of 1015 ions/cm2 in only 6 seconds per wafer [A medium-
energy ion implanter consuming 45 kW of power can process 200 wafers (100 mm diameter) with a
dose of 1015 ions/cm2 ]High beam currents are obtained by using multiple extraction electrodes and
higher voltages. To get a final beam of suitable energy a combination of acceleration and deceleration
modes of operation is used. The electrostatic scanning is not suitable for high beam currents as it
disrupts space charge neutrality and leads to beam "blow-up". Therefore a mechanical scanning system
is usually used. In this case, the wafer is scanned past a stationary beam. This method has the added
advantage of keeping the same beam angle across the whole wafer, whereas an electrostatic system can
vary by ± 2° for 100 mm wafers. However, mechanical scanning puts new requirements on the wafer
holder.
High energy implantation, at MeV energies, makes possible several new processing techniques
required for VLSI. For example, buried conductors are very useful in VLSI CMOS circuits. In such
circuit fabrication high substrate doping is needed to lower voltage drop from substrate currents and so
prevent latch up, and at the same time low substrate doping is needed to minimize junction
capacitance. High energy ion implantation offers better solution for such fabrication problem.
Buried insulator is another example where high-energy implantation is required. Buried insulators are
employed in VLSI fabrication, since they offer a compact way to isolate devices from each other and
to reduce parasitic capacitance. The high-energy implantation permits formation of buried insulators
by implantation of oxygen or nitrogen as an alternative to the epitaxial growth of silicon on sapphire
(SOS).
Properties of Ion Implantation
The depth of penetration of any particular type of ion will increase with increasing accelerating
voltage. The penetration depth will generally be in the range of .1 to 1.0 μm. Table below shows
various projected ranges, Rp, for various typical accelerating voltages for boron and phosphorus ions
in silicon.
Table 1. Projected Ranges(Rp)for Boron and (Rn) for Phosphorus Ions in Silicon
Energy (k V) Rp of boron (μm) R n o f p h o s p h o r o u s (μm)
30
20 0.067 0.026
100 0.30 0.123
200 0.52 0.254
300 0.70 0.386
Impurity Distribution of Implanted Ions.
Fig 19 Ion Implantation profile
The distribution of the implanted ions as a function of distance ,x from the silicon surface will be a
Gaussian distribution, given by
N (x) = Np exp ( - (x- Rp) 2 /2∆ Rp2)
where x = distance into substrate from surface
Rp = projected range
∆ Rp = straggle (standard deviation) of the projected range
Np = peak concentration of implanted ions.
An ion implantation impurity profile is shown in Fig.19. The peak implanted ion concentration is
related to the implantat ion dosage Q by Np= Q/ √2π∆ Rp…………………..(14)
The implantation dosage Q is the number of implanted ions per unit of surface area as given by such
units as ions/cm2. The ion density drops off rapidly from the peak value with distance as measured
from Rp in either direction. Note that the Gaussian implanted ion profile will be truncated at x = 0
Advantages of Ion Implantation.
(i) Ion implantation provides much more precise control over the density of dopants (Q)
deposited into the wafer, and hence the sheet resistance. This is possible because
both the accelerating voltage and the ion beam current are electrically controlled
outside of the apparatus in which the implants occur.
(ii) Very low dosage, low energy implantations are also used for the adjustment of the
31
threshold voltage of MOSFETs and other applications.
(iii) It can be done at relatively low temperatures, this means that doped layers can be
implanted without disturbing previously diffused regions. This means a lesser
tendency for lateral spreading.
(iv) A precise quantity of impurity can be introduced. Since the beam current can be
measured accurately during implantation
This control over doping level, along with the uniformity of the implant over the wafer surface, make
ion implantation attractive for the IC fabrication, since this causes significant improvement in the
quality of an IC. Due to precise control over doping concentration, it is possible to have very low
values of dosage Q (< 1014cm-3), so that very large values of Sheet resistance (>1000ohm/square) can
be obtained. These high sheet resistance values are useful for obtaining large value resistors (≥50KΩ)
for ICs.
Importance of Ion Implantation for VLSI Technology.
Ion implantation is a very popular process for VLSI because it provides more precise control of
dopants (as compared to diffusion) from 1011 atoms/ cm2 to greater than 1016 atoms/cm2. With the
reduction of device sizes to the submicron range, the electrical activation of ion-implanted species
relies on a rapid thermal annealing technique, resulting in as little movement of impurity atoms as
possible. Thus, diffusion process has become less important than methods for introducing impurity
atoms into silicon for forming very shallow junctions, an important feature of VLSI circuits. Ion
implantation permits introduction of the dopant in silicon that is controllable, reproducible, and free
from undesirable side effects. Its attributes of controllability and reproducibility make it a very
versatile tool, able to follow the trends to finer-scale devices.
THERMAL OXIDATION
Oxidation is the process of growing Silicon dioxide layer of 0.02 to 2 μm thickness over the surface
of Si wafer by exposing the wafer to an Oxygen atmosphere at about 1000°C to prevent the N type
epitaxial layer from getting contaminated by the surrounding atmosphere. Oxidation furnace is used
for this purpose. Thickness of oxide layer depends on temperature of the furnace, the length of time
that wafers are in it and flow rate of oxygen. The rate of oxidation can be significantly increased by
adding water vapour to the oxygen supply to the oxidizing furnace.
Utility of Thermal Oxidation
The function of a layer of silicon dioxide (SiO2) on a chip is multipurpose. SiO2 plays an important
role in IC technology because no other semiconductor material has a native oxide which is able to
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achieve all the properties of SiO2. The role of SiO2 in IC fabrication is as below :
1. It acts as a diffusion mask permitting selective diffusions into silicon wafer through the
window etched into oxide.
2. It is used for surface passivation which is nothing but creating protective SiO2 layer on the
wafer surface. It protects the junction from moisture and other atmospheric contaminants.
3. It serves as an insulator on the water surface. Its high relative dielectric constant, 3.9, which
enables metal line to pass over the active silicon regions.
4. SiO2 acts as the active gate electrode, in MOS device structure.
5. It is used to isolate one device from another (dielectric isolation as opposed to junction
isolation).
6. It provides electrical isolation of multilevel metallization used in VLSI.
Growth and Properties of Oxide Layers on Silicon
Silicon dioxide (silica) layer is formed on the surface of a silicon wafer by thermal oxidation at high
temperatures in a stream of oxygen in an oxidation furnace similar to diffusion furnace.
Si + 02 SiO2 (solid)
Si +2H2O S i O 2 +2H2
The time and temperature required to produce a particular layer thickness are obtained from
empirically determined design curves, of the type shown in Fig. 20 corresponding to dry oxygen
atmosphere and Fig. 21 corresponding to steam atmosphere. Layer thickness in the range 0.1 to 5
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μm are commonly produced at a temperatures between 1000 and 1200 °C. A typical schedule might
be to bubble oxygen through water into a furnace at 1100°C, to give an oxide growth rate of around
0.5 μm per hour. The minimum thickness of oxide required for the complete masking of a particular
dopant depends on the dopant and the diffusion parameters, e.g., time and temperature.
Growth Rate of Silicon Oxide Layer
The initial growth of the oxide is limited by the rate at which the chemical reaction takes place.
After the first 100 to 300Å of oxide has been produced, the growth rate of the oxide layer will be
limited principally by the rate of diffusion of the oxidant ( 0 2 or H20) through the oxide layer, as
shown in Fig. 22(a).The rate of diffusion of 02 or H2O through the oxide layer will be inversely
proportional to the thickness of the layer, so that we will have that
dx /dt = C/ x
where x is the oxide thickness and C is a constant of proportionality. Rearranging and integrating
this both sides yields x2/2 =Ct or x =√2Ct. We see that after an initial reaction-rate limited
linear growth phase (tox α time), the oxide growth will become diffusion-rate limited with the oxide
thickness increasing as the square root of the growth time. Fig. 22 (b). The rate of oxide growth
using H2O as the oxidant will be about four times faster than the rate obtained with 02. This is due to
the fact that the H2O molecule is about one-half the size of the O2, molecule, so that the rate of
diffusion of H2O through the SiO2layer will be much greater than the 02 diffusion rate.
Although the oxide growth rate with H2O is much faster than with 02, the "dry" (02) oxide will be a
slightly denser oxide with a higher dielectric strength than the "wet" (H20) oxide. In many cases a "dry-
wet-dry" oxidation process is used, starting off the initial oxide growth using 02. This is followed by a
H2O oxide growth phase to produce the bulk of the oxide thickness, and then completed by a final
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"dry" oxidation. This will produce a composite oxide layer as shown in Fig. 23 with the denser "dry"
oxide regions being adjacent to the silicon surface and serving as a protective cap on top, and the less
dense "wet" oxide being sandwiched in between. It should be noted that in the themal growth process of
an oxide layer some silicon from the substrate is consumed. If the resulting thickness of the SiO2layer is
designated as tox, the thickness of the silicon consumed will be 0.44 tox
Oxide Charges
The interface between silicon and silicon dioxide contains a transition region. Various charges are
associated with the oxidized silicon, some of which are related to the transition region. A charge at the
interface can induce a charge of the opposite polarity in the underlying silicon, thereby affecting the
ideal characteristics of the MOS device. This results in both yield and reliability problems. Fig. 24 shows
general types of charges.
Interface-trapped charges. These charges at Si-SiO2 are thought to result from several sources,
including structural defects related to the oxidation process, metallic impurities, or bond breaking
processes. The density of these charges is usually expressed in terms of unit area and energy in the
silicon bandgap (number/cm2-eV). Values of 1010/cm2-eV and lower have been observed.
Fixed oxide charge. This charge (usually positive) is located in the oxide within approximately 30 Å
of the Si-SiO2 interface. Fixed oxide charge cannot be charged or discharged. Its density ranges from
1010/cm2 to 1012/cm2. Its values for<100> oriented silicon are less than those for <111> silicon. This
difference is related to the number of available bonds per unit area of silicon surface. From a
processing point of view, fixed oxide charge is determined by both temperature and ambient
conditions.
Mobile ionic charge. This is attributed to alkali ions such as sodium, potassium, and lithium in the
oxides as well as to negative ions and heavy metals. The alkali ions are mobile even at mom
temperature, when electric fields are present. Densities range from 1010/cm2to 1012/cm2 or higher and
are related to processing materials, chemicals, ambient, or handling.
Oxide trapped charge. This charge may be positive or negative, due to holes or electrons trapped in
the bulk of the oxide. This charge, associated with defects in the SiO2, may result from ionizing
radiation, avalanche injection, or high currents in the oxide. Densities range from less than 109/cm2 to
1013/cm2.
The effects of various charges can be minimized as follows. The interfaced-trapped charge can be
neutralized by a low temperature hydrogen annealing (450°C). Fixed oxide charge is minimized by
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inert ambient annealing. The mobile ionic charge can be minimized by cleaning the furnace tube in a
chlorine ambient, gettering with phosphosilicate glass, and using masking layers such as silicon
nitride. The oxide-trapped charge can be annealed out by low-temperature treatment.
Effect of Impurities on the Oxidation Rate
The following impurities affect the oxidation rate (i) water (ii) sodium (iii) group III and V elements,
and (iv) halogen. In addition damage to the silicon also affects oxidation rate.
As we discussed that wet oxidation occurs at a substantially greater rate then dry oxygen, any
unintentional moisture accelerates the dry oxidation. High concentrations of sodium influence the
oxidation rate by changing the bond structure in the oxide, thereby enhancing the diffusion and
concentration of the oxygen molecules in the oxide. During thermal oxidation process, an interface is
formed, which separates the silicon from silicon dioxide. As oxidation proceeds, this interface
advances into the silicon. A doping impurity, which is initially present in the silicon, will redistribute at
the interface until its chemical potential is the same on each side of the interface. This redistribution
may result in an abrupt change in impurity concentration across the interface. The ratio of the
equilibrium concentration of the impurity, i.e., dopant in silicon to that in SiO2 at the interface is called
the equilibrium segregation coefficient. The redistribution of the dopants (group III or V elements) at
the interface influences the oxidation behaviour. If the dopant segregates into the oxide and remains
there (such as Boron, in an oxidizing ambient), the bond structure in the silica weakens. This weakened
structure permits an increased incorporation and diffusivity of the oxidizing species through the oxide,
36
thus enhancing the oxidation rate. Impurities that segregate into the oxide but then diffuse rapidly through
it (such as aluminium, gallium, and indium) have no effect on the oxidation kinetics. Phosphorus
impurity shows opposite effect to that of boron, i.e., impurity segregation occurs in silicon rather than
SiO2. The same is true for As and Sb dopants.
Halogen (such as chlorine) impurities are intentionally introduced into the oxidation ambient to improve
both the oxide and the underlying silicon properties. Oxide improvement occurs because there is a
reduction in sodium ion contamination, increase in oxide breakdown strength, and a reduction in
interface trap density. Traps are energy levels in the forbidden energy gap which are associated with
defects in the silicon.
Thermal Oxidation Practice
The oxidation practice employed depends upon the thickness and oxide properties required. For oxide
thickness more than 0.5 μm, steam is used (~1 atm or an elevated pressure). Higher pressure allows
thick oxide growth to be achieved at moderate temperatures in reasonable amounts of time. One
atmosphere oxide growth, the most commonly used technique, is typically carried out in a horizontal
diffusion tube, although vertical diffusion furnaces are being used more frequently. In the case of the
horizontal furnace, the wafers are held vertically in a slotted paddle (boat), which is normally loaded
using cassette-to-cassette equipment. Typical oxidation temperatures range from 700 to 1200°C
and could be held to within ±1°C to ensure uniformity. In a standard procedure the wafers are
chemically cleaned, dried, loaded onto the paddle, and automatically inserted into the 700 to 900°C
furnace, which is then ramped up to oxidation temperature. Ramping is used to prevent wafer warpage.
Following oxidation, the furnace is ramped down and the wafers are removed. Eliminating particles
during oxidation is necessary to grow high-quality, reproducible oxides. Innovative designs now use a
cantilevered arrangement in which the paddle is inserted into the oxidation tube in a contactless
manner and then lowered onto the tube.
Before thermal oxidation process, the wafers must be cleaned to eliminate both organic and inorganic
contamination arising from previous processing steps and handling such contaminations, if not
removed, can degrade the electrical characteristics of the devices and can contribute to reliability
problems. A common cleaning procedure uses a H20—H202—NH4OH mixture to remove organic
contamination by the solvating action of the ammonium hydroxide and the oxidizing effect of the
peroxide. To remove heavy metals a H2O—H2O2–HCl solution is commonly used. Modern diffusion
(oxidation) furnaces are microprocessor controlled to provide repeatable sequencing, temperature
control, and gas flow control. The entire procedure, from boat loading to boat withdrawal, is
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programmed.
High Pressure Oxidation
The rate of diffusion of the oxidant molecules through an oxide layer is proportional to the ambient
pressure. For example, at a pressure of 10 atm the diffusion rate will be increased by a factor of 10
and the corresponding oxidation time can be reduced by nearly the same factor. Alternatively, the
oxidation can be done for the same length of time, but the temperature required will be substantially
lower. For example, a steam (H20) oxidation at 1200°C and a 1.0 atm ambient pressure will produce
an oxide layer that is 0.6 μm thick, for an oxidation time of 36 minutes. The same thickness of oxide
can be produced in the same period of time at a temperature of only 920°C, if the ambient pressure is
increased to 10 atm. As a second example, a 10 hour steam oxidation at 920°C and at 1.0 atm ambient
pressure will result in 0.2 μm -thick oxide. If the ambient pressure is increased to 10 atm, the
temperature can be reduced to only 795°C for the same oxide thickness produced in the same period
of time. Principal benefit of high-pressure oxidation processing is lower-temperature processing. The
lower processing temperature reduces the formation of crystalline defects and produces less
effect on previous diffusions and other processes. The shorter oxidation time is also
advantageous in increasing the system throughput. The major limitation of this process is the
high initial cost of the system.
The anodic plasma-oxidation which offers the possibility of growing high quality oxides at
temperatures even lower than those achieved with the high pressure technique. This process has all
the advantages associated with low temperature processing. Anodic plasma oxidation can grow
reasonably thick oxides of the order of 1 μm at low temperatures (<600°C) at growth rates upto about
1 μm/hr. Plasma oxidation is a low-temperature vacuum process, usually carried out in a pure oxygen
discharge.
Oxide Masking and Oxide Passivation
Oxide Masking. Oxide layer is used to mask an underlying silicon surface against a diffusion (or ion
implantation) process. The oxide layer is patterned by the photltithographic process to produce regions
where there are opening or "windows" where the oxide has been removed to expose the underlying
silicon. Then these exposed silicon regions are subjected to the diffusion (or implantation) of dopants,
whereas the unexposed silicon regions will be protected. The pattern of dopant that will be deposited
into the silicon will thus be a replication of the pattern of opening in the oxide layer. The replication
is a key factor in the production of tiny electronic components. The thickness of oxide needed for
diffusion masking is a function of the type of diffusant and the diffusion time and temperature
conditions. In particular, an oxide thickness of some 5000 Å will be sufficient to mask against almost
38
all diffusions. This oxide thickness will also be sufficient to block almost all but the highest energy
ion implantation.
Oxide Passivation. The surface passivation is nothing but creating protective SiO2 layer on the wafer
surface. Fig. 25 shows a cross-sectional view of a pn junction produced by diffusion through an oxide
window. The junction depth in the vertical direction is indicated as x j. The distance from the edge of
the oxide window to the junction in the lateral direction underneath the oxide is indicated as yj. The
relationship between yj and xj is that yj = 0.8 xj so that the curvature of the junction in the regions
underneath the edge of the oxide window is nearly that of a quarter circle with a radius of curvature
that is nearly equal to the junction depth. In Fig. 25 we note that the junction intersects the silicon
surface well underneath the protective thermally grown oxide layer. This oxide layer protects the
junction against various environmental effects, and is therefore called a passivated junction. We also
note that the locus of intersection of the junction depth with the silicon surface is entirely within a
single geometric plane, and for that reason this type of junction is called a planer junction. Note that
the junction itself is not flat or plane, but rather there is a curvature of the junction in the region
underneath the edges of the oxide window. This junction curvature will result in an increase in the
electric field intensity in these regions which will cause the break down voltage of the junction to be
lower than that of a corresponding plane junction with the same doping levels.
LITHOGRAPHY
The lithography technique was first used in the late eighteenth century by people interested in art. A
lithograph is a less expensive picture made from a flat, specially prepared stone or metal plate and the
lithography is art of making lithographs. Therefore, lithography for IC manufacturing is analogous to
39
the lithography of the art world. The selective removal of the oxide in the desired area is performed by
lithographic process. In this process the exposing radiation, such as ultraviolet (UV) light in case of
photolithography, is transmitted through the "clear" parts of the mask. The circuit pattern of opaque
chromium blocks some of the radiation. This type of chromium/glass mask is used with UV light. Other
types of exposing radiations are electrons, X-rays, or ions. Thus, for IC manufacturing we have
following types of lithography :
Lithography can be divided into
1. Photo Lithography.
2. Fine Line Lithography. This is further classified as
i. Electron-beam lithography
ii. X-ray lithography
iii. Ion-beam lithography
In IC fabrication number of masks are employed. Except for the first mask, every mask must be aligned
to the pattern produced by the previous mask. This is done using mask aligner. The mask aligner
may be contact type or proximity type or projection type. Accordingly we have three types of
printing :
(i) Contact printing, (ii) Proximity printing and (iii) Projection printing.
Photolithographic Process
Photolithography or optical lithography is a kind of lithography used for selective removal of the oxide
in the desired area. Thus, the areas over which diffusions are effective are defined by the oxide layer
(which inhibits diffusion) with windows cut in it, through which diffusion can take place. The
windows are produced by the photolithographic process. This process is the means by which
microscopically small circuit and devices can be produced on silicon wafers, resulting in as many as
10000 transistors on a 1 cm x 1 cm chip.
Steps involved in Photolithographic Process are as follows
(i) Photoresist Application (Spinning). A drop of light sensitive liquid called photoresist is applied
to the centre of the oxidized silicon wafer that is held down by a vacuum chuck. The wafer is then
accelerated rapidly to a rotational velocity in the range 3000 to 7000 RPM for some 30 to 60 seconds.
This action spreads the solution in a thin, nearly uniform coat and spins off the excess liquid. The
thickness of the coat so obtained is in the range 5000 to 10000 Å, as shown in Fig. 26(a). The
thickness of the photoresist layer will be approximately inversely proportional to the square root of
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the rotational velocity. Sometimes prior to the application of the photoresist the silicon wafers are
given a "bake-out" at a temperature of at least 100°C to drive off moisture from the wafer surfaces so as
to obtain better adhesion of the photoresist. Typical photoresist used is Kodak Thin Film Resist
(KTFR).
(ii) Prebake. The silicon wafers coated with photoresist are now put into an oven at about 80°C for
about 30 to 60 min. to drive off solvents in the photoresist and to harden it into a semisolid film.
(iii) Alignment and Exposure. The coated wafer, as above, is now placed in an apparatus called a
mask aligner in very close proximity (about 25 to 125 μm) to a photo mask. The relative positions of
the wafer and the photomasks are adjusted such that the photomask is correctly lined up with reference
marks or a pre-existing pattern on the wafer. The photomask is a glass plate, typically about 125 mm
square and about 2 mm thick. The photomask has a photographic emulsion or thin film metal
(generally chromium) pattern on one side. The pattern has clear and opaque areas. The alignment of
the photomask to the wafer is often required to be accurate to within less than 1 μm, and in some cases
to within 0.5 μm. After proper alignment has been achieved, the wafer is brought into direct contact
with the photomask. A highly collimated ultraviolet (UV) light is then turned on and the areas of the
silicon wafer that are not covered by the opaque areas of the photomask are exposed to ultraviolet
radiation, as shown in Fig.26 (b). The exposure time is generally in the range 3 to 10sec. and is
carefully controlled such that the total UV radiation dosage in watt-seconds or joules is of the
required amount
(iv) Development. In the present description negative photoresist is used in which the areas of the
photoresist that are exposed to the ultraviolet radiation become polymerized. The polymerization
process increases the length of the organic chain molecules that make up the photoresist. This makes
the resist tougher and makes it essentially insoluble in the developer solution. The resisting
photoresist pattern after the development process will therefore be a replication of the photomask
pattern, with the clear areas on the photomask corresponding to the areas where the photoresist
remains on the wafers, as shown in Fig.26(c). An opposite type of process occurs with positive
photoresist. Exposure to UV radiation results in deploymerization of the photoresist. This makes
these exposed areas of the photoresist readily soluble in the developer solution, whereas the
unexposed areas are essentially insoluble. The developer solution will thus remove the exposed or
depolymerized regions of the photoresist, whereas the unexposed areas will remain on the wafer.
Thus again there is a replication of the photomask pattern, but this time the clear areas of the
photomask produce the areas on the wafer from which the photoresist has been removed.
(v) Postbake. After development and rinsing the wafers are usually given a postbake in an oven at
41
a temperature of about 150°C for about 30 to 60 min. to toughen further the remaining resist on the
wafer. This is to make it adhere better to the wafer and to make it more resistant to the hydrofluoric
acid (HF) solution used for etching of the silicon dioxide.
(vi) Oxide Etching. The remaining resist is hardened and acts as a convenient mask through which
the oxide layer can be etched away to expose areas of semiconductor underneath. These exposed
areas are ready for impurity diffusion. For etching of oxide, the wafers are immersed in or sprayed
with a hydrofluoric (HF) acid solution. This solution is usually a diluted solution of typically 10 : 1,
H2O : HF, or more often a 10 : 1 NH4F (ammonium fluoride) : HF solution. The HF solutions will
etch the SiO2 but will not attack the underlying silicon, nor will it attack the photoresist layer to any
appreciable extent. The wafers are exposed to the etching solution long enough to remove the SiO 2
completely in the areas of the wafer that are not covered by the photoresist, as shown in Fig. 26(d).
For the 10:1 buffered HF solution (NH4F : HF) the SiO2 etching rate is about 1000 A/min. at 25°C so
that only about 5 min. will be required to remove a typical oxide layer of 5000 Å. thickness. The
result of the oxide etching process will be a pattern of openings or windows in the SiO2layerthat will
replicate the photoresist pattern, and will therefore be a replication of the pattern on the photomask.
The duration of oxide etching should be carefully controlled so that all of the oxide present only in the
photoresist window is removed. If etching time is excessively prolonged, it will result in more
undercutting underneath the photoresist and widening of the oxide opening beyond what is desired.
The above oxide etching process is termed wet etching process since the chemical reagents used are
in liquid form. A newer process for oxide etching is a dry etching process called plasma etching.
Another dry etching process is ion milling.
(vi) Photoresist Stripping. Following oxide etching, the remaining resist is finally removed or stripped
off with a mixture of sulphuric acid and hydrogen peroxide and with the help of abrasion process.
Finally a step of washing and drying completes the required window in the oxide layer. Fig. 26(e)
shows the silicon wafer ready for next diffusion. Negative photoresists, as above, are more difficult to
remove. Positive photoresists can usually be easily removed in organic solvents such as acetone.
The photolithography may employ contact, proximity, or projection printing. For IC production the
line width limit of photolithography lies near 0.4 μm, although 0.2 μm features may be printed under
carefully controlled conditions. At present, the photolithography occupies the primary position
among various lithographic techniques.
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Photoresists
One of the major factors in providing increasingly complex devices has been improvement in
photolithographic art. A large part of this improvement has been due to high quality photoresist,
materials as improved techniques of coating, baking, exposing and developing photoresists.
The principal constituents of a photo resist solution are a polymer, a sensitizer and a suitable
solvent system. Polymers have properties of excellent film forming and coating. Polymers generally
used are polyvinyl cinnamate, partially cyclized isoprene family and other types are phenol
formaldehyde, Novolac etc. When photoresist is exposed to light, sensitizer absorbs energy and
initiates chemical changes in the resist. The sensitizers are chromophoric organic molecules. They
greatly enhance cross linking of the photoresist. Cross linking of polymer or long chain formation of
considerable number of monomers makes high molecular weight molecules on exposure to light
radiation, termed as photo-polymerization. Typical sensitizers are carbonyl compounds. Benzoin,
Benzoyl peroxide, Benzoyl disulphide, nitrogen compounds and halogen compounds. The
solvents used to keep the polymers in solution are mixture of organic liquids. They include aliphetic
esters such as butyl acetate and cellosolve acetate, aromatic hydrocarbons like xylene and
Ethylbenzene, chlorinated hydrocarbons like chlorobenzene and methylene chloride and ketones such
as cyclohexanone. The same solvents are used as thinners and developers.
Characteristics of Good Photoresist. To achieve faithful registration of the mask geometry over the
substrate surface, the resist should satisfy following conditions:
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(i) Uniform film formation
(ii) Good adhesion to the substrate
(iii) Resolution and
(iv) Resistance to wet and dry etch processes.
Types of Photoresist. Two types of photoresist exist : negative photoresist and positive
photoresist. According to the changes that take place, photoresists are termed negative or positive.
Materials which are rendered less soluble in a developer solution by illumination, yield a negative
pattern of the mask and are called negative photoresists. Conversely, positive photoresists become
more soluble when subjected to light and therefore yield a positive image of the mask. The selection of
photoresist depends upon specific requirement resolution and type of surface to be encountered.
Differences in solid content and viscosity determine the flow characteristics and thus the thickness of
coating. The development of modern photoresist originated at Eastman Kodak Research Laboratory.
Now-a-days there are number of manufactures producing photoresists, they are : Eastman Kodak