1. Microprocessors uses___________ type of architecture 2. Microcontroller uses ______________type of architecture 3. Microcontroller uses ______________type of processor 4. Which of the following device can be externally added to the microcontroller. a) RAM b) ROM c) timers d) None of the above 5. Which of the following device is externally connected to the microprocessor a) ALU b) program counter c) timer d) registers 6. In which of the following IC’s, Princeton or Von-Neumann type of architecture is used a) 8085 b) 8086 c) MC6800 d)all of the above 7. Microcontrollers commonly have a) RAM b) ROM c) Processors d) All of the above 8. Related to the microprocessor which statement is true a) microprocessor based system is more flexible in design point of view b) microprocessor have separate memory map for data and code c) fixed amount of RAM & ROM need not be connected externally to the microprocessor d) none of the above Module 1: Introduction to Microcontroller Page 1 of 49
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1. Microprocessors uses___________ type of architecture
2. Microcontroller uses ______________type of architecture
3. Microcontroller uses ______________type of processor
4. Which of the following device can be externally added to the microcontroller. a) RAM b) ROM c) timers d) None of the above
5. Which of the following device is externally connected to the microprocessor
a) ALU b) program counter c) timer d) registers
6. In which of the following IC’s, Princeton or Von-Neumann type of architecture is used a) 8085 b) 8086 c) MC6800 d)all of the above
7. Microcontrollers commonly have
a) RAM b) ROM c) Processors d) All of the above
8. Related to the microprocessor which statement is true a) microprocessor based system is more flexible in design point of view b) microprocessor have separate memory map for data and code c) fixed amount of RAM & ROM need not be connected externally to the microprocessor d) none of the above
Module 1: Introduction to Microcontroller
Page 1 of 49
9. Match the following
a) Intel 8048 i) 8 bit
b) Intel 80C196 ii) 8 bit (Flash memory + ADC)
c) Microchip PIC 16F877 iii) 8 bit (on chip ADC)
d) Motorola 68HC11 iv) 16 bit
10. Digital signal Processors uses which of the following design architecture
a) Hardvard + CISC
b) RISC
c) Von Neumann + CISC
d) Harvard + RISC
11. RAM chips
a) are secondary memory
b) store data indefinitely until erased
c) allow the computer to store data electronically
d) all of the above
12. The attributes volatility, holds data and processing instructions and made up of semiconductor material are of __________________ memory
13. Which is true for a typical RISC architecture
a) complex addressing modes
b) memory to register operations
c) have few CPU registers
d) execute instruction in single cycle
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14. Micro-programmed control unit
a) facilitates random logic, PLA or ROM
b) faster than the hardwired control unit
c) facilitates ease implementation of new instructions
d) all of the above
15. Name the micro computer architecture which uses a separate block of memory to store data and instructions
a) Von Neumann
b) Hardvard
c) RISC
d) CISC
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Lecture 5: Introduction
1. Every register of 8051 has address associated except ____________ register.
2. The stack pointer _____________ on every PUSH instruction and _____________ on every POP instruction.
3. On reset the program counter of 8051 has the address_________________
4. What are the functions of EA, PSEN and ALE signals?
5. 8051 has ___________ bytes of RAM from location ________________.
6. The location of RAM used as scratch pad is _________________.
7. The flag register of 8051 is called _____________
8. _____ and ______ are the registers used to access the ROM data.
9. ________ bit of PSW indicates the sign of a number.
10. DPTR is byte addressable register (True/False).
11. ___________ is the signal used to read the external memory.
12. After RESET the stack pointer hold the address _______of RAM memory
13. The bit address of 5th bit of RAM byte 2C is __________
14. Which of the following statement is false?
a) RST pin is active high
b) For 8051 the EAbar pin must be connected to Vcc
c) ALE is connected to OE pin of ROM containing program code
d) PSEN stands for program store enable
15. In 8051, each machine cycle has ______ clock cycles.
Module 2: Intel 8051 Microcontroller
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16. The process to map the I/O Register as a part of variable RAM area is called
a) data mapped I/O
b) RAM mapped I/O
c) memory mapped I/O
d) variable mapped I/O
17. What is the value of the PSW to select bank 3?
18. RS0 and RS1 are:
a) not a part of the PSW register
b) are the flag bits
c) are bit 3 and 4 respectively in the PSW register
d) are bit 6 and 7 in the PSW which are modified upon arithmetic operations
19. TH0, TL0, TMOD, and A have the addresses
a) 8Ch, 8Ah, 89h and E0h
b) E0h, 8Ch, 8Ah, and 89h
c) 8Ch, E0h, 8Ah, and 89h
d) 8Ch, 8Ah, E0h, and 89h
20. Match the following.
1. Internal RAM memory. a) bit- addressable. 2. SCON. b) 128 bytes. 3. Internal program storage memory. c) byte- addressable.
4. TMOD. d) 4 kbytes a) 1-b 2-c 3-d 4-a b) 1-d 2-a 3-b 4-c c) 1-d 2-c 3-b 4-a d) 1-b 2-a 3-d 4-c
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Lecture 6 & 7: Addressing modes, Port Structure, and External Memory Access
1. Identify the addressing modes of the given instructions:
a) MOV A, R4
b) MOV A,#05H
c) MOV R3,R2
d) MOV A, @R0
e) MOV R3, 0F5H
f) MOV 3, 2
2. Using ____________addressing mode, data can be accessed dynamically
a) direct
b) register indirect
c) indexed
d) register
3. What are the different types of Address decoding Techniques? 4. The addressing mode used in stack instructions is ____________ 5. ________________ addressing mode of 8051 is used in accessing data elements of the
lookup table entries of ROM space of 8051. 6. __ and___ are the registers used in register indirect addressing mode.
7. Which port of 8051 is used to access the upper byte of the address connected to external memory
a) port1 b) port2 c) port3 d)port0
8. Port0 is called the “quasi bidirectional port”. (True/False)
9. All higher address lines are decoded to select the memory or I/O device in absolute decoding. (True/False)
10. ___ and ____ are the port bits used to communicate serially.
11. Maximum external memory that can be interfaced to 8051 is ___________.
12. _______ instruction is normally used with external RAM or I/O address.
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13. ______ instruction is normally used with external ROM.
14. Port pins can be driven by open collector or open drain outputs. (True/False).
15. (a) Port P0 can be used as an output only because it is used as AD0-AD7 in the expanded
mode:
(b) All port bits can be used as input or output in single-chip mode
(c) A port bit can be used as an input after writing 0 at it
(d) Two ports P0 and P2 are the output ports and P1 and P3 are the input ports:
16. ________ & _______ are the port used as address and data line for external memory interface.
17. Maximum data memory that can be interfaced is _____________
18. Reset pin is:
a) active when connected to 1
b) active for a few cycles only
c) active when connected to 0
d) active only on watchdog timer reset
19. Commonly to access the data from the memory
a) EA is connected to VCC for on chip memory and to GND for external memory
b) EA is connected to GND for on chip access and to VCC for external memory
c) EA is the don't care for memory access
d) none of the above
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Lecture 8: Timer and Counters:
1. TMOD and TCON registers are
a) byte addressable and bit addressable respectively
b) byte addressable
c) bit addressable
d) bit and byte addressable respectively
2. The value of TMOD is __________ when the timer 1 operates in mode 2.
3. 8051 timer/counter operates in _____________ modes.
4. Each timer has _____ & _________registers of ____ bit wide.
5. __________ is used to start the timer.
6. The input frequency to the timer circuits is __________ times the crystal frequency.
7. The frequency and time period used by the timer for the crystal frequency of 22 MHz is ____________ and ______________.
8. The Maximum period generated by the timer in mode 2 for a crystal frequency of 11.0592MHz is _____________
9. The instruction to stop the timer is _____________
10. ___________ is the control flag which monitors the timer ON/OFF condition.
11. __________ is the status flag which puts ON/OFF the timer.
12. Maximum value that can be stored in the timer register for mode 2 operation is ____________.
13. If the initial value of TH is 14h and TL is 02Ch, then the count for which the timer will be ON when operating in mode 1 is _______________
14. Obtain the delay generated for the given code if the crystal frequency is 12 MHz.
MOV TMOD, #01H
MOV TL0, #00
MOV TH0, #0EEH
SETB TR0
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15. Analyze the code to find the count value when the TF0 flag will be raised. Assume XTAL = 11.0592MHz.
MOV TMOD, #01H
MOV TL0, #00
MOV TH0, #0EEH.
SETB TR0
16. To generate the delay of 10msec for the crystal frequency of 12 MHz, the value to be loaded in register TH0 and TL0 is ____________ & ___________
17. ___________ is the bit of TMOD set to operate the timer in counter mode.
18. In mode 0 operation of timer the register TL is of ____________ bit wide.
19. In mode 2 operation of timer the count value is loaded in _____________register and ______ register overflows to 00h.
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Lecture 9: Interrupts of 8051
1. The 8051 has ________________ interrupts.
a) INTO b) INT1 c) Timer d) RESET
2. _________ interrupt is of highest priority
a) IE0, TF0, IE1,TF1, Serial
b) IE1, TF0, IE0,TF1, Serial
c) TF0, IE1, IE0, TF1, Serial
d) IE0, TF0, IE1, Serial, TF1
3. ___________ and ___________ are triggered by the external signal.
4. The _________ flag is set, when a ___________________ transition takes place on
INTX pin.
a) IEX, low-to-high
b) IEX, high-to-low
c) ITX, low
d) IEX, high
5. ___________ is the instruction used to return from interrupt service routine.
6. On encountering RETI in ISR, the first step taken by microcontroller is
a) Pop top 2 bytes of stack to get address of next instruction b) Pops bottom 2 bytes of stack to get address of the next instruction c) Pop top 2 bytes of stack to get address of current instruction d) Pops bottom 2 bytes of stack to get address of the current instruction
7. ________ and _________ are the registers associate with interrupt programming.
8. When 8051 is reset and the EA line is LOW, the program counter points to the first program instruction in the:
a) internal code memory
b) internal data memory
c) external code memory
d) external data memory
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9. Registers IP and IE are bit addressable (TRUE/FALSE).
10. The instruction MOV IE,#10010110B enables
a) serial, timer1, EX0
b) serial, timer0, EX1
c) Timer1, timer0, EX0
d) all the interrupts
11. Map the interrupts to their vector address
a) IE0 i) 000B
b) IE1 ii) 0023
c) TF0 iii) 0003
d) TF1 iv) 001B
e) SERIAL v) 0013
12. The instruction which enables all the interrupts is ______________
13. Bytes of memory space assigned to each of the interrupts is ___________
14. Upon reset the address held in the stack pointer is ______________
15. To change level triggered interrupt to edge triggered interrupts modification must be done in which register?
a) PCON
b) TCON
c) TMOD
d) SCON
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Lecture 10: Program Branching Instructions
1. The following instruction is a relative jump instruction: a. AJMP b. JMP c. SJMP d. LJMP
2. The relative address range from the current program counter(PC) of relative jump instructions is:
a. -127 to +128 bytes b. -128 to +127 bytes c. 0 to +128 bytes d. 0 to -127 bytes
3. In the following block of code what is the significance of ‘next’? MOV A,#45h MOV B,#96h ADD A,B JNC next MOV A,R6 next: MOV A,R5 ........
a. ‘next’ is a data variable. b. ‘next’ is a constant. c. ‘next’ is relative address. d. ‘next’ has no significance.
4. While accessing short absolute jump instruction, _____ bits of program counter hold the address within the page.
a. 12 b. 11 c. 10 d. 8
5. Match the following: A B
1) CJNE a) 3-byte instruction 2) JMP @A+DPTR b) carry flag is not affected. 3) SJMP c) re-locatable 4) LCALL d) 2-byte instruction 5) JC e) carry flag is affected
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6. Consider the following block of code: MOV A,#49h MOV R5,#05h back: CPL A.6 CPL A.2 DJNZ R5,back ....... What will be the contents of Accumulator after execution of this block?
a. 49 b. D1 c. CD d. 0D
7. Consider the following code: ORG 0 MOV A,#23h MOV B,#53h CJNE A,B,next MOV R7,#0 next: JC next1 MOV R7,#’G’ SJMP n1 next1: MOV R7,#’S’ n1: NOP END After execution of following block of code, what will be the contents of R7?
a. A b. S c. G d. B
8. Consider the following block of code: ORG 0000h MOV R4,#96h back: MOV R3,#50h back1: CPL A.4 DJNZ R3,back1 DJNZ R4,back END
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How many times the loop will be executed? a. 146 b. 4800 c. 10000 d. 12000
9. Consider the following block of code: MOV A,40h JNB A.7,next MOV R6,#’A’ SJMP next1 next : MOV R6,#’B’ next1: ..... ....... If the content of the memory location 40h is AAh then what will be the content of R6 after execution of this block?
a. AA b. BB c. A d. B
10. Consider the following block of code: MOV 45h,#10 MOV A,R0 JZ next MOV R5,@R0 SJMP next1 next: MOV R5,R0 next1: ..... ....... If the content of R0 is 45h then what are the contents of R5 after execution of this block?
a. 45h b. 10h c. 01h d. 0Ah
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Lecture 11: Serial Communication
1. The timer mode which is also referred to as standard UART mode: a. mode-0 b. mode-1 c. mode-2 d. mode-3
2. Usually the timer configuration used to set the baud rate in serial communication is a. Timer-1 in mode-1 operation b. Timer-1 in mode-2 operation c. Timer-0 in mode-2 operation d. Timer-0 in mode-1 operation
3. Match the following:
Registers Address
a. SCON i. 99h b. PCON ii. 98h c. SBUF iii. 0E0h d. Register-A iv. 87h
4. Choose the odd one among the following:
a. SCON register b. PCON register c. I/O ports(P1,P2,P3) d. TCON register
5. What is the bit time if the baud rate is 4800? a. 0.1041 ms b. 0.2083 ms c. 1.0412 ms d. 2.0833 ms
6. Match the following: (Assume the clock frequency as 11.0592MHz)
Baud Rates Value to be loaded into timer-1
a. 4800 i. 0FDh b. 9600 ii. 0FAh c. 1200 iii. 0F4h d. 2400 iv. 0E8h
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7. Consider the following events: 1) Loading SCON register. 2) TR flag is set. 3) TR flag is cleared. 4) TI flag is monitored. 5) Loading TMOD register. 6) Loading SBUF register.
The correct sequence of events used to transmit a byte serially is:
a. 1,4,5,3,2,6 b. 6,5,1,4,3,2 c. 1,5,3,6,2,4 d. 5,1,2,6,4,3
8. Consider the following block of code: ORG 0000h MOV TMOD,#20h MOV TH1,#-3 MOV SCON,#50h ------------ ------------ END The serial mode used and the baud rate set in above block of code is:
a. Mode-0,2400 b. Mode-1,9600 c. Mode-0,9600 d. Mode-1,2400
9. Consider the following block of code: ORG 0000h MOV TMOD,#20h MOVA,PCON SETB ACC.7 MOV PCON,A MOV TH1,#-3 MOV SCON,#10h ------------ ------------ END
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The serial mode used and the baud rate set in above block of code is: (Assume clock frequency as 11.0592MHz)
a. Mode-0,19200 b. Mode-1,9600 c. Mode-0,9600 d. Mode-1,19200
10. Consider the following 8051 C program: #include <reg51.h> main() { TMOD = 0x20; TH1 = 0xFD; SCON = 0x50; TR1 = 1; for(i=0;i<10;i++) { SBUF = ‘Y’; while(TI == 0); TI = 0; SBUF = ‘E’; while(TI == 0); TI = 0; SBUF = ‘S’; while(TI == 0); TI = 0; } } What is the time required to transmit the data in the above program if the XTAL frequency is 11.0592 MHz.
a. 6.125 ms b. 4.125 ms c. 3.125 ms d. 1.041 ms
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Lecture 12: Serial Communication
1. The serial mode/s which is/are also referred to as Multi-processor mode is/are: a. mode-2 b. mode-3 c. mode-2 and mode-3 d. mode-1 and mode-2
2. Timer-1 can be used in different modes to set the baud rate. - State true or false.
3. The various bits transmitted/received in the Multi-processor mode are: a. 1 start-bit,8 data-bits and 1 stop-bit b. 1 start-bit,6 data-bits, 2 programmable-bit and 1 stop-bit c. 1 start-bit,6 data-bits, 1 programmable bit and 1 stop-bit d. 1 start-bit,8 data-bits, 1 programmable-bit and 1stop-bit
4. The power saving modes of operation of 8051-microcontroller are: a. Idle mode b. Multi-processor mode c. UART mode d. Power-down mode e. Both (a) and (d) f. Both (d) and (c) g. All of the above
5. During the power saving modes of 8051: a. The CPU is reset b. CPU status is changed c. CPU status is preserved d. CPU status is overwritten
6. TB8 is ___ for data byte and ___ for address byte in multi-processor mode: a. 1,1 b. 1,0 c. 0,1 d. 0,0
7. The programmable bit during multi-processor serial communication mode is ____ data bit:
a. 1st b. 8th c. 9th d. 10th
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8. Consider the following events: 1) All slaves check the address sent by master. 2) Master sends the address of slave with TB8 = 1. 3) Slave responds to master by clearing its SM2 bit. 4) Slaves have their SM2 bit set. 5) Data bits sent by master with TB8 = 0.
Arrange the events in chronological order for master-slave communication in multi-processor serial communication mode:
a. 4,2,3,1,5 b. 4,1,2,3,5 c. 4,2,1,3,5 d. 1,2,3,4,5
9. For serial mode-2 operation, what is the baud rate if SMOD = 0 and XTAL frequency is 11.0592 MHz?
a. 645300 b. 345600 c. 192700 d. 172800
10. Consider the following block of code: ORG 0000h MOV TMOD,#20h MOV TH1,#-3 MOV SCON,#0D0h ------------ ------------ END The serial mode used and the baud rate set in above block of code is: (Assume clock frequency as 11.0592MHz)
a. Mode-2,2400 b. Mode-2,9600 c. Mode-3,9600 d. Mode-3,2400
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Lecture 13: 8051 Instruction Set
1. ___________ is the instruction used with external RAM or IO address for data transfer.
2. ___________ is the instruction used with external ROM for data transfer.
3. MOV A, @R0
a) Moves the contents of R0 to A
b) Transfer the data between A and R0
c) Move the data from Memory to A
d) Transfer the data from the memory location whose address is stored in R0 to A
4. Which is the valid instruction to transfer data 25H into R0
a) MOV R0,25H
b) MOV R0, #25H
c) MOV @R0,25H
d) MOV #25H,R0
5. Command used to read data from the port 0
a) MOV P0,A
b) MOV P0, @R1
c) MOV A,P0
d) MOV P0,#0FFH
6. MOV #32h, R3
a) is a valid instruction
b) instruction moves data from R3 to memory location 32H
c) instruction copies value 32h to R3
d) is invalid instruction as destination cannot be an immediate value
7. Instruction MOV A, #FFH generates a syntax error (TRUE/FALSE)
8. MOV R2, R4 is invalid instruction. (TRUE/FALSE)
9. _________ is the instruction used to read data from the look up table.
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10. Instruction that exchanges the data between register A and B is
a) XCH A, B
b) XCH B, A
c) XCHD A,0F0H
d) XCH A, 0F0H
11. Analyze the operation of the code
PUSH 07H PUSH 06H POP 07H POP 06H
a) Restores the data in register R6 and R7 b) Swaps the data between memory location 07h and 06h c) Exchanges the data between R6 and R7 d) a or b
12. __________ instruction exchanges lower nibble data between register A and internal
RAM source
13. In rotate and swap instructions the destination register is ________________.
14. What is the content of A after the execution of the instructions:
MOV A, #0FH
RL A
a) 0FH b) 0F0H C) 00H d)FFH
15. If the carry flag is set, then the MOV 7Fh, C
a) sets the byte location 7Fh
b) sets the bit location 7FH
c) sets the 7 bit of RAM byte 2Fh
d) is a invalid instruction
16. Executing the instruction ANL C,/b alters the addressed bit b. (TRUE/FALSE).
17. __________ is the instruction that interchanges the nibbles of accumulator.
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18. Four operations of right or left rotate is equivalent to ____________ instruction.
19. Instruction that clears the contents of accumulator is:
a) MOV A, #00H
b) CLR A
c) ANL A, #00H
d) Any of the above
20. Contents of accumulator at the end of the code execution will be:
MOV R0,A
XRL A,#1FH
XRL A,R0
a) equal to R0 b) equal to A c) 1Fh d) depends on value of A
21. Increment and decrement operations alter the C, AC and OV flags (TRUE/FALSE).
22. In addition and subtraction the destination register is ________________.
23. An alternate instruction for CLR C is
a) CLR PSW.0
b) CLR PSW.2
c) CLR PSW.5
d) CLR PSW.7
24. Equivalent instruction to increment the contents of DPTR(16-bit) is
a) INC DPTR
b) INC DPL
c) INC DPH
d) Not possible in a single instruction
25. After executing the MUL instruction, lower-byte of the product is in _________ while the higher-byte is in _________ register.
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26. An equivalent instruction that decrements the register contents and checks if zero is
a) DEC and JZ
b) DEC and JNZ
c) DJNZ
d) CJNE
27. Instruction that adjusts the result to the BCD equivalent is _____________
28. Addition and subtraction alters the ___________ flags while division and multiplication alters _____________flag
29. The rotate instruction that doubles the content is _____________
30. The rotate instruction that halves the content is _____________
31. Instruction MOV A,P2
a) reads the input pin
b) reads the port latch
c) performs read-modify-write operation
d) reads the internal latch.
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1. The first PICs were a major improvement over existing microcontroller because they were _______.
a. programmable b. of high output current
c. input/output controller built d. All of the above around a RISC architecture.
2. The PIC family share the same core set of RISC instructions. True/False
3. All assembly language instructions for PIC microcontroller is execute within__________.
a. one clock cycle b. two clock cycle
c. half clock cycle d. none
4. A program can mask any and all interrupts through the _________ register.
a. SFR b. INTCON
c. TRIS d. none
5. A __________allows you to program the part from a serial port without any special programmer circuitry.
a. program circuit b. assembler
c. bootloader d. none
6. The ______file is what the PIC programmer tool uses to burn the program into the PIC’s program memory.
a. .hex b. assembler
c. bootloader d. all
Module 3: PIC Microcontroller
Page 24 of 49
7. The PIC retrieved commands from EEPROM memory one at a time and executed them. This is known as____________.
a. execution b. interpreted execution
c. compiled execution d. none
8. In PIC Basic, I2COUT represents- Send bytes to I2C device. True/False
9. In PIC basic variables can be renamed using the ____________statement.
a. Symbol b. comments
c. Line labels d. ASCII values
10. ASCII characters must not be placed within quotes. True/False
11. Line Labels are limited to a length of ____ characters and cannot start with a number.
a. 32 b. 64
c. 16 d. 8
12. ____________command reverses the state of the port pin in the data register.
a. TOGGLE pin b. REVERSE pin
c. POT pin d. none
13. The first return will go back to subroutine and second return will go back to original GOSUB. This is known as ____________.
a. nesting b. ISR
c. RETURN d. none
14. PICs use ___________ possible clock configurations.
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a. external clock b. self oscillating with external crystal
c. external or self oscillating with PLL d. self oscillating with external RC
e. ALL
15. PIC machine instructions are uploaded from PC to PIC system via the _______debugger.
a. bootloader b. ICD2
c. DIC2 d. IDC2
16. The user must ensure the direction register is set correctly via ___________.
a. set_fast_io ( ) b. set_tris ( )
c. set_tris_x( ) d. none
17. The timer/counters can be used to__________________.
a. generate timed interrupts. b. count incoming logic transitions
c. capture timer/counter on an input event. d. generate variable PWM outputs
e. ALL
18. PSA determines whether the input is pre-scaled or not. TRUE/FALSE
19. An interrupt is raised when a particular condition occurs________.
a. timer/counter overflow b. change in the state of an input line
c. data received on a serial bus d. completion of an A-D conversion
e. power supply brown-out. f. ALL
20. Calculate interrupt rate when clock frequency is 20MHz and a pre-scaler ratio of 16.
a. 4.768 Hz b. 1.25 MHz
c. 305 Hz d. none
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21. PBPro is really a full-featured interpreter. True/False
22. NAP command represents Power down processor for short period of time. True/False
23. The PIC can be reset using__________.
a. MCLR b. CLR
c. INTR d. ALL
24. The data direction register is called the ____________register.
a. DATA b. TRIS
c. DDR d. none
25. The __________register is where you set Port A to be digital or analog input mode.
a. ADCON1 b. ADON
c. DACON d. none
26. All the interrupts can be enabled or disabled by setting or clearing the ______bit in the
option register.
a. GIE b. IE
c. SIE d. none
27. The __________loop returns back to the main loop using the RETURN command.
a. for b. convrt
c. convert d. none
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28. PIC16Cxx Microcontroller Family has _______ instructions. a. 35 b. 36 c. 24 d. 8 29. Logic unit of PIC has capability of performing operations ___________. a. complementing (COMF) b. rotation (RLF and RRF). c. Both a & b d. none 30. A __________interprets each instruction written in assembly language as a series of
zeros and ones which have a meaning for the internal logic of the microcontroller. a. Translator b. Interpreter c. Assembler d. none 31. A __________ is a textual designation (generally an easy-to-read word) for a line in a
program. a. Instructions b. Operand c. Label d. Directives 32. ______________is a series of words that a programmer writes to make the program more
clear and legible. a. Directives b. Comments c. Labels d. none 33. Data directive ___________ represents defining a block for the named constants. a. CBLOCK b. DATABLOCK c. DBLOCK d. none 34. Process of translating a program written in assembler language we get file(s) like ______. a. Executing file b. Program errors file c. List file d. All 35. An approach to programming in which separate logical tasks are programmed separately
and joined later is known as___________.
a. Modules b. Modular programming
c. Assembly Programming d. none
36. Communication between two devices is easiest to achieve via _________communication.
a. Parallel b. Parallel RS-232
c. serial RS-232 d. none
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37. Microcontroller and AD converter are connected over line(s)_______.
39. XT mode — frequencies between _______________.
a. 32 kHz and 200 kHz b. 100 kHz and 4 MHz
c. 8 MHz and 20 MHz d. none
40. CCP stands for:
a. Complex Capture Pulsewidth b. Cover Capture Pulsewidth
c. Compare Capture Pulsewidth d. none
41. Special Function Registers are reserved for
a. Control / Configuration b. Peripheral access
c. Indirect Addressing d. Program Counter
e. ALL
42. IRP stands for:
a. Indirect Register Pointer b. Interrupt Register Pointer
c. Interrupt Routine Pin d. none
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43. INDF register tracks contents of FSR. True/False
44. One of the following is not a mnemonic.
a. IORWF b. XORWL
c. COMF d. SWAPF
45. SWAPF command swaps full byte. True/False
46. RC discharges in time = ______________ .
a. 2πRC b. 2RC
c. 1/2πRC d. 2πC
47. In EXTRC mode— External RC is connected between PIC pin _____________.
a. OSC1 and VDD b. OSC1 and ground
c. OSC1 and INTR d. VDD and ground
48. Master in synchronous mode synchronizes data to external clock. True/False
49. Following is (are) the core independent peripherals:
a. Configurable Logic Cell (CLC) b. Complementary Waveform/Output Generator
c. Numerically Controlled Oscillator d. Programmable Switch Mode Controller
e. ALL
50. PIC has Faster Time-to-Market because of following reason(s):
a. Free software b. Pin and code compatibility, easy migration
c. Pre-programmed parts d. all
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51. XLP stands for
a. extreme Low Power b. Interface Low Power
c. x times low power d. none
52. Baseline architecture of PIC has no interrupts. True/False
53. CVD stands for
a. Complimentary Voltage Divider b. Capacitive Voltage Divider
c. Configurable Voltage Divider d. none
54. PIC Microcontroller's __________are used in I/O data transfer.
a. Port-D and Port-E b. Port-D and Port-F
c. Port-A and Port-E d. none
55. The control pin(s) of Port-E function is/are __________for data transfer.
a. RD b. WR
c. CS d. ALL
56. __________ Mode facilitates bidirectional 8-bit parallel data transfer.
a. TMD b. PSP
c. GIE d. PSPIE
57. PIC microcontroller has following feature(s):
a. 32 I/O pins arranged b. Two 16-bit timer/counters
c. Two external and three internal d. One full duplex serial I/O
vectored interrupts e. ALL
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58. ______________ register stores the important status conditions of the PIC microcontroller.
a. PSW b. PSP
c. TCON d. none
59. Bit address of 'b' bit of register 'R' is address of register ___________.
a. R b. R-1
c. 'R' + b d. 'R' – b
60. TRBUF is an 8-bit RAM variable used for ____________storage. a. temporary b. permanent c. a or b d. none 61. SDA (RC4) and SCL (RC3) are both _________drain pins. a. closed b. open c. voltage d. current 62 When a master wants to initiate a data transfer, it pulls SDA low followed by SCL being
pulled low. This is called ___________condition. a. STOP b. LOW c. START d. none 63. START and STOP conditions are unique and they never happen within a data transfer. True/False 64. The reason for open drain connection is
a. data transfer is bi-directional b. devices connected to the I 2C bus can drive- the data line c. either a or b d. both a & b
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1. 1. Microprocessor is a general purpose device
2. Microcontroller is indented for a specific purpose
(A). (1) is true, (2) is false (B). (1) is false, (2) is true
(C). (1) is true, (2) is true (D). (1) is false, (2) is false
2. If the crystal oscillator is operating at ______, the PCLK output of 8284 is 2.5 MHz.
(A) 15 MHz. (B) 5 MHz.
(C) 7.5 MHz. (D) 10 MHz.
3. In which T-state does the CPU sends the address to memory or I/O and the ALE signal
for demultiplexing
(A) T1. (B) T2.
(C) T3. (D) T4.
4. If a 1M x 1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no
more than __________ of time must pass before another row is refreshed.
(A) 64 ms. (B) 4 ns.
(C) 0.5 ns. (D) 15.625 micro sec .
5. In a DMA write operation the data is transferred
(A) from I/O to memory. (B) from memory to I/O.
(C) from memory to memory. (D) from I/O to I/O.
Module 4: Microprocessors
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6. Which type of JMP instruction assembles if the distance is 0020 h bytes
(A) near. B) far.
(C) short. (D) none of the above.
7. A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following
modes this SRAM is operating
(A) Read (B) Write
(C) Stand by (D) None of the above
8. Which of the following is true with respect to EEPROM?
(A) contents can be erased byte wise only.
(B) contents of full memory can be erased together.
(C) contents can be erased using ultra violet rays
(D) contents cannot be erased
9. Pseudo instructions are basically
(A) false instructions. (B) instructions that are ignored by the microprocessor.
(C) assembler directives. (D) instructions that are treated like comments.
10. Number of the times the instruction sequence below will loop before coming out of loop is
MOV AL, 00h
A1: INC AL
JNZ A1
(A) 00 (B) 01
(C) 255 (D) 256
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11. What will be the contents of register AL in 8086 after the following has been executed
MOV BL, 8C MOV AL, 7E ADD AL, BL
(A) 0A and carry flag is set (B) 0A and carry flag is reset
(C) 6A and carry flag is set (D) 6A and carry flag is reset