Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Topics n Pseudo-nMOS gates. n DCVS logic. n Domino gates. n Design-for-yield. n Gates as IP.

Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf

Topics

Pseudo-nMOS gates. DCVS logic. Domino gates. Design-for-yield. Gates as IP.


Pseudo-nMOS

Uses a p-type as a resistive pullup, n-type network for pulldowns.


Characteristics

Consumes static power. Has much smaller pullup network than

static gate. Pulldown time is longer because pullup is

fighting.


Output voltages

Logic 1 output is always at VDD.

Logic 0 output is above Vss. VOL = 0.25 (VDD - VSS) is one plausible

choice.


Producing output voltages

For logic 0 output, pullup and pulldown form a voltage divider.

Must choose n, p transistor sizes to create effective resistances of the required ratio.

Effective resistance of pulldown network must be comptued in worst case—series n-types means larger transistors.


Transistor ratio calculation

In steady state logic 0 output:– pullup is in linear region,Vds = Vout - (VDD - VSS)

;– pulldown is in saturation.

Pullup and pulldown have same current flowing through them.


Transistor ratio, cont’d.

Equate two currents:– Idp = Idd.

Using 0.5 mm parameters, 3.3V power supply:– Wp/Lp / Wn/Ln = 3.9.


DCVS logic

DCVSL = differential cascode voltage logic.

Static logic—consumes no dynamic power. Uses latch to compute output quickly. Requires true/complement inputs, produces

true/complement outputs.


DCVS structure


DCVS operation

Exactly one of true/complement pulldown networks will complete a path to the power supply.

Pulldown network will lower output voltage, turning on other p-type, which also turns off p-type for node which is going down.


DCVS example


Precharged logic

Precharged logic uses stored charge to help evaluation.

Precharge node, selectively discharge it. Take advantage of higher speed of n-types. Requires multiple phases for evaluation.


Domino logic

Uses precharge clock to compute output in two phases:– precharge;– evaluate.

Is not a complete logic family—cannot invert.


Domino gate structure


Domino phases

Controlled by clock . Precharge: p-type pullup precharges the

storage node; inverter ensures that output goes low.

Evaluate: storage node may be pulled down, so output goes up.


Domino buffer

Output inverter is needed for two reasons:– make sure that outputs start low, go high so that

domino output can be connected to another domino gate;

– protects storage node from outside influence.


Domino operation


Domino effect

Gate outputs fall in sequence:

gate 1 gate 2 gate 3


Monotonicity

Domino gates inputs must be monotonically increasing: glitch causes storage node to discharge.


Output buffer

Inverting buffer isolates storage node. Storage node and inverter have correlated values.


Using domino logic

Can rewrite logic expression using De Morgan’s Laws:– (a + b)’ = a’b’– (ab)’ = a’ + b’

Add inverters to network inputs/outputs as required.


Domino and stored charge

Charge can be stored in source/drain connections between pulldowns.

Stored charge can be sufficient to affect precharge node.

Can be averted by precharging the internal pulldown network nodes along with the precharge node.


Design-for-yield

Design processes that improve chip yield in very deep submicron/nanometer technologies.

Must treat design and manufacturing as a unified processing to maximize yield in nanometer technologies.


Variations in manufacturing

Three types of variations:– Systematic variations can be predicted based on

design and mask information plus manufacturing equipment.

– Random variations include variations in parameters, etc.

– Environmental variations include temperature, etc.


Trends in manufacturing

Larger variations in process and circuit parameters.

Higher leakage currents. Patterning problems caused by specific

combinations of geometric features. Metal width and thickness variations. Stress in vias.


Design-for-yield examples

Lithographic simulation to find yield problems not covered by standard design rules.

Extra vias added to increase the reliability of connections.

Statistical timing analysis to identify problems caused by variations in wiring.


Gates as IP

The standard cell library was one of the first forms of IP.– Reusable across many chips.– Portable from one process to another.

Standard cell compatibility issues:– Layout: cell size, pin placement.– Delay: driving specified load.– Power consumption.


Standard cell physical design

Basic cell organization is dictated by placement and routing system.

All cells are the same height.– May be one of a set of standard widths.

Pins must be placed on routing grid, usually determined by wiriing layers used.


Standard cell logical design

Must support a Boolean complete set of functions.

Should support enough gate types for good logic synthesis results.

Need several electrical variations of each function:– Low power.– High speed.


Cell verification and qualification

Cells are verified by layout extraction and circuit simulation.– Simulate a variety of process parameter

combinations. Qualification requires fabrication of cells on

the target process.

Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Topics n Pseudo-nMOS gates. n DCVS logic. n Domino gates. n Design-for-yield. n Gates as IP.

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