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Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Topics
Sequential machine (§5.2, §5.3)
FSM construction (§5.4)
Testing and design for testability (§4.8, §5.7)– Fault models– Combinational logic testing– Sequential logic testing
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Manufacturing Testing
Errors are introduced during manufacturing Testing: manufacturing validation Varieties of testing:
– functional testing– performance testing (binning chips by speed)
Testing also weeds out infant mortality
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Fault Modeling
Fault model– Convert a physical problem to a logical problem– Stuck-at, stuck-open, delay ... fault models– Single-fault assumption
With fault models+ Simulate the I/O behavior produced by the fault + Find possible locations of faults– impossible to incorporate all manufacturing faults
» Can’t guarantee the circuit is fault-free even if no fault is found under the fault model
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Stuck-at-0/1 Faults
Stuck-at-0/1 (s-a-0/1): a wire is always stuck at 0 or 1, independent of its drive value– Easiest and useful in practice, thus most popular
10B
A
C
01B
A
C
01B
A
C
10B
A
C
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Stuck-at-open/closed Model
Models transistors always on/off– how do we test t1
stuck-open?
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Full Scan Method
Connect all the system flip-flops in a scan chain as a big shift register
When in “test” mode– Stop system clock– Scan in the value for each flip-flop in the chain – Run the system clock for one or more cycles– Scan out the value for each flip-flop in the chain
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Scan Chain
Scan-in
Scan-out
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
An LSSD Latch
D1
CK1
CK2
CK3
D2
Q
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
A Multiplexed D Flip-flop
D Q
TE
D Q
D2
D1
Q
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei
Partial Scan
Full scan is expensive—must roll out and roll in state many times during a set of tests.
Partial scan selects some registers for scannability.
Requires analysis to choose which registers are best for scan.
Modern VLSI Design 3e: Chapter 5,6 Copyright 2002 Prentice Hall PTR Adapted by Yunsi Fei