Model Predictive Control of DSTATCOM employing …Model predictive control of DSTATCOM employing a single DC source cascaded H-bridge multilevel inverter in a weak distribution system

Model predictive control of DSTATCOM employinga single DC source cascaded H-bridge multilevel

inverter in a weak distribution system

Ramyani Chakrabarty1,2∗ and Ravindranath Adda1

1Department of Electronics and Electrical Engineering, IIT Guwahati, Guwahati, India2Department of Electrical Engineering, NIT Meghalaya

Email: ∗[email protected]

Abstract—This paper presents the performance of distributionstatic compensator (DSTATCOM) for load compensation in aweak distribution system. The DSTATCOM topology is realizedusing a single DC source based cascaded H-bridge multilevelinverter (SDCHBMLI). In SDCHBMLI, the multilevel waveformis generated by cascading the output of the transformers con-nected to individual full-bridge cells. The use of single DC sourceeliminates the requirement for capacitor voltage balancing, whichis one of the limitations of diode-clamped and flying-capacitorbased multilevel inverters. Also, the transformers in SDCHBMLIprovide inbuilt isolation between the DSTATCOM and the distri-bution system. In a weak distribution system, feeder impedancesmake the voltages at point of common coupling (PCC) susceptibleto distortions. To improve the PCC voltage waveform, shuntfilter capacitors are incorporated in each phase, which make thesystem more complex to control. In this paper, the DSTATCOMis controlled using Finite Control Set Model Predictive Control(FCS-MPC) technique, which can independently ensure desiredcompensator current tracking and PCC voltage improvementsimultaneously. The operation of proposed DSTATCOM has beenverified using PSCAD/EMTDC. The system behavior is simulatedfor load step changes and voltage sag condition. The robustnessof the control algorithm is also validated with variations in modelparameters.

Index Terms—DSTATCOM, FCS-MPC, Single DC sourcebased CHBMLI, weak distribution system,

I. INTRODUCTION

With increase in complexity of loads, the problem of

maintaining power quality in distribution system is garnering

widespread attention. Poor power quality adversely impacts

customers and network suppliers by increasing losses and

deteriorating the health of connected equipments. Any power

quality issues in voltage or current profile translate to a direct

financial loss for the consumer [1]. Power Quality issues

can be addressed by employing custom power devices in the

distribution system. DSTATCOM is a shunt compensating type

custom power device. It is used to mitigate power quality

problems such as harmonic distortions in the source current,

poor power factor and unbalances [2].The main component of DSTATCOM is a voltage source

inverter (VSI) operated in current controlled mode. The VSI

can either be a two-level or a multilevel inverter. As com-

pared to two-level inverters, multilevel inverters are gaining

popularity because of their numerous advantages. The output

waveform of a multilevel inverter is an accumulation of a

number of smaller voltage steps. This results in decrease of

harmonic content in the output waveform of the inverter, lesserdvdt , reduction in common mode voltages, smaller filter sizes

and operation with a lower switching frequency [3]. A number

of multilevel topologies, and their applications are reported in

literature [3]- [10].

The most widely used multilevel inverter (MLI) topologies

for DSTATCOM applications are diode-clamped (DCMLI) [4],

[5]; flying-capacitor (FCMLI) [6], [7] and cascaded H-bridge

(CHBMLI) multilevel inverters [8]- [10]. The high require-

ment of diodes and capacitors increase the design complexities

in DCMLI and FCMLI. In both DCMLI and FCMLI, increase

in number of levels in the output waveform also increase

the number of DC link capacitors. In FCMLI, redundant

switching combinations are available which can be utilized for

capacitor voltage balancing [6]. Also, for satisfactory operation

of the inverters as DSTATCOM, it is important to regulate

the voltage of DC link capacitors at desired value. In both

cases, higher number of DC capacitors lead to complex voltage

balancing methods, either by increasing auxiliary circuits or

adding to control constraints. Larger component count increase

the converter size and cost. Moreover, the capacitors used

in FCMLI need to be pre-charged to the desired voltages

before switching [11]. As compared to FCMLI and DCMLI,

CHBMLI appears as a convenient choice since it doesnot

require any clamping diodes or capacitors. CHBMLI has a

modular structure and the control procedure is easier [8]. One

drawback of this topology is the requirement of individual

capacitors for each of the full-bridge cells [11]. Usage of

individual capacitors require balancing their voltages for a

symmetrical multilevel output waveform. Additional controls

or circuits have to be designed to balance and equalize the

capacitor voltages.

This drawback can be overcome by connecting the individ-

ual cells in parallel to the same DC capacitor [12]. In this

configuration, the multilevel output waveform of the inverter

module is obtained by cascading the output voltages at the

secondaries of the transformers connected to each full-bridge

cell. This topology is referred to as SDCHBMLI in this

paper. SDCHBMLI eliminates the requirement of balancing

the capacitor voltages, without compromising the simplicity978-1-5386-6159-8/18/$31.00 © 2018 IEEE

Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India

and modularity of the inverter.

For load compensation using DSTATCOM, the switching

signals of the VSI are obtained using a closed loop current

control technique. For multilevel inverter based DSTATCOM,

various current control techniques like deadbeat control [13],

hysteresis control [5]- [9], [14], sliding mode control [10] are

used. Deadbeat control is sensitive to variability of parameters

in current control loop. Hysteresis control presents some

advantages over deadbeat and other control techniques, like

simple implementation and faster dynamic response, but it

cannot be used in higher order systems [2]. Application of

hysteresis controllers for load compenstation in systems with

feeder impedance is possible by excluding the shunt capac-

itors, as demonstrated in [9], but the absence of shunt filter

capacitors cause distortions in PCC voltages. In most systems

with feeder impedance, hysteresis control can be implemented

only in conjuction with some other control techniques [4],

[10]. This is a major drawback of hysteresis control.

In this paper, a DSTATCOM connected to a weak distri-

bution system is realized using an SDCHBMLI. The control

signals for the SDCHBMLI are generated using finite control

set-model predictive control (FCS-MPC). Shunt filter capaci-

tors are added at PCC to improve the quality of PCC voltage

waveform. Despite the presence of shunt filter capacitors, FCS-

MPC can be used independently without the requirement of

any other supplementing control methods. Also, the applica-

tion of FCS-MPC to SDCHBMLI is easier as compared to

other control techniques available for MLIs.

The paper is organized into four sections. Section II presents

DSTATCOM using SDCHBMLI topology, the DC-link param-

eter selection, reference current generation and DC-bus voltage

control. Current control of the DSTATCOM by FCS-MPC is

described in section III. Section IV presents the results and

Section V gives the conclusions.

II. DSTATCOM USING SDCHBMLI

A. The SDCHBMLI topology

A distribution system supplying unbalanced loads through

feeder impedances is shown in Fig. 1(a). The DSTATCOM is

realized using a 7-level SDCHBMLI. It is connected to the

PCC through a filter inductor Lf and a capacitor Cf . The

SDCHBMLI consists of three single-phase inverter modules

supplied from a common DC-link capacitor Cdc. Each single

phase module consists of three full-bridge cells, as shown

in Fig. 1(b). The output from each cell is connected to

the primary of a transformer. The output waveform of each

inverter module is a series combination of the transformer

secondary voltages, given by,

vox = vx1 + vx2 + vx3, x ∈ (a, b, c) (1)

The switching logic combinations for a single cell is shown

in Table I, where k ∈ (1, 2, 3). The output voltages of an

individual inverter module are shown in Table II, where Sx

indicate the level of the inverter operation.

vta

vtbvtc

isa

isb

isc

ila

ilb

ilc

vsa

Unbalancedand

DistortedLoad

ifcc

ifb ifc

RL

Invertermodule forphase A

Rf

Lf

RL

RL

Rf

Lf

icc

vsb

vsc

Cf Cf

+voa−

Invertermodule forphase B

+vob−

Invertermodule forphase C

+voc−

+vdc−

icbifa

Rf

Lf

Cf

ica

Cdc

ifcbifcc

(a)

sx13

sx14

sx11

sx12

vx1vdc

sx23

sx24

sx21

sx22

sx33

sx34

sx31

sx32

vx2

vx3

vox

+

_

+

_ Cdc

(b)

Fig. 1. Topology for a 7 level SDCHBMLI based DSTATCOM:(a) A threephase DSTATCOM connected to a weak supply point. (b) Inverter modulefor phase a

B. DC link parameter design

The compensation capability of DSTATCOM is dependent

on the average DC-link voltage, Vdc, which can be selected to

be higher than two times the peak phase voltage [18]. Thus,

for a two-level inverter,

Vdc =2√2VLL√3

(2)

As the output voltage of SDCHBMLI is in integral steps of

the DC-link voltage, for an N-level SDCHBMLI,

Vdc =2√2VLL

M√3

, M =(N − 1)

2(3)

Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India

TABLE ISWITCHING LOGIC COMBINATIONS FOR A SINGLE CELL

sxk1 sxk2 sxk3 sxk4 vxk0 1 0 1 00 0 1 1 −Vdc

1 1 0 0 +Vdc

1 0 1 0 0

TABLE IIOUTPUT VOLTAGE OF AN INVERTER MODULE

vx1 vx2 vx3 vx =3∑

k=1

vxk Sx

0 0 0 0 00 0 ±Vdc ±Vdc ±10 ±Vdc ±Vdc ±2Vdc ±2

±Vdc ±Vdc ±Vdc ±3Vdc ±3

Thus, Vdc reduces by ‘M’ in case of a DSTATCOM realized

using SDCHBMLI.

Depending upong the kVA rating of the system and DC

link voltage, the required capacitance of DC capacitor, Cdc,

can be obtained. If X be the kVA rating of the system, let

the compensator be capable of handling a ±50% variation in

the system rating for n cycles. In this time, let the DC link

voltage be allowed to undergo a ±20% change in its value.

With the fundamental cycle of the system being T seconds,

Cdc is calculated as [14]

Cdc =2(X − X

2 )nT

(1.2Vdc)2 − (0.8Vdc)2(4)

C. Reference Current Generation

The compensator is operated in current controlled mode for

distortion reduction, power factor improvement and unbalance

elimination. For current controlled operation, the inverter

output should track a pre-evaluated set of reference currents.

Instantaneous symmetrical components theory is applied to

calculate the reference currents. As only the real power de-

manded by the load should be drawn from the source, the

desired reference source currents for a system without feeder

impedance are given by [2]

⎡⎣i

∗sa

i∗sbi∗sc

⎤⎦ =

1c∑

x=av2sx

⎡⎣ 1 1 −1−1 1 11 −1 1

⎤⎦⎡⎣vsavsbvsc

⎤⎦ (ploss + plavg)

(5)

where plavg is the active power consumed by the load and

ploss is output from the DC bus voltage controller, discussed

in subsection-II-D. In a weak distribution system, due to the

presence of feeder impedance, source voltages (vsx) and PCC

voltages (vtx) have different values. Also, unbalance in the

loads is reflected at PCC voltages. Hence if vsx is replaced

with vtx in (5), the resultant reference source currents will be

unbalanced, nullifying the objective of DSTATCOM. Hence,

in a weak distribution system, fundamental component of the

positive sequence PCC voltages (v+tx1) are utilized to generate

the reference currents,

⎡⎣i

∗sa

i∗sbi∗sc

⎤⎦ =

1c∑

x=av+

2

tx1

⎡⎢⎣

1 1 −1

−1 1 1

1 −1 1

⎤⎥⎦⎡⎢⎢⎣v+ta1

v+tb1

v+tc1

⎤⎥⎥⎦ (ploss + plavg)

(6)

The unbalanced terminal voltages are converted to its sequence

components using symmetrical transformation⎡⎢⎣v0t

v+t

v−t

⎤⎥⎦ =

1√3A

⎡⎢⎣vta

vtb

vtc

⎤⎥⎦ A =

1√3

⎡⎣1 1 11 α α2

1 α2 α

⎤⎦ (7)

The fundamental of the sequence components are extracted

using Fourier transformation [2],

v+t1 =

√2

T

∫T

v+t e−(ωt−π

2 )dt, T =ω

2π(8)

The fundamental component of the symmetrical components

are subjected to an inverse transformation to generate the

fundamental components of the PCC voltages.⎡⎢⎢⎣v+ta1

v+tb1

v+tc1

⎤⎥⎥⎦ = A−1

⎡⎢⎣v0t1

v+t1

v−t1

⎤⎥⎦ (9)

At PCC, reference compensator currents, i∗fx, are given by

i∗fx = ilx − i∗sx (10)

From Fig. 1(a), the reference current for the DSTATCOM,

i∗fcx, is

i∗fcx = i∗fx + Cfdvtxdt

(11)

The model predictive current control ensures that the voltages

at PCC are equal to their fundamental positive sequence

components, vtx = v+tx1

D. DC bus voltage controlThe voltage of the DC-link capacitor should be maintained

at the desired value under disturbances. To control the afore-

mentioned voltage at the required value calculated in (3), a PI

controller is commonly used. The error between the reference

DC-link voltage, Vdcref and the averaged capacitor voltage,

Vdc, is fed into a proportional-integral controller as depicted

in Fig. 2 [17]. The output from the control loop is ploss which

is the real power drawn by the compensator from the source

to sustain the DC-link capacitor voltage at the desired value.

This term is used in (6) for reference current generation.

PIcontroller

Movingaveragefilter

Vdcref

vdc

ploss+_Vdc

Fig. 2. DC bus voltage control loop

Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India

vtis ilif

vs

L

Cost functionminimization

Predictivemodel

xm

Sxopt

LoadR

x*

xp

Fig. 3. Schematic of Model predictive control of DSTATCOM

LoadRf

Lf

Cf

isx iloadvtx

SxVdc

ifcxifx

idxR

L

Loop 1vs

Fig. 4. Single-phase equivalent circuit diagram

III. PREDICTIVE CURRENT CONTROL

The predictive control methods utilize the explicit mathe-

matical model to predict subsequent responses of system. The

cost function, which gives a measurement of error between

the reference value and predicted value of the desired output

variable, is minimized to generate the control signals [15].

The advantages of MPC method are fast response in tran-

sient states, possibility of multi-objective cost function, and

easier inclusion of non-linearities [16]. The particular benefit

of implementing predictive control for load compensation

in systems with feeder impedance is that it overcomes the

problems posed by hysteresis control. Hysteresis control alone

cannot ensure stability in distribution networks that includes

shunt capacitor filters and generally requires inclusion of

another control technique [2], [4]. Predictive control can be

independently implemented in a weak distribution system with

shunt capacitors. A deterrent against predictive controls is the

large computational demand due to requirement of optimizing

the cost function. To circumvent this problem, FCS-MPC is

used. In this method, the finite combinations of switching

states that are possible in a converter are exploited to reduce

the computation load.

In the application investigated in this paper, the 7-level

SDCHBMLI has to be operated so that the actual output

current from the the inverter, ifcx, tracks reference current

i∗fcx as determined in (11). The schematic for the proposed

FCS-MPC method is outlined in Fig. 3. The mathematical

model for predicting the values of DSTATCOM currents at

next sampling instants is obtained by applying KVL in Loop

1, as shown in Fig. 4,

−SxVdc + Lfdifcxdt

+Rf ifcx + vtx = 0 (12)

If Ts is the sampling time interval, then in discrete time

domain,

difcxdt

≈ ifcx(k)− ifcx(k − 1)

Ts(13)

Predict fcx(k+1) using (15)

Compute gx using (16)

IsSx> M?

Apply Sxopt (k+1) correspondingto minimum gx

NO

YES

Set Sx= −M

Measure ifcx(k), vtx(k)

Sx=Sx+1

i

Fig. 5. Flowchart for determining switching sequences according to FCS-MPC

Thus (12) can be written as

−SxVdc(k) + Lfifcx(k)− ifcx(k − 1)

Ts

+Rf ifcx(k) + vtx(k) = 0

(14)

The value of ifcx at kth sampling instant is obtained from

(14)

ifcx(k) =1

1 +TsRf

Lf

ifcx(k − 1)

+1

Rf +Lf

Ts

[SxVdc(k)− vtx(k)]

(15)

Predictive control requires the value of ifcx at the (k + 1)th

instant. Thus , advancing (15) by one sampling instant, the

predicted value of ifcx, denoted by ifcx(k + 1), is given by

ifcx(k + 1) =1

1 +TsRf

Lf

ifcx(k)

+1

Rf +Lf

Ts

[SxVdc(k + 1)− vtx(k + 1)]

(16)

Fig. 5 shows the flowchart of FCS-MPC algorithm to generate

the switching signals for SDCHBMLI. The cost function gxis calculated for all feasible switching combinations, −M ≤Sx ≤ M , where M is defined in (3).

gx =| i∗fcx(k + 1)− ifcx(k + 1) | (17)

The switching combination, Sxopt, corresponding to the min-

imum gx, is applied to the inverter. If Ts, is sufficiently small,

then, vtx(k + 1) ≈ vtx(k), i∗fcx(k + 1) ≈ i∗fcx(k) [19].

IV. RESULTS

The performance of DSTATCOM realized with a 7-level

SDCHBMLI is investigated using PSCAD/EMTDC with the

simulation parameters given in Table III.

Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India

TABLE IIISIMULATION PARAMETERS

Source voltage 11 kV, line-to-line RMSFeeder impedance (1 + j3.14)ΩFilter parameters Rf = 1.0Ω, Lf = 3.5 mH, Cf = 10μF

Transformer parameters 1 : 1, 2.5 MVADC link voltage 6500 V

DC link capacitance 4400 μFSampling time, Ts 10 μS

Fig. 6. Optimum switching level Saopt of phase-a

Fig. 7. Output of individual full-bridge cells and phase a inverter module

Fig. 8. Uncompensated system response: Unbalanced source currents(top),scaled terminal voltage (vta/50) and source current in phase a(bottom)

The system is supplying a load of (30 + j94.24) Ω,

(60 + j62.83) Ω and (70 + j31.46) Ω in phases a, b and crespectively. A three phase uncontrolled rectifier with an RC

load of 50 μF and 500 Ω is also connected at PCC.

(a)

(b)

Fig. 9. Compensated system response: (a)Balanced source currents (top),scaled terminal voltage (vta/50) and source current in phase a(bottom) and,(b)Tracking of DSTATCOM current(top), tracking of source current(bottom)

The output from the controller, Sxopt is plotted in Fig. 6.

The voltage levels at which each inverter module should

operate is determined by Sxopt according to Fig. 3 and Table

II. The switching signals are then chosen as per Table. I.

The output of the individual full-bridge cells and the inverter

module for phase a is shown in Fig. 7. For example, when

Saopt is +1, voa is +vdc and when Saopt is −2, voa is −2vdcand so on.

The unbalanced and distorted source currents in the un-

compensated system is plotted in Fig. 8. The scaled PCC

voltage of phase a and source current isa are plotted to exhibit

poor power factor of the load. It can also be noted that

the effect of feeder impedance is reflected in the distortion

creeping into PCC voltages. The compensated system response

in which the source currents become balanced and distortion

free is shown in Fig. 9(a). It is seen that source current in

phase a is in phase with the PCC voltage. The PCC voltage

becomes free from distortions in the compensated system as

compared to Fig. 8. A step change is given in the load current

in phase c at 0.35 seconds. The source currents continue to

remain balanced and sinusoidal even after change in load. The

total harmonic distortion in source currents in each phase of

the compensated system reduces to 1%. Thus the objective

of mitigating unbalance and distortions in source currents

while preserving the quality of PCC voltages, taking feeder

impedance into consideration, is achieved by the DSTATCOM.

Fig. 9(b) gives the performance of FCS-MPC technique. It is

observed that the measured source currents and DSTATCOM

currents are tracking the reference source and DSTATCOM

currents respectively.

Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India

(a)

(b)

Fig. 10. DSTATCOM performance under 20% voltage sag: (a) Balancedsource currents (top), source voltages(bottom) and, (b)ploss/plavg(top),averaged capacitor voltage (bottom)

Fig. 11. Source currents with variations in filter parameters (top), trackingof DSTATCOM current(bottom)

Fig. 10 shows the performance of DSTATCOM when there

is a voltage sag. The average capacitor voltage Vdc is regulated

close to desired value by the controller. It can be observed from

Fig. 10(b) that ploss is very less as compared to plavg .

It is desired that the control algorithm should be robust if

there is a small deviation of actual system parameters from the

parameters utilized in (16) and (17). To verify this, the filter

parameters Cf , and Lf are changed to 1.2 times the value

given in Table III. It is observed from Fig. 11 that source

currents are balanced sinusoids despite the variations in filter

parameters.

V. CONCLUSION

A three-phase DSTATCOM is realized with a 7-level SD-

CHBMLI. A mathematical model of the system for application

of FCS-MPC is derived utilizing the quantities that are avail-

able at the PCC. The algorithm is presented for selecting the

optimum switching sequence by exploiting the finite possible

switching combinations for reference tracking. The DSTAT-

COM is successful in eliminating unbalance, harmonics and

improving power factor of the load, along with maintaining

a clean PCC voltage. The performance is tested with step

changes in load and sag in source voltage. The FCS-MPC

technique is verified by subjecting it to deviations in the filter

REFERENCES

[1] S. Bhattacharyya, J. Myrzik, and W. Kling, “Consequences of PoorPower Quality- An Overview,” in Proc. 42nd Int. Univ. Power Eng.Conf.(UPEC), pp. 651–656, 2007.

[2] A. Ghosh and G. Ledwich, Power Quality Enhancement using CustomPower Devices. Norwell, MA: Kluwers, 2002.

[3] J. Rodrguez, J-S. Lai, B. Wu, J. O. Pontt, and F. Z. Peng , “Multilevelinverters: a survey of topologies,controls, and applications,” IEEE Trans.Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.

[4] A. Shukla, A. Ghosh, and A. Joshi, “State feedback control of multilevelinverters for DSTATCOM applications,” IEEE Trans. Power Deliv., vol.22, no. 4, pp. 2409–2418, Oct. 2007.

[5] S. Srikanthan and M. K. Mishra, “DC Capacitor Voltage Equalizationin Neutral Clamped Inverter for DSTATCOM Application,” IEEE Trans.Ind. Electron., vol. 57, no. 8, pp. 2768–2775, May 2010.

[6] A. Shukla, A. Ghosh, and A. Joshi, “Hysteresis current control operationof flying capacitor multilevel inverter and its application in shuntcompensation of distribution systems,” IEEE Trans. Power Del., vol.22, no. 1, pp.396–405, Dec. 2007.

[7] K. Antoniewicz, M. Jasinski, M. P. Kazmierkowski, and M. Malinowski,“Model predictive control for three-level four-leg flying capacitor con-verter operating as shunt active power filter,” IEEE Trans. Ind. Electron.,vol. 63, no. 8, pp. 5255–5262, Aug. 2016.

[8] R. Gupta, A. Ghosh, and A. Joshi, “Cascaded multilevel control ofDSTATCOM using multiband hysteresis modulation,” in Proc. IEEEPower Eng. Soc. Gen. Meet., pp. 18–22, Jun. 2006

[9] R. Gupta, A. Ghosh, A. Joshi, “Control of cascaded transformer mul-tilevel inverter based DSTATCOM,” Electr. Power Syst. Res. (EPSR),Elsevier, vol. 77, no. 8, pp. 989–999, Jun. 2007.

[10] R. Gupta, A. Ghosh, A. Joshi, “Multiband hysteresis modulation andswitching characterization for sliding-mode-controlled cascaded multi-level inverter,” IEEE Trans. Ind. Electron. vol. 57 no. 7 pp. 2344–2353Jul. 2010.

[11] S. Khomfoi, L. M. Tolbert, Power Electronics Handbook, Elsevier, 2007[12] S. G. Song, F. S. Kang, and S. J. Park, “Cascaded multilevel inverter

employing three-phase transformers and single DC input,” IEEE Trans.Ind. Electron., vol. 56, no. 6, pp. 2005–2015, Jun. 2009.

[13] A. Luo H. Xiao Z. Shuai, “Double deadbeat-loop control method fordistribution static compensator,” IET Power Electron. vol. 8 no. 7 pp.1104–1110 Jul. 2015.

[14] M. K. Mishra and K. Karthikeyan, “A Fast-Acting DC-Link VoltageController for Three-Phase DSTATCOM to Compensate AC and DCLoads,” IEEE Trans. Power Del., vol. 24, no. 4, pp. 2291–2299, Oct2009.

[15] D.E.Quevedo, R.P.Aguilera, and T.Geyer, Predictive Control in PowerElectronics and Drives. 3rd ed. John Wiley and Sons.Inc, 2002.

[16] J. Rodriguez, M. P. Kazmierkowski, J. R. Espinoza, P. Zanchetta, H.Abu-Rub, H. A. Young, and C. A. Rojas, “State of the art of finitecontrol set model predictive control in power electronics,” IEEE Trans.Ind. Informat., vol. 9, no. 2, pp. 1003–1016, 2013.

[17] G. Ledwich and A.Ghosh, “A flexible dstatcom operating in voltage orcurrent controlled mode,” IEE Proc.-Gener. Transm. Distib., vol. 149,no. 2, pp. 215-224, March 2002.

[18] B. Singh, A. Chandra, and K. Al-Haddad, Power Quality:Problems andmitigation techniques, John Wiley and Sons, 2014.

[19] P. Cortes, A. Wilson, S. Kouro, J. Rodriguez, H. Abu-Rub, “Modelpredictive control of multilevel cascaded H-bridge inverters,” IEEETrans. Ind. Electron., vol. 57, no. 8, pp. 2691–2699, Aug. 2010.

Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India