Mobile TV Integrated Circuits Design of a Low-Voltage Multi-Standard Sigma-Delta Modulator Carlos André Faria Calisto Dissertation submitted for obtaining the degree of Master in Electrical and Computer Engineering Jury Supervisor: Prof. Carlos Leme Co-Supervisor: Prof. João Vaz President: Prof. Marcelino Santos Members: Prof. Jorge Fernandes January 2009
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Mobile TV Integrated Circuits
Design of a Low-Voltage Multi-Standard Sigma-Delta Modulator
Carlos André Faria Calisto
Dissertation submitted for obtaining the degree of
Master in Electrical and Computer Engineering
Jury
Supervisor: Prof. Carlos Leme
Co-Supervisor: Prof. João Vaz
President: Prof. Marcelino Santos
Members: Prof. Jorge Fernandes
January 2009
i
Acknowledgments
First, I would like to thank the board of Chipidea, for giving me the opportunity to develop my master
thesis in a state-of-the-art industrial environment and for the excellent working conditions that were
given.
I would like to acknowledge my advisor, Professor Carlos Leme, for his guidance and support. I also
want to thank Marco Oliveira for his invaluable assistance and advice on issues related to the design
of sigma-delta modulators and Tiago Patrão for his knowledge and insights in analog design.
I would like to thank all my colleagues at Chipidea for their friendship and all their help, Diogo Calado,
André Teixeira, André Carvalho, Hélder, José Brito, José Jesus, Proença, Rodrigo Duarte, Angelo,
Alexandre, Luis, Pedro Acabado, David Lousada, just to name a few.
I would also like to thank all my colleagues at Instituto Superior Técnico for the conversations and
José Guerra, Gabriel, Miguel Barros, Sara, Guilherme, Hugo Varandas, Vasco Andrade e Silva and
Rui Francisco, among others.
I would like to express my gratitude to my personal friends that supported me over the last few years,
Rui Pascoal, Luis João, Renato Sousa, Joana Sismeiro, João Monteiro, André Sousa, Nuno Moita
and Miguel Marques.
Finally I would like to thank my parents, my brother and my sister for their love and encouragement. I
admire my parents’ determination and sacrifice to put me through college.
ii
Abstract
Mobile Television integrates two of the most popular consumer products ever: television and mobile
phone. Moreover, the co-existence of numerous standards defined for wireless communication
increases the need for interoperability between various technologies. Therefore, the integration of
several radio interfaces into programmable and reconfigurable hardware supporting multiple standards
and multiple frequency bands becomes extremely important.
This thesis describes the design of a programmable bandwidth, low-voltage and low-power Sigma-
Delta Modulator in an 80nm CMOS technology. First the system is modeled and validated in Matlab
environment with use of behavioral models. Then the electrical design is optimized for low-power and
robustness.
The 3rd
order, 12 levels architecture supports the standards GSM, CDMA2000, UMTS and DVB-H.
The Sigma-Delta Modulator designed in a 1V supply technology, achieves a peak SNR of 64dB for
GSM (100kHz signal band) and 57dB for DVB-H (4MHz signal band) consuming between 2.6 and
6mA.
Keywords
Mobile Television, programmable, multiple standards, Sigma-Delta Modulator, low-voltage, low-power.
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Resumo
Televisão móvel integra dois dos produtos mais populares de sempre: a televisão e o telefone móvel.
Além disso, a co-existência de vários standards para comunicação sem fios aumenta a necessidade
de interoperabilidade entre várias tecnologias. Desta forma, a integração de várias interfaces de rádio
em hardware reconfigurável e programável capaz de suportar múltiplos standards e múltiplas bandas
de sinal, torna-se muito importante.
Esta tese descreve o desenho de um modulador Sigma-Delta de baixo consumo e de baixa tensão de
alimentação com largura de banda programável, numa tecnologia CMOS de 80nm. Primeiro, o
sistema é modelado e validado no ambiente Matlab com o apoio de modelos comportamentais. De
seguida, o desenho eléctrico é optimizado para consumo reduzido e robustez.
A arquitectura de 3ª ordem e de 12 níveis suporta os standards GSM, CDMA2000, UMTS e DVB-H. O
modulador Sigma-Delta alimentado a 1V, atinge SNR máximo de 64dB para GSM (banda de sinal de
100kHz) e um SNR máximo de 57dB para DVB-H (banda de sinal de 4MHz).
Palavras-chave
Televisão móvel, programável, múltiplos standards, modulador Sigma-Delta, baixo consumo, tensão
de alimentação baixa
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Table of Contents
ACKNOWLEDGMENTS ..................................................................................................................................... I
ABSTRACT ..................................................................................................................................................... II
RESUMO ....................................................................................................................................................... III
TABLE OF CONTENTS .................................................................................................................................... IV
LIST OF FIGURES ......................................................................................................................................... VIII
LIST OF ACRONYMS ...................................................................................................................................... XI
LIST OF SYMBOLS ....................................................................................................................................... XIII
2.2 WIRELESS TRANSCEIVER GENERAL ARCHITECTURE ............................................................................................... 6
2.3 THE Σ-∆ ADC ............................................................................................................................................. 6
2.4 SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE ................................................................................................... 7
2.5 SYSTEM SPECIFICATIONS ................................................................................................................................ 7
CHAPTER 3 THE ΣΣΣΣ−−−−∆∆∆∆ ADC ........................................................................................................................... 9
3.1 ANALOG TO DIGITAL CONVERSION ................................................................................................................... 9
3.1.1 Sampling and the Anti-Aliasing filter ............................................................................................... 9
4.3 SYSTEM MODELING ..................................................................................................................................... 30
5.2.4 Offset voltage ................................................................................................................................ 61
5.4 DWA DAC ............................................................................................................................................... 70
7.2 FUTURE WORK .......................................................................................................................................... 82
A1.2.2 MOS transistor ............................................................................................................................... 86
SNRVN(T) Signal-to-thermal-noise ratio 70 68 65 65 dB
VN(T),INT,input2
Thermal Noise Power 12,5 19,8 39,5 39,5 nV2
SR Slew-Rate 18 90 203 405 V/µs
56
Conceptually, the three integrators are identical; only the specifications differ. The specifications for
the 2nd
and 3rd
integrators are more relaxed, as the corresponding non-idealities when referred at the
input of the modulator appear attenuated by the gains of the preceding stages; consequently, the
specifications for the corresponding operational amplifiers are also relaxed.
5.2 Programmable Amplifier Design
This section describes the design of the operational amplifier for the first integrator. The design
methodology can be extended to the design of the 2nd
and 3rd
integrator OpAmps with the difference
being the relaxation of the specifications.
5.2.1 Topology
The selected topology for the operational amplifier is a two-stage amplifier with cascode compensation
[Ahuja1983], as shown in Figure 5.4. For a matter of simplicity, bias and common-mode feedback
circuits are not included. The input-stage is a folded cascode with a PMOS differential pair while the
output-stage is a class-A common source.
Figure 5.4. Two-stage cascode compensated operational amplifier with folded first-stage.
Some form of compensation is necessary to maintain stability in a two-stage amplifier. The standard
Miller compensation [Johns1997] places a pole-splitting capacitor between the output of the amplifier
and the output of the first stage (between the drains of M11 and M5, Figure 5.4). This technique creates
a dominant low-frequency pole and moves the second pole to a higher frequency which ensures
amplifier stability. On the other hand the cascode compensation technique places a compensation
capacitor between the amplifier output and the first stage cascode node, Figure 5.4, creating a
dominant pole and two complex poles at higher frequencies. This also ensures amplifier stability with
the advantage of increasing the speed compared to Miller compensation. Higher speed amplifier
topologies achieve low power dissipation under a fixed settling constraint, thus the cascode
compensation technique is preferred.
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5.2.2 Frequency response
To analyze the open-loop frequency response of the operational amplifier, the small-signal equivalent
model for weak signals valid for small variations around the bias point is elaborated, represented in
Figure 5.5., where gmi is the incremental transconductance of the transistor Mi (Figure 5.4), rn e cn
represent the total incremental resistance and capacitance respectively at nodes n, rnp represents the
total incremental resistance between nodes n and p and CC is the compensation capacitor.
The behavior of the circuit is described by the equation system
( )( )( ) ( )
( )( )
5 1 12 1 1 12 2 1
5 12 1 12 2 2 2
1 11 2
0
0
C C out in
C out out C out
gm g g s c C v g v sC v gm v
gm g v g g sc v
sC v gm v g s C C v
+ + + + − − = −
− + + + + =
− + + + + =
(5.19)
where conductances gn are used instead of resistances rn to ease the writing.
Figure 5.5. Small-signal equivalent model for weak signals.
Comparing the circuits of Figure 5.4 and Figure 5.5, it is possible to give a physical meaning to the
conductances gn and capacities cn,
1 1 3
12 5
2
7 7 9
11 13
1 1 5
2 5 7 11
11 13
1
out
out L
g gds gds
g gds
ggm rds rds
g gds gds
c cgd cgs
c cgd cgd cgs
c cgd cgd C
= +
=
=
= + = + = + +
= + +
(5.20)
where gdsi represents the incremental channel conductance of transistor Mi, rdsi represent the
incremental channel resistance of transistor Mi, cgsi and cgdi represent respectively the gate-to-source
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and gate-to-drain capacitances of the transistor Mi and CL represents the load capacity of the
operational amplifier.
Solving the equation system (5.19), the circuit presents a frequency response with a low-frequency
dominant pole, two off-axis complex poles and two high-frequency symmetric zeros [Hurst2004].
DC Gain
From Figure 5.5, the low-frequency gain1 of the operational amplifier is given by
( )( )( )
1 11 5 12
5 12 1 2 1 12
DC
out
gm gm gm gA
g gm g g g g g
+=
+ + +(5.21)
Considering that the conductances g12 and g1 are small compared to gm5 and that g1g12 is small
compared to gm5gm2, the simplified expression is
1 11
2
DC
out
gm gmA
g g= (5.22)
In the expression (5.22) the gain contributions of the first and second stage of the operational amplifier
are clearly identifiable. The gain of the first stage is given by the differential pair incremental
transconductance gm1 divided by the first-stage output conductange g2. The gain of the second stage
is given by the incremental transconductance of the gain transistor of the second stage (M11), divided
by the output conductance gout.
Gain-bandwidth product
The approximate expression for the gain-bandwidth product of a properly compensated two-stage
operational amplifier with a compensation capacitor CC is given by [Johns1997],
11
C
gmGBW rad s
C
− = ⋅ (5.23)
Dominant pole
Considering the definition of the gain-bandwidth product, the approximate expression for the dominant
pole of the amplifier can be obtained through expressions (5.22) and (5.23) and is given by
(5.24)
High frequency poles and zeros
For the high-frequency poles and zeros, the exact solutions require a mathematical complexity that
does not allow taking conclusions over the dominant factors, and so some simplifications are made, 1 Frequency range before the dominant-pole, where the circuit presents an approximate flat response.
59
[Feld1997] and [Tavares2002]. Therefore, in high-frequencies, the incremental channel conductances
(gds) of the transistors are considered despicable compared to the capacitors’ susceptance (sC).
The non-dominant complex poles pair is given by
2 1
, 1 ,P ND n nw j rad sξϖ ξ ϖ − ≅ ± − ⋅ (5.25)
with damping factor ξ and natural frequency ϖn.
( )5 2
11 1
15 11
2 1
1
2
out C
out CC
out C
n
out C
out C
gm c c C
c Cgm C c
c C
gm gmrad s
c Cc c
c C
ξ
ϖ −
+ ≅
+ +
≅ ⋅ +
+
(5.26)
It is interesting to note that the real part of the complex poles ξϖn only depends on the cascode
transistor transconductance and can be written as:
5
12
n
out C
out C
gm
c Cc
c C
ξϖ =
+ +
(5.27)
Solving the equations system (5.26) in order to gm5 and gm11 the project equations relating the
incremental transconductances of the transistors M5 and M11 with the non-dominant poles location,
can be obtained.
5 1
11
2
11
out Cn
out C
n out
c Cgm c
c C
cgm
ξϖ
ϖ
ξ
= +
+
= +
(5.28)
The expression for the real symmetric zeros pair is given by
(5.29)
Replacing expression (5.28) in (5.29, a new expression for the symmetrical real zeros pair is obtained,
which is independent from the transconductances gm5 and gm11
60
1
1
1 outout
C
z n
C
cc c
Crad s
Cω ω −
+ +
= ± ⋅
(5.30)
If it is assumed that the compensation capacitor CC and the output capacitance cout are of the same
order of magnitude and that the capacitor c1 is despicable when compared to the prior ones, then a
simplified expression for the symmetrical zeros pair is given by
1out
z n
C
crad s
Cω ω − ≅ ± ⋅
(5.31)
Note that once the values for gm5 and gm11 are defined, the symmetrical zeros pair frequency
depends only of the specifications (ωn, cout and CC). Consequently, it can be concluded that the
symmetrical zeros pair frequency ωz and the natural frequency of the complex non-dominant poles
pair ωn are of the same order of magnitude, whenever the previous assumptions are valid.
Once the project equations relating circuit parameters and poles and zeros frequencies are deduced,
it is necessary to define their location.
In switched-capacitors circuits the settling time of the operational amplifier must be minimized and it is
closely related to its impulsive response. It is important to define the non-dominant poles and zeros
location on the complex plane.
A proper analysis of the settling time in 3rd
order systems [Mar1998a], allows a decision about the
location of the zeros and non-dominant poles to minimize the settling time,
1 2
0,9
2,4
2
n d
z z d
ξ
ω ω
ω ω ω
=
= = − =
(5.32)
where ωd is the closed-loop dominant-pole frequency, which is equal to GBWβ, where β is the circuit
feedback factor.
From the GBW specification, and for a given β, determined by the circuit topology, it is possible to
obtain the transconductances for the cascode transistor M5 and for the second-stage gain transistor
M11 for optimal impulsive response.
5.2.3 Noise
From Figure 5.4, the devices that contribute to the noise of the operational amplifier are transistors M1,
M3, M9, M6, M5 M13 and M11 (half of fully-differential circuit), but the contributions of the last two when
61
referred to the input of the OpAmp, are attenuated by the output-stage gain, thus being considered
despicable. It is also considered that, as referred in Appendix1, within certain limits, Flicker noise can
be made as small as it is wanted, and therefore is not included in this analysis.
Considering each MOS transistor thermal noise, expression (A1.7, and applying the superposition
theorem, the power sum of the several noise contributions is obtained, and the PSD of the OpAmp’s
thermal noise referred to its input is given by,
( ) 2
( ),
1
8 1
3VN T OAS f kT m V Hz
gm =
(5.33)
where m is
3 9 5 7
1 1 1 1
1gm gm gm gm
mgm gm gm gm
= + + + +
(5.34)
This factor m represents the same factor of the expressions (A1.22) and (A1.23) and it represents the
noise contribution of the transistors others than the differential pair one. To make the OpAmp’s noise
dominated by the differential pair, it is necessary to make gm3, gm9, gm5 and gm7 a few times smaller
than gm1. To reduce the factor m, the transconductances of transistors M3 and M9 must be decreased
by maximizing their overdrive voltages 2and the differential pair transconductance gm1 must be
increased by minimizing its overdrive voltage, by placing it in the weak inversion region (between
40mV and 80mV).
The minimum value for the compensation capacitor of the operational amplifier (half of a fully-
differential) for a given specification can be calculated from the expression (A1.26) which is repeated
here for convenience:
( )
2 2
2 2
, , 2
2
3
i f
N T OA INT
C i
g gkTV m V
C OSR gβ +
=
(5.35)
5.2.4 Offset voltage
The offset voltage analysis of an operational amplifier is similar to the one performed for the noise,
given the fact that the offset voltage can be considered as continuous noise (with zero frequency), as
its value does not change over time.
The differential offset voltage referred to the input of the operational amplifier, measured as a standard
deviation is given by
(5.36)
2 It represents the strength of the channel and is usually given by VOD=VGS-VTH.
62
where σ(∆VTHk) represents the threshold standard deviation of the MOS transistor Mk, which can be
related to its physical dimensions
( ) [ ]1
VTTH
AV V
WLσ ∆ = (5.37)
where AVT is a technology parameter for MOS devices.
From the observation of the expression (5.36), if the transconductance of the transistor M3 is a few
times smaller than the transconductance of transistor M1, the OpAmp’s offset voltage is dominated by
the contribution of the differential pair, thus its area must be properly chosen.
5.2.5 Slew-rate
The amount of current an amplifier with a class-A output stage can supply to a load is limited by the
polarization of the output stage. In switched-capacitors circuits the load is predominantly capacitive
and this, there is a limit for the output voltage variation. This limit is called slew-rate, it comes from the
equation that relates the instantaneous values of current and voltage on a capacitor (iC=C.dVC/dT) and
can occur in the output node as well as in internal ones.
The slew-rate specification determines the minimum value for the bias current of the output stage.
Assuming a fully-differential amplifier is loaded at each single output with a capacitance CL3, the non-
differential slew-rate is given by
[ ]2
L
ISR V s
C= (5.38)
where I2 represents the bias current of the output stage of the operational amplifier. In addition, some
attention has to be paid to the slew-rate at the output of the first-stage of the amplifier (drain of
transistor M6), as there is also an equivalent capacitor due to CC.
5.2.6 Distortion
In linear circuits, the non-linear distortion effect is caused generally by the relative current variation in
transistors. To analyze the distortion in an OpAmp it is necessary to analyze the transistors that have
the highest relative bias current variation, which normally occur at the output stage.
To ensure the desired distortion level, it is necessary to design properly (i) the relative output-stage
bias current variation and (ii) the amplifier’s gain at the maximum signal frequency (GBW design).
3 Equivalent to a differential load capacitance 2CL.
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5.2.7 Project
Usually, the project of an operational amplifier is an iterative process supported in a Spice like
simulation tool. However, this process tens to be slow and inefficient in terms of the quality of the
project when the designer does not make a critical analysis.
This section describes the project flow that allows the initial project of a programmable two-stage
operational amplifier with cascode compensation, used in the integrators of the Σ−∆ modulator.
Compensation capacitor
From expression (5.35) the minimum value for the compensation capacitor CC can be calculated to
guarantee the noise specification of the operational amplifier, assuming m=3 (to have some margin
during the design). If the capacitor value is too small (smaller than 100fF for instance) it is convenient
to use a higher value so the frequency compensation does not become too dependent of the parasitic
capacitances (badly controlled).
The tightest noise specification is for the GSM standard – 70dB – and in order to ensure that the
operational amplifier complies with this specification, the compensation capacitor value is chosen
according to this specification.
First-stage
With the obtained value for the compensation capacitor CC, it is possible to calculate the differential
pair transconductance (gm1) that satisfies the gain-bandwidth product (GBW) specification, or in
particular the circuit one (GBWβ).
From the tightest GBWβ specification, which corresponds to the DVB-H standard, the value for gm1 is
calculated. From this value it is possible to calculate the input stage bias current. Considering that
different GBWβ specifications generate different gm1 and consequently different input stage bias
current, it is possible to change the transconductance gm1 according to each mode specification. This
is done by creating a programmable bias circuit, which depending on the active mode, generates
different bias current for the input-stage.
From the consumption point of view, it is better to bias the differential pair in weak inversion region
because that is where the maximum transconductance value can be obtained for the same bias
current. From the noise and offset voltage point of view it is also beneficial to bias the differential pair
in the weak inversion region to minimize the quotient gm3/gm1, making those parameters dominated
by the differential pair. For higher frequencies sometimes it is not possible to bias the differential pair
in the weak inversion region, as the transition frequency4 (fT) is minimal.
It is also important to note that, placing an input differential pair transistor biased in the saturation with
a fixed bias current in the weak inversion region corresponds to increasing the W/L relation. For a
fixed L this corresponds to increasing the parameter W, thus increasing the input parasitic capacitance
4 Frequency at which the transistor yields unity gain.
64
of the operational amplifier. This parasitic capacitance tents do decrease the circuit feedback factor
(β), which has to be compensated with an increase in the GBW, resulting in a consumption increase.
A compromise must be achieved between maximum transconductance for a given bias current (weak
inversion) and the minimum input parasitic capacitance (strong inversion).
The cascode transistor conductance gm5 determines the real part of the complex non-dominant poles
pair. Once established their optimum location, from expression (5.27) it is possible to obtain gm5. It is
also best to bias this cascode transistor in the weak inversion region to obtain the maximum
transconductance for the same bias current, which increases its noise contribution.
The transistors functioning as current sources (M3 and M9) must be biased with the maximum possible
overdrive voltage, in order to minimize the mirroring errors. This value is only limited by the voltage
swing in each node, so that none of the involved transistors enter the triode region.
Second-stage
The bias current of the second-stage is the maximum between three values: (i) the minimum current
that satisfies the slew-rate specification (given by expression (5.38)), (ii) the minimum current that
generates enough transconductance to place the non-dominant poles at a frequency sufficiently
higher than the GBW and therefore ensure the phase margin specification (continuous circuits) or
settling time (sampled circuits) (given by expression (5.28)) and (iii) the minimum current required to
guarantee the distortion specification. Normally in continuous time circuits the current is dominated by
second or third factor, while in switched-capacitors circuits any of the factors can dominate.
To ensure the correct location of the non-dominant poles for each mode, it is possible to change the
transconductance gm11 depending on the active mode. This way, the consumption is also optimized
for each mode. This is done with a programmable bias circuit, just like the one used for the input-
stage. To maximize both the output signal swing and the maximum transconductance for the same
bias current it is best to use low overdrive voltages.
5.2.8 Common-mode feedback circuit
Being a fully-differential operational amplifier, it requires a common-mode feedback circuit that
controls the common-mode voltage of the outputs, normally half of the supply voltage. This circuit is
usually referred to as the common-mode feedback (CMFB) circuit.
There are two typical ways to design CMFB circuits: continuous-time and switched-capacitors circuits,
[Johns1997]. The former approach is frequently the limiting factor on maximizing signal swings, and if
nonlinear, may even introduce common-mode signals. The latter approach is usually only used in
switched-capacitors circuits, since in continuous-time applications it introduces clock-feedthrough
glitches.
The CMFB circuit used is a switch-capacitors implementation, Figure 5.6. The capacitors CC generate
the average of the output voltages. The DC voltage across CC is determined by capacitors CS, which
65
are switched between the desired common-mode voltage and being in parallel with CC. During phase
Φ2d, the switched capacitors CS define the proper voltage on the sense capacitors. It is necessary to
use a negative gain amplifier, as the CMFB circuit output voltage (VBNS) actuates on the NMOS current
source transistors M3 and M4 (Figure 5.4) - an increase in the ouput common-mode voltage must be
compensate with a decrease in bias voltage of the transistors M3 and M4.
Figure 5.6. Common-Mode Feedback circuit for the operational amplifier.
The common-mode feedback circuit must have sufficient GBW and ADC to ensure the proper
functioning of the OpAmp.
5.2.9 Bias Circuit
The bias circuit used for the operational amplifier is show in Figure 5.7. For proper biasing, high-swing
cascode biasing is used. Detailed information about biasing circuits, namely the high-swing cascode,
can be consulted in e.g. [Johns1997].
As referred in section 5.2.7, both input-stage and output-stage bias current depends on the active
mode. The programming of the amplifier is done by the bias current selection vector IB<1:0> that
selects more or less current to the bias circuitry (IIN), according to the selected mode, Table 5.6.. Note
that the bias voltages for the differential pair bias transistor M15 (VBPS) is the same bias voltage for the
folded-cascode PMOS current-sources transistors M9 and M10 (VBPL). The power-down transistors are
not presented in Figure 5.7, for a matter of simplicity.
Each operational amplifier used in the integrators has a similar biasing circuit. The difference is in the
specifications, and therefore, different transconductance values are generated.
66
Figure 5.7. OpAmp bias circuit.
Table 5.6. Bias current programming.
Mode IB<1:0> IIN
1 - GSM 11 0,4
2 – CDMA2000 10 0,5
3 – UMTS 01 0,75
4 – DVB-H 00 1
5.3 Internal A/D Converter
The block referred to as internal A/D converter is responsible for the internal quantification process of
the Σ−∆ modulator. The converter chosen is the flash ADC, since this topology has the highest
conversion ratio and is conceptually the simplest to implement. All digital signals are generated
simultaneously, thus its latency is very low (being limited essentially by the dynamic characteristics of
the comparators). For this work, the flash ADC block does not present problems in terms of project
effort and area occupation, given the reduced number of implemented quantification levels (12).
In this work, for simulation purposes, it was used an already designed 12-level flash ADC (it does not
limit the performance of the system). Nevertheless, this section presents the main constraints in the
design of a flash converter, show in Figure 5.8. A complete design procedure for the flash ADC can be
consulted in [Tavares2002].
From Figure 5.8, a string of resistor divides the differential reference voltage (VREF=VREF,P – VREF,N) in a
set of 12 transition voltages that define the 12 quantification levels of the converter. The input signal is
compared, in parallel, with these transition voltages, through the use of 12 identical comparators, that
generate a thermometer coded output. The comparators are implemented in a switched-capacitors
topology, using the clock phases of the Σ−∆ modulator. The circuit is fully-differential, i.e. each
67
comparator compares the differential input signal (inp-inn) with a differential voltage (lkp-lkn, where k
can be any value between 1 and 6).
Figure 5.8. Simplified schematic of the internal Flash A/D converter.
5.3.1 Resolution
The resolution of the converter is limited, mainly by the precision of the transition voltages. The non-
ideal factors that can degrade the references values are: (i) static precision, (ii) dynamic
characteristics of the resistors string and (iii) the performance of the comparators.
To prevent comparison errors, the absolute error of the differential voltage has to be lower than half
the amplitude of a LSB:
max
142
2LSBV mVε = = (5.39)
68
5.3.2 Comparator
Figure 5.9 presents a simplified electrical schematic of the comparator. The circuit is constituted by a
switched-capacitor (C1p(n)) that alternatively connects to a reference voltage and to the input signal
through a latched-comparator with a pre-amplifier employing the auto-zero technique [Moreno1996].
During clock phase Φ1d the capacitor stores a charge that at its terminal the voltage is equal to vrefp(n)
In the next clock phase Φ2d, the capacitor’s voltage is subtracted to the input signal and the result is
amplified by the pre-amplifier and then is applied to the latched-comparator that generates the
correspondent logic level at the output.
Figure 5.9. Simplified electrical schematic of the latched-comparator.
If the comparator did not have the pre-amplifier, the offset input voltage of the latched-comparator (can
easily reach 100mV) is higher than the maximum error allowed (42mV). Also, the parasitic input
capacitance of the comparator (some dozens of fF) creates a capacitive divider that attenuates
considerably the input signal amplitude, making it necessary an increase in the comparator’s
resolution specification.
The pre-amplifier before the latched-comparator using an auto-zero technique, minimizes its offset
voltage, and the offset voltage of the comparator when referred to the input of the pre-amplifier,
appears attenuated by the pre-amplifier gain. The pre-amplifier is also used to amplify the input signal.
The input differential voltage of the latched-comparator is
( ) ( ) 1
1
V
par
Cincp incn vinp vinn vrefp vrefn A
C C − = − + − +
(5.40)
Where C1 is the sampling capacitance, Cpar is the pre-amplifier input parasitic capacitance and AV is
the voltage gain of the pre-amplifier (normally between 4 and 10, although it may simply be a unity-
gain buffer).
The value chosen for C1 is about 20fF. This is a sufficiently low value, so minimum dimension switches
can be used to switch C1 without introducing high value parasitic capacitances, and allows the
implementation of a resistor divider with a sufficiently high value, so its consumption is not significant.
69
Pre-Amplifier
The project and design of the pre-amplifier does not bring any particular difficulties. It can be easily
implement with a one-stage amplifier with an input differential pair and NMOS transistors as active
load. [Johns1997].
Latched-Comparator
Figure 5.10 presents the simplified electrical schematic of the latched-comparator. The dynamic
characteristics of the comparator are very important, since the available time for the output signal to
be defined is lower than half of clock period5.
The design of the latch and of the inverters is not problematic. In specialized literature, [Baker2008],
several design options are shown. The switches can be realized with the minimum dimensions.
Figure 5.10. Simplified electrical schematic of the latched-comparator.
5.3.3 Resistors String
The design of the resistors that constitute the flash ADC resistive divider results from a compromise
between two factors: (i) the settling error of the transition voltages and (ii) the power consumption of
the voltage references generator (VREF,P and VREF,N).
To avoid comparison errors, it must be assured that at the instant the reference voltages are observed
(at the end of the clock phase Φ1d), their values are well settled (with an error), thus the RC time
constant must be properly designed.
The switched-capacitors of each of the 12 comparators are connected to the resistors divider
simultaneously. Being fully-differential, each comparator has two outputs connected to each transition
voltage. This means that in the sampling instant of the reference voltages, there are two capacitors
connected to the reference node at the same time, and so a rigorous analysis of the equivalent circuit
5 Taking into account the delays between delayed and non-delayed phases (ph1 and ph1d; ph2 and ph2d) and
the superposition times between phases (ph1 and ph2; ph1d and ph2d), the effect time interval in which each phase is active is less than half clock period.
70
is not trivial and it must be considered as a distributed circuit. From this analysis, which is not on the
scope of this thesis, the value of the total resistance (Rtotal) can be calculated.
The expressions that define the resistors value, as functions of the reference voltages and transition
voltages are
0
, ,
1
, ,
,
6
, ,
, 1, 2,3, 4,5
ktotal
REF P REF N
k kk total
REF P REF N
REF P k
total
REF P REF N
lR R
V V
l lR R k
V V
V lR R
V V
+
=
− −
= =−
− =
−
(5.41)
where lk represents the value of the transition k voltage.
5.4 DWA DAC
The output signal of the Σ−∆ modulator is obtained through the internal 12-level flash ADC (about 3,5
bit) that quantifies the output of the 3rd
integrator. This signal is then applied to an internal feedback
DAC that assures the closing of the loop of the modulator.
The DAC is implemented by a matrix of unity capacitor in each integrator. The mismatch between the
several capacitors represent distortion directly added at the output of the modulator, thus the linearity
of the internal DAC limits the resolution of the entire system.
In current technologies it is possible to obtain a mismatch between capacitors of about 0,5% to
capacitor values as low as a one hundred fF. This value corresponds to about 6,5 bit of linearity, which
is not sufficient to guarantee the worst mode SNR specification of 64dB.
The use of a DWA dynamic element matching technique improves the linearity of the DAC. As
referred in section 4.3.2, the DWA is the most adequate solution to the linearization of D/A converters
for Σ−∆ modulator.
In this work, for simulation purposes, a DWA already implemented in Verilog was used. Nevertheless,
this section presents the principles of the DWA operation.
The principle behind DWA is the assumption that the errors of the unity elements that constitute the
DAC matrix are randomly distributed. Therefore, if the unity elements are activated in a sequence
determined by the digital word to be converted, the non-linearity error depends only of the average of
the error along the matrix. This effect corresponds to a 1st order high-pass error modulation, which for
the worst mode SNR specification with an OSR of 15, represents an increase in linearity of about
52dB (8,4bit).
71
5.5 Clock Generator
Switched-capacitor circuits require the generation of two-phase non-overlapping clocks with delayed
clocks to reduce signal-dependent charge injection.
The clock generator circuit is a sequential circuit that from a clock reference signal generates several
clock signals with the same frequency, but with different characteristics.
From this circuit it is possible to obtain:
Two opposite-phase and non-overlapping clock signals (Φ1 and Φ2) that implement the
switched-capacitors structures;
Two delayed clocks (Φ1d and Φ2d) that are used to minimize the clock feedthrough
phenomenon associated with the opening of the MOS switches;
Complementary versions of some of the above signals, whenever necessary.
Figure 5.11 shows the time diagram of the input and outputs of the clock generator circuit.
Figure 5.11. Time diagram of the clock signals.
The clock phases generator circuit is no more than a SR (Set-Reset) type bistable circuit, in which the
inputs S and R are excited, respectively, by the clock reference and by the respective complement,
resulting in a D (Data) type bistable circuit. Several delay blocks are added in the respective feedback
loop, allowing the extension of the non-overlapping time (tno) of the resulting clock phases (Φ1 and Φ2).
The delay introduced by these blocks, implemented as slow inverters, should be designed to
guarantee that every switch commanded by a given phase (e.g Φ1) is completely deactivated
(transistors in the cut region) before the next phase (eg. Φ2) is activated. With this condition, it is
assured that the switched nodes are never simultaneously connected to two different voltage sources,
which would cause the circuit to work improperly.
Figure 5.12 shows the electrical schematic of the clock generator circuit implemented.
72
Figure 5.12. Electrical schematic of the clock generator circuit.
The circuit is implemented in CMOS technology, thus the power consumption of the circuit is
associated with the charge and discharge of the internal parasitic capacitances and load of the circuit.
From the design point view, the transistor dimensions must be made as small as possible, but they
must guarantee the delay, transition and non-overlapping times specified.
From the simulation point of view, it should be verified that the circuit works for every temperature,
supply voltage and technology parameters and with the equivalent switches capacitances and
respects the following parameters:
Minimum non-overlapping interval between active phases (tno);
Maximum transition time in each phase (rise time and fall time);
Minimum/maximum delay between phases for the purpose of cancelation of the clock
feedthrough.
73
Chapter 6
Results
This chapter present the most important results obtained through electrical simulation of the designed
system, in the HSpice environment.
The design of the system is validated through electrical simulation in every functioning conditions
(temperature and voltage supply) and considering the process variations specified by TSMC (MOS
transistors, resistances and capacitances). A Montecarlo6 statistic simulation with 30 iterations
7 and
Gaussian distribution functions is performed for blocks where their performance depends on a good
match between transistors.
To validate the performance of the system (SNR), only the results for the worst-case SNR mode
(Mode 1 – GSM) and worst-case signal bandwidth and OSR mode (Mode 4 – DVB-H) are presented.
Table 6.1 presents the types of electrical simulations performed to evaluate the system. Depending on
the complexity and specifications of each block, all or some simulations are performed.
Table 6.1. Types of electrical simulations performed
Code Type of Simulation Conditions Results
OP Operating point closed-loop analysis
MOS, Rpoly and Cpoly variations;
T ∈ [-40;125] ºC;
VDD ∈ [0,95;1,05] V
Monte Carlo simulation with 30 iterations
Voltages and currents of the transistors;
Saturation margin:
AC_OLOOP Open-loop frequency analysis
DC Gain;
GBW;
PM.
AC_NOISE Closed-loop noise analysis Noise Power (Thermal+Flicker)
AC_PSR Power-Supply Rejection analysis PSSR
TR_SETT Transient settling analysis MOS, Rpoly and Cpoly variations;
T ∈ [-40;125] ºC;
Vdd ∈ [0,95;1,05] V
nτ
TR_SNR SNR analysis SNR
6 The Montecarlo simulation principle is based on a random number generator that creates random distributions
of parameters (Gaussian, uniform or limited) for electrical simulation. 7 According to the HSpice manual, if the circuit functions properly for all the 30 iterations, there is a 99%
probability that it will work for, at least, 80% of the possible parameters values.
74
6.1 1st Integrator
The loop feedbacks are different in each phase and therefore, both phases of functioning must be
analyzed.
The bode diagrams of the 1st integrator for both phases of Mode 1 – GSM are shown in Figure 6.1.
Figure 6.1. Bode diagram of the 1st
integrator, Mode 1 – GSM.
The bode diagrams of the 1st integrator for both phases of Mode 2 – CDMA20000 are shown in Figure
6.2.
Figure 6.2. Bode diagram of the 1st
integrator, Mode 2 – CDMA2000.
75
The impulsive responses of the 1st integrator for Mode 1 – GSM and Mode 2 – CDMA2000 are
presented in Figure 6.3.
Figure 6.3. Impulsive response of the 1st
integrator for Mode 1 –GSM and Mode 2 – CDMA2000.
Table 6.2 summarizes the results of OP, AC_OLOOP and TR_SETT simulations for Mode 1 – GSM
and Mode 2 – CDMA2000.
Table 6.2. Results of Operating Point, AC and Settling simulations for the 1
st integrator for GSM and
CDMA2000.
Mode 1 Mode 2
Differential Amplifier GSM CDMA2000
Operating Point Min. Typ. Max. Min. Typ. Max. Units
VOS,dif Output differential Offset voltage < 24,6 < 24,3 mV
IDD Current consumption 0,568 0,704 0,894 0,788 0,972 1,190 mA
ADC DC Gain 44,7 61,6 67,5 46,5 61,9 67,7 dB
AC Analysis
GBW Open-loop Gain-bandwidth product
- Phase F1 - Phase F2
67,0
66,4
102,0
100,0
153,0
151,0
89,9
89,1
137,0
135,0
207,0
203,0
MHz
PM Phase Margin
- Phase F1 - Phase F2
62,9
63,7
64,9
65,7
70,3
71,3
62,4
63,2
64,5
65,3
70,1
71,1
º
Settling Analysis
nττττ 1st order settling time constants > 8,8 > 10 τ
76
The bode diagrams of the 1st integrator for both phases of Mode 3 – UMTS are shown in Figure 6.4
Figure 6.4. Bode diagram of the 1st
integrator, Mode 3 – UMTS.
The bode diagrams of the 1st integrator for both phases of the Mode 4 – DVB-H are shown in Figure
6.5.
Figure 6.5. Bode diagram of the 1st
integrator, Mode 4 – DVB-H.
The impulsive responses of the 1st integrator for Mode 3 – UMTS and Mode 4 – DVB-H are presented
in Figure 6.6.
Table 6.3 summarizes the results of OP, AC_OLOOP and TR_SETT simulations for Mode 3 – UMTS
and Mode 4 – DVB-H.
77
Figure 6.6. Impulsive response of the 1st
integrator for Mode 3 – UMTS and Mode 4 – DVB-H
Table 6.3. Results of Operating Point, AC and Settling simulations for the 1st
integrator for UMTS and DVB-H.
Mode 3 Mode 4
Differential Amplifier UMTS DVB-H
Operating Point Min. Typ. Max. Min. Typ. Max. Units
VOS,di Output differential Offset voltage <23,8 <23,1 mV
IDD Current consumption 1,093 1,305 1,600 1,745 2,075 2,475 mA
ADC DC Gain 48,4 61,9 67,8 51,5 61,9 67,7 dB
AC Analysis
GBW Open-loop Gain-bandwidth product
- Phase F1 - Phase F2
119,0
117,0
178,0
175,0
272,0
268,0
177,0
174,0
261,0
257,0
270,0
265,0
MHz
PM Phase Margin
- Phase F1 - Phase F2
61,9
62,8
64,1
65,0
69,7
70,8
61,0
61,9
63,5
64,4
68,9
70,2
º
Settling Analysis
nττττ 1st order settling time constants > 7,5 > 5,6 τ
Results from Table 6.2 and Table 6.3 show that the 1st integrator presents stability greater than 60º in
any clock phase and for all modes. From Figure 6.3 and Figure 6.6 it is possible to verify that the time
response of the 1st integrator is very stable and with number of time constants nτ always greater than
5,6τ.
78
Operating Point and open loop AC simulations are also performed to verify the behavior of the CMFB
circuit, namely its stability. The results for Mode 1 – GSM and for Mode 2 – CDMA2000 are
summarized in Table 6.4 and results for Mode 3 – UMTS and Mode 4 – DVB-H are summarized in
Table 6.5.
Table 6.4. Results of Operating Point and AC simulation for the CMFB circuit for GSM and CDMA2000.
Mode 1 Mode 2
Common-Mode Amplifier GSM CDMA2000
Operating Point Min. Typ. Max. Min. Typ. Max. Units
VOS,c Output differential Offset voltage <28,2 <27,9 mV
ADC DC Gain 34,8 48,1 54,6 36,3 48,6 54,9 dB
AC Analysis
GBW Open-loop Gain-bandwidth product
- Phase F1 - Phase F2
14,3
12,5
19,2
16,9
29,3
24,7
18,9
16,6
25,1
22,1
38,0
31,8
MHz
PM Phase Margin
- Phase F1 - Phase F2
79,1
81,4
81,6
82,6
83,3
84,2
78,8
81,3
81,3
82,5
82,8
83,8
º
Table 6.5. Results of Operating Point and AC simulation for the CMFB circuit for UMTS and DVB-H.
Mode 3 Mode 4
Common-Mode Amplifier UMTS DVB-H
Operating Point Min. Typ. Max. Min. Typ. Max. Units
VOS,cm Output differential Offset voltage <28,0 <29,1 mV
ADC DC Gain 37,9 48,9 55,1 39,7 48,8 55,0 dB
AC Analysis
GBW Open-loop Gain-bandwidth product
- Phase F1 - Phase F2
24,4
21,4
32,1
28,0
49,0
41,1
34,9
30,1
46,2
39,1
69,4
57,5
MHz
PM Phase Margin
- Phase F1 - Phase F2
78,4
81,2
81,0
82,3
82,3
83,5
77,9
81,1
80,5
82,1
81,5
83,0
º
AC_NOISE and AC_PSR simulations are also performed to evaluate the noise power level at the input
of the 1st integrator, and to evaluate the power supply and ground noise. The results of the AC_NOISE
and AC_PSR simulations are summarized in Table 6.6.
79
Table 6.6. Results of Noise simulation for all modes.