Mobile SoC Verification

Full Chip Verification of Hardware, Software, and Peripherals

Chen, ZaiMan

Emulation Business Development Manager, Mentor

Mobile SoC Verification

© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com

Agenda

Trends and challenges in system-on-chip verification

Mentor’s solution for Multi-core SOC chip verification

Summary

Total SOC Verification TDF 20122


78% of all Designs Have Embedded Processors

0%

10%

20%

30%

40%

50%

60%

NONE 1 2 3 4 5 or MORE

2004

2007

2010Resp

on

ses

Wilson Research Group and Mentor Graphics2010 Functional Verification Study, Used with permission

3 Total SOC Verification TDF 2012

2004 – mean # embedded processor 1.06 2007 – mean # embedded processor 1.46 2010 – mean # embedded processor 2.14

Wilson Research Group


ARM Embedded Processors Dominate SoC

40%

54%

0%

10%

20%

30%

40%

50%

60%

2007

2010

Resp

on

ses

Wilson Research Group and Mentor Graphics2010 Functional Verification Study, Used with permission

4 Total SOC Verification TDF 2012

35% increase in ARM embedded processor core adoption!

Wilson Research Group


What’s changed in design and verification?Trends: It’s the software—stupid! -Gary Smith


Source: 2007 ITRS Roadmap

2009 2010 2011f 2012f0

20

40

60

80

100

120

Impact of Design Technology on SOC Consumer Portable Implementation Cost

Hardware Costs

Software Costs

$ U

S M

illio

ns

Software is fastest growing component of SoC development cost

All this software requires a lot of verification!

© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.comRAK Sept 2008

Flatline

What do you do when your processor goes into “flatline” or just stops working?


Agenda

Trends and challenges in system-on-chip verification

Mentor’s solution for Multi-core SOC chip verification

Summary



Driving the Virtual Target Environment


USB PCIe

Physical Peripherals (ICE)Physical I/O

Transactors (xMVCs)

OVM/UVM SystemVerilog SystemC

Simulation Acceleration

Testb

ench

Xpre

ss

....iSolve

Design IP and virtual iSolve

USB

Virtual PeripheralsPCIe Video

Ethernet

....

Debug Port Transactor (JTAG)

Codelink

SW Debug VStrea

m

8

Video JTAG

Co-M

od

el

Ch

an

nel


Veloce Family


Use Model Simulation Acceleration

Simulation Acceleration,

ICE


ICE


ICE


ICE

TargetDesign Team Acceleration

Design Team Acceleration/Emulatio

n

Verification Team Acceleration/Emulation



# of Users 3 Users 1 User Up to 4 Users Up to 8 Users Up to 4 Users

Design SizeTypical

12MG/user12 MG 100 MG 200 MG 400 MG

Memory 0.5 or 1GB/User 0.5 or 1GB 0.5 to 8GB 0.5 to 16GB 0.5 to 32GB

Performance Up to 1.5 MHz Up to 1.5 MHz Up to 1.5 MHz Up to 1.0 MHz Up to 1.0 MHz

Compile Performance

Up to 15 MG/hour

Up to 15 MG/hour Up to 15 MG/hour Up to 15 MG/hour Up to 15 MG/hour

Veloce Solo Veloce QuattroVeloce Trio Veloce Grande

Single Silicon Technology, Common Logic Board, Compile S/W, Debug/UI

Veloce Maximus


Emulate a Mobile chip on Veloce

R&S EX-IQ

R&S CMW500

UE BaseBand chip

R&S SMU200

Analyze

R&S FSV/FSU

R&S Ex-IQ Box iSolve DigIQ I/F

Stimulus Gen

Protocol Test

Digital IQ interface– EX-IQ box: Adapting the R&S

I/Q-interface for Emulation (iSolve DigIQ)

– Reduced system clock rate Slow IQ to adapt from full speeds to SoC Emulation


Codelink Architecture - Velcoe

11

SW Debugger

Waveform View

CodelinkReplayServer

ReplayDatabase

Standard GDBRSP interface

© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com12

Hardware/Software Correlation


Economical Support for Many SW Engineers

Support 10 times more SW engineers

Non-intrusive multi-core debug

Synchronized SW and HW views

10 times faster than JTAGTotal SOC Verification TDF 2012

Codelink offline SW debug

JTAG probe

Codelink logfiles

Batch runs

4 hour session typical for online SW debug

Digital camera batch run was 20 minutes

Run 12 batch jobs in 4 hours

13

JTAG online debug


SW Development

Functional Verification Trends- Emulation used for Software Development and Integration

Reduce time-to-market Start software earlier Verify hardware with software Perform hardware/software trade-off

analysis Correct functional, architectural and

performance issues in hardware before tape-out rather than in software later

Time-to-Market Reduced

Large Time-to-Market potential

SW Development

Integration

HW Development Fab

TraditionalVerification Flow

Integration

HW Development Fab

Hardware AssistedVerification Flow


Summary

DAC 201215

• HW/SW co-verification becomes more challenging and important

• Veloce + Tester can help you to setup system level verification solution

• Veloce + Codelink can provide unique methodology in SW/HW co-verification

© 2010 Mentor Graphics Corp. Company Confidentialwww.mentor.com16 DAC 2012

Mobile SoC Verification

Documents

mentor mobile soc verification

company confidentialwww

lot of verification

verification todayand

compresentation title

chip verification of

month year

embedded processor trends