MOBILE AGENT HARDWARE DESIGN FOR DISTRIBUTED WIRELESS NETWORKS Sergey Ovcharenko Master of Technology of Electronic Equipment, Kharkov Aviation Institute, 1984 PROJECT SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF ENGINEERING In the School of Engineering Science of School of Applied Science O Sergey Ovcharenko 2006 SIMON FRASER UNIVERSITY Spring 2006 All rights reserved. This work may not be reproduced in whole or in part, by photocopy or other means, without permission of the author.
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MOBILE AGENT HARDWARE DESIGN FOR DISTRIBUTED WIRELESS NETWORKS
Sergey Ovcharenko Master of Technology of Electronic Equipment, Kharkov Aviation Institute,
1984
PROJECT SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF
MASTER OF ENGINEERING
In the School of Engineering Science
of School of Applied Science
O Sergey Ovcharenko 2006
SIMON FRASER UNIVERSITY
Spring 2006
All rights reserved. This work may not be reproduced in whole or in part, by photocopy
or other means, without permission of the author.
APPROVAL
Name:
Degree:
Title of Project:
Sergey Ovcharenko
Master of Engineering
Mobile Agent Hardware Design for Distributed Wireless Networks
Examining Committee:
Chair: Professor of School of Engineering Science Dr. Ljiljana Trajkovic
Date DefendedIApproved:
Senior ~ u ~ e & i s o r Professor of School of Engineering Science Dr. William A. Gruver
'a' SIMON FRASER W ~ ~ ~ l ~ ~ s d i b r a r y %%&
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ABSTRACT
For more than a century, the communications systems have been evolving
towards hierarchical networking architectures. The central problem in such networks is
that the communications domain is a separate entity to the applications domain. With the
advent of powerful and small microcontrollers and cheap memory, it is now feasible to
start merging these two domains into one Holonic domain, where all contributing nodes
participate together providing both roles of communication and application functionality.
A flatter network infrastructure becomes possible, and the entire system of nodes can be
viewed as a distributed intelligent system.
This report is based upon the examination and design of an electronic device
enabling the development of distributed intelligent systems. Specifically focusing on the
key hardware requirements for constructing a small modular package for communication,
data processing, and memory support for a wireless distributed intelligent system.
Dedication ......................................................................................................................... iv
Acknowledgements ............................................................................................................ v
............................................................................................................. Table of Contents vi ...
List of Figures ................................................................................................................ VIII
...................................................................................................................... List of Tables x
............................................................................................................................ Glossary xi
1 Introduction ................................................................................................................ 1 ................................................................ 1.1 Conventional Communication Systems 2
1.2 Distributed Systems vs . Centralized Systems ....................................................... 3 1.2.1 Degrees of Distribution .................................................................................. 4 1.2.2 Existing Decentralised Systems ..................................................................... 9
....................................................................... 1.3 Holonic Communication Systems 14 1.3.1 Holonic Systems ........................................................................................... 14
............ 1.3.2 Holonic Systems as An Alternative to Traditional Communication 15 1.4 Scope of the Design ............................................................................................. 17
..................................................................... 2.3.1 Non-volatile Memory Devices 23 2.3.2 Volatile Memory Devices ............................................................................ 40 2.3.3 Comparative Analysis of SRAM and DRAM Devices ................................ 43
2.4 CPU Selection ..................................................................................................... 45 ........................................................................... 2.4.1 Prototype I CPU Solutions 45
..................................................................... 2.5 Components for Wireless Interface 51 ................................................ 2.5.1 Fundamentals of 802.1 1 Wireless Networks 51
............................................................. 3.3.1 Architecture of the HCS Controller 65 ........................................................... 3.3.2 Architecture of the HCS Transceiver 67
................................................................ 3.4 Electrical Circuit Design and Analysis 69 .............................................................. 3.4.1 Characteristics of Micro-controller 69
........................................................................................ 3.4.2 Design Challenges 70 3.4.3 Design Solutions .......................................................................................... 71 3.4.4 Power Distribution ....................................................................................... 77
..................................................................................... 3.4.5 PCB Considerations 78 ......................... 3.5 Comparative Analysis of Prototype I and Prototype 11 Designs 91
.................................................................. 4 Manufacturing. testing. quality control 92 ................................................................................... 4.1 Design for Manufacturing 92
Figure 1-5 . Steps required to establish data transfer in a purely decentralized P2P network .............................................................................................. 1
Figure 1-6 . An example of a mesh network configuration ............................................. 13
Figure 1-7 . Relation between domains in traditional communication systems .............. 16
Figure 1-8 . Merging communication and application domains in a holonic network ......................................................................................................... 17
Figure 2-2 . Architecture of NOR flash memory ............................................................. 27 Figure 2-3 . Erase and programming methods of the flash cell ....................................... 29
Figure 2-4 . Architecture of NAND flash memory .......................................................... 33 Figure 2-5 . Organization of a small block 1GBit NAND flash ...................................... 34
Figure 2.6 . Organization of a large block 1Gbit NAND flash ........................................ 35 Figure 2-7 . SRAM cells: a) typical 4T2R cell, b) 6T-cell .............................................. 41
Figure 2-8 . DRAM cell: a) Schematic representation, b) Planar cross-section .............. 42 Figure 2-9 . Architecture of independent basic service set (IBSS) .................................. 52 Figure 2-1 0 . Architecture of basic service set (BSS) network type .................................. 53 Figure 2-1 1 . Architecture of extended service set (ESS) wireless LAN ........................... 54 Figure 2- 12 . An example of a frequency hopping pattern ................................................ 55 Figure 2- 13 . Three non-overlapping channels of the DSSS 802.1 1 WLAN .................... 57
Figure 2- 14 . Multipath signal propagation ....................................................................... 59 Figure 3-1 . Architecture of the holonic mobile agent ..................................................... 63 Figure 3-2 . Architecture of the holonic mobile agent controller .................................... 67
Figure 3-3 . Architecture of the holonic mobile agent transceiver .................................. 68 Figure 3-4 . Blocks of the PXA270 processor essential for HCS controller design ........ 69 Figure 3-5 . SDRAM array organization ......................................................................... 72 Figure 3.6 . NOR flash array organization ...................................................................... 73 Figure 3-7 . NAND flash array organization ................................................................... 74
Figure 3-8 . Power distribution of the HCS controller ..................................................... 77
Figure 3.9 . HCS controller 8-layer board layer stack-up ................................................ 80 Figure 3.10 . Escape routing for the PXA270 (a) and NOR Flash (b) on the top
layer ......................................................................................................... 1 Figure 3-1 1 . Memory components placement on the board ............................................. 87
Figure 3.12 . 3D model of the top side of the controller board ......................................... 88
Figure 3.13 . 3D model of the bottom side of the controller board ................................... 89
Commercially available NOR flash devices ................................................ 32 Small-block vs . large-block NAND flash performance ............................... 35 Small-block NAND flash devices ................................................................ 36 Large-block NAND flash devices ................................................................ 36
Commercially available ML flash devices ................................................... 38 Serial EEPROMIFLASH devices ................................................................. 39
Random access memory devices .................................................................. 44 Comparative characteristics of the StrongArm family processors ............... 46 Comparative characteristics of some commercially available processors for mobile applications ............................................................... 49 Symbol to frequency mapping in 4 GPSK ................................................... 56 Chip to differential phase mapping in 4 DQPSK ......................................... 57 Commercially available system-in-package 802.1 1 Solutions .................... 62
....................................................................... HCS controller memory map 75 Summary of currently available PCB features ............................................. 78
Design rules for the holonic controller PCB ................................................ 81 Comparative characteristics of Prototype #1 and Prototype #2 ................... 91
Summary of the controller prototypes building costs .................................. 94 Summary of the transceiver prototypes building costs ................................ 94 Total best and worst costs per prototype unit ............................................... 95
Access Point Ball Grid Array Binary Phase Shift Keying Basic Service Set International Telephone and Telegraph Consultative Committee (see ITU) Channel Hot-Electron Injection Chip Select Dynamic Random Access Memory Distribution System Digital Subscriber Line Direct Sequence Spread Spectrum Electroplated Nickel / Immersion Gold Extended Service Set Floating Gate Frequency Hopping Spread Spectrum Fowler-Nordheim Tunnelling Gaussian Frequency Shift Keying General Purpose Input/Output Hot Air Solder Level Holonic Communication System Holonic Intelligence System Holonic Logistic System Holonic Strategic System Integrated Basic Service Set Integrated Circuit Integrated Services '~i~ita1 Network International Telecommunications Union, formerly CCITT Least Significant Bit Most Significant Bit Printed Circuit Board - Synchronous DRAM System-in-Package Surface Mount Design Surface Mount Technology Static Random Access Memory
1 INTRODUCTION
The past century may be recognised as the fastest period of technical progress in
many areas of human life. However, without any doubt it can be called an era of
achievements in communications. During this period, communication systems progressed
from the very simple methods of information exchange to sophisticated techniques,
devices, and equipment. The following is a list of some important dates from the history
of communication systems development.
1876 - telephone invented
1895 - first radio signal sent and received
19 14 - first cross-continental telephone call made
1926 - first radio network, NBC, is formed
1957 - first satellite launched and first case of satellite communication established
1979 - first commercial cellular telephone system deployed in Tokyo
1982 - introduction of TCPIIP by DoD as a standard
1984 - initial deployment of Advanced Mobile Phone Service (AMPS) cellular
system
1984 - introduction of ISDN in CCITT Recommendation I. 120
1989 - DSL designed
199 1 - World-Wide Web (WWW) is released
1.1 Conventional Communication Systems
Traditionally, communication networks have been organized as highly centralized
hierarchical systems, where each device in a given hierarchical layer is connected to a
device in a layer above. Usually, a server or switch links communication units to each
other and to the external world. An example of a contemporary communication network
is presented in Figure 1.1.
Regional Communication
(i/B Metropditan Area Network
Figure 1-1. Architecture of a contemporary communication network
Such networks can be built using different structures. They can be based on
various, or even diverse, communication protocols and mediums, but most have one
feature in common: they are organised as centralised systems incorporating a hierarchical
topology as the fundamental principle of their architecture.
Having been developed for significant time, these systems achieved high
efficiency and have a set of numerous advantages, including:
Good control from top to bottom;
Easily provided security;
High manageability;
Potential for scalability.
However, all these benefits of centralised systems decline with growing
hierarchy:
Resources are not easily available for all participants of the network;
Intelligence is removed from the communication domain;
Control at the top of hierarchy is separated from knowledge at the bottom;
Effectiveness drops and maintenance costs grow.
1.2 Distributed Systems vs. Centralized Systems
As an alternative to widely spread centralised networks, decentra
have been introduced and developed. They are intended to directly
d systems
connect
communicating devices and make their communication more effective. However, most of
such systems implement only some degree of decentralisation and require proper analysis
before classifying them as decentralised or distributed. Some strategies of approach to
analysing a network in terms of distribution are described in the following section.
1.2.1 Degrees of Distribution
Relative centralization or decentralization of the system elements can be
described by degrees of distribution. A collection of system resources may be distributed
in terms of the following characteristics:
Location: physical distances among the elements of a network. It results in
o highly efficient and cost-effective utilization of resources,
o investment concentrated in a single location and resources not duplicated
elsewhere in the system,
o relative ease of enforcing policies and procedures uniformly,
o removing information processing functions from sources of transactions
and the locations of user groups.
Function: position of an activity or responsibility within the structure of a network.
Centralization of function is particularly ineffective if
o different functions are highly interdependent,
o close working contact is required among the functions,
o required to respond to exceptional or unique situations.
Control: disperses responsibilities among different levels of the system.
o applies and enforces policies consistently and uniformly,
o problems solving is removed from their immediate circumstances.
o delays or failures in communication can result in inappropriate decisions.
1.2.1.1 Network configurations
Different network configurations represent different degrees of distribution
required to balance efficiency with effectiveness. Options available to the system
designer include
Centralized processing with remote access
Distributed processing with centralized control
Semi-autonomous distribution of processes
Satellite processing
Standalone facilities with shared resources
Load sharing.
Centralized processing with remote access.
In this structure, network elements serve as terminals that share access to the central host.
This type of network is distributed with respect to input and output hnctions. Processing
and data storage functions are centralized. Terminals submit data to the host, and, under
control of the host, provide outputs. (e.g., ATM machines at banks.)
Distributed processing with centralized control. A supermarket checkout
system is an example of distributed processing with centralized control. In this
configuration, entire processing cycles are performed at the store level. That is, normal
store operation does not depend on intervention from the central computer. However,
control is retained centrally, since the corporate computer could cause either program or
data in the store computers to be updated during any polling cycle.
Semi-autonomous distribution of processing. In this network, the local
computers each act as hosts within their own respective networks of distributed terminals.
Most processing cycles are performed completely at the regional level. The central
computer in this case does not control the processing cycles of the regional systems.
Rather, it collects summaries from the regions periodically.
Satellite processing. Under this approach, the central computer is, in effect,
eliminated and all processors within the network have roughly equal status. That is, none
of the units can be identified as a controller to which others might respond. Thus, a
satellite configuration typically reflects a high degree of regional or divisional autonomy
with minimal central control.
Standalone facilities with shared resources. An example of such a system is a
local area network (LAN) that supports independent operations of numerous units. Each
unit is capable of controlling complete processing cycles without the aid of others.
However, for the reasons of economy, or the need of information sharing, some elements
within the network are shared.
Load sharing. Within such networks, each node is a semi-autonomous processor
capable of executing any task that is presented to the system. Particularly in high volume
applications and during peak periods, contention, or conflicting access demands, might
cause one of the processors to become swamped. [ l ]
1.2.1.2 Network Topologies
To distinguish a centralized system from decentralized system it is appropriate to
consider them in terms of topology. Most of the contemporary communication networks
can be classified according to their topologies as follows.
The most popular and well-known is the centralized type of topology. This system
is utilized by various databases, clientlserver systems and web servers. This type of
systems is depicted in the Figure 1.2.a and characterized by good manageability,
information coherence and security located at a single host. On the other hand, they have
low-level fault tolerance and resistance to external intervention.
a) Centralized
Figure 1-2. Centralized, ring, and
0 0' '
I
b) Ring c) Hierarchical
hi ~erarchical network topologies
The ring systems are built for the communicating devices located nearby. It is
typical for such systems to have high-level manageability, information coherence, fault
tolerance and security. However, these systems are not easily extensible and are easy to
shut down. It can be seen in the Figure 1.2.b.
In the hierarchical systems, information exchange is realized along tree-like paths,
as shown in the Figure 1 . 2 ~ . As a result, they have good scalability combined with
moderate manageability, information coherence, extensibility and fault tolerance,
however, they have low-level security.
Decentralized systems are based on the topology shown in Figure 1.3a. The
devices in such a structure have equal roles and communicate symmetrically. The
advantages of decentralized systems are extensibility, fault tolerance and resistance to
intervention. As weaknesses, they have low manageability, information coherence and
security.
There is also a variety of hybrid topologies available for communication
networks, two examples of which are shown in Figures 1.3b and 1 . 3 ~ .
a) Decentralized b) Centralized + Ring c) Centralized + Decentralized
Figure 1-3. Examples of hybrid network topologies
These systems are recognized for their moderation of advantages pertaining to a
pure topology as a cost for the mitigation of weaknesses due to the merging of two or
more types.
1.2.2 Existing Decentralised Systems
A number of attempts have been made to compromise on shortcomings of
centralised systems. Below, there are some examples of the solutions offered in creating
decentralised networks.
1.2.2.1 Peer-to-Peer Systems
A peer-to-peer (P2P) network is a network in which clients communicate and
share information via large number of ad hoc connections rather than relying on the
network severs. In such a network equal peers act as clients and servers simultaneously.
Numerous P2P networks have been introduced and widely used for data, audio and video
exchange. Such networks as Napster, Kazaa, Gnutella and others use P2P principles for
all purposes or as an extension to a clientlserver structure. Existing architectures can be
classified as [2]:
Hybrid,
Partially Centralized,
Purely Decentralised.
In the Hybrid architecture, a computer that wants to join the network informs the
server about the contents it has. A client sends a request to server, and the server looks
for machines carrying the requested file. After such an owner has been found, a direct
connection between the requester and the file owners is established and data exchange
starts. An example of a Hybrid peer-to-peer architecture can be seen in the Figure 1.4.
Figure 1-4. Hybrid P2P architeicture
Advantages of Hybrid decentralised systems are:
- Simple to implement,
- Quick and efficient in locating data.
The main weakness are susceptibility to censorship, malice attack and technical
failure due to access control maintained by a single entity. For the same reason, these
systems are non-scaIable.
In a Purely Decentralised System., its members do not rely on the information
stored at a single server location, but send broadcast query messages to all neighbours.
Once a response from a node: owning a requested file has been received though the path
along which the request propagated, a. direct connection is established and downloading
begins. An example of request propagation and reply is presented in Figure. 1.5.
/-----,, ( Client r L--_1_1---1
Figure 1-5. Steps required to establish data transfer in a purely decentralized P2P network
Partially Centralised Systems are sfmilair to Purely Centralised and differ from the
former in having super node:^". These s~lpernodes are dynamically selected from the
other network nodes as devices with suffic:ient bandwidth and processing power and are
responsible for servicing a small subpart of the peer network.
As it is has been shown, the P2P so'lution for distribution is realised mlostly on the
application level and does not change physical routing of the information streams.
1.2.2.2 Mesh Networks
A Mesh network is an approach to create a distributed system for routing data,
voice and commands between nodes by employment of hopping from node to node until
continuous communication established. These systems are recognised for their self-
healing, meaning that if a node is broken the communication path can be re-established
via other nodes. Mesh networks especially benefit from implementation of wireless
methods of communication and find application in providing Internet service for houses
and buildings in same neighbourhood, security and surveillance information exchange,
military solutions, etc. An example of a Mesh network configuration and application can
be seen in Figure 1.6.
Networks of this type have been developed by Microsoft, Motorola, Nortel, and
other companies. Among the advantages of mesh networks are
Sharing access to a higher cost infrastructure;
Dynamic routing capabilities;
Applicability to mobile devices;
High reliability.
Figure 1-6. An example of a mesh network configuration
Even though the networks described above and others similar to them are
frequently presented as distributed, they remain centralised from the topological point of
view because they rely on the existing physical network components. The only way to
build a purely distributed system is to abandon approaches and system elements and
realize a new design, an example of which is a Holonic network described in the next
section.
1.3 Holonic Communication Systems
1.3.1 Holonic Systems
Holonic systems are based on highly decentralized communication networks built
from a modular mix of semi-standardized, autonomous, cooperative, and intelligent
elements, called "holons".
The term "holon" was introduced by Arthur Koestler as a combination of the
Greek word "holos" meaning "whole" and the suffix "on", which is present in such
words as proton or electron to portray a particle or part. Thus, holon stands for an entity
that has a dual nature of being seen as a whole for subordinated elements and as a part
when viewed from a higher level of hierarchy.
The physical holons consist of equipment responsible for fulfilment of assigned
tasks and of holonic control devices, providing inter-holon communication, real-time
control, and physical interfaces between processing equipment.
A holonic system targets the following performance features:
Holonic Control Devices (HCD) must be implemented as interoperable and
heterogeneous units organized as a distributed control system;
HCDs must be rapidly automatically reconfigurable by software agents due
to the rapidly reconfigurable physical equipment;
HCDs must provide adequate user interfaces at all functional levels.
These goals can be achieved by fulfilling two basic requirements:
High degree of software encapsulation, portability, and reusability;
Independence of platform and communication layer from the control
applications combined with dynamic self-reorganization
A key component of a holonic communication system is spontaneous networking
that is characterised by the following features and described by Coulouris et a1 in [3]:
Easy connection to a network: A device should be transparently reconfigured
to obtain connectivity when brought into the network.
Easy integration with services: Devices automatically discover what services
are provided by the network.
Limited connectivity: System must respond to the situation when devices
appear and disappear from the network as they travel due to the nature of
mobility.
Security and privacy: While supporting continuously changing number of
mobile agents, the system should provide an adequate level of security
distinguishing eligible participants from intruders.
1.3.2 Holonic Systems as An Alternative to Traditional Communication
If we look at the Holonic network as an alternative to existing communication
structures, it is possible to summarise their features as described below and in Figures
1.7. and 1.8.
Traditional Systems:
Intelligence distributed only at the fringes of the communications network
High network utilization; services are remote requiring large number of hops
c tructure High reliance on single network iinfra,;
- Communications infrastructure only links intelligent systems.
Figure 1-7. Relation between domains in traditionall communication systems.
Holonic Systems:
Applications and Communications Domains are merged to a Holonic Domain
Lower network utilization; services are local to users
Network communication has high, redundancy
Communications infrastructure proviaks an intelligent system.
Figure 1-8. Merging communica~tion and application domains in a holonic network
1.4 Scope of the Design
In order to implement a wireless network system based on a holonic architecture,
the Holonic Technology Platform relies on two major components - Holonic
Communication System (HCS) hardwar'e and Holonic Intelligence System (HIS)
software. The HIS is composed of two sub--systems: Holonic Logistic System (HLS) and
Holonic Strategic System (HSS). The former is responsible for monitoring the
administration functionality of each holon, collecting and managing the resources that are
available throughout the network, and the communication functionality. The latter
coordinates and plans activities between the holons spread over the network [4:1. The HTP
architecture is depicted in Figure 1.9.
To perform strategic analysis, the HSS requests a list of the resources acquired by
each node of the network. The HLS fetches this information from the nodes located
within a specified number of hops. Once the analysis has been completed by the HSS, the
HLS can allocate resources and transfer data. One of the tools the HLS uses to carry out
these duties is based on keeping track of the different network topologies available to the
holon, including Virtual Networks (VN). It is important to provide that several VNs can
be accessed simultaneously.
Figure 1-9. Architecture of the IIolonic Technology .Platform (HTP)
1.4.1 Objectives and Goals
To develop a highly decentralized communication network based on principles of
holonic devices, the objective of this project is to design and build a physical prototype
demonstrating feasibility of this approach and supporting further research in this
direction. The highest level of distribution is to be combined with unconstrained mobility.
Wireless communication provides the best choice to satisfy these requirements.
1.4.2 Design Requirements
As shown above, since mobile holonic devices contain both an information part
and a physical part, and are essentially adaptive agent-machine systems, they are
intended to transmitlreceive, process and store significant volumes of information. This
raises a special set of requirements for the hardware portion of the design:
High volumes of information exchanged between the holons require
a) significant space for data storage;
b) high speed communication channels;
c) high speed data processing.
Mobile devices are to be compact to meet constraints for various
applications.
Hardware design must provide flexibility to change the communication
protocol/medium, if necessary.
Taking into account that the prototype is intended for extended software development it
may have additional features and capabilities to support expected as well as unexpected
needs imposed by all levels of software.
In addition, since this device is being introduced as a second generation in the family of
the holonic hardware prototypes [5] , it should provide maximum compatibility for the
low-level software previously created for the first prototype.
2 ENGINEERING ANALYSIS
2.1 Project Initialization
This project represents a second step in Holonic Mobile Agent development.
Previous work has been done to create a start-up platform for building an information
layer of a Holon-based mobile network. This work, described by Wong in [5], realized a
hardware prototype designed around an Intel PXA255 core processor. At a certain
development stage, this device, even though efficient at the earlier design phases and
comprising 128 Mbits of SDRAM and 128 Mbits of NOR flash, had required further
modifications to satisfy the growing needs of the software.
Thus, to provide an effective physical part for the holonic mobile agent a device
of a higher performance level is to be built. At this stage, the design is expected to:
- provide communication via a real wireless medium;
- support a high-speed communication interface to a host device;
- provide sufficient storage for embedded software and data;
- be built using modern technologies and advanced components base;
- provide an effective platform for further integration and micro-miniaturization
2.2 System Architecture Considerations
This chapter provides architectural design considerations that are necessary for
the components selection and effective utilisation of the system resources.
2.2.1 System Requirements
Analysis of previous results helped to create a list of the system requirements for
the prototype that I developed. These requirements are as follows:
Architecture
The mobile device is to be built of two entities - a Controller responsible for
intelligent networking and data processing, and a Wireless Transceiver providing
communication interface with other mobile agents.
Memory
at least 1 GByte space for embedded programs,
1 GByte of non-volatile data storage,
1 GByte of high-speed random access memory for programs and data.
Central Processor Unit (CPU)
run at frequencies 400 MHz and higher,
provide on-chip CASH memory for frequently accessed data,
support various communication interfaces,
be available in compact packages.
Communication Medium
The device should communicate with other mobile devices via a wireless (WiFi)
interface
Periphery should be available in the form of commonly used interfaces, such as:
USB,
SPI,
PCMCIA.
2.2.2 Components Selection Criteria
For further architectural design, all components required for the devices can be
arranged into several major groups:
Memory devices
a) Non-volatile memory,
b) Random Access Memory (RAM),
CPU
Wireless communication components,
Discreet semiconductors and low-integration Integrated Circuits (ICs).
To assist with components selection for each group required for the design a
review of the existing technologies and modern devices for mobile communication is
provided in the following subsections.
2.3 Existing Memory Technologies
To provide sufficient space for potentially vast arrays of data and, at the same
time, have large residence for the application programmes it is appropriate to utilize two
types of non-volatile memory - NAND flash and NOR flash. Additionally, the device
needs the equivalent area of memory to unpack the software saved in flash upon booting
and to store temporary products of data processing.
2.3.1 Non-volatile Memory Devices
Non-volatile memories are essential part of any intelligent electronic system that
is characterised by the capability to store information in the absence of power. In the past,
various types of non-volatile memory have been available, including Read-only
Memories (ROM), Programmable ROM (PROM), Erasable PROM (EPROM), and Ultra-
Violet EPROM (UV - EPROM). Electrically Erasable PROM had a wide range of
applications because along with fast random read and write access to any location it
offered the advantage of in-circuit programming and erasing. First-generation EEPROM
devices had parallel interface, which at higher densities leads to large package sizes. In
addition, EEPROM architecture is based on a two-transistor cell that consists of a large
write transistor and a small read transistor that results in a significant area required for
large memory arrays.
2.3.1.1 Flash Memory Architectures
Flash memory is a variant of EEPROM that is developed in two main directions:
traditional random access type and byte serial memories. All flash memories are similar
in employing sectored memory arrays. Depending on the Flash memory type, sectors -
also referred as blocks - can be equal in size or consist of different number of cells.
The major difference of a flash memory cell from EEPROM is the absence of the
select transistor in order to achieve higher density and cost saving. This feature brings the
concern of possible interference with one portion of the memory while writing to another
portion, thereby requiring tighter control of the process parameters for manufacturing [6] .
A cross-section of the standard flash memory cell (T-cell) is based on the floating gate
MOSFET and shown in Figure 2.1.
Control Gate
lnterpoly Dielectric 15 ... 30 nrn I Floating Gate
To provide fault-free layout without applying for the leading edge PCB
technologies the PBGA 23x23 mm package olf the processor with 1 rnm pin pitch was
chosen. This choice allows fix the escape routing using 0.005" traces with 0.004" space
without application of microvias. A fragment of the routing area for the processor is
depicted in the Figure 3.1 O.a. It is worth to notice that there are no vias placed inside the
components pins; this makes the design acceptable by a significantly larger number of
manufacturers and guarantees significantly lower failure rate for higher product
reliability.
Figure 3-10. Escape routing for the PXA270 (a) and NOR Flash (b) on the top layer
Even a greater challenge for routing is presented by the NOR flash chips that
feature 0.8 mm pin pitch in their BGA package. One of the routing segments is depicted
in Figure 3.10.b. These two devices essentially define the design rules for the board that
are summarized in the Table 3.3
Table 3.3: Design rules for the holonic controller PCB
Features Values Inch I mm 1
Minimal Signal Trace Width / Space Minimal Power and Ground Trace Width Signal Via / Hole Power and Ground Via / Hole Minimum Space Between Polygon Planes Number of Layers
0.005 / 0.004 0.010
0.10 16 / 0.1270 0.25
*Composed from capabilities advertised by several PCB manufacturers
0.01 8 / 0.008 0.025 / 0.013 0.025 8
0.4572 / 0.2032 0.6350 / 0.3302 0.6350
Signal Integrity Analysis
Propagation Delay
As it is well known, the propagation speed of an electromagnetic signal in a
conductor in presence of a dielectric is not equal to speed of light anymore. It is rather
characterised by propagation delay that is defined as follows in pslinch for microstrip:
and for stripline in pslinch:
where Er is the dielectric constant of the insulator near conductor. Typical value of E, for
prepreg is 4.5 and for core is 4.8. Substituting E, by its value for prepreg in (1) results in
propagation delay for traces on the Top and Bottom layers equal to:
For the inner signal layers, which are surrounded by insulators with different E, an
approximation formula helps to find the resultant dielectric constant [18]:
Er = GI .VI + G2 .V2,
where and ~2 are dielectric constants for two adjacent insulators and
V1 and V2 - volume fractions of the insulators.
Assuming that both prepreg and core are of the same thickness, V1 = V2 = 0.5.
The resultant dielectric constant of the insulators surrounding traces in the internal layers
can be found as:
Applying this value in Eq(2) the propagation delay in the internal signal layers is:
tpd (stripline) = 183.3 pslinch.
Electrically Long Traces
An electrically long trace is defined as a trace in a specified layer in which (trace)
a signal transition time from (low to high or from high to low state) is greater than double
propagation delay:
t, L,, = --------
%-I
For the PXA270 processor, the shortest falllrise time is given for the SDCLK - 0
(SDRAM) signal and equals 0.5 ns [16].
Thus, using this value and data for propagation delay found above, the electrically
long trace on the Top and Bottom layers
Similarly, the electrically long trace value can be found for the internal layers as:
These results imply that high speed traces longer that 1.75" in the external layers
and 1.36" in the internal layers require signal integrity analysis, and, most likely,
application of impedance matching techniques. Obviously, it is not possible with the
existing technologies to route a data, address, or control bus between the processor and
eight SDRAM chips while having connections shorter than calculated lengths.
Trace Impedance Calculations
Trace impedance for the external layers can be calculated with the following
formula for microstrips:
where H is height of the dielectric (H = 0.2mm (7.874 mil) for prepreg in the stackup),
W is the trace width (W = 0.127mm (5.0mil)),
T is the thickness of the copper trace (T = 0.018mm (0.709mil)), and
E, is the prepreg dielectric constant equal 4.5.
For the given board parameters, the trace impedance in the outer layers is equal:
For the inner layers, formula for stripline impedance calculation can be applied:
For the approximated value of E, = 4.65 found earlier and the same board
parameters:
Driver's Output Impedance
This impedance can be approximately estimated as ratio between the low-level
output voltage of the driver and current supplied at this state:
As it can be found from the datasheet for PXA270, it can drive a load not higher
than 4 rnA when the output level of the memory bus signals is 0.3V. Thus, the driver's
output impedance will be equal:
To minimize signal reflection from the source, the load impedance ZL should
match the impedance of the driver. The reflection coefficient can be found by applying
the following formula:
where ZL is the total line impedance. Since the input impedance of the receiver is
significantly high (100KSZ and above) comparing to the line impedance, the reflection
coefficient for the receiver is typically equal 1. However, it is possible to reduce
considerably the reflection coefficient at the source. It can be easily noticed that to keep
KR = 0, it is necessary to have ZL = ZO. (In this case, load impedance is presented by Z,.
Comparing values of Zo found for outer and inner layer, it is obvious that the signals
require no or small value termination resistors (in the range of 20 SZ).
Holonic Controller PCB Physical Layout
The most critical part of the electronic design proposed for the Holonic Controller
Hardware implementation is the memory address and data bus and control signals. Not
surprisingly, the same portion is very demanding in terms of the PCB design, especially
the high-speed clock signals. There are two major types of topologies used for the
memory bus layout. Both of them have their own advantages and weaknesses.
First, the most common topology for memory devices layout is a Daisy-Chain.
This technique is very convenient because all traces go from the driver to all memory
chips on the board sequentially following the same pattern.
Advantages:
- Easy to layout,
- Traces are usually of the same length.
Weaknesses:
- Uneven signal distribution between the closest and farthest devices in the
chain,
- Performs poorly for different packages in one design.
The other common topology is the Tree:
Advantages:
- Easy to provide equal distance to each device in the bus,
- Traces are usually of the same length.
Weaknesses:
- More complex for routing,
- More board space consuming.
To provide good signal integrity for the high-speed signals on the b'oard it was
decided to implement the Tree type topology with double-side mounting. This approach
requires symmetric placement of the same type chips that would guarantee balanced load
at any moment of external memory operation cycle.
PCMCIA Buffers
Figure 3-1 1. Memory components placement on the board
The diagram of the memory devices layout on the board and their connections are shown
in Figure 3.11. At the same time, it is crucial to have as few layer switches - that result in
vias - per trace as possible. It is well h o w n that vias and soldering instants create points
of reflection that cause signal distorting and degrading and should be used with caution in
high-speed designs. It is implortant to remember that [19]:
- Properties of a via are changed by the parameters of the trace to which it is
connected.
- A via adds incremental shunt capacitance and incremental series inductance to
a trace.
- Long dangling vias can create points of resonance, aggravating the effects of
its capacitance.
- Vias that pass tlirough the same space between two reference planes (stripline
cavity) create crosstalk.
Figure 3-12. 3D model of the top side of the controller board
8 8
Figures 3.12. and 3.13. show 3D models of the top and bottom sides of the board,
respectively. At the opposite end of the data bus, there is a connector for PCMCIA
devices. Since the PXA270 controller does not support this type of interface directly, it is
separated from the internal bus with three buffers. Additionally, some signals of the
PCMCIA bus require +5V power source. Such a power supply exists on the Controller
board, but two open drain buffers were addled to shift signal levels from +3.3V to +5V to
provide interface level matching.
Manufacturing files for the HCS Colntroller PCB are provided in Appendix B.
Figure 3-13. 3D model of the bottom side of the tontroller board
3.4.5.2 Holonic Mobile Agent Transceiver PCB Design
The RF Transceiver printed circuit board is relatively simple compared to the
Controller. Considering usage of the System-in-Package (Sip) device for the 802.1 1b
physical layer, it is possible to realize the entire RF module in a two-layer single side
mount PCB. A layer stackup for this board is presented in Figure 3.14.
Even though power for this module is provided by the Controller board, this
device is accompanied by its own power supply located on the bottom side to give more
freedom at the prototyping, troubleshooting and firmware development stages. This
option will allow to connect periphery devices with power requirements different from
1 - I =.I. "P.. -- I - g p w = == .... .....=? !f $E ....m ..... .....a.
1 o,,.:, -- .... 1 -(I
PtlT Top Paste Hol on. GTP
Controller top solder paste layer
SST Top Overlay Hol on. GTO
Controller top silkscreen layer
SUT Top Solder Mask Hol on. GTS
B I.. I D . . -I
11 B D.. mm B I.. I- . . . . . m D = = r
Controller top solder mask layer
LO1 Siqnall Hol on. GTL
Controller top signal layer
LO2 GNDl Hol on. GP1
Controller ground plane 1 copper layer
t03 Srqna12 Hal on. GI
Controller signal 2 internal layer
LO5 UCC-I0 Hol on. GP2
Controller power plane 1 copper layer
Controller power plane 2 copper layer
LO4 Slgnal3 Hol on. G2
Controller signal 3 internal layer
Controller ground plane 2 copper layer
LO6 Siqnalt Hol on. GBL
Controller bottom signal layer
SUB Bottom Solder Mask Hol on. GBS
Controller bottom solder mask layer
SSB Bottom Over lay Hol on. GBO
Controller bottom silkscreen layer
PflB Bottom Paste Hol on. GBP
Controller bottom solder paste layer
Appendix C: Schematic Diagram of the HCS Transceiver
Appendix D: Manufacturing Files (Gerbers) of the HCS Transceiver
T r anscel ver, GBL
Transceiver top (top image) and bottom (bottom image) signal layers
127
Tr anscei ver . GTO
Transceiver. GBO
Transceiver top silkscreen (top image) and bottom silkscreen (bottom image) layers
T r a n s c e i v e r . GTP
Tr anscei ver . GBP
Transceiver top solder paste (top image) and bottom solder paste (bottom image) layers
Transceiver . GTS
T r anscei ver . GBS
Transceiver top solder mask (top image) and bottom solder mask (bottom image) layers
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1 1. B. Pattan, "Robust Modulation Methods and Smart Antennas in Wireless Communications, " Prentice Hall PTR , 2000.
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13. "Connecting NAND Flash to the Intel PXA27x Processor Family"