ml505_bsb_std_ip_addition

ML505/506/507 BSB DesignAdding Standard IP

February 2009

Overview• Hardware Setup• Software Requirements• Adding Standard Supported IP• Adding LWIP• Generate a Bitstream • Transfer the Bitstream onto the FPGA• Loading a Bootloop into the Block RAM

Note: This Presentation applies to the ML505, ML506, and ML507

Overview• Standard IP Added:

– TFT – xps_tft– PS/2 – xps_ps2– General Purpose IO – xps_gpio– IIC Interface – xps_iic– Second PLB v46 bus – plb_v46– PLB to PLB Bridge – plbv46_plbv46_bridge

• Standard IP Modified:– SRAM Interface – xps_mch_emc

Note: Presentation applies to the ML505, ML506, and ML507

ML505 BSB Hardware• The ML505 MicroBlaze design

hardware includes:– DDR2 Interface (256 MB)– External Memory Controller (EMC)

• ZBT SRAM– BRAM – Networking – UART– Interrupt Controller– System ACE CF Interface– GPIO (IIC, LEDs and LCD)– PLB Arbiter

Note: Presentation applies to the ML505, ML506, and ML507

Additional Setup Details• Refer to ml505_overview_setup.ppt for details on:

– Software Requirements– ML505 Board Setup

• Equipment and Cables• Software• Network

– Terminal Programs• This presentation requires the

9600-8-N-1 Baud terminal setup

Note: Presentation applies to the ML505, ML506, and ML507

Hardware Setup• Connect the Xilinx Platform

Cable USB to the ML505 board

• Connect the RS232 nullmodem cable to the ML505 board

Note: Presentation applies to the ML505, ML506, and ML507

Setting Up the Hardware• Set ML505 Jumpers for GMII

– Set both J22 and J23 to positions 1-2 (as shown)

Note: Presentation applies to the ML505, ML506, and ML507

ISE Software Requirement• Xilinx ISE 10.1i SP3 software

Note: Presentation applies to the ML505, ML506, and ML507

EDK Software Requirement• Xilinx EDK 10.1i SP3 software

Note: Presentation applies to the ML505, ML506, and ML507

Software Setup• Start the Terminal Program:

Note: Presentation applies to the ML505, ML506, and ML507

Using the Pre-Built Design• Unzip ml505_bsb_std_ip_design.zip and locate pre-built

bitstream and executable software files:ml505_bsb_std_ip_design/implementation/download.bitml505_bsb_std_ip_design/microblaze_0/code/*.elf

• Configure FPGA– Launch XPS project, ml505_bsb_system.xmp– From the menu, select Project → Launch EDK Shell and type:

impact –batch etc/download.cmd– Go to Slide 93, to run the software application

• For a tutorial on how to create the contents of the ml505_bsb_std_ip_design.zip continue to the next slide

Note: Presentation applies to the ML505, ML506, and ML507

Extracting the Design• Unzip the ml505_bsb_design.zip file

– This creates ISE and EDK project directories

Note: Presentation applies to the ML505, ML506, and ML507

Extracting the Design• Rename the project directory to

ml505_bsb_std_ip

Note: Presentation applies to the ML505, ML506, and ML507

Extracting the Design• Unzip the ml505_bsb_std_ip_overlay.zip file

– Unzip to the ml505_bsb_std_ip directory– This adds the Standard IP UCF and software to the design directory

Note: ML506: ml506_bsb_std_ip_overlay.zip ML507: ml507_bsb_std_ip_overlay.zip

Add and Configure IP

Add Standard IP• Launch XPS project <design path>\ml505_bsb_system.xmp• Right-click on the XPS General Purpose IO and select Add IP …

Note: Presentation applies to the ML505, ML506, and ML507

Add Standard IP• Add 4 more instances of the XPS General Purpose IO IP

Note: Presentation applies to the ML505, ML506, and ML507

Add Standard IP• Add two instances of the XPS IIC Interface

Note: Presentation applies to the ML505, ML506, and ML507

Add Standard IP• Add a PLB v46 Bus

Note: Presentation applies to the ML505, ML506, and ML507

Add Standard IP• Add a PLBv46 to PLBv46 Bridge

Note: PLBv46 v1.03a supports a maximum of 16 devices attached

Add Standard IP• Right-click on XPS TFT and select Add IP…

Note: Presentation applies to the ML505, ML506, and ML507

Add Standard IP• Right-click on XPS PS2 Interface and select Add IP…

Note: Presentation applies to the ML505, ML506, and ML507

Add Standard IP• Right-click on Utility Vector Logic and select Add IP…

Note: Presentation applies to the ML505, ML506, and ML507

Connect Buses• Expand the PLBv46 to PLBv46 Bridge and connect:

– SPLB to mb_plb– MPLB to plb_v46_0

Note: Presentation applies to the ML505, ML506, and ML507

Connect Buses• Expand DIP_Switches_8Bit, LEDs_8Bit, LEDs_Positions,

Push_Buttons_5Bit, and IIC_EEPROM and connect them to plb_v46_0

Note: Presentation applies to the ML505, ML506, and ML507

Connect Buses• Connect each of the GPIO and IIC instances to the second

PLBv46 bus

Note: Presentation applies to the ML505, ML506, and ML507

Connect Buses• Connect xps_ps2_0 to plb_v46_1• Connect xps_tft_0 to plb_v46_0

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Right-click on the xps_gpio_0 and select Configure IP…

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP

• Under the User tab, set the following parameters:– GPIO Bus Width: 2

• This is for the 2 Error LEDs

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Configure the other

xps_gpio instances:– xps_gpio_1: Bus Width: 1

• Piezo transducer– xps_gpio_2: Bus Width: 3

• Rotary encoder and PB– xps_gpio_3: Bus Width: 2

• SMA Diff CLK In– xps_gpio_4: Bus Width: 7

• LCD Display

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Right-click on the xps_iic_0 and select Configure IP …

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP

• Under the User tab, set the following parameters:– PLB Bus Frequency:

125 MHz• Configure the other

xps_iic instance to 125 MHz PLB Bus Frequency

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Add Flash to the existing SRAM IP• Right-click on the SRAM and select Configure IP…

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP

• Under the User Misc tab, set the following parameters:– Number of Memory

Banks: 2

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Under the User Bank 1 tab,

set the following parameters:– Data Bus Width

of Bank 1: 16– Set Data Width Matching

to True– Set TCEDV and TAVDV

to: 110000– Set THZCE to: 35000– Set THZOE to: 15000– Set TWC to: 110000– Set TWP to: 70000– Set TLZWE to: 35000

• Click OK

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Right-click on xps_ps2_0 and select Configure IP…

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP

• Under the User →Common, set the following parameters:– Enable Port 2– Set Clock Frequency to

125 MHz

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Right-click on xps_tft_0 and select Configure IP…

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP

• Under the User → All, set the following parameters:– Base Address of PLB

Attached Video Memory: 0x90000000

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Right-click on the clock_generator_0 and select

Configure IP…

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Connect CLKOUT4 to net xps_tft_0_SYS_TFT_Clk

– Set the frequency to 25 MHz

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP• Right-click on util_vector_logic_0 and select

Configure IP…

Note: Presentation applies to the ML505, ML506, and ML507

Configure IP

• Under the User Tab, set the following parameters:– Vector Operation: not– Vector Size: 1

Note: Presentation applies to the ML505, ML506, and ML507

Add External Ports

Connect Ports• Select the Ports tab, expand xps_gpio_0, and select Make

External for the GPIO_IO port

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• For each of the remaining xps_gpio_x instances, select

Make External for the GPIO_IO port

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• For each of the xps_iic_x instances, select Make External

for the Scl and Sda ports

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Expand SRAM, and select Make External for the

Mem_LBON port

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Expand plb_v46_0 and connect these nets:

– SYS_Rst to sys_bus_reset– PLB_Clk to sys_clk_s

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Open the external ports and set

fpga_0_SRAM_Mem_CEN and fpga_0_SRAM_Mem_OEN to a range of [0:1]

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Expand xps_tft_0 and select Make External for

TFT_IIC_SDA and TFT_IIC_SCL

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Connect SYS_TFT_Clk port to xps_tft_0_SYS_TFT_Clk

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Select Make External for TFT_DVI_DATA,

TFT_DVI_CLK_N, TFT_DVI_CLK_P, TFT_DE, TFT_VSYNC, and TFT_HSYNC

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Add an external port

– Pin name: vga_reset_pin– Net name: sys_periph_reset_n, Dir: O, Class: RST, Reset Polarity: 0

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Expand proc_sys_reset_0 and connect Slowest_sync_clk

to xps_tft_0_SYS_TFT_Clk

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Expand xps_ps2_0 and select Make External for

PS2_2_CLK and PS2_2_DATA

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Select Make External for PS2_1_CLK and PS2_1_DATA

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Select New Connection for IP2INTC_Irpt_2 and

IP2INTC_Irpt_1

Note: Presentation applies to the ML505, ML506, and ML507

Connect Ports• Expand util_vector_logic_0, and connect these nets:

Res to sys_periph_reset_nOp1 to sys_periph_reset

Note: Presentation applies to the ML505, ML506, and ML507

Setup Interrupts• Expand xps_intc_0 and click on the gray Intr area to open

the Interrupts dialog

Note: Presentation applies to the ML505, ML506, and ML507

Setup Interrupts• Add xps_ps2_0_IP2INTC_Irpt_1 to the Interrupts

Note: Presentation applies to the ML505, ML506, and ML507

Setup Interrupts• Add xps_ps2_0_IP2INTC_Irpt_2 to the Interrupts

Note: Presentation applies to the ML505, ML506, and ML507

Generate Addresses

Generate Addresses• Select the Addresses tab and lock the addresses as shown

Note: Presentation applies to the ML505, ML506, and ML507

Generate Addresses• Select the Addresses tab and lock the addresses as shown

Note: The DDR2_SDRAM address will be used in the software settings

Generate Addresses• Select the Addresses tab and Set the size for the Flash

memory (C_MEM1_BASEADDR) to 32M

Note: Presentation applies to the ML505, ML506, and ML507

Generate Addresses• Click Generate Addresses and view the new addresses

Note: The SRAM Flash address will be used in the software settings

Generate Addresses• View the new addresses

Note: Presentation applies to the ML505, ML506, and ML507

Lock Addresses• Lock these new addresses

Note: Presentation applies to the ML505, ML506, and ML507

Lock Addresses• Lock these new addresses

Note: Presentation applies to the ML505, ML506, and ML507

Software Settings

Software Platform Settings• Select Software →

Software PlatformSettings… (1)

1

Note: Presentation applies to the ML505, ML506, and ML507

Software Platform Settings• Under Software

Platform (1) – Set OS to xilkernel (2)– Select xilmfs (3) xilflash ,

xilfatfs and lwip (4)

Note: Presentation applies to the ML505, ML506, and ML507

3

4

2

1

Software Platform Settings• Under OS and Libraries (1),

set these xilkernel settings:– sysintc_spec = xps_intc_0– stdout = RS232_Uart_1– stdin = RS232_Uart_1– enhanced_features = true– config_yield = true

1

Note: Presentation applies to the ML505, ML506, and ML507

Software Platform Settings• Under OS and Libraries (1),

set these xilkernel settings:– config_sema = true– max_sem_waitq = 20– max_sem = 50– config_time = true– max_tmrs = 20– max_readyq = 20

1

Note: Presentation applies to the ML505, ML506, and ML507

Software Platform Settings• Under OS and Libraries (1),

set these xilkernel settings:– max_pthread_mutex = 20– pthread_stack_size = 32768– systmr_freq = 300000000

1

Note: Presentation applies to the ML505, ML506, and ML507

Software Platform Settings• Under OS and Libraries (1),

set these xilkernel settings:– Click on

static_pthread_table

1

Note: Presentation applies to the ML505, ML506, and ML507

Software Platform Settings• Click Add and set

– pthread_start_func = main_thread

– pthread_prio = 1

Note: Presentation applies to the ML505, ML506, and ML507

Software Platform Settings• Under OS and Libraries (1),

set this lwip setting:– api_mode = SOCKET_API

1

Note: Presentation applies to the ML505, ML506, and ML507

Software Platform Settings• Under OS and Libraries (1),

set these xilfatfs settings to true:– CONFIG_DIR_SUPPORT– CONFIG_WRITE

1

Note: Presentation applies to the ML505, ML506, and ML507

2

Software Platform Settings• Under OS and

Libraries (1) set these xilflashsettings (2):– base_address (set to

match sram flash address): 0x88000000

– num_parts: 1

2

Note: Presentation applies to the ML505, ML506, and ML507

1

Software Platform Settings• Under OS and

Libraries (1) set these xilmfssettings (2):– need_utils to true– int_type to

MFSINIT_IMAGE– base_address (set to

match sram address): 0x8a400000

– numbytes: 400000• Click OK

1

Note: Presentation applies to the ML505, ML506, and ML507

Create MFS Image

Create MFS Image• Open an EDK shell

– Select Project →LaunchEDK Shell (1)

Note: Presentation applies to the ML505, ML506, and ML507

1

Create MFS Image• At the bash prompt, type (1):

cd sw/standalone/lwipdemo/memfsmfsgen -cvbfs ../image.mfs 750 *

1

Note: Presentation applies to the ML505, ML506, and ML507

Compile Design

Generate Bitstream• Generate the libraries

needed to create the bitstream– Select Software →

Generate Librariesand BSPs (1)

Note: Presentation applies to the ML505, ML506, and ML507

1

Generate Bitstream• Compile the

applications and create an executable (executable.elf)– Select Software →

Build All User Applications (1)

Note: Presentation applies to the ML505, ML506, and ML507

1

Generate Bitstream• Create the hardware

design that is located in <project directory>/implementation– Select Hardware →

Generate Bitstream (1)(Takes roughly 60 minutes)

Note: Presentation applies to the ML505, ML506, and ML507

1

Loading Bootloop into BRAM• A concatenated software/hardware file, known as

an ACE file, is useful for loading large programs, such as a VxWorks or Linux demo, into the external memory

• A bootloop program must be used to occupy the processor until the software is loaded into memory

• The following pages show how to initialize a bootloopprogram into block RAM and to test its existence

Note: Presentation applies to the ML505, ML506, and ML507

Loading Bootloop into BRAM• Update the bitstream

(download.bit) with a bootloop ELF file (microblaze_0.elf)– Select Device

Configuration →Update Bitstream (1)

Note: Presentation applies to the ML505, ML506, and ML507

1

Loading Bootloop into BRAM• Load the new design

onto the FPGA and load the bootloopprogram into the blockRAM– Select Device

Configuration →Download Bitstream (1)

Note: Presentation applies to the ML505, ML506, and ML507

1

Loading Bootloop into BRAM• A memory read can

be executed to test if the bootloop was successfully loaded– Select Debug →

Launch XMD (1)

Note: Presentation applies to the ML505, ML506, and ML507

1

XMD Setup• The first time XMD runs

on a project, the options will be set– Click OK (1)– Click OK (2)

1

2

Note: Presentation applies to the ML505, ML506, and ML507

Loading Bootloop into BRAM• XMD opens and connects to the processor, using the default

options

Note: Presentation applies to the ML505, ML506, and ML507

Loading Bootloop into BRAM• To execute a memory read, type mrd 0x00000000• This will read the memory address at the reset vector; the

value should be 0xB8000000 as shown below

Note: Presentation applies to the ML505, ML506, and ML507

Download ELF File• Download the iic_ddr2 ELF file from XMD

dow microblaze_0/code/iic_ddr2.elf (1)con (2)

1

Note: Presentation applies to the ML505, ML506, and ML507

2

Run iic_ddr2• View the output in the terminal program

Note: Presentation applies to the ML505, ML506, and ML507

Create an ACE File• Open an EDK shell

– Select Project →LaunchEDK Shell (1)

– This shell is used for entering and executing thecommands to create a concatenated (HW+SW ) ACE file

Note: Presentation applies to the ML505, ML506, and ML507

1

Create an ACE File• At the bash prompt, type (1):

cd ace./genace_iic_ddr2.sh

1

Note: Presentation applies to the ML505, ML506, and ML507

Create an ACE File• This creates a concatenated (HW+SW) ACE file

– Input: iic_ddr2 ELF file, download.bit• genace_iic_ddr2.sh uses XMD and a genace.tcl script with

ML505 appropriate options to generate an ACE file (1)

1

Note: Presentation applies to the ML505, ML506, and ML507

Run ACE File• Copy iic_ddr2.ace to the ML50X\cfg6

directory on your CompactFlash card– Important: Delete any existing ace files

in this cfg6 directory– Note: Use a CompactFlash reader to

mount the CompactFlash as a disk drive

Note: Presentation applies to the ML505, ML506, and ML507

Run ACE File• Eject the CompactFlash from your PC and insert it back into

the ML505• Type 6 to run the newly created ACE file

Note: Presentation applies to the ML505, ML506, and ML507

Using the ACE File• iic_ddr2 output after booting ACE file

Note: Presentation applies to the ML505, ML506, and ML507

Appendix 1 – Running the Lwipdemo Application

Running the LWIP Demo• Open an EDK shell

– Select Project →LaunchEDK Shell (1)

Note: Presentation applies to the ML505, ML506, and ML507

1

Running the LWIP Demo• At the bash prompt, type (1):

cd ace./genace_lwipdemo.sh

1

Note: Presentation applies to the ML505, ML506, and ML507

Run ACE File• Copy lwipdemo.ace to the ML50X\cfg6

directory on your CompactFlash card– Important: Delete any existing ace files

in this cfg6 directory– Note: Use a CompactFlash reader to

mount the CompactFlash as a disk drive

Note: Presentation applies to the ML505, ML506, and ML507

Running the LWIP Demo• Eject the CompactFlash from your PC and insert it back into

the ML505• Type 6 to run the newly created ACE file

Note: Presentation applies to the ML505, ML506, and ML507

Running the LWIP Demo• Lwipdemo UART output after booting ACE file

Note: Presentation applies to the ML505, ML506, and ML507

Running the LWIP Demo• Open a web browser to address 192.168.1.10

Note: Presentation applies to the ML505, ML506, and ML507

Running the LWIP Demo• Click the Toggle LEDs button; view change on ML505

Note: Presentation applies to the ML505, ML506, and ML507

Documentation• Virtex-5

– Silicon Deviceshttp://www.xilinx.com/products/devices.htm

– Virtex-5 Multi-Platform FPGAhttp://www.xilinx.com/products/virtex5/index.htm

– Virtex-5 Family Overview: LX, LXT, SXT, and FXT Platformshttp://www.xilinx.com/support/documentation/data_sheets/ds100.pdf

– Virtex-5 FPGA DC and Switching Characteristics Data Sheethttp://www.xilinx.com/support/documentation/data_sheets/ds202.pdf

Documentation• Virtex-5

– Virtex-5 FPGA User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug190.pdf

– Virtex-5 FPGA Configuration User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug191.pdf

– Virtex-5 System Monitor User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug192.pdf

– Virtex-5 Packaging and Pinout Specificationhttp://www.xilinx.com/support/documentation/user_guides/ug195.pdf

Documentation• Virtex-5 RocketIO

– RocketIO GTP Transceivershttp://www.xilinx.com/products/virtex5/lxt.htm

– RocketIO GTP Transceiver User Guide – UG196http://www.xilinx.com/support/documentation/user_guides/ug196.pdf

– RocketIO GTX Transceivers http://www.xilinx.com/products/virtex5/fxt.htm

– RocketIO GTX Transceiver User Guide – UG198http://www.xilinx.com/support/documentation/user_guides/ug198.pdf

Documentation• Design Resources

– ISE Development Tools and IPhttp://www.xilinx.com/ise

– Integrated Software Environment (ISE) Foundation Resourceshttp://www.xilinx.com/ise/logic_design_prod/foundation.htm

– ISE Manualshttp://www.xilinx.com/support/software_manuals.htm

– ISE Development System Reference Guidehttp://toolbox.xilinx.com/docsan/xilinx10/books/docs/dev/dev.pdf

– ISE Development System Libraries Guidehttp://toolbox.xilinx.com/docsan/xilinx10/books/docs/virtex5_hdl/virtex5_hdl.pdf

Documentation• Additional Design Resources

– Customer Supporthttp://www.xilinx.com/support

– Xilinx Design Services: http://www.xilinx.com/xds

– Titanium Dedicated Engineering: http://www.xilinx.com/titanium

– Education Services: http://www.xilinx.com/education

– Xilinx On Board (Board and kit locator): http://www.xilinx.com/xob

Documentation• Platform Studio

– Embedded Development Kit (EDK) Resourceshttp://www.xilinx.com/edk

– Embedded System Tools Reference Manualhttp://www.xilinx.com/support/documentation/sw_manuals/edk10_est_rm.pdf

– EDK Concepts, Tools, and Techniqueshttp://www.xilinx.com/support/documentation/sw_manuals/edk_ctt.pdf

Documentation• PowerPC 440

– Embedded Processor Block in Virtex-5 FPGAs Reference Guide – UG200http://www.xilinx.com/support/documentation/user_guides/ug200.pdf

– PPC440 Virtex-5 Wrapper – DS621http://www.xilinx.com/support/documentation/ip_documentation/ppc440_virtex5.pdf

– DDR2 Memory Controller for PowerPC 440 Processors – DS567http://www.xilinx.com/support/documentation/data_sheets/ds567.pdf

Documentation• MicroBlaze

– MicroBlaze Processorhttp://www.xilinx.com/microblaze

– MicroBlaze Processor Reference Guide – UG081http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf

Documentation• ChipScope Pro

– ChipScope Pro 10.1i Serial IO Toolkit User Manualhttp://www.xilinx.com/ise/verification/chipscope_pro_siotk_10_1_ug213.pdf

– ChipScope Pro 10.1i ChipScope Pro Software and Cores User Guidehttp://www.xilinx.com/ise/verification/chipscope_pro_sw_cores_10_1_ug029.pdf

Documentation• Memory Solutions

– Demos on Demand – Memory Interface Solutions with Xilinx FPGAs http://www.demosondemand.com/clients/xilinx/001/page_new2/index.asp#35

– Xilinx Memory Cornerhttp://www.xilinx.com/products/design_resources/mem_corner

– Additional Memory Resourceshttp://www.xilinx.com/support/software/memory/protected/index.htm

– Xilinx Memory Interface Generator (MIG) 2.1 User Guidehttp://www.xilinx.com/support/software/memory/protected/ug086.pdf

– Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface Generatorhttp://www.xilinx.com/support/documentation/white_papers/wp260.pdf

Documentation• Ethernet

– Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Data Sheethttp://www.xilinx.com/support/documentation/ip_documentation/v5_emac_ds550.pdf

– Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guidehttp://www.xilinx.com/support/documentation/ip_documentation/v5_emac_gsg340.pdf

– Virtex-5 Tri-Mode Ethernet Media Access Controller User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug194.pdf

– LightWeight IP (lwIP) Application Examples – XAPP1026http://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf

Documentation• PCIe

– LogiCORE Endpoint Block Plus for PCI Express Data Sheethttp://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ds551.pdf

– LogiCORE Endpoint Block Plus for PCI Express Designshttp://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf

– LogiCORE Endpoint Block Plus Getting Started Guide for PCI Express Designshttp://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_gsg343.pdf

– Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designshttp://www.xilinx.com/support/documentation/user_guides/ug197.pdf

Documentation• System Generator

– System Generator for DSPhttp://www.xilinx.com/sysgen

– Xilinx System Generator for DSP User Guideshttp://www.xilinx.com/support/documentation/sw_manuals/sysgen_bklist.pdf

– XtremeDSP Design Considerationshttp://www.xilinx.com/support/documentation/user_guides/ug193.pdf

Documentation• PLB v4.6 IP

– Processor Local Bus (PLB) v4.6 Data Sheet – DS531http://www.xilinx.com/support/documentation/ip_documentation/plb_v46.pdf

– Multi-Port Memory Controller (MPMC) – DS643http://www.xilinx.com/support/documentation/ip_documentation/mpmc.pdf

– XPS Multi-CHannel External Memory Controller (XPS MCH EMC) – DS575http://www.xilinx.com/support/documentation/ip_documentation/xps_mch_emc.pdf

– XPS LocalLink TEMAC – DS537http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_temac.pdf

– XPS LocalLink FIFO – DS568http://www.xilinx.com/support/documentation/ip_documentation/xps_ll_fifo.pdf

Documentation• PLB v4.6 IP

– XPS IIC Bus Interface – DS606http://www.xilinx.com/support/documentation/ip_documentation/xps_iic.pdf

– XPS SYSACE (System ACE) Interface Controller – DS583http://www.xilinx.com/support/documentation/ip_documentation/xps_sysace.pdf

– XPS Timer/Counter – DS573http://www.xilinx.com/support/documentation/ip_documentation/xps_timer.pdf

– XPS Interrupt Controller – DS572http://www.xilinx.com/support/documentation/ip_documentation/xps_intc.pdf

– Using and Creating Interrupt-Based Systems Application Notehttp://www.xilinx.com/support/documentation/application_notes/xapp778.pdf

Documentation• PLB v4.6 IP

– XPS General Purpose Input/Output (GPIO) – DS569http://www.xilinx.com/support/documentation/ip_documentation/xps_gpio.pdf

– XPS External Peripheral Controller (EPC) – DS581http://www.xilinx.com/support/documentation/ip_documentation/xps_epc.pdf

– XPS 16550 UART – DS577http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf

– PLBV46 to DCR Bridge Data Sheet – DS578http://www.xilinx.com/support/documentation/ip_documentation/plbv46_dcr_bridge.pdf

Documentation• IP

– Local Memory Bus Data Sheet – DS445http://www.xilinx.com/support/documentation/ip_documentation/lmb_v10.pdf

– Block RAM Block Data Sheet – DS444http://www.xilinx.com/support/documentation/ip_documentation/bram_block.pdf

– Microprocessor Debug Module Data Sheet – DS641http://www.xilinx.com/support/documentation/ip_documentation/mdm.pdf

– LMB Block RAM Interface Controller Data Sheet – DS452http://www.xilinx.com/support/documentation/ip_documentation/lmb_bram_if_cntlr.pdf

– Device Control Register Bus (DCR) v2.9 Data Sheet – DS406http://www.xilinx.com/support/documentation/ip_documentation/dcr_v29.pdf

Documentation• IP

– JTAGPPC Controller Data Sheet – DS298http://www.xilinx.com/support/documentation/ip_documentation/jtagppc_cntlr.pdf

– Processor System Reset Module Data Sheet – DS402http://www.xilinx.com/support/documentation/ip_documentation/proc_sys_reset.pdf

– Clock Generator v2.0 Data Sheet – DS614http://www.xilinx.com/support/documentation/ip_documentation/clock_generator.pdf

– Util Bus Split Operation Data Sheet – DS484http://www.xilinx.com/support/documentation/ip_documentation/util_bus_split.pdf

Documentation• ML505/506/507

– ML505 Overviewhttp://www.xilinx.com/ml505

– ML506 Overviewhttp://www.xilinx.com/ml506

– ML507 Overviewhttp://www.xilinx.com/ml507

– ML505/506/507 Evaluation Platform User Guide – UG347http://www.xilinx.com/support/documentation/boards_and_kits/ug347.pdf

– ML505/506/507 Getting Started Tutorial – UG348http://www.xilinx.com/support/documentation/boards_and_kits/ug348.pdf

– ML505/506/507 Reference Design User Guide – UG349http://www.xilinx.com/support/documentation/boards_and_kits/ug349.pdf

Documentation• ML505/506/507

– ML505/506/507 Schematicshttp://www.xilinx.com/support/documentation/boards_and_kits/ml50x_schematics.pdf

– ML505/506/507 Bill of Materialhttp://www.xilinx.com/support/documentation/boards_and_kits/ml505_501_bom.xls