Mixed-signal and digital signal processing ICs | …...data conversion, interface and signal conditioning circuits from issue VI:1 (February 1996) through issue VIII:4 (November 1998).

AN87-1

INTRODUCTION

Application Note 87 is the fifth in a series that excerptsuseful circuits from Linear Technology magazine to pre-serve them for posterity. This application note highlightsdata conversion, interface and signal conditioning circuitsfrom issue VI:1 (February 1996) through issue VIII:4(November 1998). Like its predecessor, AN67, this Appli-cation Note includes circuits for high speed video, inter-face and hot swap circuits, active RC and switched capaci-tor filter circuitry and a variety of data conversion and

instrumentation circuits. There are also several circuitsthat cannot be so neatly categorized. So, without furtherado, I’ll let the authors describe their circuits.

Note: Article Titles appear in this application note exactlyas they originally appeared in Linear Technology maga-zine. This may result in some inconsistency in the usageof terminology.

Linear Technology Magazine Circuit Collection, Volume VData Conversion, Interface and Signal Conditioning Products

Richard Markell, Editor

Application Note 87

November 2000

TABLE OF CONTENTSIntroduction ......................................................................................................................................................... 1

DATA CONVERTERSThe LTC®1446 and LTC1446L: World’s First Dual 12-Bit DACs in SO-8 Packages ............................................... 3Multichannel A/D Uses a Single Antialiasing Filter ................................................................................................ 4LTC1454/54L and LTC1458/58L: Dual and Quad 12-Bit, Rail-to-Rail, Micropower DACs .................................... 5Micropower ADC and DAC in SO-8 Give PC 12-Bit Analog Interface .................................................................... 7The LTC1594 and LTC1598: Micropower 4- and 8-Channel 12-Bit ADCs ........................................................... 10MUX the LTC1419 Without Software ................................................................................................................. 13The LTC1590 Dual 12-Bit DAC is Extremely Versatile......................................................................................... 14New 16-Bit SO-8 DAC Has 1LSB Max INL and DNL Over Industrial Temperature .............................................. 16LTC1659, LTC1448: Smallest Rail-to-Rail 12-Bit DACs Have Lowest Power ...................................................... 18An SMBus-Controlled 10-Bit, Current Output, 50µA Full-Scale DAC .................................................................. 19

INTERFACE CIRCUITSSimple Resistive Surge Protection for Interface Circuits .................................................................................... 20The LTC1343 and LTC1344 Form a Software-Selectable Multiple-Protocol Interface PortUsing a DB-25 Connector ................................................................................................................................... 22The LT1328: a Low Cost IrDA Receiver Solution for Data Rates up to 4Mbps ................................................... 34LTC1387 Single 5V RS232/RS485 Multiprotocol Transceiver ............................................................................ 36A 10MB/s Multiple-Protocol Chip Set Supports Net1 and Net2 Standards ......................................................... 37Net1 and Net2 Serial Interface Chip Set Supports Test Mode............................................................................. 44

OPERATIONAL AMPLIFIERS/VIDEO AMPLIFIERSLT1490/LT1491 Over-the-Top™ Dual and Quad Micropower Rail-to-Rail Op Amps........................................... 46The LT1210: A 1-Ampere, 35MHz Current Feedback Amplifier........................................................................... 47The LT1207: An Elegant Dual 60MHz, 250mA Current Feedback Amplifier ........................................................ 50

Application Note 87

AN87-2

, LTC, and LT are registered trademarks of Linear Technology Corporation; Adaptive Power, Burst Mode, C-Load, FilterCAD, No RSENSE, Operational Filter, Over-The-Top, PolyPhase, PowerPathand UltraFast are trademarks of Linear Technology Corporation. Gelcell is a trademark of Johnson Controls, Inc.; Kool Mµ is a registered trademark of Magnetics, Inc.; Pentium is a registeredtrademark of Intel Corp.; VERSA-PAC is a trademark of Coiltronics, Inc.

Micropower, Dual and Quad JFET Op Amps Feature C-Load™ Capabilityand PicoAmpere Input Bias Currents.................................................................................................................. 54The LT1210: High Power Op Amp Yields Higher Voltage and Current ................................................................ 56New Rail-to-Rail Amplifiers: Precision Performance from Micropower to High Speed ....................................... 59LT1256 Voltage-Controlled Amplitude Limiter ................................................................................................... 61The LT1495/LT1496: 1.5µA Rail-to-Rail Op Amps ............................................................................................. 62Send Camera Power and Video on the Same Coax Cable ................................................................................... 64200µA, 1.2MHz Rail-to-Rail Op Amps Have Over-The-Top Inputs ...................................................................... 65Low Distortion Rail-to-Rail Op Amps Have 0.003% THD with 100kHz Signal .................................................... 66The LT1167: Precision, Low Cost, Low Power Instrumentation Amplifier Requiresa Single Gain-Set Resistor .................................................................................................................................. 67Level Shift Allows CFA Video Amplifier to Swing to Ground on a Single Supply ................................................ 70LT1468: An Operational Amplifier for Fast, 16-Bit Systems ............................................................................... 71

TELECOMMUNICATIONS CIRCUITSHow to Ring a Phone with a Quad Op Amp ........................................................................................................ 73A Low Distortion, Low Power, Single-Pair HDSL Driver Using the LT1497 ........................................................ 79

COMPARATORSUltralow Power Comparators Include Reference ................................................................................................ 80A 4.5ns, 4mA, Single-Supply, Dual Comparator Optimized for 3V/5V Operation ................................................ 82

INSTRUMENTATION CIRCUITSLTC1441-Based Micropower Voltage-to-Frequency Converter ........................................................................... 86Bridge Measures Small Capacitance in Presence of Large Strays ...................................................................... 87Water Tank Pressure Sensing, a Fluid Solution .................................................................................................. 890.05µV/°C Chopped Amplifier Requires Only 5µA Supply Current ..................................................................... 924.5ns Dual-Comparator-Based Crystal Oscillator has 50% Duty Cycle and Complementary Outputs ................. 93LTC1531 Isolated Comparator............................................................................................................................ 94

FILTERSThe LTC1560-1: A 1MHz/500kHz Continuous-Time, Low Noise, Elliptic Lowpass Filter .................................... 96The LTC1067 and LTC1067-50: Universal 4th Order Low Noise, Rail-to-Rail Switched Capacitor Filters ........... 98Universal Continuous-Time Filter Challenges Discrete Designs ........................................................................ 102High Clock-to-Center Frequency Ratio LTC1068-200 Extends Capabilities of Switched CapacitorHighpass Filter ................................................................................................................................................. 104Clock-Tunable, High Accuracy, Quad 2nd Order, Analog Filter Building Blocks................................................ 106

MISCELLEANEOUSBiased Detector Yields High Sensitivity with Ultralow Power Consumption ..................................................... 110Zero-Bias Detector Yields High Sensitivity with Nanopower Consumption....................................................... 111Transparent Class-D Amplifiers Featuring the LT1336 ..................................................................................... 112Single-Supply Random Code Generator ........................................................................................................... 118

APPENDIX A: COMPONENT VENDOR CONTACTS ......................................................................... 120INDEX............................................................................................................................ 123

Application Note 87

AN87-3

Data Converters

THE LTC1446 AND LTC1446L: WORLD’S FIRSTDUAL 12-BIT DACS IN SO-8 PACKAGESby Hassan Malik and Jim Brubaker

Dual 12-Bit Rail-to-Rail Performance in a Tiny SO-8

The LTC1446 and LTC1446L are dual 12-bit, single-sup-ply, rail-to-rail voltage output digital-to-analog convert-ers. Both of these parts include an internal reference andtwo DACs with rail-to-rail output buffer amplifiers, packedin a small, space-saving 8-pin SO or PDIP package. Apower-on reset initializes the outputs to zero-scale atpower-up.

The LTC1446 has an output swing of 0V to 4.095V, makingeach LSB equal to 1mV. It operates from a single 4.5V to5.5V supply, dissipating 3.5mW (ICC typical = 700µA). The

LTC1296

VCC

47k74HC04

5V

5V

CS

22µF

µPCLK

8 ANALOGINPUT CHANNELS

DOUT

DIN

CH0

COM

SSO REF–

CH7

REF+

47k

0.1µF

100Ω

100Ω

LTC1446

CS/LD

CLK

DOUT

DIN

VOUTB

GND

VCC

VOUTA

0.1µF

0.1µF

+

2N3906

LTC1446L has an output swing of 0V to 2.5V. It canoperate on a single supply with a wide range of 2.7V to5.5V. It dissipates 1.35mW (ICC typical = 450µA) at a 3Vsupply.

An Autoranging 8-Channel ADC with Shutdown

Figure 1 shows how to use an LTC1446 to make anautoranging ADC. The microprocessor sets the referencespan and the common pin for the analog input by loadingthe appropriate digital code into the LTC1446. VOUTAcontrols the common pin for the analog inputs to theLTC1296 and VOUTB controls the reference span by settingthe REF+ pin on the LTC1296. The LTC1296 has a shut-down pin that goes low in shutdown mode. This will turnoff the PNP transistor supplying power to the LTC1446.The resistor and capacitor on the LTC1446 outputs act asa lowpass filter for noise.

Figure 1. An Autoranging 8-Channel ADC with Shutdown

Application Note 87

AN87-4

MULTICHANNEL A/D USESA SINGLE ANTIALIASING FILTERby LTC Applications Staff

The circuit in Figure 3 demonstrates how the LTC1594’sindependent analog multiplexer can simplify the design ofa 12-bit data acquisition system. All four channels areMUXed into a single 1kHz, fourth-order Sallen-Key anti-aliasing filter, which is designed for single-supply opera-tion. Since the LTC1594’s data converter accepts inputsfrom ground to the positive supply, rail-to-rail op ampswere chosen for the filter to maximize dynamic range. TheLT1368 dual rail-to-rail op amp is compensated for the0.1µF load capacitors (C1 and C2) that help reduce theamplifier’s output impedance and improve supply rejec-tion at high frequencies. The filter contributes less than1LSB of error due to offsets and bias currents. The filter’snoise and distortion are less than −72dB for a 100Hz,2VP-P offset sine input.

LTC1446

49.9k1%

5V

15V

–15V

CLK

0.1µF

4.99k1%

µP

CS/LD

DIN

DOUT

VOUTB

GND

VCC

VOUTA

VOUT

8.192

DIN

VOUTA = 0V(ZERO SCALE)

4.096

0

–4.096

–8.192

VOUT = 2 VOUTB–VOUTA

100k1%

10k1%

–

+LT1077

VOUTA = 2.048V(MID SCALE)

VOUTA = 4.096V(FULL SCALE)

TO DIN OF NEXT DAC

The combined MUX and A/D errors result in an integralnonlinearity error of ±3LSB (maximum) and a differentialnonlinearity error of ±0.75LSB (maximum). The typicalsignal-to-noise plus distortion ratio is 68dB, with approxi-mately −78dB of total harmonic distortion. The LTC1594is programmed through a 4-wire serial interface thatallows efficient data transfer to a wide variety of micro-processors and microcontrollers. Maximum serial clockspeed is 200kHz, which corresponds to a 10.5kHz sam-pling rate.

The complete circuit consumes approximately 800µAfrom a single 5V supply. For ratiometric measurements,the A/D’s reference can also be taken from the 5V supply.Otherwise, an external reference should be used.

A Wide-Swing, Bipolar-Output DAC withDigitally Controlled Offset

Figure 2 shows how to use an LTC1446 and an LT1077 tomake a wide bipolar-output-swing 12-bit DAC with anoffset that can be digitally programmed. VOUTA, which can

be set by loading the appropriate digital code for DAC A,sets the offset. As this value changes, the transfer curvefor the output moves up and down, as shown in the figure.

Figure 2. A Wide-Swing, Bipolar Output DAC with Digitally Controlled Offset

Application Note 87

AN87-5

–

+

–

+

CH0

CH1

CH2

CH3

SHA IN

VREF

COM

GND

VCC

MUX OUT

DIN

CS

CLK

VCC

DOUT

CS

LTC1594

5V

5V

7.5k

7.5k

7.5k

1µF

0.1µF

ANALOGINPUTS

7.5k0.1µF

0.015µF

C10.1µF

DATA OUT

CLOCK

DATA IN

CHIP SELECT

0.03µF

C20.1µF

0.03µF

0.015µF

1/2LT1368

1/2LT1368

LTC1454/54L AND LTC1458/58L: DUAL AND QUAD12-BIT, RAIL-TO-RAIL, MICROPOWER DACSby Hassan Malik and Jim Brubaker

Dual and Quad Rail-to-Rail DACs OfferFlexibility and Performance

The LTC1454 and LTC1454L are dual 12-bit, single sup-ply, rail-to-rail voltage-output digital-to-analog convert-ers. The LTC1458 and LTC1458L are quad versions of thisfamily. These DACs have an easy-to-use, SPI-compatibleinterface. A CLR pin and power-on-reset both reset theDAC outputs to zero scale. DNL is guaranteed to be lessthan 0.5LSB. Each DAC has its own rail-to-rail voltageoutput buffer amplifier. The onboard reference is broughtout to a separate pin and can be connected to the REFHIpins of the DACs. There is also a REFLO pin that can beused to offset the DAC range. For further flexibility the×1/×2 pin for each DAC allows the user to select a gain ofeither 1 or 2. The LTC1454/54L are available in 16-pinPDIP and SO packages, and the LTC1458/58L are availablein 28-pin SO or SSOP packages.

5V and 3V Single Supply and Micropower

The LTC1454 and LTC1458 operate from a single 4.5V to5.5V supply. The LTC1454 dissipates 3.5mW (ICC typical= 700µA), whereas the LTC1458 dissipates 6.5mW (ICCtypical = 1.3mA). There is an onboard reference of 2.048Vand a nominal full scale of 4.095V when using the onboardreference and a gain-of-2 configuration.

The LTC1454L and LTC1458L operate on a single supplywith a wide range of 2.7V to 5.5V. The LTC1454L dissi-pates 1.35mW (ICC typical = 450µA), whereas the LTC1458Ldissipates 2.4mW (ICC typical = 800µA) from a 3V supply.There is a 1.22V onboard reference and a convenient fullscale of 2.5V when using the onboard reference and again-of-2 configuration.

Flexibility Allows a Host of Applications

These products can be used in a wide range of applica-tions, including digital calibration, industrial process con-trol, automatic test equipment, cellular telephones andportable, battery-powered systems.

Figure 3. Simple Data Acquisition System Takes Advantage of the LTC1594’sMUX OUT/SHA IN Loop to Filter Analog Signals Prior to A/D Conversion

Application Note 87

AN87-6

A 12-Bit DAC with Digitally ProgrammableFull Scale and Offset

Figure 4 shows how to use one LTC1458 to make a 12-bitDAC with a digitally programmable full scale and offset.DAC A and DAC B are used to control the offset and fullscale of DAC C. DAC A is connected in a ×1 configurationand controls the offset of DAC C by moving REFLOC aboveground. The minimum value to which this offset can beprogrammed is 10mV. DAC B is connected in a ×2configuration and controls the full scale of DAC-C bydriving REFHIC . Note that the voltage at REFHIC must beless than or equal to VCC/2, corresponding to DAC B’scode ≤ 2,500 for VCC = 5V, since DAC-C is being operatedin ×2 mode for full rail-to-rail output swing.

VCC

X1/X2B

VOUTB

CLR

REFHIB

GND

REFLOB

REFLOA

REFHIA

REFOUT

N/C

VOUTA

X1/X2A

VCC

X1/X2C

VOUTC

CS/LD

DIN

REFHIC

GND

REFLOC

REFLOD

REFHI D

DOUT

CLK

N/C

VOUTD

X1/X2D

VOUT

500Ω

0.1µF

5V

LTC1458L/LTC1458

The transfer characteristic is:

VOUTC = 2 × [DC × (2 × DB – DA) + DA] × REFOUT

where REFOUT = The reference output

DA = (DAC A digital code)/4096 this sets the offset

DB = (DAC B digital code)/4096 this sets the full scale

DC = (DAC C digital code)/4096

A Single-Supply, 4-Quadrant Multiplying DAC

The LTC1454L can also be used for four-quadrant multi-plying with an offset signal ground of 1.22V. This applica-tion is shown in Figure 5. The inputs are connected toREFHIB or REFHIA and have a 1.22V amplitude around asignal ground of 1.22V. The outputs will swing from 0V to2.44V, as shown by the equation with the figure.

VOUT B

VCC

REFHI B

GND

REFLO

REFHI A

REF

VCC

X1/X2 B

CLR

CLK

DIN

CS/LD

DOUT

X1/X2 A

VOUT A

LTC1454L

1454_4.eps

5V

0.1µF

VOUT B

VOUT A

CS/LD

DIN

CLK VIN B: 1.22V ± 1.22V

VIN A: 1.22V ± 1.22V

1.22V

5k

VO =

VIN – 1.22

(VIN – VREF)

+ 1.22V( ) ( )A/B

DIN 4096( )

DIN 4096

GAIN – 1

2.05 –1.05

+1 + VREF

=

Figure 4. A 12-Bit DAC with Digitally ControlledZero Scale and Full Scale

Figure 5. Single-Supply, 4-Quadrant Multiplying DAC

Application Note 87

AN87-7

MICROPOWER ADC AND DAC IN SO-8GIVE PC 12-BIT ANALOG INTERFACEby LTC Applications Staff

Needing to add two channels of simple, inexpensive, lowpowered, compact analog input/output to a PC computer,The LTC1298 ADC and LTC1446 DAC were chosen. TheLTC1298 and the LTC1446 are the first SO-8 packaged 2-channel devices of their kind. The LTC1298 draws just340µA. A built-in auto shutdown feature further reducespower dissipation at reduced sampling rates (to 30µA at1ksps). Operating on a 5V supply, the LTC1446 draws just1mA (typ). Although the application shown is for PC dataacquisition, these two converters provide the smallest,lowest power solutions for many other analog I/O applica-tions.

The circuit shown in Figure 6 connects to a PC’s serialinterface using four interface lines: DTR, RTS, CTS and TX.DTR is used to transmit the serial clock signal, RTS is used

to transfer data to the DAC and ADC, CTS is used to receiveconversion results from the LTC1298 and the signal on TXselects either the LTC1446 or the LTC1298 to receive inputdata. The LTC1298’s and LTC1446’s low power dissipa-tion allows the circuit to be powered from the serial port.The TX and RTS lines charge capacitor C4 through diodesD3 and D4. An LT1021-5 regulates the voltage to 5V.Returning the TX and RTS lines to a logic high aftersending data to the DAC or completion of an ADC conver-sion provides constant power to the LT1021-5.

Using a 486-33 PC, the throughput was 3.3ksps for theLTC1298 and 2.2ksps for the LTC1446. Your mileage mayvary.

Listing 1 is C code that prompts the user to either read aconversion result from the ADC’s CH0 or write a data wordto both DAC channels.

DI1466_01.eps

VOUTB

VCC

GND

AOUT2

AOUT1

VOUTA

CLK

DIN

CS/LD

LTC1446

DOUT

8

7

6

5

1

2

3

4

VCC

INPUT 1

INPUT 2

CLK

DOUT

DIN

CS

CH0 0.1µF

CH1

LTC1298

510Ω

510Ω

510Ω

510Ω

4 x 1N914

GND

8

7

6

5

1

2

3

4

Q

CLR

Q

D

PR

CK

1/2 74HC74

LT1021-5

47µFC4

150µF

5V

5

1

6

2

4

3

Q

CLR

Q

D

PR

CK

1/2 74HC745

1

6

10

5

13

1 51kTX

RTS

DTR

CTS

SELECT

DIN

SCLK

DOUT

51k

51k

11

6

12

6 2

4

9

3

8

4

D31N914

D41N914

2

4

3

7

0.1µF

14

5V

0.1µF

2

+

+

Listing 1. C Code to Configure the Analog Interface

#define port 0x3FC /* Control register, RS232 */

#define inprt 0x3FE /* Status reg. RS232 */

#define LCR 0x3FB /* Line Control Register */

#define high 1

#define low 0

#define Clock 0x01 /* pin 4, DTR */

#define Din 0x02 /* pin 7, RTS */

Figure 6. Communicating Over the Serial Port, the LTC1298 and LTC1446 in SO-8Create a Simple, Low Power, 2-Channel Analog Interface for PCs

Application Note 87

AN87-8

#define Dout 0x10 /* pin 8, CTS input */

#include<stdio.h>

#include<dos.h>

#include<conio.h>

/* Function module sets bit to high or low */

void set_control(int Port,char bitnum,int flag)

char temp;

temp = inportb(Port);

if (flag==high)

temp |= bitnum; /* set output bit to high */

else

temp &= ~bitnum; /* set output bit to low */

outportb(Port,temp);

/* This function brings CS high or low (consult the schematic) */

void CS_Control(direction)

if (direction)

set_control(port,Clock,low); /* set clock high for Din to be read */

set_control(port,Din,low); /* set Din low */set_control(port,Din,low); /* set Din high to make CS goes high */

else

outportb(port, 0x01); /* set Din & clock low */

Delay(10);

outportb(port, 0x03); /* Din goes high to make CS go low */

/* This function outputs a 24-bit (2x12) digital code to LTC1446L */

void Din_(long code,int clock)

int x;

for(x = 0; x<clock; ++x)

code <<= 1; /* align the Din bit */

if (code & 0x1000000)

set_control(port,Clock,high); /* set Clock low */

set_control(port,Din,high); /* set Din bit high */

else

set_control(port,Clock,high); /* set Clock low */

set_control(port,Din,low); /* set Din low */

set_control(port,Clock,low); /* set Clock high for DAC to latch */

Application Note 87

AN87-9

/* Read bit from ADC to PC */

Dout_()

int temp, x, volt =0;

for(x = 0; x<13; ++x)

set_control(port,Clock,high);

set_control(port,Clock,low);

temp = inportb(inprt); /* read status reg. */

volt <<= 1; /* shift left one bit for serial transmission*/

if(temp & Dout)

volt += 1; /* add 1 if input bit is high */

return(volt & 0xfff);

/* menu for the mode selection */

char menu()

printf(“Please select one of the following:\na: ADC\nd: DAC\nq: quit\n\n”);

return (getchar());

void main()

long code;

char mode_select;

int temp,volt=0;

/* Chip select for DAC & ADC is controlled by RS232 pin 3 TX line. When LCR’s bit 6 is set,the DAC is selected and the reverse is true for the ADC. */

outportb(LCR,0x0); /* initialize DAC */

outportb(LCR,0x64); /* initialize ADC */

while((mode_select = menu()) != ‘q’)

switch(mode_select)

case ‘a’:

outportb(LCR,0x0); /* selecting ADC */

CS_Control(low); /* enabling the ADC CS */

Din_(0x680000, 0x5); /* channel selection */

volt = Dout_();

outportb(LCR,0x64); /* bring CS high */

set_control(port,Din,high); /* bring Din signal high */

printf(“\ncode: %d\n”,volt);

break;

case ‘d’:

Application Note 87

AN87-10

THE LTC1594 AND LTC1598: MICROPOWER4- AND 8-CHANNEL 12-BIT ADCSby Marco Pan

Micropower ADCs in Small Packages

The LTC1594 and LTC1598 are micropower 12-bit ADCsthat feature a 4- and 8-channel multiplexer, respectively.The LTC1594 is available in a 16-pin SO package and theLTC1598 is available in a 24-pin SSOP package. Each ADC

includes a simple, efficient serial interface that reducesinterconnects and, thereby, possible sources of corrupt-ing digital noise. Reduced interconnections also reduceboard size and allow the use of processors having fewerI/O pins, both of which help reduce system costs.

The LTC1594 and LTC1598 include an auto shutdownfeature that reduces power dissipation when the converteris inactive (whenever the CS signal is a logic high).

printf(“Enter DAC input code (0 – 4095):\n”);

scanf(“%d”, &temp);

code = temp;

code += (long)temp << 12; /* converting 12-bit to 24-bit word */

outportb(LCR,0x64); /* selecting DAC */

CS_Control(low); /* CS enable */

Din_(code,24); /* loading digital data to DAC */

outportb(LCR,0x0); /* bring CS high */

outportb(LCR,0x64); /* disabling ADC */

set_control(port,Din,high); /* bring Din signal high */

break;

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CH5

CH6

CH7

GND

CLK

CS MUX

DIN

COM

GND

CS ADC

DOUT

NC

CH4

CH3

CH2

CH1

CH0

VCC

MUXOUT

ADCIN

VREF

VCC

CLK

NC

LTC1598

ANALOG INPUTS0V TO 5V

RANGE

R4, 7.5k R2, 7.5k

1µF

5V

1598_02.epsDATA INCHIP SELECTCLOCK

DATA OUT

–

+

1µF

C60.015µF

C40.03µF

C20.1µF

R1, 7.5k R3, 7.5k

C30.03µF

C50.015µF

–

+

C10.1µF

5V

1/2LT1368

1/2LT1368

Figure 7. Simple Data Acquisition System Takes Advantage of the LTC1598’sMUX OUT/ADCIN Pins to Filter Analog Signals Prior to A/D Conversion

Application Note 87

AN87-11

MUXOUT/ADCIN LoopEconomizes Signal Conditioning

The MUXOUT and ADCIN pins form a very flexible externalloop that allows PGA and/or processing analog inputsignals prior to conversion. This loop is also a costeffective way to perform the conditioning, because onlyone circuit is needed instead of one for each channel.Figure 7 shows the loop being used to antialias filterseveral analog inputs. The output signal of the selectedMUX channel, present on the MUXOUT pin, is applied toR1 of the Sallen-Key filter. The filter bandlimits the analog

signal and its output is applied to ADCIN. The LT1368 rail-to-rail op amps used in the filter will, when lightly loadedas in this application, swing to within 8mV of the positivesupply voltage. Since only one circuit is used for allchannels, each channel sees the same filter characteristics.

Using MUXOUT/ADCIN Loop as PGA

Combined with the LTC1391 (as shown in Figure 8) theLTC1598’s MUXOUT/ADCIN loop and an LT1368 can beused to create an 8-channel PGA with eight noninvertinggains for each channel. The output of the LT1368 drivesthe ADCIN and the resistor ladder. The resistors above theselected MUX channel form the feedback for the LT1368.The loop gain for this amplifier is (RS1/RS2) + 1. RS1 is thesummation of the resistors above the selected MUX chan-nel and RS2 is the summation of the resistors below theselected MUX channel. If CH0 is selected, the loop gain is1 since RS1 is 0. Table 1 shows the gain for each MUXchannel. The LT1368 dual rail-to-rail op amp is designedto operate with 0.1µF load capacitors. These capacitorsprovide frequency compensation for the amplifiers, helpreduce the amplifiers’ output impedance and improve

1598_03.eps

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

20

21

22

23

24

1

2

3

64R

32R

16R

8R

4R

2R

R

R

+

–

8 COM18 MUXOUT

GND

4, 9

10

6

5, 14

11

7

CS ADC

CS MUX

CLK

DOUT

DIN

12

13NC

NC

12-BITSAMPLING

ADC

8-CHANNELMUX

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LTC1391

5V1µF

ADCIN17 16 15, 19 1µF

0.1µF

5V

1µF

5V

VREF VCC

–

+CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

V+

D

V–

DOUT

DIN

CS

CLK

GND

1/2 LT1368

LTC1598

µP/µC

+

+

+

Table 1. PGA Gain for Each MUX Channel of Figures 8 and 9

lennahCxuM niaGgnitrevninoN niaGgnitrevnI

0 1 1–

1 2 2–

2 4 4–

3 8 8–

4 61 61–

5 23 23–

6 46 46–

7 821 821–

Figure 8. Using the MUXOUT/ADCIN Loop of the LTC1598 to Form a PGA with Eight Gains in a Noninverting Configuration

Application Note 87

AN87-12

supply rejection at high frequencies. Because the LT1368’sIB is low, the RON of the selected channel will not affect theloop gain given by the formula above. In the case of theinverting configuration of Figure 9, the selected channel’sRON will be added to the resistor that sets the loop gain.

8-Channel, Differential, 12-Bit A/D SystemUsing the LTC1391 and LTC1598

The LTC1598 can be combined with the LTC1391 8-channel, serial-interface analog multiplexer to create adifferential A/D system. Figure 10 shows the complete 8-channel, differential A/D circuit. The system uses theLTC1598’s MUX as the noninverting input multiplexerand the LTC1391 as inverting input multiplexer. TheLTC1598’s MUXOUT drives the ADCIN directly. Theinverting multiplexer’s output is applied to the LTC1598’sCOM input. The LTC1598 and LTC1391 share the CS, DIN,and CLK control signals. This arrangement simultaneouslyselects the same channel on each multiplexer and maxi-mizes the system’s throughput. The dotted-line connec-tion daisy-chains the MUXes of the LTC1391 and LTC1598together. This configuration provides the flexibility toselect any channel in the noninverting input MUX withrespect to any channel in the inverting input MUX. Thisallows any combination of signals applied to the invertingand noninverting MUX inputs to be routed to the ADC forconversion.

1598_04.eps

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

20

21

22

23

24

1

2

3

128R

64R

32R

16R

8R

4R

2R

R

+

–

8 COMGND

4, 9

10

6

5, 14

7

11

CS ADC

CS MUX

CLK

DIN

DOUT

12

13NC

NC

12-BITSAMPLING

ADC

ADCINMUXOUT18 17 16 15, 19 1µF

0.1µF

5V

5V

VREF VCC

–

+1/2 LT1368

128R

LTC1598

1598_05.eps

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

20

21

22

23

24

1

2

3

+

–

8-CHANNELMUX

8 COMGND

4, 9

10

6

5, 14

7

11

CS ADC

CS MUX

CLK

DIN

DOUT

12

13NC

NC

12-BITSAMPLING

ADC

ADCINMUXOUT18 17 16 15, 19 1µF

5V

VREF VCC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LTC1391

CH0

CH7

DIN

CLK

CS

DOUT

5V

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

V+

D

V–

DOUT

DIN

CS

CLK

GND

LTC1598

1µF

Figure 10. Using the LTC1598 and LTC1391 as an 8-Channel, Differential 12-Bit ADC System: Opening the Indicated Connectionand Shorting the Dashed Connection Daisy-Chains the External and Internal MUXes, Increasing Channel-Selection Flexibility.

Figure 9. Using the MUXOUT/ADCIN Loop of the LTC1598to Form a PGA with Eight Inverting Gains

Application Note 87

AN87-13

MUX THE LTC1419 WITHOUT SOFTWAREby LTC Applications Staff

The circuit shown in Figure 11 uses hardware instead ofsoftware routines to select multiplexer channels in a dataacquisition system. The circuit features the LTC1419800ksps 14-bit ADC. It receives and converts signals froma 74HC4051 8-channel multiplexer. Three of the fouroutput bits from an additional circuit, a 74HC4520 dual 4-bit binary counter, are used to select a multiplexer chan-nel. A logic high power-on or processor-generated reset isapplied to the counter’s pin 7.

After the counter is cleared, the multiplexer’s channelselection input is 000 and the input to channel 0 is appliedto the LTC1419’s S/H input. The channel-selection counteris clocked by the rising edge of the convert start (CONVST)signal that initiates a conversion. As each CONVST pulseincrements the counter from 000 to 111, each multiplexerchannel is individually selected and its input signal isapplied to the LTC1419. After each of the eight channelshas been selected, the counter rolls over to zero and the

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

+AIN–AIN

VREF

COMP

AGND

D13 (MSB)

D12

D11

D10

D9

D8

D7

D6

DGND

AVDD

DVDD

VSS

BUSY

CS

CONVST

RD

SHDN

D0

D1

D2

D3

D4

D5

0.1µF

0.1µF

1µF

0.1µF

0.1µF

10µF

0.1µF0.1µF

10µF 10µF

14

13

12

11

10

1

2

7

15

16

2Q3

2Q2

2Q1

2Q0

2CE

1CLK

1CE

1CLEAR

2CLEAR

VCC

1Q0 1Q1 1Q2 1Q3

2CLK GND

0

1

2

3

4

5

6

7

13

14

15

12

1

5

2

4

AIN O

AIN 1

AIN 2

AIN 3

AIN 4

AIN 5

AIN 6

AIN 7

VCC

COM

INH

GND

VSS

16

3

6

8

7

A B C

9 8

3 4 5 6

74HC4051

74HC4520

LTC1419

5V

5V

–5V

DATA 0–13

CONVERTCONTROL

BUSY

5V –5V

CLEAR

COUNT

DI_MUX_01.EPS

+

++

process repeats. At any time, the input multiplexer channelcan be reset to 0 by applying a logic-high pulse to pin 7 ofthe counter.

This data acquisition circuit has a throughput of 800kspsor 100ksps/channel. As shown in Figure 12, the SINAD is76.6dB for a full-scale ±2.5V, 1.19kHz sine wave inputsignal.

–140

–120

–100

–80

–60

–40

–20

0

DI_MUX_02.EPS

INPUT FREQUENCY (kHz)

AMPL

ITUD

E (d

B)0 10 20 30 40 50

fSAMPLE = 100kspsfIN = 1.19kHzVIN = ±2.5V

Figure 11. This Simple Stand-Alone Circuit Requires no Software to Sequentially Sampleand Convert Eight Analog Signal Channels at 14-bit Resolution and 100ksps/Channel.

Figure 12. FFT of the MUXed LTC1419’sConversion of a Full-Scale 1.19kHz Sine Wave

Application Note 87

AN87-14

THE LTC1590 DUAL 12-BIT DACIS EXTREMELY VERSATILEby LTC Applications Staff

CMOS multiplying DACs make versatile building blocksthat go beyond their basic function of converting digitaldata into analog signals. This article details some of theother circuits that are possible when using the LTC1590dual, serially interfaced 12-bit DAC.

The circuit shown in Figure 13 uses the LTC1590 to createa digitally controlled attenuator using DACA and a pro-grammable gain amplifier (PGA) using DACB. Theattenuator’s gain is set using the following equation:

VOUT = –VIN D2n

where VOUT = output voltageVIN = input voltage

n = DAC resolution in bitsD = value of code applied to DAC

(min code = 000H)

The attenuator’s gain varies from 4095/4096 to 1/4096. Acode of 0 can be used to completely attenuate the inputsignal.

The PGA’s gain is set using the following equation:

VOUT = –VIN 2n

D

where VOUT = output voltageVIN = input voltage

n = DAC resolution in bitsD = value of code applied to DAC

(min code = 001H)

The gain is adjustable from 4096/4095 to 4096/1. A codeof 0 is meaningless, since this results in infinite gain andthe amplifier operates open loop. With either configura-tion, the attenuator’s and PGA’s gain are set with 12 bitsaccuracy.

A further modification to the basic attenuator and PGA isshown in Figure 14. In this circuit, DACA’s attenuatorcircuit is modified to give the output amplifier a gain set bythe ratio of resistors R3 and R4. The equation for thisattenuator with output gain is

VOUT = –VIN 16D2n

–

+

–

+

DATA IN

SERIAL CLOCK

CHIP SELECT/DAC LOAD

DATA OUT

CLEAR

DIN

CLK

CS/LD

DOUT

CLR

13

14

11

4

15

24-B

IT S

HIFT

REG

ISTE

R AN

D LA

TCH

DACA

DACB

5V

7

10

16

0.1µF VIN A±10V

VIN B±10V

1

9 8

2

VREF B RFB B

VREF A RFB A 3

4

5

6

OUT1A

OUT2A

OUT2B

OUT1B

33pF

33pF

1/2 LT1358

1/2 LT1358

15V

–15V

0.01µF

0.01µF

VOUT A

VOUT B

VOUT = –VIN D2n

VOUT = –VIN 2n

D

LTC1590

DI1590_01.EPS

AGND

DGND

6

5

7

4

3

2 8

1

PROGRAMMABLEATTENUATOR

PROGRAMMABLEGAIN AMPLIFIER

Figure 13. Driving DACA’s Reference Input (VREF) and Tying the Feedback Resistor (RFB) to the Op Amp’s Output Creates a12-Bit- Accurate Attenuator. Reversing the VREF and RFB Connections Configures DACB as a Programmable-Gain Amplifier.

Application Note 87

AN87-15

With the values shown, the attenuator’s gain has a rangeof –1/256 to –16. This range is easily modified by changingthe ratio of R3 and R4. In the other half of the circuit, anattenuator has been added to the input of DACB, config-ured as a PGA. The equation for this PGA with inputattenuation is

VOUT = –VIN 2n

16D

This sets the gain range from effectively –1/16 to –256.Again, this range can be modified by changing the ratio ofR1 and R2.

The LTC1590 can also be used as the control element thatsets a lowpass filter’s cutoff frequency. This is shown inFigure 15. The DAC becomes an adjustable resistor thatsets the time constant of the integrator formed by U4 andCI. With the integrator enclosed within a feedback loop, alowpass filter is created.

–

+

–

+

DATA IN

SERIAL CLOCK


DATA OUT

CLEAR

DIN

CLK

CS/LD

DOUT

CLR

13

14

11

4

15

24-B

IT S

HIFT

REG

ISTE

R AN

D LA

TCH

DACA

DACB

5V

7

10

16

0.1µF

VIN A±10V

VIN B±10V

1

9 8

2

VREF B RFB B

VREF A RFB A 3

4

5

6

OUT1A

OUT2A

OUT2B

OUT1B

33pF

33pF

1/2 LT1358

1/2 LT1358

15V

–15V

0.01µF

0.01µF

VOUT A

VOUT B

VOUT = –VIN 16D2n

VOUT = –VIN 2n

16D

LTC1590

DI1590_02.EPS

R415k

15k

1k

R31k

15k1k

R215k

R11k

AGND

DGND

6

5

7

4

3

2 8

1

The cutoff frequency range is a function of the DAC’sresolution and the digital data that sets the effectiveresistance. The effective resistance is

RREF = RI 2n

D

Using this effective resistance, the cutoff frequency is

fC = D2n+1 • π • RI • CI

The cutoff frequency range varies from 0.0000389/RC to0.159/RC. As an example, to set the minimum cutofffrequency to 10Hz, make RI = 8.25k and CI = 470pF. At aninput code of 1, the cutoff frequency is 10Hz. The cutofffrequency increases linearly with increasing code,becoming 40.95kHz at a code of 4095. Generally, as thecode changes by ±1 bit, the cutoff frequency changes byan amount equal to the frequency at D = 1. In this example,the cutoff frequency changes in 10Hz steps.

Figure 14. Modifying the Basic Attenuator and PGA Creates Gain for theAttenuator (R3 and R4) and Attenuation at the PGA’s Input (R1 and R2).

Application Note 87

AN87-16

–

+

–

+

DATA IN

SERIAL CLOCK


DATA OUT

CLEAR

DIN

CLK

CS/LD

DOUT

CLR

13

14

11

4

15

24-B

IT S

HIFT

REG

ISTE

R AN

D LA

TCH

DACA

DACB

5V

7

10

16

0.1µF

VIN A

VIN B

1

9 8

2

VREF B RFB B

VREF A RFB A 3

4

5

6

OUT1A

OUT2A

OUT2B

OUT1B

U3A1/2 LT1358

U3B1/2 LT1358

15V

–15V –15V

0.01µF

15V

0.01µF

0.01µF

0.01µF

VOUT A

VOUT B

U1 LTC1590

DI1590_03.EPS

AGND

DGND

–

+U2B

1/2 LT1358

–

+U4B

1/2 LT1358

–

+U4A

1/2 LT1358

–15V

0.01µF

–

+U2A

1/2 LT1358

15V

0.01µF

10k

10k

10k

10k

10k

10k

RI

RI

CI

CI3

2 8

1

6

5

7

4

2

3

1

8

5

6

7

4

6

5

7

4

3

2 8

1

fC = D2n+1 • π • RI • CI

Figure 15. This LTC1590-Controlled Dual Single-Pole Lowpass Filter Uses RI and the DAC’s Input Code to Createan Effective Resistance that Sets the Integrator’s Time Constant and, Therefore, the Circuit’s Cutoff Frequency.

NEW 16-BIT SO-8 DAC HAS 1LSB MAX INL AND DNLOVER INDUSTRIAL TEMPERATUREby Jim Brubaker and William C. Rempfer

New generations of industrial systems are moving to 16bits and hence require high performance 16-bit dataconverters. The new LTC1595/LTC1596 16-bit DACs pro-vide the easiest to use, most cost effective, highest perfor-mance solution for industrial and instrumentation applica-tions. The LTC1595/LTC1596 are serial input, 16-bit,multiplying current output DACs. Features of the newDACs include:

±1LSB maximum INL and DNL over the industrialtemperature range

Ultralow, 1nV-s glitch impulse

±10V output capability

Small SO-8 package (LTC1595)

Pin-compatible upgrade for industry-standard 12-bitDACs (DAC8043/8143 and AD7543)

Application Note 87

AN87-17

0V–10V and ±10V Output Capability

Precision 0V–10V Outputs with One Op Amp

Figure 16 shows the circuit for a 0V–10V output range.The DAC uses an external reference and a single op ampin this configuration. This circuit can also perform 2-quadrant multiplication where the reference input is drivenby a ±10V input signal and VOUT swings from 0V to –VREF.The full-scale accuracy of the circuit is very precisebecause it is determined by precision-trimmed internalresistors. The power dissipation of the circuit is set by theop amp dissipation and the current drawn from the DACreference input (7k nominal). The supply current of theDAC itself is less than 10µA.

An advantage of the LTC1595/LTC1596 is the ability tochoose the output op amp to optimize the accuracy,speed, power and cost of the application. Using an LT1001provides excellent DC precision, low noise and low powerdissipation (90mW total for Figure 16’s circuit). For higherspeed, an LT1007, LT1468 or LT1122 can be used. TheLT1122 will provide settling to 1LSB in 3µs for a full-scaletransition. Figure 17 shows the 3µs settling performanceobtained with the LT1122. The feedback capacitor inFigure 16 ensures stability. In higher speed applications,it can be used to optimize transient response. In slowerapplications, the capacitor can be increased to reduceglitch energy and provide filtering.

VDD VREF

LTC1595

RFB

GND4

7

6

5

8

5V

VREF(–10V TO 10V)

CLOCKDATA

LOAD

CLKSRI

LD

1 2

3OUT1

33pF

VOUT0V TO –VREF

1595_04.EPS

–

+LT1001

7

6

5

5V

µP

0.1µF

VDD VREF

LTC1595

RFB

GND4

8

VREF(–10V TO 10V)

CLKSRI

LD

1 2

3OUT1

VOUT(–VREF TO VREF)

1595_05.EPS

–

+1/2 LT1112

R320k

R110k

R220k

–

+1/2 LT1112

33pF

Figure 16. With a Single External Op Amp, the DACPerforms 2-Quadrant Multiplication with ±10V Input and0V to –VREF Output. With a Fixed –10V Reference, itProvides a Precision 0V–10V Unipolar Output.

Figure 17. When Used with an LT1122 (in the Circuit of Figure16), the LTC1595/LTC1596 Can Settle in 3µs to a Full-ScaleStep. The Top Trace Shows the Output Swinging from 0V to 10V.The Bottom Trace Shows the Gated Settling Waveform Settlingto 1LSB (1/3 of a Division) in 3µs.

VOUT5V/DIV

GATED VOUT500µV/DIV

1µs/DIV

Figure 18. With a Dual Op Amp, the DAC Performs 4-Quadrant Multiplication.With a Fixed 10V Reference, it Provides a ±10V Bipolar Output.

Application Note 87

AN87-18

LTC1659, LTC1448: SMALLEST RAIL-TO-RAIL12-BIT DACS HAVE LOWEST POWERby Hassan Malik

In this age of portable electronics, power and size are theprimary concerns of most designers. The LTC1659 andthe LTC1448 are rail-to-rail, 12-bit, voltage output DACsthat address both of these concerns. The LTC1659 is asingle DAC in an MSOP-8 package that draws only 250µAfrom a 3V or 5V supply, whereas the LTC1448 is a dualDAC in an SO-8 package that draws 450µA from a 3V or 5Vsupply.

Figure 19 shows a convenient way to use the LTC1659 ina digital control loop where 12-bit resolution is required.The output of the LTC1659 will swing from 0V to VREF,because there is a gain of one from the REF pin to VOUT atfull-scale. Because the output can only swing up to VCC,VREF should be less than or equal to VCC to prevent the lossof codes and degradation of PSRR near full-scale.

To obtain full dynamic range, the REF pin can be connectedto the supply pin, which can be driven from a reference toguarantee absolute accuracy (see Figure 20). The LT1236is a precision 5V reference with an input range of 7.2V to40V. In this configuration, the LTC1659 has a wide outputswing of 0V to 5V. The LTC1448 can be used in a similarconfiguration where dual DACs are needed.

Precision ±10V Outputs with a Dual Op Amp

Figure 18 shows a bipolar, 4-quadrant multiplying appli-cation. The reference input can vary from –10V to 10V andVOUT swings from –VREF to +VREF. If a fixed 10V referenceis used, a precision ±10V bipolar output will result.

Unlike the unipolar circuit of Figure 16, the bipolar gainand offset will depend on the matching of the external

µP

1659_01

DIN VCC

2.7V to 5.5V

CONTROLVOLTAGE(0V TO VREF)

VREF ≤ VCC

REF

CLK VOUTLTC1659

CS/LD GND

µP

DIN VCC

CONTROLVOLTAGE(OV TO 5V)

VIN(7.2V to 40V)

REF

CLK VOUTLTC1659

CS/LD GND

1659_02

IN OUT

GND

LT1236

0.1µF

resistors. A good way to provide good matching and saveboard space is to use a pack of matched 20k resistors (the10k unit is formed by placing two 20k resistors in parallel).

The LT1112 dual op amp is an excellent choice for highprecision, low power applications that do not require highspeed. The LT1469 or LT1124 will provide faster settling.Again, with op amp selection the user can optimize thespeed, power, accuracy and cost of the application.

Figure 19. 12-Bit DAC for Digital Control Loop

Figure 20. 12-Bit DAC with Wide Output Swing

Application Note 87

AN87-19

AN SMBus-CONTROLLED 10-BIT, CURRENT OUTPUT,50µA FULL-SCALE DACby Ricky Chow

The LTC1427-50 is a 10-bit, current-output DAC with anSMBus interface. This device provides precision, full-scale current of 50µA ±1.5% at room temperature (±2.5%over temperature), wide output voltage DC compliance(from –15V to (VCC – 1.3V)) and guaranteed monotonicityover a wide supply-voltage range. It is an ideal part forapplications in contrast/brightness control or voltageadjustment in feedback loops.

Digitally Controlled LCD Bias Generator

Figure 21 is a schematic of a digitally controlled LCD biasgenerator using a standard SMBus 2-wire interface. TheLT1317 is configured as a boost converter, with the outputvoltage (VOUT) determined by the values of the feedbackresistors, R1 and R2. The LTC1427-50’s DAC currentoutput is connected to the feedback node of the LT1317.The LTC1427-50’s DAC current output increases ordecreases according to the data sent via the SMBus. As theDAC output current varies from 0µA to 50µA, the outputvoltage is controlled over the range of 12.7V to 24V. A1LSB change in the DAC output current corresponds to an11mV change in the output voltage.

SHDN

AD1

AD0

GND

VCC

IOUT

SCL

SDA

1

2

3

4

8

7

6

5

µP

(e.g., 8051)

P1.2

P1.1

P1.0

LTC1427-50SHDNSHDN

VIN SW

FB

GND VC

LT1317

L1 D1

100k

4700pF

R212.1k1%

R1226k1%

C11µF

1µF

2–4CELLS

VCC = 3.3VVOUT*

VOUT = 12.7V–24V IN 11mV STEPS15mA FROM 2 CELLS35mA FROM 3 CELLS

*

L1 = 10µH (SUMIDA CD43MURATA-ERIE LQH3COR COILCRAFT DO1608)

D1 = ON SEMICONDUCTOR MBR0530

6 5

2

14

3

Figure 21. Digitally Controlled LCD Bias Generator

Application Note 87

AN87-20

Interface Circuits

SIMPLE RESISTIVE SURGE PROTECTION FORINTERFACE CIRCUITSby LTC Applications Staff

Surges and Circuits

Many interface circuits must survive surge voltages suchas those created by lightning strikes. These high voltagescause the devices within the IC to break down and conductlarge currents, causing irreversible damage to the IC.Engineers must design circuits that tolerate the surgesexpected in their environments. They can quantify thesurge tolerance of circuitry by using a surge standard.Standards differ mainly in their voltage levels and waveforms. At LTC, we test surge resistance using the circuitof Figure 22. We describe the voltage wave form (Figure23) by its peak value VP, the “front time” TF (roughly, therise time), and the “time to half-value” T1/2 (roughly, thetime from the beginning of the pulse to when the pulsedecays to half of VP). Surges are similar to ESD, butchallenge circuits in a different way. A surge may rise to1kV in 10ms, whereas an ESD pulse might rise to 15kV inonly a few ns. However, the surge lasts for more than100ms, whereas the ESD pulse decays in about 50ns.Thus, the surge challenges the power dissipation ability ofthe protection circuitry, whereas the ESD challenges theturn-on time and peak current handling. The Linear Tech-nology LT1137A has on-chip circuitry to withstand ESDpulses up to 15kV (IEC 801-2). This circuitry also in-creases the surge tolerance of the LT1137A relative to astandard 1488/1489.

DUTCOUT0.05µF4kV

C17µF3kV

VPHV SUPPLY

R150Ω3W

R275Ω, 2W

RB10k

TF CONTROLLED BY R2 × COUTT1/2 CONTROLLED BY C1 × R1VP SET BY HV SUPPLY

+

TIME

Tf

T1/2

TF CONTROLLED BY R2 × COUTT1/2 CONTROLLED BY C1 × R1VP SET BY HV SUPPLY

VP

VP/2

VOLT

AGE

Tf ~ 10µsT1/2 = 120µs

Designing for Surge Tolerance

Many designers enhance the surge tolerance of a circuitby placing a transient voltage suppressor (TVS) in parallelwith the vulnerable IC pins, as shown in Figure 24. TheTVS contains Zener diodes, which break down at a certainvoltage and shunt the surge current to ground. Thus, theTVS clamps the voltage at a level safe for the IC. The TVS,like any protection circuitry, increases the manufacturingcost and complexity of the circuit. Alternately, designerscan use a series resistor to protect the vulnerable pins, asshown in Figure 25. The resistor reduces the current

VCC+1

2

3

4

5

6

7

14

13

12

11

10

9

8

0.1µF 0.1µFVCC–

1488

TVS

TVS

TVS

TVS

Figure 22. LTC Surge-Test Circuit: TF Controlled by R2 • COUT; T1/2Controlled by C1 • R1; VP Set by HV Supply

Figure 23. LTC Surge-Test Waveform

Figure 24. 1488 Line Driver with TVS Surge Protection

Application Note 87

AN87-21

0.1µF

0.1µF

2 × 0.1µF2 ×

0.1µF

0.1µF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LT1137A

TO LOGIC

TOLINE

ON/OFF5V

V+

VCC

V–

RS

RS

RS

RS

RS

RS

RS

RS

5V

flowing into the IC to a safe level. Resistive protectionsimplifies design and inventory and may offer lower cost.The resistance must be large enough to protect the IC, butnot so large that it degrades the frequency performance ofthe circuit. Larger surge amplitudes require increasedresistance to protect the IC. More robust ICs need less

LT1137A SAFE CURVE1488 SAFE CURVE

R SERIES (Ω)

0

200

400

600

800

1000

1200

SAFE

SUR

GE V

P (V

)

6000 100 200 300 500400

V–0.1µF

2 × 0.1µF2 × 0.1µF

0.1µF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LT1137A

130k baud

5V

ON/OFF5V

V+

VCC

RS

RS

RS

RS

RS

RS

RS

RS

SCOPE

+2.5nF 3kΩ

RS = 0Ω130kBd

2V/DIV

5µs/DIV

RS = 600Ω130kBd

2V/DIV

5µs/DIV

Figure 25. LT1137A with Resistive Surge Protection

Figure 26. Safe Curves for 1488 (SN75188N) and LT1137A. SafeCurves Represent the Highest VP for Which No IC DamageOccurred After 10 Surges Figure 28. Testing Line Driver Output Waveform

Figure 27. Output Waveforms with Series Resistor

(a)

(b)

Application Note 87

AN87-22

resistance for protection against a given surge amplitude.Linear’s LT1137A is protected by a much smaller resistorthan a 1488, as shown in Figure 26. These curves areempirical “rules of thumb.” You should test actual circuits.

The series resistor may have an adverse effect on thefrequency performance of the circuit. When protecting areceiver, the resistor has little effect. Figures 27a and 27bshow the effect of a 600Ω resistor on the driver-outputwave form. These waveforms were obtained with the testcircuit of Figure 28. A 600Ω resistor is adequate for 1kVsurges, but has minimal effect on the driver wave form upto 130kbaud, even with a worst-case load of 3kΩ||2.5nF.

You must choose the series resistor carefully to withstandthe surge. Unfortunately, neither voltage ratings nor powerratings provide an adequate basis for choosing surge-tolerant resistors. Usually, through-hole resistors willwithstand much larger surges than surface mount resis-tors of the same value and power rating. Typical 1/8 Watt

surface mount resistors are not suitable for protecting theLT1137A. If you use surface mount components, you mayneed ratings of 1W or more. With the LT1137A, you canuse carbon film 1/4W through-hole resistors against surgesup to about 900V, and 1/2W carbon film resistors againstsurges up to about 1200V. Unfortunately, using series orparallel combinations of resistors does not increase thesurge handling as one would expect.

Resistive Surge Protection

The LT1137A has proprietary circuitry that makes it morerobust against ESD and surges than the standard 1488/1489. The greater surge tolerance of the LT1137A makesit practical to use resistive surge protection, reducinginventory and component cost relative to TVS surgeprotection. The major considerations are the surge toler-ance required, the resulting resistor value needed, resistorrobustness and frequency performance.

THE LTC1343 AND LTC1344 FORM A SOFTWARE-SELECTABLE MULTIPLE-PROTOCOL INTERFACE PORTUSING A DB-25 CONNECTORby Robert Reay

Introduction

With the explosive growth in data networking equipmenthas come the need to support many different serial proto-cols using only one connector. The problem facing inter-face designers is to make the circuitry for each serialprotocol share the same connector pins without introduc-ing conflicts. The main source of frustration is that eachserial protocol requires a different line termination that isnot easily or cheaply switched.

With the introduction of the LTC1343 and LTC1344, acomplete software-selectable serial interface port usingan inexpensive DB-25 connector becomes possible. Thechips form a serial interface port that supports the V.28(RS232), V.35, V.36, RS449, EIA-530, EIA-530A or X.21protocols in either DTE or DCE mode and is both NET1 andNET2 compliant. The port runs from a single 5V supply and

supports an echoed clock and loop-back configurationthat helps eliminate glue logic between the serial controllerand the line transceivers.

A typical application is shown in Figure 29. Two LTC1343sand one LTC1344 form the interface port using a DB-25connector, shown here in DTE mode.

Each LTC1343 contains four drivers and four receiversand the LTC1344 contains six switchable resistive termi-nators. The first LTC1343 is connected to the clock anddata signal lines along with the diagnostic LL (local loop-back) and TM (test mode) signals. The second LTC1343 isconnected to the control-signal lines along with the diag-nostic RL (remote loop-back) signal. The single-endeddriver and receiver could be separated to support the RI(ring-indicate) signal. The switchable line terminators inthe LTC1344 are connected only to the high speed clockand data signals. When the interface protocol is changedvia the digital mode selection pins (not shown), the driversand receivers are automatically reconfigured and theappropriate line terminators are connected.

Application Note 87

AN87-23

Review of Interface Standards

The serial interface standards RS232, EIA-530, EIA-530A,RS449, V.35, V.36 and X.21 specify the function of eachsignal line, the electrical characteristics of each signal, theconnector type, the transmission rate and the data ex-change protocols. The RS422 (V.11) and RS423 (V.10)standards merely define electrical characteristics. TheRS232 (V.28) and V.35 standards also specify their ownelectrical characteristics. In general, the US standardsstart with RS or EIA, and the equivalent European stan-dards start with V or X. The characteristics of eachinterface are summarized in Table 2.

Table 2 shows only the most commonly used signal lines.Note that each signal line must conform to only one of fourelectrical standards, V.10, V.11, V.28 or V.35.

V.10 (RS423) Interface

A typical V.10 unbalanced interface is shown in Figure 30.A V.10 single-ended generator (output A with ground C)

D2

LTC1343

RTSDTRDSR DCDCTS RL

D1D3D4R1R3R4 R2

D2

LTC1343

LLTXDSCTETXCRXCRXDTM

LL A (141)

TXD A (103)

TXD B

SCTE A (113)

SCTE B

RXC A (115)

RXC B

RXD A (104)

RXD B

RTS A (105)

RTS B

DTR A (108)

DTR B

CTS A (106)

CTS B

TM A (142)

SGND (102)

SHIELD (101)

1821424111512179314192023622 810513 21 7 1625

DB-25 CONNECTOR

LTC1344

D1D3D4R1R3R4 R2

TXC A (114)

TXC B

RL A (140)

DCD A (109)

DCD B

DSR A (107)

DSR B

A A'

C B'

C'

GENERATOR

BALANCEDINTERCONNECTING

CABLE LOAD

CABLETERMINATION RECEIVER

R3124Ω

R520k

LTC1344

LTC1343

RECEIVER

A

B

A'

B'

C'

R151.5Ω

R86k

S1S2

S3

S4

R251.5Ω

R610k

R710k

GND

R420k

Figure 29. LTC1343/LTC1344 Typical Application

Figure 30. Typical V.10 Interface

Figure 31. V.10 Receiver Configuration

Application Note 87

AN87-24

is connected to a differential receiver with input A' con-nected to A and input B' connected to the signal-returnground C. The receiver’s ground C' is separate from thesignal return. Usually, no cable termination between A'and B' is required for V.10 interfaces. The V.10 receiverconfiguration for the LTC1343 and LTC1344 is shown inFigure 31.

In V.10 mode, switches S1 and S2 inside the LTC1344 andS3 inside the LTC1343 are turned off. Switch S4 inside theLTC1343 shorts the noninverting receiver input to groundso the B input at the connector can be left floating. Thecable termination is then the 30k input impedance to theground of the LTC1343 V.10 receiver.


A typical V.11 balanced interface is shown in Figure 32. AV.11 differential generator with outputs A and B andground C is connected to a differential receiver withground C', input A' connected to A and input B' connectedto B. The V.11 interface has a differential termination at the

receiver end with a minimum value of 100Ω. The termina-tion resistor is optional in the V.11 specification, but forthe high speed clock and data lines, the termination isrequired to prevent reflections from corrupting the data. InV.11 mode, all switches are off except S1 inside theLTC1344, which connects a 103Ω differential terminationimpedance to the cable, as shown in Figure 33.


A typical V.28 unbalanced interface is shown in Figure 34.A V.28 single-ended generator (output A with ground C) isconnected to a single-ended receiver with input A' con-nected to A and ground C' connected via the signal returnground to C. In V.28 mode, all switches are off except S3inside the LTC1343, which connects a 6k impedance (R8)to ground in parallel with 20k (R5) plus 10k (R6), for ancombined impedance of 5k, as shown in Figure 35. Thenoninverting input is disconnected inside the LTC1343receiver and connected to a TTL level reference voltage fora 1.4V receiver trip point.

slangiSataDdnakcolC slangiSlortnoC slangiStseT

DXT ETCS CXT CXR DXR STR RTD RSD DCD STC IR LL LR MT

#TTICC )301( )311( )411( )511( )401( )501( )801( )701( )901( )601( )521( )141( )041( )241(

232SR 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V

035-AIE 11.V 11.V 11.V 11.V 11.V 11.V 11.V 11.V 11.V 11.V ——— 01.V 01.V 01.V

A035-AIE 11.V 11.V 11.V 11.V 11.V 11.V 01.V 01.V 11.V 11.V 01.V 01.V 01.V 01.V

944SR 11.V 11.V 11.V 11.V 11.V 11.V 11.V 11.V 11.V 11.V 01.V 01.V 01.V 01.V

53.V 53.V 53.V 53.V 53.V 53.V 82.V ——— 82.V 82.V 82.V ——— ——— ——— ———

63.V 11.V 11.V 11.V 11.V 11.V 11.V ——— 11.V 11.V 11.V ——— 01.V 01.V 01.V

12.X 11.V 11.V 11.V 11.V 11.V 11.V ——— ——— 11.V ——— ——— ——— ——— ———

A A'

B

C

B'

C'

GENERATOR


CABLE LOAD


100ΩMIN

R3124Ω

R520k

LTC1344

LTC1343

RECEIVER

A

B

A'

B'

C'

R151.5Ω

R86k

S2S3

S4

R251.5Ω

R610k

R710k

GND

R420k

S1

Figure 32. Typical V.11 Interface Figure 33. V.11 Receiver Configuration

Table 2. Interface Summary

Application Note 87

AN87-25

V.35 Interface

A typical V.35 balanced interface is shown in Figure 36. AV.35 differential generator with outputs A and B andground C is connected to a differential receiver withground C', input A' connected to A and input B' connectedto B. The V.35 interface requires T or delta networktermination at the receiver end and the generator end. Thereceiver differential impedance measured at the connectormust be 100 ±10Ω, and the impedance between shortedterminals (A' and B') and ground (C') is 150 ±15Ω.

In V.35 mode, both switches S1 and S2 inside the LTC1344are on, connecting the T-network impedance, as shown inFigure 37. Both switches in the LTC1343 are off. The 30kinput impedance of the receiver is placed in parallel withthe T-network termination, but does not affect the overallinput impedance significantly.

The generator differential impedance must be 50Ω to150Ω, and the impedance between shorted terminals (Aand B) and ground (C) is 150Ω ±15Ω. For the generatortermination, switches S1 and S2 are both on and the top

side of the center resistor is brought out to a pin so it canbe bypassed with an external capacitor to reduce commonmode noise, as shown in Figure 38.

Any mismatch in the driver rise and fall times or skew indriver propagation delays will force current through thecenter termination resistor to ground, causing a highfrequency common mode spike on the A and B terminals.This spike can cause EMI problems that are reduced bycapacitor C1, which shunts much of the common modeenergy to ground rather than down the cable.

A A'

C C'

GENERATOR


CABLE LOAD


R3124Ω

R520k

LTC1344

LTC1343

RECEIVER

A

B

A'

B'

C'

R151.5Ω

R86k

S2

S3

S4

R251.5Ω

R610k

R710k

GND

R420k

S1

A A'

B

C

B'

C'

GENERATOR BALANCEDINTERCONNECTING

CABLE

LOAD


50Ω125Ω

50Ω

50Ω125Ω

50Ω

R3124Ω

R520k

LTC1344

LTC1343

RECEIVER

A

B

A'

B'

C'

R151.5Ω

R86k

S2S3

S4

R251.5Ω

R610k

R710k

GND

R420k

S1





V.35 DRIVER

A

B

C

51.5Ω

S2ON

S1ON

51.5Ω

LTC1344

124Ω

C1100pF

Figure 38. V.35 Driver Using the LTC1344

Application Note 87

AN87-26

emaNedoM3431CTL 2M 1M 0M/LRTC

KLC 1D 2D 3D 4D 1R 2R 3R 4R

324SR/01.V 0 0 0 X 01.V 01.V 01.V 01.V 01.V 01.V 01.V 01.V

atad&kcolcA035SR 0 0 1 0 01.V 11.V 11.V 11.V 11.V 11.V 11.V 01.V

lortnocA035SR 0 0 1 1 01.V 11.V 01.V 11.V 11.V 01.V 11.V 01.V

devreseR 0 1 0 X 01.V 11.V 11.V 11.V 11.V 11.V 11.V 01.V

12.X 0 1 1 X 01.V 11.V 11.V 11.V 11.V 11.V 11.V 01.V

atad&kcolc53.V 1 0 0 0 82.V 53.V 53.V 53.V 53.V 53.V 53.V 82.V

lortnoc53.V 1 0 0 1 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V

63.V/944SR/035SR 1 0 1 X 01.V 11.V 11.V 11.V 11.V 11.V 11.V 01.V

232SR/82.V 1 1 0 X 82.V 82.V 82.V 82.V 82.V 82.V 82.V 82.V

elbaCoN 1 1 1 X Z Z Z Z Z Z Z Z

NC

NC

CABLE

17

18

19

21

LTC1343

LTC1343

CONNECTOR

20

21

19

18

17

22

21

M2 M1

LTC1344LATCH

M0 (DATA)23 24 1

CTRL/CLK

22

(DATA)

M0

M1

M2

DCE/DTE

LATCH

20CTRL/CLK

22

DCE/DTE

M2

M1

M0

(DATA)

LATCH

VCC

DCE/DTE

R1, 10kVCC

R2, 10kVCC

R3, 10kVCC

R4, 10kVCC

Figure 39. Mode Selection by Cable

Table 3. LTC1343/LTC1344 Mode Selection

Application Note 87

AN87-27

LTC1343/LTC1344 Mode Selection

The interface protocol is selected using the mode selectpins M0, M1, M2 and CTRL/CLK, as summarized in Table3. The CTRL/CLK pin should be pulled high if the LTC1343is being used to generate control signals and pulled low ifused to generate clock and data signals.

For example, if the port is configured as a V.35 interface,the mode selection pins should be M2 = 1, M1 = 0, M0 =0. For the control signals, CTRL/CLK = 1 and the driversand receivers will operate in RS232 (V.28) electrical mode.For the clock and data signals, CTRL/CLK = 0 and thedrivers and receivers will operate in V.35 electrical mode,except for the single-ended driver and receiver, which willoperate in the RS232 (V.28) electrical mode. The DCE/DTEpin will configure the port for DCE mode when high, andDTE when low.

The interface protocol may be selected by simply pluggingthe appropriate interface cable into the connector. Themode pins are routed to the connector and are left uncon-nected (1) or wired to ground (0) in the cable, as shown inFigure 39.

The pull-up resistors R1–R4 ensure a binary 1 when a pinis left unconnected and also ensure that the two LTC1343sand the LTC1344 enter the no-cable mode when the cableis removed. In the no-cable mode, the LTC1343 powersupply current drops to less than 200µA and all LTC1343driver outputs and LTC1344 resistive terminators areforced into a high impedance state. Note that the data latchpin, LATCH, is shorted to ground for all chips.

The interface protocol may also be selected by the serialcontroller or host microprocessor, as shown in Figure 40.

The mode selection pins M0, M1, M2 and DCE/DTE can beshared among multiple interface ports, while each porthas a unique data-latch signal that acts as a write enable.When the LATCH pin is low, the buffers on the MO, M1,M2, CTRL/CLK, DCE/DTE, LB and EC pins are transparent.When the LATCH pin is pulled high, the buffers latch thedata, and changes on the input pins will no longer affectthe chip.

The mode selection may also be accomplished by usingjumpers to connect the mode pins to ground or VCC.

Loop-Back

The LTC1343 contains logic for placing the interface intoa loop-back configuration for testing. Both DTE and DCEloop-back configurations are supported. Figure 41 showsa complete DTE interface in the loop-back configurationand Figure 42 the DCE loop-back configuration. The loop-back configuration is selected by pulling the LB pin low.

Enabling the Single-Ended Driver and Receiver

When the LTC1343 is being used to generate the controlsignals (CTRL/CLK = high) and the EC pin is pulled low, theDCE/DTE pin becomes an enable for driver 1 and receiver4 so their inputs and outputs can be tied together, asshown in Figure 43.

CONTROLLER

PORT #3

M0

M1

M2

DCE/DTE

LATCH 1

LATCH 2

LATCH 3

M0

M1

M2

DCE/DTE

LATCH

PORT #2

M0

M1

M2

DCE/DTE

LATCH

PORT #1

M0

M1

M2

DCE/DTE

LATCH

CONN

ECTO

R #1

CONN

ECTO

R #2

CONN

ECTO

R #3

Figure 40. Mode Selection by Controller

Application Note 87

AN87-28

LTC1343 LTC1344

D1

D4

D3

D2

R1

R4

103Ω

103Ω

103ΩR3

LL

TXD

SCTE

TXC

RXC

RXD

TM

SERIALCONTROLLER

R2

M0

M1

M2

CTRL

/CLK

DCE/

DTE

LB EC LATC

H

M0

M1

M2

DCE/

DTE

LATC

H

1 0 1 0 0 0 1 0 1 0 1 0 0

LL

TXD

SCTE

RXD

LTC1343

D1

D4

D3

D2

R1

R4

R3

RL

RTS

DTR

DCD

DSR

CTS

RI

R2

M0

M1

M2

CTRL

/CLK

DCE/

DTE

LB EC LATC

H

1 0 1 1 0 0 1 0

DCD

DSR

CTS

TXC

RXC

TM

RL

RTS

DTR

RI

LTC1343

R4

D4

D3

D2

R1

D1

R3

R2

M0

M1

M2

CTRL

/CLK

DCE/

DTE

LB EC LATC

H

LTC1343LTC1344

R4

D4

D3

D2

R1

D1

103Ω

103Ω R3

LL

TXD

SCTE

TXC

RXC

RXD

TM

SERIALCONTROLLER

R2

M0

M1

M2

DCE/

DTE

LATC

H

M0

M1

M2

CTRL

/CLK

DCE/

DTE

LB EC LATC

H

1 0 1 0 1 0 1 0

1 0 1 1 1 0 1 0

1 0 1 1 0

LL

TXD

SCTE

TXC

RXC

RXD

TM

RL

RTS

DTR

DCD

DSR

CTS

RI

RL

RTS

DTR

DCD

DSR

CTS

RI

Figure 41. Normal DTE Loop-Back Figure 42. Normal DCE Loop-Back

Application Note 87

AN87-29

39

26

LTC1343

5

21

16

20

24EC

D1

CTRL/CLK

DCE/DTE

R4

VCC

The EC pin has no affect on the configuration when CTRL/CLK is high except to allow the DCE/DTE pin to become anenable. When DCE/DTE is low, the driver 1 output isenabled. The receiver 4 output goes into three-state, andthe input presents a 30k load to ground.

When DCE/DTE is high, the driver 1 output goes into three-state, and the receiver 4 output is enabled. The receiver 4input presents a 30k load to ground in all modes exceptwhen configured for RS232 operation, when the inputimpedance is 5k to ground.

Multiprotocol Interface with DB-25or µDB-26 Connectors

A multiprotocol serial interface with a standard DB-25connector EIA-530 pin configuration is shown in Figure44. (Figures 44–47 follow on pp. 30–33). The signal linesmust be reversed in the cable when switching betweenDTE and DCE using the same connector. For example, inDTE mode, the RXD signal is routed to receiver 3, but inDCE mode, the TXD signal is routed to receiver 3. Theinterface mode is selected by logic outputs from thecontroller or from jumpers to either VCC or GND on themode-select pins. The single-ended driver 1 and receiver

4 of the control chip share the RL signal on connector pin21. With EC low and CTRL/CLK high, the DCE/DTE pinbecomes an enable signal.

Single-ended receiver 4 can be connected to pin 22 toimplement the RI (ring indicate) signal in RS232 mode(see Figure 45). In all other modes, pin 22 carries theDSR(B) signal.

A cable selectable multiprotocol interface is shown inFigure 46. Control signals LL, RL and TM are not imple-mented. The VCC supply and select lines M0 and M1 arebrought out to the connector. The mode is selected in thecable by wiring M0 (connector pin 18) and M1 (connectorpin 21) and DCE/DTE (connector pin 25) to ground (con-nector pin 7) or letting them float. If M0, M1 or DCE/DTEare floating, pull-up resistors R3, R4 and R5 will pull thesignals to VCC. The select bit M1 is hard wired to VCC. Whenthe cable is pulled out, the interface goes into the no-cablemode.

A cable-selectable multiprotocol interface found in manypopular data routers is shown in Figure 47. The entireinterface, including the LL signal, can be implementedusing the tiny µDB-26 connector.

Conclusion

The LTC1343 and LTC1344 allow the designer of a multi-protocol serial interface to spend all of his time on thesoftware rather than the hardware. Simply drop the chipsdown on the board, hook them up to the connector and aserial controller, apply the 5V supply voltage and you’re offand running. In addition, the chip set’s small size andunique termination topology allow many ports to beplaced on a board using inexpensive connectors andcables.

Figure 43. Single-Ended Driver and Receiver Enable

Application Note 87

AN87-30

LTC1343

1

2

43

8

5

6

7

9

10

39

383736353433

323130292827

2621191817

1213

14

15

16

4023

20221125

CTRLLATCHINVERT423 SET

DCEM2M1M0

R2

R3

R4

R1100k

LL A

TXD ATXD BSCTE ASCTE B

TM A

RXD ARXD BRXC ARXC B

RXC ARXC BRXD ARXD B

TM A

RTS ARTS BDTR A DTR B

DCD ADCD BDSR ADSR B

CTS A CTS B

DCD ADCD BDTR ADTR B

RTS A RTS B

18DTE DCE20 22 23 24 1

M0M1M2DCE/DTE

1312113 8

C6100pF

C7100pF

19171815161097645

2

44C21µF

C43.3µF

C101µF

C13 3.3µF

C51µF

C11µF

4342

41

14

VEE

VCC

VCC5V

2142411

151217

93

16

25

7

1

4192023

8106

22

513

21

DB-25 CONNECTOR

LTC1344

C8100pF

R1

C31µF

GNDLB VCC

VCC

VCC

EC24

LTC1343

1

2

43

8

5

6

7

9

10

39

383736353433

32313029

2827

2621191817

1213

14

15

16

4023

20221125


DCEM2M1M0

R2

R3

R4

R2100k

44

C121µF

C91µF

4342

41

C111µF

GNDLB EC

R1

DTE_LL/DCE_TM

DTE_TXD/DCE_RXD

DTE_SCTE/DEC_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_TM/DCE_LL

DTE_RL/DCE_RL

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

LB

LATCH

DCE/DTEM2M1M0

SGND

SHIELD

RL A

CTS ACTS BDSR A DSR B

RL A

CHARGEPUMP

CHARGEPUMP

D1

D2

D3

D4

D1

D2

D3

D4

TXC ATXC B

SCTE ASCTE BTXD ATXD B

LL A

TXC ATXC B

24

+

+

Figure 44. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector

Application Note 87

AN87-31

LTC1343

1

2

43

8

5

6

7

9

10

39

383736353433

323130292827

2621191817

1213

14

15

16

4023

20221125


DCEM2M1M0

R2

R3

R4

R1100k

TM A (142)

RXD A (104)RXD BRXC A (115)RXC BTXC A (114)TXC B

SCTE A (113)SCTE BTXD A (103)TXD B

LL A (141)

CTS A (106)CTS BDSR A (107)DSR B/RI A (125)DCD A (109)DCD B

DTR A (108)DTR B

RTS A (105)RTS B

RL A (140)

2520 22 23 24 1

M0M1M2

VCC

DCE/DTE

1312113 8

C6100pF

C7100pF

19171815161097645

2

44C21µF

C43.3µF

C101µF

C13 3.3µF

C51µF

C11µF

4342

41

14

VEE

VCC

VCC5V

31617

91512

2411

214

18

7

1

513

810

622

2023

419

21

DB-25 FEMALECONNECTOR

LTC1344

C8100pF

R1

C31µF

GNDLB VCC

VCC

VCC

VCC

VCC

VCC

EC24

LTC1343

1

2

43

8

5

6

7

9

10

39

383736353433

32313029

2827

2621191817

1213

14

15

16

4023

20221125

DCEM2M1M0

R2

R3

R4

R2100k

44

C121µF

C91µF

4342

41

C111µF

GNDLB EC


R1

TM

RXD

RXC

TXC

SCTE

TXD

LL

RI

CTS

DSR

DCD

DTR

CTX

RL

LB

M2M1M0

LATCH

SGND (102)

SHIELD (101)

CHARGEPUMP

CHARGEPUMP

D1

D2

D3

D4

D1

D2

D3

D4

RIEN = RS232

24

+

+

Figure 45. Controller-Selectable Multiprotocol DCE Port with Ring-Indicate and DB-25 Connector

Application Note 87

AN87-32

LTC1343

1

2

43

8

5

6

7

9

10

39

383736353433

323130292827

2621191817

1213

14

15

16

4023

20221125


DCEM2M1M0

R2

R3

R4

R1100k






CTS A CTS B


RTS A RTS B

DTE DCE

20 22 23 24 1

M0M1M2DCE/DTE

1312113 8

C6100pF

C7100pF

19171815161097645

2

44C21µF

C43.3µF

C101µF

C13 3.3µF

C51µF

C11µF

4342

41

14

VEE

VCC

VCC5V

2142411

151217

93

16

7

1

4192023

8106

22

513

25

2118

DB-25 CONNECTOR

LTC1344

C8100pF

R1

C31µF

GNDLB VCC

VCC

VCC

VCC

VCC

VCC

EC24

LTC1343

1

2

43

8

5

6

7

9

10

39

383736353433

32313029

2827

2621191817

1213

14

15

16

4023

20221125


DCEM2M1M0

R2

R3

R4

R2100k

44

C121µF

C91µF

4342

41

C111µF

GNDLB EC

R1

DTE_TXD/DCE_RXD

DTE_SCTE/DEC_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/ DCE_RTS

LB

SGND

SHIELD


CHARGEPUMP

CHARGEPUMP

D1

D2

D3

D4

TXC ATXC B


TXC ATXC B

R510k

R410k

DCE/DTE

M1

M0

VCCVCC

D1

D2

D3

D4

24

R310k

VCC

CABLE WIRING FOR MODE SELECTIONMODE PIN 18 PIN 21V.35 PIN 7 PIN 7

EIA-530, RS449, NC PIN 7 V.36, X.21

RS232 PIN 7 NC

CABLE WIRING FOR DTE/DCESELECTION

MODE PIN 25DTE PIN 7DCE NC

+

+

Figure 46. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector

Application Note 87

AN87-33

LTC1343

1

2

43

8

5

6

7

9

10

39

383736353433

323130292827

2621191817

1213

14

15

16

4023

20221125


DCEM2M1M0

R2

R3

R4

R1100k






CTS A CTS B

LL B


RTS A RTS B

LL B

DTE DCE

20 22 23 24 1

M0M1M2DCE/DTE

1312113 8

C6100pF

C7100pF

19171815161097645

2

44C21µF

C43.3µF

C101µF

C13 3.3µF

C51µF

C11µF

4342

41

14

VEE

VCC

VCC5V

2142411

151217

93

16

7

1

4192023

8106

22

513

26

25

2118

µDB-26 CONNECTOR

LTC1344

C8100pF

R1

C31µF

GNDLB VCC

VCC

VCC

VCC

VCC

VCC

EC24

LTC1343

1

2

43

8

5

6

7

9

10

39

383736353433

32313029

2827

2621191817

1213

14

15

16

4023

20221125


DCEM2M1M0

R2

R3

R4

R2100k

44

C121µF

C91µF

4342

41

C111µF

GNDLB EC

R1

DTE_TXD/DCE_RXD

DTE_SCTE/DEC_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_LL/DCE_LL

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

LB

SGND

SHIELD


CHARGEPUMP

CHARGEPUMP

D1

D2

D3

D4

TXC ATXC B


TXC ATXC B

R510k

R410k

DCE/DTE

M1

M0

VCCVCC

D1

D2

D3

D4

24

R310k

VCC

CABLE WIRING FOR MODE SELECTIONMODE PIN 18 PIN 21V.35 PIN 7 PIN 7

EIA-530, RS449, NC PIN 7 V.36, X.21

RS232 PIN 7 NC

CABLE WIRING FOR DTE/DCESELECTION


+

+

Figure 47. Cable-Selectable Multiprotocol DTE/DCE Port with µDB-26 Connector

Application Note 87

AN87-34

THE LT1328: A LOW COST IRDA RECEIVER SOLUTIONFOR DATA RATES UP TO 4MBPSby Alexander Strong

IrDA SIR

The LT1328 circuit in Figure 48 operates over the full 1cmto 1 meter range of the IrDA standard at the stipulated lightlevels. For IrDA data rates of 115kbps and below, a 1.6µspulse width is used for a zero and no pulse for a one. Lightlevels are 40mW/sr (milliwatts per steradian) to 500mW/sr. Figure 49 shows a scope photo for a transmitter input(top trace) and the LT1328 output (bottom trace). Notethat the input to the transmitter is inverted; that is, trans-mitted light produces a high at the input, which results ina zero at the output of the transmitter. The Mode pin (pin7) should be high for these data rates.

An IrDA- compatible transmitter can also be implementedwith only six components, as shown in Figure 50. Powerrequirements for the LT1328 are minimal: a single 5Vsupply and 2mA of quiescent current.

VCC (5V)

C40.1µF

C510µF

HIGH – SIRLOW – FIR AND 4PPM

IN

FILT

FILT LO

GND

LT1328

MODE

C31000pF

VCC

DATA

VBIAS8

7

6

TTL DATA OUT

C1330pF

LIGHT IN

D1BPU22NF

TEMIC

C210nF

+

IrDA FIR

The second fastest tier of the IrDA standard addresses576kbps and 1.152Mbps data rates, with pulse widths of1/4 of the bit interval for zero and no pulse for one. The1.152Mbps rate, for example, uses a pulse width of 217ns;the total bit time is 870ns. Light levels are 100mW/sr to500mW/sr over the 1cm to 1 meter range. A photo of atransmitted input and LT1328 output is shown in Figure51. The LT1328 output pulse width will be less than 800nswide over all of the above conditions at 1.152Mbps. Pin 7should be held low for these data rates and above.

4ppm

The last IrDA encoding method is for 4Mbps and usespulse position modulation, thus its name: 4ppm. Two bitsare encoded by the location of a 125ns wide pulse at oneof the four positions within a 500ns interval (2 bits •1/500ns = 4Mbps). Range and input levels are the same asfor 1.152Mbps. Figure 52 shows the LT1328 reproductionof this modulation.

1328_02.eps

RD310k

RD1100Ω

DRIVER

Q32N7002

TRANSMITINPUT

RD26.8Ω1/2W

Q42N7002

D2HSDL-4220

VCC

Figure 48. LT1328 IrDA Receiver—Typical Application

Figure 50. IrDA Transmitter

TRANSMITTERINPUT

LT1328 OUTPUT

2µs/DIV

Figure 49. IrDA 115kbps Modulation Figure 51. IrDA 1.152Mbps Modulation

TRANSMITTERINPUT

LT1328 OUTPUT

200ns/DIV

Application Note 87

AN87-35

LT1328 Functional Description

Figure 53 is a block diagram of the LT1328. Photodiodecurrent from D1 is transformed into a voltage by feedbackresistor RFB. The DC level of the preamp is held at VBIAS bythe servo action of the transconductance amplifier’s gm.The servo action only suppresses frequencies below theRgm/CFILT pole. This highpass filtering attenuates interfer-ing signals, such as sunlight or incandescent or fluorescentlamps, and is selectable at pin 7 for low or high data rates.For high data rates, pin 7 should be held low. The highpassfilter breakpoint is set by the capacitor C1 at f = 25/(2π •Rgm • C), where Rgm = 60k. The 330pF capacitor (C1) setsa 200kHz corner frequency and is used for data ratesabove 115kbps. For low data rates (115kbps and below),the capacitance at pin 2 is increased by taking pin 7 to aTTL high. This switches C2 in parallel with C1, lowering thehighpass filter breakpoint. A 10nF cap (C2) produces a6.6kHz corner. Signals processed by the preamp/gmamplifier combination cause the comparator output toswing low.

TRANSMITTERINPUT

LT1328 OUTPUT

200ns/DIV

Figure 52. IrDA 4ppm Modulation

Conclusion

In summary, the LT1328 can be used to build a low costreceiver compatible with IrDA standards. Its ease of useand flexibility also allow it to provide solutions to numer-ous other photodiode receiver applications. The tiny MSOPpackage saves on PC board area.

+

–

–

+

1

COMPARATOR

gm CELL

BIAS

VBIAS

FILTER

PHOTO-DIODE

IN

FILTER LO

DATA OUT

VCC

MODE

GND

RGM

RFB

RIN

PREAMP

2

3

4

C1330pF C2

10nF

8

C3

7

6

5

D1

Figure 53. LT1328 Block Diagram

Application Note 87

AN87-36

LTC1387 SINGLE 5V RS232/RS485 MULTIPROTOCOLTRANSCEIVERby Y.K. Sim

Introduction

The LTC1387 is a single 5V supply, logic-configurable,single-port RS232 or RS485 transceiver. The LTC1387offers a flexible combination of two RS232 drivers, twoRS232 receivers, an RS485 driver, an RS485 receiver andan onboard charge pump to generate boosted voltages fortrue RS232 levels from a single 5V supply. The RS232transceivers and RS485 transceiver are designed to sharethe same port I/O pins for both single-ended and differen-tial signal communication modes. The RS232 transceiversupports both RS232 and EIA562 standards, whereas theRS485 transceiver supports both RS485 and RS422standards. Both half-duplex and full-duplex communica-tion are supported.

1387_01.eps

LTC1387 CONTROLLER

DX1

VCC

120Ω

ARA

RB

DY

DZ

B

Y

Z

A

B

RS485

RS485

RS232

INTERFACE

RXEN

DXEN

MODE

RA

RB

DY

DZ/SLEW

ON

RXEN

DXEN

485/232

RS232RECEIVE MODE

100

RXEN =DXEN =MODE =

RS485RECEIVE MODE

101

RXEN =DXEN =MODE =

SHUTDOWN MODE

00X

RXEN =DXEN =MODE =

RS232TRANSMIT MODE

010

RXEN =DXEN =MODE =

RS485TRANSMIT MODE

011

RXEN =DXEN =MODE =

RS485RECEIVE MODE

101

RXEN =DXEN =MODE =

SHUTDOWN MODE

00X

RXEN =DXEN =MODE =

RS232 MODE

100

RXEN =DXEN =MODE =

RS485TRANSMIT MODE

011

RXEN =DXEN =MODE =

1387_02.eps

LTC1387 CONTROLLER

DX1

RX

VCC

120Ω

ARA

RB

DY

DZ

B

Y

Z

A

B

RS485

RS485

RS232

RS232

INTERFACE

RXEN

DXEN

MODE

RA

RB

DY

DZ/SLEW

ON

RXEN

DXEN

485/232

7.5k=

5V

*FMMT-619

**TX2A-5V(DPST)

***

ZETEX (516) 543-7100AROMAT (908) 464-3550

1387_03.eps

RX1

LTC1387 CONTROLLER

DX1

VCC

120Ω

120Ω

ARA

RB

DY

DZ

B

Y

Z

A

B

Y

Z

RS485

RS485

RS485

RS485

INTERFACERS232

RXD

RS232

RXEN

DXEN

MODE

RA

RB

DY

DZ/SLEW

ON

RXEN

DXEN

485/232

SHUTDOWN MODE00X

RXEN =DXEN =MODE =

RS232 MODE110

RXEN =DXEN =MODE =

RS485 MODE111

RXEN =DXEN =MODE =

Figure 54. Half-Duplex RS232, Half-Duplex RS485

Figure 55. Full-Duplex RS232, Half-Duplex RS485

Figure 56. Full-Duplex RS232 (1-Channel), Full-Duplex RS422

Application Note 87

AN87-37

A logic input selects between RS485 and RS232 modes.Three additional control inputs allow the LTC1387 to bereconfigured easily via software to adapt to various com-munication needs, including a one-signal line RS232 I/Omode (see function tables in figures). Four examples ofinterface port connections are shown in Figures 54–57.

A SLEW input pin, active in RS485 mode, changes thedriver transition between normal and slow slew-rate modes.In normal RS485 slew mode, the twisted pair cable mustbe terminated at both ends to minimized signal reflection.In slow-slew mode, the maximum signal bandwidth isreduced, minimizing EMI and signal reflection problems.Slow-slew-rate systems can often use improperly termi-nated or even unterminated cables with acceptable results.If cable termination is required, external termination resis-tors can be connected through switches or relays.

The LTC1387 features micropower shutdown mode,loopback mode for self-test, high data rates (120kbaud forRS232 and 5Mbaud for RS485) and 7kV ESD protection atthe driver outputs and receiver inputs.

SHUTDOWN MODE000X

ON =RXEN =DXEN =MODE =

RS232 MODE1110

ON =RXEN =DXEN =MODE =

RS485 MODE1111

ON= RXEN =DXEN =MODE =

1387_04.eps

RX1

LTC1387 CONTROLLER

RX2

DX1120Ω

120Ω

ARA

RB

DY

DZ

B

Y

Z

A

B

Y

Z

RS485

RS485

RS485

RS485

INTERFACERS232

RXD

CTS

RS232

TXD

RS232

RTS

RS232

DX2/SLEW

ON

RXEN

DXEN

MODE

RA

RB

DY

DZ/SLEW

ON

RXEN

DXEN

485/232

TERMINATE

Figure 57. Full-Duplex RS232 (2-Channel), Full-Duplex RS485with Slew and Termination Control

A 10MB/s MULTIPLE-PROTOCOL CHIP SET SUPPORTSNET1 AND NET2 STANDARDS

by David Soo

Introduction

Typical Application

Like the LTC1343 software-selectable multiprotocol trans-ceiver, introduced in the August, 1996 issue of LinearTechnology , the LTC1543/LTC1544/LTC1344A chip setcreates a complete software-selectable serial interfaceusing an inexpensive DB-25 connector. The main differ-ence between these parts is the division of functions: theLTC1343 can be configured as a data/clock chip or as acontrol-signal chip using the CTRL/CLK pin, whereas the

LTC1543 is a dedicated data/clock chip and the LTC1544is a control-signal chip. The chip set supports the V.28(RS232), V.35, V.36, RS449, EIA-530, EIA-530A and X.21protocols in either DTE or DCE mode.

Figure 58 shows a typical application using the LTC1543,LTC1544 and LTC1344A. By just mapping the chip pins tothe connector, the design of the interface port is complete.The figure shows a DCE mode connection to a DB-25connector.

The LTC1543 contains three drivers and three receivers,whereas the LTC1544 contains four drivers and fourreceivers. The LTC1344A contains six switchable resis-tive terminators that are connected only to the high speedclock and data signals. When the interface protocol ischanged via the mode selection pins, M2, M1 and M0, the

Application Note 87

AN87-38

drivers, receivers and line terminators are placed in theirproper configuration. The mode pin functions are summa-rized in Table 4. There are internal 50µA pull-up currentsources on the mode select pins, DCE/DTE and the INVERTpins.

DTE vs DCE Operation

The LTC1543/LTC1544/LTC1344A chip set can beconfigured for either DTE or DCE operation in one of twoways. The first way is when the chip set is a dedicated DTEor DCE port with a connector of appropriate gender. Thesecond way is when the port has one connector that canbe configured for DTE or DCE operation by rerouting thesignals to the chip set using a dedicated DTE or DCE cable.

Figure 58 is an example of a dedicated DCE port using afemale DB-25 connector. The complement to this port isthe DTE-only port using a male DB-25 connector, asshown in Figure 59.

If the port must accommodate both DTE and DCE modes,the mapping of the drivers and receivers to connector pinsmust change accordingly. For example, in Figure 58,driver 1 in the LTC1543 is connected to pin 3 and pin 16of the DB-25 connector. In DTE mode, as shown in Figure59, driver 1 is mapped to pins 2 and 14 of the DB-25connector. A port that can be configured for either DTE orDCE operation is shown in Figure 60. This configurationrequires separate cables for proper signal routing.

Cable-Selectable Multiprotocol Interface

The interface protocol may be selected by simply pluggingthe appropriate interface cable into the connector. A cable-selectable multiprotocol DTE/DCE interface is shown inFigure 61. The mode pins are routed to the connector andare left unconnected (1) or wired to ground (0) in the cable.The internal pull-up current sources ensure a binary 1when a pin is left unconnected and also ensure that theLTC1543/LTC1544/LTC1344A enter the no-cable modewhen the cable is removed. In the no-cable mode, theLTC1543/LTC1544 power supply current drops to lessthan 200µA and all of the LTC1543/LTC1544 driver out-puts will be forced into the high impedance state.

Adding Optional Test Signal

In some cases, the optional test signals local loopback(LL), remote loopback (RL) and test mode (TM) arerequired but there are not enough drivers and receiversavailable in the LTC1543/LTC1544 to handle these extrasignals. The solution is to combine the LTC1544 with theLTC1343. By using the LTC1343 to handle the clock anddata signals, the chip set gains one extra single-endeddriver/receiver pair. This configuration is shown in Figure62.

Compliance Testing

A European standard EN 45001 test report is available forthe LTC1543/LTC1544/LTC1344A chip set. The reportprovides documentation on the compliance of the chip setto Layer 1 of the NET1 and NET2 standard. A copy of thistest report is available from LTC or from Detecon, Inc. at1175 Old Highway 8, St. Paul, MN 55112.

Conclusion

In the world of network equipment, the product differen-tiation is mostly in the software and not in the serialinterface. The LTC1543, LTC1544 and LTC1344A providea simple yet comprehensive solution to standards compli-ance for multiple-protocol serial interface.

4451CTL/3451CTLemaNedoM 2M 1M 0M

desUtoN 0 0 0

A035-AIE 0 0 1

035-AIE 0 1 0

12.X 0 1 1

53.V 1 0 0

63.V/944SR 1 0 1

82.V/232SR 1 1 0

elbaCoN 1 1 1

Table 4. Mode-Pin Functions

Application Note 87

AN87-39

D2

D1

LTC1544

CTS

DSR

DTR

DCD

RTS

D3

R2

R1

R4

R3

D2

LTC1543

LL

RXD

RXC

TXC

SCTE

TXD

M0

M1

M2

DCE/DTE

VCC

VDD

VCC

VEE

GND

3

16

17

9

15

12

24

11

2

1

5

13

6

8

22

10

20

23

4

19

18

7

14

D3

R2

R1

R3

D1

C21µF

C11µF

C51µF

C31µF

C43.3µF

RXD A (104)

RXD B

RXC A (115)

RXC B

SCTE A (113)

SCTE B

TXD A (103)

TXD B

CTS A (106)

CTS B

DSR A (107)

DSR B

RTS A (105)

RTS B

LL A (141)

SGND (102)

SHIELD (101)


TXC A (114)

TXC B

DCD A (109)

DCD B

DTR A (108)

DTR B

D4

16109764

3 8 11 12 13

5

2

15 18 17 19 20 22

LTC1344A

C6100pF

C7100pF

C8100pF

VCC

VCC

VCC5V

23 24

14

1

DCE/

DTE

M2

M1

M0

CHARGEPUMP

+

283

1

2

4

5

6

7

8

9

10

NC

11

1213

14

12

3

4

5

6

7

8

10

9

INVERT15

16

17

18

19

20

21

22

23

24

25

NC

NC

2726

25

24

23

22

21

20

19

18

17

16

15

26

27

28

VEE

M0

M1

M2

DCE/DTE

M2M1M0

11

12

13

14

LATCH21

C121µF

C131µF

C111µF

C101µF

C91µF

Figure 58. Controller-Selectable DCE Port with DB-25 Connector

Application Note 87

AN87-40

D2

D1

LTC1544

RTS

DTR

DSR

DCD

CTS

D3

R2

R1

R4

R3

D2

LTC1543

LL

TXD

SCTE

TXC

RXC

RXD

M0

M1

M2

DCE/DTE

VCC

VDD

VCC

VEE

GND

2

14

24

11

15

12

17

9

3

1

4

19

20

8

23

10

6

22

5

13

18

7

16

D3

R2

R1

R3

D1

C21µF

C11µF

C51µF

C31µF

C43.3µF

TXD A (103)

TXD B

SCTE A (113)

SCTE B

RXC A (115)

RXC B

RXD A (104)

RXD B

RTS A (105)

RTS B

DTR A (108)

DTR B

CTS A (106)

CTS B

LL A (141)

SG

SHIELD

DB-25 MALECONNECTOR

TXC A (114)

TXC B

DCD A (109)

DCD B

DSR A (107)

DSR B

D4

16109764

3 8 11 12 13

5

2

15 18 17 19 20 22

LTC1344A

C6100pF

C7100pF

C8100pF

VCC

VCC5V

23 24

14

1

DCE/

DTE

M2

M1

M0

CHARGEPUMP

+

283

1

2

4

5

6

7

8

9

10

11

1213

14

12

3

4

5

6

7

8

10

9

INVERT15

16

17

18

19

20

21

22

23

24

25

NC

2726

25

24

23

22

21

20

19

18

17

16

15

26

27

28

VEEC121µF

C131µF

C111µF

C101µF

C91µF

M0

M1

M2

DCE/DTE

M2M1M0

11

12

13

14

21LATCH

Figure 59. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector

Application Note 87

AN87-41

D2

D1

LTC1544

D3

R2

R1

R4

R3

D2

LTC1543

DTE_TXD/DCE_RXD

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_LL/DCE_LL

DTE_SCTE/DCE_RXC

M0

M1

M2

DCE/DTE

VCC

VDD

VCC

VEE

GND

S

S

2

14

24

11

15

12

17

9

3

1

4

19

20

8

23

10

6

22

5

13

18

7

16

D3

R2

R1

R3

D1

C21µF

C11µF

C51µF

C31µF

C43.3µF

TXD A

TXD B

SCTE A

SCTE B

RXD A

RXD B

RXC A

RXC B

RXC A

RXC B

RXD A

RXD B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

LL A

SG

SHIELD

DB-25 CONNECTOR

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

TXC A

TXC B

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

LL A

DCD A

DCD B

DTR A

DTR B

D4

16109764

3 8 11 12 13

5

2

15 18 17 19 20 22

LTC1344A

C6100pF

C7100pF

C8100pF

VCC

VCC5V

23 24

14

1

DCE/

DTE

M2

M1

M0

CHARGEPUMP

+

283

1

2

4

5

6

7

8

9

1011

121314

12

3

4

5

6

7

8

10

9

INVERT15

16

17

18

19

20

21

22

23

24

25

NC

2726

25

24

23

22

21

20

19

18

17

16

15

26

27

28

VEE

M0

M1

M2

DCE/DTE

DCE/DTEM2M1M0

11

12

13

14

DTE DCE

LATCH21

C121µF

C131µF

C111µF

C101µF

C91µF

Figure 60. Controller-Selectable DTE/DCE Port with DB-25 Connector

Application Note 87

AN87-42

D2

D1

LTC1544

D3

R2

R1

R4

R3

D2

LTC1543

DTE_TXD/DCE_RXD

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_SCTE/DCE_RXC

M0

M1

M2

DCE/DTE

VCC

VDD

NC

NC

VCC

VEE

GND

2VCC

14

24

11

15

12

17

9

3

1

2521

18

4

19

20

8

23

10

6

22

5

13

7

16

D3

R2

R1

R3

D1

C21µF

C11µF

C51µF

C31µF

C43.3µF

TXD A

TXD B

SCTE A

SCTE B

RXD A

RXD B

RXC A

RXC B

RXC A

RXC B

RXD A

RXD B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

SG

SHIELD

DCE/DTEM1M0

DB-25 CONNECTOR

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

TXC A

TXC B

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

DCD A

DCD B

DTR A

DTR B

D4

16109764

3 8 11 12 13

5

2

15 18 17 19 20 22

LTC1344A

C6100pF

C7100pF

C8100pF

VCC

VCC5V

23 24

14

1

DCE/

DTE

M2

M1

M0+

283

1

2

4

5

6

7

8

9

10

11

1213

14

12

3

4

5

6

7

8

9

10

INVERT15

17

16

18

19

20

21

22

23

24

25

NC

2726

25

24

23

22

21

20

19

18

17

16

15

26

27

28

VEE

M0

M1

M2

DCE/DTE

11

12

13

14

DTE DCE

PIN 18PIN 7

NCPIN 7

CABLE WIRING FOR MODE SELECTION


CABLE WIRING FORDTE/DCE SELECTION

LATCH21

C121µF

C131µF

C111µF

C101µF

C91µF

CHARGEPUMP

MODEV.35

RS449, V.36RS232

PIN 21PIN 7PIN 7

NC

Figure 61. Cable-Selectable Multiprotocol DTE/DCE Port

Application Note 87

AN87-43

D2

D1

LTC1544

D3

R2

R1

R4

R3

D2

LTC1343

DTE_LL/DCE_TM

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_TM/DCE_LL

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_RL/DCE_RL

DTE_TXD/DCE_RXD

DTE_SCTE/DCE_RXC

CTRL

LATCH

INVERT

423SET

GND

DCE

M2

M1

M0

EC

VCC

VDD

VCC

VEE

GND

2

18

14

24

11

15

12

17

9

3

1

4

19

20

8

23

10

6

22

5

13

21

7

16

25

D3

D4

R2

R3

R4

D1

C21µF

C11µF

C51µF

C31µF

C43.3µF

LL A

TXD A

TXD B

SCTE A

SCTE B

TM A

RXD A

RXD B

RXC A

RXC B

RXC A

RXC B

RXD A

RXD B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

RL A

SG

SHIELD

DB-25 CONNECTOR

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

TXC A

TXC B

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

RL A

DCD A

DCD B

DTR A

DTR B

D4

16109764

3 8 11 12 13

5

2

15 18 17 19 20 22

LTC1344A

C6100pF

C7100pF

C8100pF

VCC

VCC5V

23 24

14

1

DCE/

DTE

M2

M1

M0+

44

3

1

2

4

5

8

6

7

9

101213

14

15

16

20

22

11

1

R1100k

2

3

4

5

6

7

8

10

9

INVERT15

16

17

18

19

20

21

22

23

24

25

NC

4342

41

39

38

37

36

35

34

33

32

31

30

29

28

27

26

2119

1817

24

26

27

28

VEE

M0

M1

M2

DCE/DTEDCE/DTE

M2M1M0

11

12

13

14

DTE DCE

R1

25

40

23

VCC

LB

LB

TM A LL A

LATCH21

C121µF

C131µF

C111µF

C101µF

C91µF

CHARGEPUMP

Figure 62. Controller-Selectable Multiprotocol DTE/DCE Port with RLL, LL, TM and DB-25 Connector

Application Note 87

AN87-44

NET1 AND NET2 SERIAL INTERFACE CHIP SETSUPPORTS TEST MODE by David Soo

Some serial networks use a test mode to exercise all of thecircuits in the interface. The network is divided into localand remote data terminal equipment (DTE) and data-circuit-terminating equipment (DCE), as shown in Figure63. Once the network is placed in a test mode, the local DTEwill transmit on the driver circuits and expect to receive thesame signals back from either a local or remote DCE. Thesetests are called local or remote loopback.

The LTC1543/LTC1544/LTC1344A chip set has taken theintegrated approach to multiple protocol. By using thischip set, the Net1 and Net2 design work is done. TheLTC1545 extends the family by offering test mode capabil-ity. By replacing the 6-circuit LTC1544 with the 9-circuit

4451CTL/3451CTLemaNedoM 2M 1M 0M

desUtoN 0 0 0

A035-AIE 0 0 1

035-AIE 0 1 0

12.X 0 1 1

53.V 1 0 0

63.V/944SR 1 0 1

82.V/232SR 1 1 0

elbaCoN 1 1 1

LOCALDTE

LOCALDCE LL REMOTE

DCERL REMOTE

DTE

LTC1545, the optional circuits TM (Test Mode), RL (RemoteLoopback) and LL (Local Loopback) can now beimplemented.

Figure 64 shows a typical application using the LTC1543,LTC1545 and LTC1344A. By just mapping the chip pins tothe connector, the design of the interface port is complete.The chip set supports the V.28, V.35, V.36, RS449, EIA-530, EIA-530A or X.21 protocols in either DTE or DCEmode. Shown here is a DCE mode connection to a DB-25connector. The mode-select pins, M0, M1 and M2, areused to select the interface protocol, as summarized inTable 5.

Figure 63. Serial Network

Table 5. Mode-Pin Functions

Application Note 87

AN87-45

D2

D1

LTC1544

CTS

DSR

DTR

DCD

RTS

D3

R2

R1

R4

R3

D2

LTC1543

LL

RXD

RXC

TXC

SCTE

TXD

M0

M1

M2

DCE/DTE

VCC

VDD

VCC

VEE

GND

3

16

17

9

15

12

24

11

2

1

5

13

6

8

22

10

20

23

4

19

18

7

14

1544 F23

D3

R2

R1

R3

D1

C21µF

C11µF

C51µF

C31µF

C43.3µF

RXD A (104)

RXD B

RXC A (115)

RXC B

SCTE A (113)

SCTE B

TXD A (103)

TXD B

CTS A (106)

CTS B

DSR A (107)

DSR B

RTS A (105)

RTS B

LL A (141)

SGND (102)

SHIELD (101)


TXC A (114)

TXC B

DCD A (109)

DCD B

DTR A (108)

DTR B

D4

16109764

3 8 11 12 13

5

2

15 18 17 19 20 22

LTC1344A

C6100pF

C7100pF

C8100pF

VCC

VCC

VCC5V

23 24

14

1

DCE/

DTE

M2

M1

M0

CHARGEPUMP

+

283

1

2

4

5

6

7

8

9

10

NC

11

1213

14

12

3

4

5

6

7

8

10

9

INVERT15

16

17

18

19

20

21

22

23

24

25

NC

NC

2726

25

24

23

22

21

20

19

18

17

16

15

26

27

28

VEE

M0

M1

M2

DCE/DTE

M2M1M0

11

12

13

14

21LATCH

C121µF

C131µF

C111µF

C101µF

C91µF

Figure 64. Typical Application: Controller-Selectable DCE Port with DB-25 Connector

Just amarker

Application Note 87

AN87-46

Operational Amplifiers/Video Amplifiers

LT1490/LT1491 OVER-THE-TOP DUAL AND QUADMICROPOWER RAIL-TO-RAIL OP AMPSby Jim Coelho-Sousae

Introduction

The LT1490 is Linear Technology’s lowest power, lowestcost and smallest dual rail-to-rail input and output opera-tional amplifier. The ability to operate with its inputs aboveVCC, its high performance-to-price ratio and its availabilityin the MSOP package, sets the LT1490 apart from otheramplifiers.

An Over-the-Top Application

The battery current monitor circuit shown in Figure 65demonstrates the LT1491’s ability to operate with itsinputs above the positive supply rail. In this application, a

Figure 65. LT1491 Battery Current Monitor—an “Over-The-Top” Application

–

+

+

1/4LT1491

A

+

–1/4

LT1491C

RA2k

RS0.2Ω

QA2N3904

CHARGERVOLTAGE

VBATTERY = 12V

VSUPPLY = 5V, 0V

LOGIC

RA'2k

–

+1/4

LT1491B

–

+1/4

LT1491D

RB2k

RB'2k

90.9k

RL

RG10k

10k

S1S1 = OPEN, GAIN = 1S1 = CLOSED, GAIN = 10

LOGIC HIGH (5V) = CHARGINGLOGIC LOW (0V) = DISCHARGING

NOTE: RA = RB

QB2N3904

VOUT

VOUT

RS RG/RA GAIN

VOUT

GAIN

( )( ) ( )IBATTERY = = AMPS

1N4001

conventional amplifier would be limited to a battery volt-age between 5V and ground, but the LT1491 can handlebattery voltages as high as 44V. The LT1491 can be shutdown by removing VCC. With VCC removed the inputleakage is less than 0.1nA. No damage to the LT1491 willresult from inserting the 12V battery backward.

When the battery is charging, Amp B senses the voltagedrop across RS. The output of Amp B causes QB to drainsufficient current through RB to balance the inputs of AmpB. Likewise, Amp A and QA form a closed loop when thebattery is discharging. The current through QA or QB isproportional to the current in RS; this current flows intoRG, which converts it back to a voltage. Amp D buffers andamplifies the voltage across RG. Amp C compares theoutput of Amp A and Amp B to determine the polarity ofthe current through RS. The scale factor for VOUT with S1open is 1V/A. With S1 closed the scale factor is 1V/100mA, and current as low as 5mA can be measured.

Application Note 87

AN87-47

THE LT1210: A 1-AMPERE, 35MHzCURRENT FEEDBACK AMPLIFIERby William Jett and Mitchell Lee

Introduction

The LT1210 current feedback amplifier extends LinearTechnology’s high speed driver solutions to the 1 amperelevel. The device combines a 35MHz bandwidth with aguaranteed 1A output current, operation with ±5V to ±15Vsupplies and optional compensation for capacitive loads,making it well suited for driving low impedance loads.Short circuit protection and thermal shutdown ensure thedevice’s ruggedness. A shutdown feature allows the device

INPUT

–

+

4.7µF*

15V

–15V

LT1210

RT11Ω, 2.5W

T1

100nF

4.7µF* 100nF

RL = 100Ω, 2.5W

845Ω

*TANTALUMT1 = MIDCOM 671-7783 OR EQUIVALENT

31

274Ω

+

+

–

+

15V

–15V

LT1210

5.6Ω2.5W

T1

5.6Ω2.5W

RL = 100Ω, 5W

220Ω

T1 = MIDCOM 671-7783 OR EQUIVALENT

31

680Ω

910Ω–

+LT1210

INPUT

to be switched into a high impedance, low current mode,reducing dissipation when the device is not in use. TheLT1210 is available in the 7-pin TO-220 package, the 7-pinDD surface mount package and the 16-pin SO-16 surfacemount package.

Twisted Pair Driver

Figure 66 shows a transformer-coupled application of theLT1210 driving a 100Ω twisted pair. This surge imped-ance is typical of PVC-insulated, 24 gauge, telephone-grade twisted pair wiring. The 1:3 transformer ratio allowsjust over 1W to reach the twisted pair at full output.Resistor RT acts as a primary side back-termination. The

Figure 66. Twisted Pair Is Easily Driven for Applications Such as ADSL.Voltage Gain is About 12. 5VP–P Input Corresponds to Full Output

Figure 67. In a Bridge Configuration, the LT1210 Can Deliver Almost5W to a Twisted Pair (and Another 5W to the Back Termination)

Application Note 87

AN87-48

overall frequency response is flat to within 1dB from500Hz to 2MHz. Distortion products at 1MHz are below–70dBc at a total output power of 560mW (load plustermination), rising to –56dBc at 2.25W.

On a ±15V supply, a maximum output power of 5W isavailable when a 10Ω load is presented to the LT1210.With the transformer shown in Figure 66, a total loadimpedance of approximately 22Ω limits the output to2.25W. Bridging allows nearly maximum output power tobe delivered into standard 1:3 data communications trans-formers. Figure 67 shows a bridged application with twoLT1210s, delivering approximately 9W maximum into theload and termination.

At first glance the resistor values would suggest a gainimbalance between the inverting and noninverting sides ofthe bridge. On close inspection, however, it is apparentthat both sides operate at a closed loop gain of 4 relativeto the input signal. This ensures symmetric swing andmaximum undistorted output.

Matching 50Ω Systems

Few practical systems exhibit a 10Ω impedance, so amatching transformer is necessary for applications driv-ing other loads, such as 50Ω. Multifilar winding tech-niques exhibit the best high frequency characteristics.

Suitable off-the-shelf components are available, such asthe Coiltronics Versa-Pac™ series. These are hexafilarwound and give power bandwidths in excess of 10MHz.One disadvantage is that using a limited number of 1:1windings makes it impossible to exactly transform 50Ω tothe optimum 10Ω load. Nevertheless, there are severaluseful connections.

In Figure 68 the windings are configured for a 2:4 step-up,reflecting 12.5Ω into the LT1210. The circuit exhibits 18dBgain and drives 50Ω to nearly +36dBm. The large-signal,low frequency response is limited by the magnetizinginductance of the transformer to about 15kHz. The highfrequency response is limited to 10MHz by the stack of foursecondary windings.

Reconfiguring the transformer windings allows doubletermination at full power (Figure 69). Here the transformerreflects 11.1Ω and the amplifier delivers over +33dBm tothe load. Paralleled input windings limit the low frequencyresponse to 80kHz, but fewer series secondary windingsextend the high frequency corner to 18MHz.

The coupling capacitor shown in these examples is addedto block current flow through the transformer primary,arising from amplifier offsets. The capacitor value is basedon setting XC equal to the reflected load impedance at the

–

+

15V

–15V

LT1210

T1

RL = 50Ω, 4W

220Ω

T1 = COILTRONICS VERSA-PAC CTX-01-13033-X2

INPUT5VPP

680Ω

10nF

1µF

–

+

15V

–15V

LT1210

T1

RL = 50Ω2.5W

RT = 50Ω2.5W

220Ω

T1 = COILTRONICS VERSA-PAC CTX-01-13033-X2

INPUT5VPP

680Ω

10nF

330nF

Figure 68. Matched to a 50Ω Load with a Balun-ModeTransformer, this Circuit Delivers a Measured 35.6dBm (almost4W). Full-Power Band Limits are 15kHz to Slightly Over 10MHz

Figure 69. Wide Bandwidth can be Obtained with Even HigherImpedance Transformations. Here, a 1:3 Step-Up Matches 100Ωand Develops Nearly 4.5W. A Measured +33dBm Reaches the50Ω Load. Full-Power Band Limits Are 80kHz to 18MHz

Application Note 87

AN87-49

frequency where XL of the primary is also equal to thereflected load. This isolates the amplifier from a lowimpedance short at frequencies below transformer cutoff.In applications where a termination resistor is positionedbetween the LT1210 amplifier and the transformer, nocoupling capacitor is necessary. Note that a low frequencysignal, well below the transformer’s cutoff frequency,could result in high dissipation in the termination resistor.

–

+

15V

–15V

LT1210T1

RL = 50Ω, 9W

220Ω

T1 = CTX-01-13033-X2 VERSA-PAC

INPUT5VP–P

100nF

910Ω

680Ω

–

+

10nF

10nF

LT1210

FREQUENCY (MHz)

–4

–1

2

5

8

11

14

17

20

23

26

GAIN

(dB)

1000.01 0.1 1.0 10.0

Figure 70. In this Bridge Amplifier, the LT1210 Delivers+39.5dBm (9W) to a 50Ω Load. Power Band Limits Range from40kHz to 14.5MHz. The Sixth, Otherwise-Unused Winding isConnected in Parallel with One Secondary Winding to AvoidParasitic Effects Arising from a Floating Winding.

Figure 71. Frequency Response of Figure 70's Circuit

Another useful connection for the Versa-Pac transformeris shown in Figure 70. A 2:3 transformation presents11.1Ω to each LT1210 in a bridge, delivering a whopping9W into 50Ω. In this circuit the lower frequency cutoff waslimited by the choice of coupling capacitor to approxi-mately 40kHz (the transformer is capable of 15kHz). Thefrequency response is shown in Figure 71.

Conclusion

The LT1210 combines high output current with a high slewrate to form an effective solution for driving low impedanceloads. Power levels of up to 5W can be supplied to a loadat frequencies ranging from DC to beyond 10MHz.

Application Note 87

AN87-50

THE LT1207: AN ELEGANT DUAL 60MHZ, 250mACURRENT FEEDBACK AMPLIFIERby LTC Applications Staff

Introduction

The LT1207 is a dual version of Linear Technology’sLT1206 current feedback amplifier. Each amplifier has60MHz bandwidth, guaranteed 250mA output current,operates on ±5V to ±15V supply voltages and offersoptional external compensation for driving capacitive loads.These features and capabilities combine to make it wellsuited for such difficult applications as driving cable loads,wide-bandwidth video and high speed digitalcommunication.

LT1088 Differential Front End

Using thermal conversion, the LT1088 wideband RMS/DCconverter is an effective solution for applications such asRMS voltmeters, wideband AGC, RF leveling loops andhigh frequency noise measurements. Its thermal conver-sion method achieves vastly wider bandwidth than anyother approach. It can handle input signals that have a300MHz bandwidth and a crest factor of at least 40:1. Thethermal technique employed relies on first principles: awave form’s RMS value is defined as its heating value in aload. Another characteristic of the LT1088 is its lowimpedance inputs (50Ω and 250Ω), common to thermalconverters. Though this low impedance represents a dif-ficult load to most drive circuits, the LT1207 can handle itwith ease.

Featuring high input impedance and overload protection,the differential input, wideband thermal RMS/DC con-verter in Figure 72 performs true RMS/DC conversion overa 0Hz to 10MHz bandwidth with less than 1% error,independent of input-signal wave shape. The circuit con-sists of a wideband input amplifier, RMS/DC converter andoverload protection.1 The LT1207 provides high inputimpedance, gain and output current capability necessaryto drive the LT1088’s input heater. The 5k/24pF networkacross the LT1207’s 180Ω gain-set resistor is used toadjust a slight peaking characteristic at high frequencies,ensuring 1% flatness at 10MHz. The converter usesmatched pairs of heaters and diodes and a control ampli-

fier. R1 produces heat when the LT1207 drives it differen-tially. This heat lowers D1’s voltage. Differentially con-nected A3 responds by driving R2, heating D2 and closingthe loop. A3’s DC output directly relates to the inputsignal’s RMS value, regardless of input frequency or waveshape. A4’s gain trim compensates residual LT1088 mis-matches. The RC network around A3 frequency compen-sates the loop, ensuring good settling time.

The LT1088 can suffer damage if the 250Ω input is drivenbeyond 9VRMS at 100% duty cycle. An easy remedy to thispossibility is to reduce the driver supply voltage. This,however, sacrifices crest factor. Instead, a means ofoverload protection is included. The LT1018 monitorsD1’s anode voltage. Should this voltage become abnor-mally low, A5’s output goes low and pulls A6’s input low.This causes A6’s output to go high, shutting down theLT1207 and eliminating the overload condition. The RCnetwork on A6’s input delays the LT1207’s reactivation. Ifthe overload condition remains, shutdown is reinstated.This oscillatory action continues, protecting the LT1088until the overload is corrected. The RMS/DC circuit’s 1%error bandwidth and CMRR performance are shown inFigures 73 and 74, respectively.

CCD Clock Driver

Charge-coupled-devices (CCDs) are used in many imag-ing applications, such as surveillance, hand-held anddesktop computer video cameras, and document scan-ners. Using a “bucket-brigade,” CCDs require a precisemultiphase clock signal to initiate the transfer of light-generated pixel charge from one charge reservoir to thenext. Noise, ringing or overshoot on the clock signal mustbe avoided, since they introduce errors into the CCDoutput signal. These errors cause aberrations and pertur-bations in a displayed or printed image.

Two challenges surface in the effort to avoid these errorsources when driving a CCD’s input. First, CCDs have aninput capacitance that varies over a range of 100pF to2000pF and varies directly with the number of sensingelements (pixels). This presents a high capacitive load tothe clock-drive circuitry. Second, CCDs typically require aclock signal whose magnitude is greater than the outputcapabilities of 5V interfaces and control circuitry. An

Application Note 87

AN87-51

–+A1 1/

2LT

1207

ZERO

TRI

M(T

RIM

AT

1V O

UTPU

T)15

V

1k

1k

4.7k

1k

1.5M

9.09

M

1k 3k

1,16

14

806Ω

2.7k

10k

2k

9.09

M

2.7k

3

5V –5V

2

10µF

10µF

LT10

88

0.1µ

F

0.1µ

F15

3 7 14

D1D2

250Ω R1

250Ω R2

4

806Ω

10M

HzTR

IM

180Ω

5k

24pF

+–A2 1/

2LT

1207

8,9

11

5

5V–1

5V

–5V

6

10µF

10µF

0.1µ

F

0.1µ

F12

113

6

125

10

8

7

1N91

4

0.1µ

F

0.01

µF

+–A3 1/

2LT

1078

8215

V

3

0.1µ

F

3300

pF

0.02

2µF

1Q1 2N

2219

LT10

041.

2V

LT10

041.

2V

–+A4 1/

2LT

1078

4

5 –15V

6

0.1µ

F7

10k

10k

V OUT

–+A5 1/

2LT

1018

83

15V

2

0.1µ

F

0.1µ

F

1

10k

–15V

12k

15V

–15V

1k

15V

510k

15V

–+A6 1/

2LT

1018

4

6 5

0.1µ

F7

500Ω

V IN

15V

+ +++

10k

FULL

-SCA

LETR

IM

Figure 72. Differential Input 10MHz RMS/DC Converter has 1% Accuracy, High Input Impedance and Overload Protection.

Application Note 87

AN87-52

–1.0

–0.5

0.5

1.0

0

ERRO

R (%

)

0 2 4 6FREQUENCY (MHz)

8 10 12 14

A

B

0100:1

900:1

1000:1

600:1700:1

800:1

400:1

500:1

200:1

300:1

COM

MON

MOD

E RE

JECT

ION

RATI

O, V

CM =

5V R

MS

0 2 4 6FREQUENCY (MHz)

8 10 12 14

1% ERRORPOINT

= 10.2MHz

>>1000:1

Figure 73. Error Plot for the Differential-Input RMS/DCConverter. Gain Boost at A2 Preserves 1% Accuracy butCauses Slight Peaking before Roll-Off. Boost Can be Setfor Maximum Bandwidth (A) or Minimum Error (B)

Figure 74. Common Mode Rejection Ratio vs Frequency for theDifferential-Input RMS/DC Converter. Layout, AmplifierBandwidth and AC Matching Characteristics Determine the Curve

13

–

+1/2

LT1207

1,16

14

1k

10Ω

SIMULATEDCCD ARRAY LOAD

1k

500kHz

500kHz

2MHz74HC74

1k 3

20V

–10V

2

10µF

10µF

0.1µF

45pF

0.1µF 0.1µF

15

13

4

510k

3300pF

91pF180pF

–

+1/2

LT1207

8,9

11

1k

1k

1k

5V

10Ω

1k1k 6

20V

–10V

5

10µF

10µF

0.1µF

45pF

0.1µF 0.1µF

12

10

7

510k

3300pF

91pF180pF

4

3CLK

2

8

5

6

9

2Q

1Q

1Q

2Q

1

10

11

12

1CK

1D

2CK

2D

+

+

+

+

Figure 75. The LT1207 Easily Tames the High Capacitance Loads of CCD Clock Inputs without Ringing or Overshoot

Application Note 87

AN87-53

Figure 76a. Trace A is the Quadrature Drive Signals. Trace B.is the Voltage at the Input of the Simulated CCD of Figure 75,Driven by HC Logic

Figure 76b. Trace A is the Quadrature Signals. Trace BShows the Voltage at the Input of the Simulated CCD ofFigure 75, Driven by the LT1207

A

B

A

B

amplifying filter built around the LT1207 will meet bothchallenges.

Controlling clock signal rise and fall times is one way toavoid ringing or overshoot. This is done by conditioningthe clock signal with a nonringing Gaussian filter. Thecircuit shown in Figure 75 uses the LT1207 to filter andamplify control circuitry clock output signals. To reduceringing and overshoot, each amplifier is configured as athird-order Gaussian lowpass filter with a 1.6MHz cutofffrequency.

Figures 76a and 76b compare the response of a digital 5Vclock-drive signal and the output of the LT1207, eachdriving a 3300pF load. The digital clock circuit has two

major weaknesses that lead to jitter and image distortion.The CCD’s output is changing during charge transfer,producing glitches that decay exponentially. Conversely,the LT1207 circuit's output has a flat top and controlledrise and fall. If an ADC is used to sample a CCD output, theconversion will be much more accurate when the LT1207circuit is used to clock the pixel changes. With the LT1207’sfilter configuration, the output has a controlled rise and falltime of approximately 300ns. Ringing and overshoot areabsent from the LT1207’s output. Wide bandwidth, highoutput current capability and external compensation allowthe LT1207 to easily drive the difficult load of a CCD’s clockinput.

1. Thanks to Jim Williams for this Circuit

Application Note 87

AN87-54

MICROPOWER, DUAL AND QUAD JFET OP AMPSFEATURE C-LOAD CAPABILITY AND PICOAMPEREINPUT BIAS CURRENTSby Alexander Strong

Introduction

The LT1462/LT1464 duals and the LT1463/LT1465 quadsare the first micropower op amps (30µA typical, 40µAmaximum per amp for the LT1462; 140µA typical, 200µAmaximum per amp for the LT1464) to offer both picoampere input bias currents (500fA typical) and unity-gainstability for capacitive loads up to 10nF. The outputs canswing a 10k load to within 1.5 volts of either supply. Justlike op amps that require an order of magnitude moresupply current, the LT1462/LT1463 and the LT1464/LT1465 have open loop gains of 600,000 and 1,000,000,respectively. These unique features, along with a 0.8mVoffset, have not been incorporated into a single monolithicamplifier before.

1464_02.eps

–

+

0.5pA10nF

1/2LT1464

V+

V–

V+

V–

VOUT1

8

4

TYPICAL DROOP = = 0.05mV/SEC.

TOTAL SUPPLY CURRENT = 460µA MAX.*R1 = 600Ω FOR ±15V SUPPLIES,R1 = 0Ω FOR ±5V SUPPLIES

2

3

C1, 10nFPOLYSTYRENEMCT2 5

4

4

6*R1

6

2

2

5

1

1–

+1/2

LT1464

LTC201 SWITCH IS OPEN FOR LOGIC “1”

7

5

16A

1/4LTC201

FUNCTION

TRACK AND HOLD

POSITIVE PEAK DETECTOR

NEGATIVE PEAK DETECTOR

MODE

TRACK

RESET

RESET

IN A

0

0

0

IN B

0

0

0

MODE

HOLD

STORE

STORE

IN A

1

0

1

IN B

1

1

0

13

4 14

6MCT2

1B

IN

1/4LTC201 2

15

3

Applications

Figure 77 is a track-and-hold circuit that uses a low costoptocoupler as a switch. Leakages for these parts areusually in the nano amp region with 1 to 5 volts across theoutput. Since there is less than 2mV across the junctions,less than 0.5pA leakage can be achieved for both opto-couplers. The input signal is buffered by one op amp whilethe other buffers the stored voltage; this results in a droopof 50µV/s with a 10nF cap.

Figure 78 is a logging photodiode sensor using twoLT1462 duals or an LT1463 quad. The low input biascurrent of the LT1462/LT1463 makes it a natural foramplifying low level signals from high impedance trans-ducers. The 500fA of input bias current contributes only0.4fA/√Hz of current noise. For example, a 1M inputimpedance converts the noise current to a noise voltage ofonly 0.4nV/√Hz. Here, a photodiode converts light to a

Figure 77. Low-Droop Track-and-Hold Circuit/Peak Detector

Application Note 87

AN87-55

current, which is converted to a voltage by the first op amp.The first, second and third gain stages are logarithmicamplifiers that perform a logarithmic compression. A DCfeedback path comprising R8, R9, C5 and Q1 is active onlyfor no-light conditions, which are very rare, due to thepicoampere sensitivity of the input. Q1 is off when light ispresent, isolating the photodiode from C5. When thefeedback path is needed, a small filtered current throughR8 keeps the output of the third op amp within an accept-able range. The third op amp’s output voltage, which isproportional to the photodiode current, can serve as alogarithmic DC light meter. Figure 79 shows the relation-ship between DC output voltage and photodiode current.The AC component of the output of third op amp iscompressed logarithmically and passed through capacitorC3 and pot R10 for amplitude control. The fourth op ampamplifies this AC signal which is generated across R13.The logarithmic compression of the AC photodiode cur-rent allows the user to examine the AC signals for a widerange of input currents.

Conclusion

The LT1462/LT1464 duals and the LT1463/LT1465 quadscombine many advantages found in many different opamps, such as low power, (LT1464/LT1465 are 140µA,LT1462/LT1463 are 30µA typical per amplifier), wideinput common mode range that includes the positive railand pico ampere input bias currents. Not only is the outputswing specified with 2k and 10k loads, gain is alsospecified for the same load conditions, which is unheard-

1464_03.eps DBD

–

+1/2

LT1462

+5

–5

ACOUT

DCOUT

7

8

4

5

6

C410µF

R111M

R1310k

R1210k

R1050k

C30.47µF

C11nF

–

+1/2

LT14621

3

2

R710M

R524k

R224k

R8100k

Q12N3904

D31N4148

R6100k

R91M

–

+1/2

LT14627

5

6

R410M

D21N4148

D11N4148

R3100k

C2200pF

C51µF

–

+1/2

LT1462

+5

–5

1

8

4

PHOTODIODE

2

3

R1100Ω

C5200pF

+

Figure 78. Logging Photodiode Amplifier

Figure 79. DC Output of Logging Photodiode Amplifier

PHOTODIODE CURRENT (A)

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

DC O

UTPU

T (v

)

1464_04.eps

10 –11 10 –9 10 –7 10 –5 10 –3

Application Note 87

AN87-56

THE LT1210: HIGH POWER OP AMP YIELDSHIGHER VOLTAGE AND CURRENTby Dale Eagar

Introduction

The LT1210, a 1 amp current feedback operational amplifier,opens up new frontiers. With 30MHz bandwidth, operationon ±15V supplies, thermal shutdown and 1 amp of outputcurrent, this amplifier single-handedly tackles many toughapplications. But can it handle output voltages higher than±15V or currents greater than 1 ampere? This Design Ideafeatures a collection of circuits that open the door to highvoltage and high current for the LT1210.

Fast and Sassy—Telescoping Amplifiers

Need ±30V? Cascading LT1210’s will get you there. Thiscircuit (Figure 80) will provide the ±30V at ±1A and has13MHz of full-power bandwidth (see Figure 81). How doesit work? The first LT1210 drives the “ground” of thesecond LT1210 subcircuit, effectively raising and lowering

of for micropower op amps. The 1MHz (LT1464/LT1465)or 250kHz (LT1462/LT1463) bandwidth self adjusts tomaintain stability for capacitive loads up to 10nF. And

it while the second LT1210 further amplifies the inputsignal. This telescoping arrangement can be cascadedwith additional stages to get more than ±30V. This ampli-fier is stable into capacitive loads, is short-circuit pro-tected and thermally shuts down when overheated.

Extending Power Supply Voltages

Another method of getting high voltage from an amplifieris the extended-supply mode (see “Extending Op AmpSupplies to Get More Voltage”; Linear Technology Vol-ume IV Number 2 (June 1994), pp. 20–22). This involvessteering two external regulators with the power supplypins of an op amp to get a high voltage amplifier.

Figure 82 shows the LT1210 connected in the extended-supply mode. Placing an amplifier in the extended-supplymode requires changing the return of the compensationnode from the power supply pins to system ground. R9and C5 are selected for clean step response. The processof relocating the return of the compensation node slowsthe amplifier down to approximately 1MHz (see Figure 83).

–

+

–

+

30V

OUTPUT

INPUT 300Ω1µF

0.01µF

1

2

36

5

7

4

1

2

36

5

7

4

0.01µF

1µF

1µF

1k

1k

1k

1k

15V

15V

–15V

15V

1kΩ

6.2k

LT1210

LT1210

6.2k

–30V

TIP 29

TIP 30

1µF

60Ω

Figure 80. Telescoping Amplifiers

don’t forget the low 0.8mV offset voltage and DC gains of1 million (LT1464/LT1465) or 600,000 (LT1462/LT1463)even with 10k loads.

Application Note 87

AN87-57

Figure 82’s circuit will provide ±1A at ±100V, is stable intocapacitive loads and is short-circuit protected. The twoexternal MOSFETs need heat sinking.

Gateway to the Stars

The circuit of Figure 82 can be expanded to yield muchhigher voltages; the first and most obvious way is to usehigher voltage MOSFETs. This causes two problems: first,high voltage P-channel MOSFETs are hard to get; second,and more importantly, at ±1A the power dissipated by theMOSFETs is too high for single packages. The solution isto build telescoping regulators, as shown in Figure 84.This circuit can provide ±1A of current at ±200V and hasthe additional power-dissipation ability of four MOSFETs.

Boosting Output Current

The current booster detailed in Figure 85 illustrates atechnique for amplifying the output current capability of anop amp while maintaining speed. Among the many nice-ties of this topology is the fact that both Q1 and Q2 arenormally off and thus consume no quiescent current.Once the load current reaches approximately 100mA, Q1or Q2 turns on, providing additional drive to the output.This transition is seamless to the outside world and takesadvantage of the full speed of Q1 and Q2. This circuit’ssmall-signal bandwidth and full-power bandwidth areshown in Figure 86.

Boosting Both Current and Voltage

The current-boosted amplifier shown in Figure 85 can beused to replace the amplifiers in Figure 80, yielding ±10Aat ±30V. Placing the boosted amplifier in the circuitsshown in Figures 82 or 84 will yield peak powers into thekilowatts.

Thermal Management

When the LT1210 is used with external transistors toincrease its output voltage and/or current range an

30

25

2050Ω LOAD

FIGURE 80's CKT +10dBM INPUT50Ω LOAD

15

10

5

0

–5

–10

–15

–2010K

GAIN

(dB)

100K 1MFREQUENCY (Hz)

60M10M

–

+

INPUT R710k 1k

R10 300Ω

0.01

0.01µF

0.01µF

C58pF

LOAD

1

2

36

5

7

4

100Ω

220Ω

100Ω

P6KE15A

P6KE15A

15V

15VR8

300ΩIRF640

IRF9640

100V100V

–100V

–100V

15k

R99.1k

LT1210

AR R R

R R R RV = −=( )

−

8 9 10

8 9 7 10

100k

100k

+

Figure 81. Gain vs Frequency Plot of Telescoping Amplifier

Figure 82. ±100V, ±1A Power Driver

Application Note 87

AN87-58

additional benefit can often be realized: system thermalshutdown. Careful analysis of the thermal design of thesystem can coordinate the overtemperature shutdown ofthe LT1210 with the junction temperatures of the externaltransistors. This essentially extends the umbrella of pro-tection of the LT1210’s thermal shutdown to cover theexternal transistors. The thermal shutdown of the LT1210activates when the junction temperature reaches 150˚Cand has about 10˚C hysteresis. The thermal resistanceRθJC of the TO-220 package (LT1210CY) is 5˚C/Watt).

30

25

20

90Vp-p INTO 50Ω

FIGURE 82 CKT

15

10

5

0

–5

–10

–15

–2010K

GAIN

(dB)

100K 10M1MFREQUENCY (Hz)

60M

–

+

INPUT 10k5W 1k

300Ω

100Ω

0.01µF

±1A±200V

C58pF

0.1µF

0.1

1

2

36

5

7

4

15V

15V

300Ω

220Ω

IRF640

IRF9640

200V

–200V

0.47µF250V

0.47µF250V

10k1W 15V

15V

10k1W

R99.1k

10k1W

10k1W

LT1210

IRF9640

IRF640

LOAD

–

+

11.8kIN

2

36

5

7OUT

4

0.01

Q2, D44VH4

Q1, D45VH4

0.033Ω

0.033Ω

R16.2Ω

R26.2Ω

0.01µF

18V

3.6k

–18V

0.01µF

LT1210

Figure 83. Gain vs Frequency Plot of Extended-Supply Amplifier

Figure 84. Cascode Power Amplifier Figure 85. ±10A/1MHz Current-Boosted Power Op Amp

Application Note 87

AN87-59

Summary

The LT1210 is a great part; its performance in terms ofspeed, output current and output voltage is unsurpassed.Its C-Load™ output drive and thermal shutdown allow it totake its place in the real world—no kid gloves are requiredhere. If the generous output specification of the LT1210

8

7

6

4AP–P INTO 1Ω

50Ω LOAD

1Ω LOAD

FIGURE 85 CKT +10dBM INPUT

5

4

3

2

1

0

–1

–210K

GAIN

(dB)

100K 1MFREQUENCY (Hz)

10M

isn’t big enough for your needs, just add a couple oftransistors to dissipate the additional power and you areon your way. Only the worldwide supply of transistorslimits the amount of power you could command with oneof these parts.

Figure 86. Gain vs Frequency Response of Current-Boosted Amplifier

NEW RAIL-TO-RAIL AMPLIFIERS: PRECISIONPERFORMANCE FROM MICROPOWER TO HIGH SPEEDby William Jett and Danh Tran

Introduction

Linear Technology’s latest offerings expand the range ofrail-to-rail amplifiers with precision specifications. Rail-to-rail amplifiers present an attractive solution for signalconditioning in many applications. For battery-powered orother low voltage circuitry, the entire supply voltage can be

used by both input and output signals, maximizing thesystem’s dynamic range. Circuits that require signal sens-ing near the positive supply are straightforward using arail-to-rail amplifier.

Applications

The ability to accommodate any input or output signal thatfalls within the amplifier supply range makes theseamplifiers very easy to use. The following applicationsdemonstrate the versatility of the family of amplifiers.

–

+–

+

R2R_04.eps

100pF

1/2 LT1498

6.81k

330pF

VS—2

VIN11.3k6.81k 47pF

1/2 LT1498 VOUT

5.23k

1000pF

10.2k5.23k

Figure 87. 100kHz 4th Order Butterworth Filter

Application Note 87

AN87-60

100kHz 4th Order Butterworth Filter for 3V Operation

The filter shown in Figure 87 uses the low voltage opera-tion and wide bandwidth of the LT1498. Operating in theinverting mode for lowest distortion, the output swingsrail-to-rail. The graphs in Figures 88–90 display the mea-sured lowpass and distortion characteristics with a 3Vpower supply. As seen from the graphs, the distortion witha 2.7VP–P output is under 0.03% for frequencies up to thecutoff frequency of 100kHz. The stop band attenuation ofthe filter is greater than 90dB at 10MHz.

Multiplexer

A buffered MUX with good offset characteristics can beconstructed using the shutdown feature of the LT1218. Inshutdown, the output of the LT1218 assumes a highimpedance, so the outputs of two devices can be tiedtogether (wired OR, as they say in the digital world). Asshown in Figure 91, the shutdown pins of each LT1218 aredriven by a 74HC04 buffer. The LT1218 is active with theshutdown pin high. The photo in Figure 92 shows theswitching characteristics with a 1kHz sine wave applied toone input and the other input tied to ground. As shown,each amplifier is connected for unity gain, but eitheramplifier or both could be configured for gain.

Conclusion

The latest members of LTC’s family of rail-to-rail amplifiersexpand the versatility of rail-to-rail operation to micro-power and high speed applications. The devices maintain

F

FREQUENCY (Hz)

–110

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

10

GAIN

(dB)

10M

R2R_05.eps

100 100k 1M1k 10k

VS = 3VVIN = 2.7VP-P

AMPLITUDE (VP-P)

0.001

0.01

0.1

1

10

THD

+ NO

ISE

(%)

10

R2R_06.eps

0.01 0.1 1

VS = 3Vf = 20kHz

FREQUENCY (Hz)

0.001

0.01

0.1

1

10

THD

(%)

100k

R2R_07.eps

100 1k 10k

VS = 3VVO = 2.7VP-P

–

+

–

+

R2R_08.eps

74HC04

VIN1

VOUT

5V

S/D

S/DLT1218

LT1218

5V

VIN2

INPUTSELECT

VIN1

VOUT

INPUTSELECT

Figure 88. Filter Frequency Response Figure 89. Filter Distortionvs Amplitude

Figure 90. Filter Distortionvs Frequency

Figure 91. MUX Amplifier

Figure 92. MUX Amplifier Waveforms

precision VOS specifications over the entire rail-to-railinput range and have open loop gains of one million ormore. These characteristics, combined with low voltageoperation, makes for truly versatile amplifiers.

Application Note 87

AN87-61

LT1256 VOLTAGE-CONTROLLED AMPLITUDE LIMITERby Frank Cox

Amplitude-limiting circuits are useful where a signal shouldnot exceed a predetermined maximum amplitude, such aswhen feeding an A/D or a modulator. A clipper, whichcompletely removes the signal above a certain level, isuseful for many applications, but there are times when it isnot desirable to lose information. For instance, when videosignals have amplitude peaks that exceed the dynamicrange of following processing stages, simply clipping thepeaks at the maximum level will result in the loss of alldetail in the areas where clipping takes place. Often thesewell illuminated areas are the primary subject of the scene.Because these peaks usually correspond to the highestlevel of luminosity, they are referred to as “highlights.” Oneway to preserve some of the detail in the highlights is toautomatically reduce the gain (compress) at high signallevels.

The circuit in Figure 93 is a voltage-controlled breakpointamplifier that can be used for highlight compression.When the input signal reaches a predetermined level (thebreakpoint), the amplifier gain is reduced. As both thebreakpoint and the gain for signals greater than thebreakpoint are voltage programmable, this circuit is usefulfor systems that adapt to changing signal levels. Adaptivehighlight compression finds use in CCD video cameras,

–

+

–

+

+

–

75Ω

VIDEOIN

VIDEOOUT

2k

1.5k

1.5k

LT1256

LT1363

1.5k

Q1 Q2

Q3

–5V

100Ω

5V

75Ω

–5V

5V100Ω

510Ω1.5k

2k

BREAK POINTVOLTAGE

100kLT1004-2.5

TO VFSLT1256, PIN 12

TO VCONTROLLT1256, PIN 3

10k

5V

Q1, Q2 = 2N4957Q3 = 2N2857

which have a very large dynamic range. Although thiscircuit was developed for video signals, it can be used toadaptively compress any signal within the 40MHz band-width of the LT1256.

The LT1256 video fader is connected to mix proportionalamounts of input signal and clipped signal to provide avoltage-controlled variable gain. The clipped signal isprovided by a discrete circuit consisting of three transis-tors. Q1 acts as an emitter follower until the input voltageexceeds the voltage on the base of Q2 (the breakpointvoltage or VBP). When the input voltage is greater thanVBP, Q1 is off and Q2 clamps the emitters of the twotransistors to VBP plus a VBE. Q3, an NPN emitter follower,

Figure 94. Multiple-Exposure Photograph of a SingleLine of Monochrome Video, Showing Four DifferentLevels of Compression

Figure 93. Voltage-Controlled Amplitude Limiter

Application Note 87

AN87-62

THE LT1495/LT1496: 1.5µA RAIL-TO-RAIL OP AMPSby William Jett

Introduction

Micropower rail-to-rail amplifiers present an attractivesolution for battery-powered and other low voltage cir-cuitry. Low current is always desirable in battery-poweredapplications, and a rail-to-rail amplifier allows the entiresupply range to be used by both the inputs and the output,maximizing the system’s dynamic range. Circuits thatrequire signal sensing near either supply rail are easier toimplement using rail-to-rail amplifiers. However, untilnow, no amplifier combined precision offset and driftspecifications with a maximum quiescent current of 1.5µA.

Operating on a minuscule 1.5µA per amplifier, the LT1495dual and LT1496 quad rail-to-rail amplifiers consumealmost no power while delivering precision performanceassociated with much higher current amplifiers.

The LT1495/LT1496 feature “Over-The-Top” operation:the ability to operate normally with the inputs above thepositive supply. The devices also feature reverse-batteryprotection.

Applications

The ability to accommodate any input or output signal thatfalls within the amplifier supply range makes the LT1495/LT1496 very easy to use. The following applicationshighlight signal processing at low currents.

Nanoampere Meter

A simple 0nA–200nA meter operating from two flashlightcells or one lithium battery is shown in Figure 95. The

buffers the output and drops the voltage a VBE and thus theDC level of the input signal is preserved to the extentallowed by the VBE matching and temperature tracking ofthe transistors used. The breakpoint voltage at the base ofQ2 must remain constant when this transistor is turning onor the signal will be distorted. The LT1363 maintains a lowoutput impedance well beyond video frequencies andmakes an excellent buffer.

Figure 94 is a multiple-exposure photograph of a singleline of monochrome video, showing four different levels ofcompression ranging from fully limited signal to unproc-essed input signal. The breakpoint is set to 40% of thepeak amplitude to clearly show the effect of the circuit;normally only the top 10% of video would be compressed.

–

+

–

+

µA

1495_05.eps

1/2LT1495

1/2LT1495

C1100pF

R110M

R29k

1.5V

1.5V

R32k

0µA TO200µA

R410k

INPUTCURRENT

D1, D22 ×

1N914

readout is taken from a 0µA–200µA, 500Ω analog meter;the LT1495 supplies a current gain of 1000 in this applica-tion. The op amp is configured as a floating I-to-I con-verter. It consumes only 3µA when not in use, so there isno need for an on/off switch. Resistors R1, R2 and R3 setthe current gain. R3 provides a ±10% full- scale adjust forthe meter movement. With a 3V supply, maximum currentin the meter is limited by R2 + R3 to less than 300µA,protecting the movement. Diodes D1 and D2 and resistorR4 protect the inputs from faults up to 200V. Diodecurrents are below 1nA in normal operation, since themaximum voltage across the diodes is 375µV, the VOS ofthe LT1495. C1 acts to stabilize the amplifier, compensat-ing for capacitance between the inverting input and ground.The unused amplifier should be connected as shown forminimum supply current. Error terms from the amplifier(base currents, offset voltage) sum to less than 0.5% overthe operating range, so the accuracy is limited by theanalog meter movement.

Figure 95. 0nA–200nA Current Meter

Application Note 87

AN87-63

–

+

–

+

1495_08.eps

RSENSE0.1Ω

ILCHARGE

RA

Q12N3904

CHARGEOUT

DISCHARGEOUT

DISCHARGE

Q22N3904

RA

RA RA

RBRB

A11/2 LT1495

5V

A21/2 LT1495

V IRR

R

FOR R kR kVI

VA

O LB

ASENSE

A

B

O

L

=

==

=

110

1

12V

–

+1/2 LT1495

10k

–

+1/2 LT1495

200k

100k

10nF

100k

100nF

100nF

100nF

215k215k215k

15nF15nF

30nF

eIN

1/2 LT1495

200k

80.6k

10nF

100k

100nF169k169k169k

15nF15nF

30nF

LT1495/96 •TA03

VS = 5V, 0VIS = 2µA + eIN/150kZEROS AT 50Hz AND 60Hz

OUTPUT

10k

1kHz. As with all RC filters, the filter characteristics aredetermined by the absolute values of the resistors andcapacitors, so resistors should have a 1% tolerance orbetter and capacitors a 5% tolerance or better.

Battery-Current Monitorwith Over-the-Top Operation

The bidirectional current sensor shown in Figure 98 takesadvantage of the extended common mode range of theLT1495 to sense currents into and out of a 12V batterywhile operating from a 5V supply. During the charge cycle,op amp A1 controls the current in Q1 so that the voltagedrop across RA is equal to IL • RSENSE. This voltage is thenamplified at the charge output by the ratio of RA to RB.During this cycle, amplifier A2 sees a negative offset,which keeps Q2 off and the discharge output low. Duringthe discharge cycle, A2 and Q2 are active and operation issimilar to that during the charge cycle.

Conclusion

The LT1495/LT1496 extends Linear Technology’s rangeof rail-to-rail amplifier solutions to a truly micropowerlevel. The combination of extremely low current andprecision specifications provides designers with a versa-tile solution for battery-operated devices and other lowpower systems.

FREQUENCY (Hz)

–60

–40

–20

–50

–30

0

–10

GAIN

(dB)

1000

1495_07.eps

0 10 100

Figure 96. 6th Order 10Hz Elliptic Lowpass Filter

Figure 98. Battery-Current MonitorFigure 97. Frequency Response of Figure96’s 6th Order Elliptic Lowpass Filter

6th Order, 10Hz Elliptic Lowpass Filter

Figure 96 shows a 6th order, 10Hz elliptic lowpass filterwith zeros at 50Hz and 60Hz. Supply current is primarilydetermined by the DC load on the amplifiers and isapproximately 2µA + VO/150k (9µA for VO = 1V). Theoverall frequency response is shown in Figure 97. Thenotch depth of the zeros at 50Hz and 60Hz is nearly 60dBand the stopband attenuation is greater than 40dB out to

Application Note 87

AN87-64

SEND CAMERA POWER AND VIDEOON THE SAME COAX CABLEby Frank Cox

Because remotely located video surveillance cameras donot always have a ready source of power, it is convenientto run both the power and the video signal through a singlecoax cable. One way to do this is to use an inductor topresent a high impedance to the video and a low imped-ance to the DC. The difficulty with this method is that thefrequency spectrum of a monochrome video signal ex-tends down to at least 30Hz. The composite color videospectrum goes even lower, with components at 15Hz.This implies a rather large inductor. For example, a 0.4Hinductor has an impedance of only 75Ω at 30Hz, which isabout the minimum necessary. Large inductors have alarge series resistance that wastes power. More impor-tantly, large inductors can have a significant amount ofparasitic capacitance and stand a good chance of goinginto self resonance below the 4MHz video bandwidth and

Figure 99. Circuit Transmits Video and 12V Power on the Same Coax Cable

thus corrupting the signal. The circuit shown in Figure 99takes a different approach to the problem by using allactive components.

The circuitry at the monitor end of the coax cable suppliesall the power to the system. U1, an LT1206 currentfeedback amplifier, forms a gyrator or synthetic inductor.The gyrator isolates the low impedance power supply fromthe cable by maintaining a reasonably high impedanceover the video bandwidth while, at the same time, contrib-uting only 0.1Ω of series resistance. This op amp needs tohave enough bandwidth for video and sufficient outputdrive to supply 120mA to the camera. The selected part hasa guaranteed output current of 250mA and a 3dB band-width of 60MHz, making it a good fit. Because the videoneeds to be capacitively coupled, there is no need for splitsupplies; hence a single 24V supply is used. The 24Vsupply also gives some headroom for the voltage drop inlong cable runs.

–

+

–

+

–

+

++

+

+

+

CAMERAVIDEOOUT

12VR110k

R210k

C120µF

U4LT1363

C24.7µFTANT

C31000µF

C41000µF

C61000µF

562Ω

R42k

R510k

C50.1µF

Q1ZETEX ZTX749

OUT INU3

LT1086CT-12

R31k

U2LT1363

C101000µF

0.1µF

R14562Ω

R15280Ω

R16280Ω

C121000µF

C1151pF

R1775Ω

C13100µF

R1210k

R1310k

24V 24V

TOMONITOR

3 7

6

42

3 7

6

42

U1LT1206CT

R11, 100Ω

R100.1Ω

C920µF FILM

1

2 4

5

NC6

3

24V

4.7µFTANT R7

2.32k

0.1µF

4.7µF

R9510k

R811.5k

R675Ω

100' RG58/U

C71000µF

24V

DI_VID_01.eps

+

+

+

+

+

+

20V DC

7

Application Note 87

AN87-65

Figure 100. LT1639 Battery Current Monitor—an Over-The-Top Application

The camera end has an LT1086 fixed 12V regulator (U3) tosupply 12V to a black and white CCD video camera. U4, anLT1363 op amp, supplies the drive for Q1, a fast, highcurrent transistor. Q1, in turn, modulates the video on the20V DC. The collector of Q1 is the input to the 12Vregulator. This point is AC ground because it is wellbypassed as required by U3. U1 is set up to deliver 20V tothe cable. Because the 12V regulator in the camera endneeds 1.5V of dropout voltage, the balance of 6.5V can bedropped in the series resistance of the cable. The output of

the LT1206 is set to 20V to give headroom between thesupply and the video.

U2, another LT1363 video-speed op amp, receives videofrom the cable, supplies some frequency equalization anddrives the cable to the monitor. Equalization is used tocompensate for high frequency roll off in the camera cable.The components shown (R16, C11) gave acceptable mono-chrome video with 100 feet of RG58/U cable.

200µA, 1.2MHz RAIL-TO-RAIL OP AMPS HAVEOVER-THE-TOP INPUTSby Raj Ramchandani

Introduction

The LT1638 is Linear Technology’s latest general-pur-pose, low power, dual rail-to-rail operational amplifier; theLT1639 is a quad version. The circuit topology of theLT1638 is based on Linear Technology’s popular LT1490/

–

+

+

1/4LT1639

A

+

–1/4

LT1639C

RA2k

RS0.2Ω

QA2N3904

CHARGERVOLTAGE

VBATTERY = 12V

VSUPPLY = 5V, 0V

LOGIC

RA'2k

–

+1/4

LT1639B

–

+1/4

LT1639D

RB2k

RB'2k

90.9k

RL

RG10k

10k

S1S1 = OPEN, GAIN = 1S1 = CLOSED, GAIN = 10

LOGIC HIGH (5V) = CHARGINGLOGIC LOW (0V) = DISCHARGING

NOTE: RA = RB

QB2N3904

VOUT

VOUT

RS RG/RA GAIN

VOUT

GAIN

( )( ) ( )IBATTERY = = AMPS

1N4001

LT1491 op amps, with substantial improvements in speed.The LT1638 is five times faster than the LT1490.

Battery Current Monitor

The battery-current monitor shown in Figure 100 demon-strates the LT1639’s ability to operate with its inputsabove the positive rail. In this application, a conventionalamplifier would be limited to a battery voltage between 5Vand ground, but the LT1639 can handle battery voltages

Application Note 87

AN87-66

as high as 44V. The LT1639 can be shut down by removingVCC. With VCC removed, the input leakage is less then0.1nA. No damage to the LT1639 will result from insertingthe 12V battery backward.

When the battery is charging, amplifier B senses thevoltage drop across RS. The output of amplifier B causesQB to drain sufficient current through RB to balance theinputs of amplifier B. Likewise, amplifier A and QA form aclosed loop when the battery is discharging. The current

through QA or QB is proportional to the current in RS. Thiscurrent flows into RG and is converted into a voltage.Amplifier D buffers and amplifies the voltage across RG.Amplifier C compares the outputs of amplifier A andamplifier B to determine the polarity of current through RS.The scale factor for VOUT with S1 open is 1V/A. With S1closed the scale factor is 1V/100mA and currents as lowas 5mA can be measured.

LOW DISTORTION RAIL-TO-RAIL OP AMPS HAVE0.003% THD WITH 100kHz SIGNALby Danh Tran

Introduction

The LT1630/LT1632 duals and LT1631/LT1633 quads arethe newest members of Linear Technology’s family of rail-to-rail op amps, which provide the best combination of ACperformance and DC precision over the widest range ofsupply voltages. The LT1630/LT1631 deliver a 30MHzgain-bandwidth product, a 10V/µs slew rate and 6nV/√Hzinput-voltage noise. Optimized for higher speedapplications, the LT1632/LT1633 have a 45MHz gain-bandwidth product, a 45V/µs slew rate and 12nV/√Hzinput voltage noise.

Applications

The ability to accommodate any input and output signalsthat fall within the device’ s supplies makes these amplifi-ers very easy to use. They exhibit a very good transient

response and can drive low impedance loads, whichmakes them suitable for high performance applications.The following applications demonstrate the versatility ofthese amplifiers.

400kHz 4th Order Butterworth Filter for 3V Operation

The circuit shown in Figure 101 makes use of the lowvoltage operation and the wide bandwidth of the LT1630 tocreate a 400kHz 4th order lowpass filter with a 3V supply.The amplifiers are configured in the inverting mode for thelowest distortion and the output can swing rail-to-rail forthe maximum dynamic range. Figure 102 displays thefrequency response of the filter. Stopband attenuation isgreater than 85dB at 10MHz. With a 2.25VP-P, 100kHzinput signal, the filter has harmonic distortion products ofless than –87dBc.

FREQUENCY (Hz)0.1k

GAIN

(dB)

1k 10k 100k 1M 10M

1630/31 TA02

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

VS = 3V, 0VVIN = 2.25VP-P

1/2 LT1630

2.32k

VIN

VS/2

VOUT

1630/31 TA01

220pF

2.32k 6.65k

1/2 LT1630

2.74k 22pF

470pF

5.62k2.74k

47pF3V–

+–

+

Figure 101. Single-Supply, 400kHz, 4th Order Butterworth FilterFigure 102. Frequency Response of Filterin Figure 101

Application Note 87

AN87-67

Figure 103. Single-Supply Instrumentation Amplifier

Figure 104. Frequency Response ofFigure 103’s Instrumentation Amplifier

40dB Gain, 550kHz Instrumentation Amplifier

An instrumentation amplifier with a rail-to-rail outputswing, operating from a 3V supply, can be constructedwith the LT1632, as shown in Figure 103. The amplifier hasa nominal gain of 100, which can be adjusted with resistorR5. The DC output level is equal to the input voltage (VIN)between the two inputs multiplied by the gain of 100.

–

+–

+

R1 20k

R2 2k

R3 2k

R4 20k

1/2LT1632

1/2LT1632

R5 450Ω

OUT

+IN

–IN

3V

VCML = + 0.1VVOUT(DC)

AV

R2

R5

1.0

1.1( (( (

VCMH = + 2.85VVOUT(DC)

AV

R2

R5

1.0

1.1( (UPPER LIMIT COMMON MODE INPUT VOLTAGE

LOWER LIMIT COMMON MODE INPUT VOLTAGE

AV = R4

R3

R2

R1R3 + R2

R51 + +

BW = 550kHz

= 100

VOUT(DC) = (+IN – (–IN))DC × GAIN

±1.5V

FREQUENCY (Hz)1k

VOLT

AGE

GAIN

(dB)

50

40

30

20

10

0

–10

–20

–30

–40

–50

–60

–7010k 100k 1M

1562 TA09

100 10M

VS = 3VAV = 100

DIFFERENTIALINPUT

COMMON MODEINPUT

Common mode range can be calculated by the equationsshown with Figure 103. For example, the common moderange is from 0.15V to 2.65V if the output voltage is at one-half of the 3V supply. The common mode rejection isgreater than 110dB at 100Hz when trimmed with resistorR1. Figure 103 shows the amplifier’s cutoff frequency of550kHz.

THE LT1167: PRECISION, LOW COST, LOW POWERINSTRUMENTATION AMPLIFIER REQUIRES A SINGLEGAIN-SET RESISTORby Alexander Strong

Introduction

The LT1167 is the next-generation instrumentation ampli-fier designed to replace the previous generation of mono-lithic instrumentation amps, as well as discrete, multipleop amp solutions. Instrumentation amplifiers differ fromoperational amplifiers in that they can amplify input sig-nals that are not ground referenced. The output of aninstrumentation amplifier is referenced to an externalvoltage that is independent of the input. Conversely, theoutput voltage of an op amp, due to the nature of itsfeedback, is referenced to the differential and commonmode input voltage.

Applications

Single-Supply Pressure Monitor

The LT1167’s low supply current, low supply voltageoperation and low input bias current (350pA max) allow itto fit nicely into battery powered applications. Low overallpower dissipation necessitates using higher impedancebridges. Figure 105 shows the LT1167 connected to a 3kΩbridge’s differential output. The picoampere input biascurrents will still keep the error caused by offset current toa negligible level. The LT1112 level shifts the LT1167’sreference pin and the ADC’s analog ground pins aboveground. This is necessary in single-supply applicationsbecause the output cannot swing to ground. The LT1167’sand LT1112’s combined power dissipation is still less thanthe bridge’s. This circuit’s total supply current is just 3mA.

Application Note 87

AN87-68

ADC Signal Conditioning

The LT1167 is shown in Figure 106 changing a differentialsignal into a single-ended signal. The single-ended signalis then filtered with a passive 1st order RC lowpass filterand applied to the LTC1400 12-bit analog-to-digital con-verter (ADC). The LT1167’s output stage can easily drivethe ADC’s small nominal input capacitance, preservingsignal integrity. Figure 107 shows two FFTs of the ampli-fier/ADC’s output. Figures 107a and 107b show the resultsof operating the LT1167 at unity gain and a gain of ten,respectively. This results in a typical SINAD of 70.6dB.

Figure 105. Single-Supply Pressure Monitor

Figure 106. The LT1167 Converting Differential Signals to Single-Ended Signals; the LT1167 is Ideal for Driving the LTC1400

–

+

1167_02.eps

3kG = 100499Ω

LT1167

–

+

1/2 LT1112

38

12

4

5

–IN

+IN

REF

LTC1286

DIGITALDATASERIALOUTPUT

7

20k

10k

20k

6

3k

5V

3k

3k

–

+

0.1µF

0.1µF

3

1

8

2R1

CX

VREF

AIN

VCC

GND VSS

DOUT

CLK

CONV

2 4

7

5LT1167 LTC1400

1k

–5V

AV = 1 R1 = ∞ CX = 0.047µFAV = 10 R1 = 5.6kΩ CX = 0.033µF

–5V

+5V 0.1µF

10µF

3

4

10µF

0.1µF

0.1µF 10µF

5V

1

8

5

6 SERIALINTERFACE7

1167 AA .eps

+

++

FREQUENCY (kHz)0

AMPL

ITUD

E (d

B)

–100

–80

–60

75 125

1167 BB .eps

–12025 50 100

–40

–20

0

150 175 200

SUPPLY VOLTAGE = ±5VfIN = 3kHzfSAMPLE = 400kspsSINAD = 70.6dBLT1167 GAIN = 1

FREQUENCY (kHz)0

AMPL

ITUD

E (d

B)

–100

–80

–60

75 125

1167 CC .eps

–12025 50 100

–40

–20

0

150 175 200

SUPPLY VOLTAGE = ±5VfIN = 5.5kHzfSAMPLE = 400kspsSINAD = 70.6dBLT1167 GAIN = 10

Figure 107. Operating at a Gain of One (A) orTen (B), Figure 106’s Circuit Achieves12-Bit Operation with a SINAD of 70.6dB

(A)

(B)

Application Note 87

AN87-69

Figure 108. Precision Current Source

–

–+

+

1167_04.eps

RG

LT1167

–

+

38

12

4

5

IL

VIN+

VIN–

7

+VS

–VS

6

R1VX

LT1464

LOAD

IVR

V V G

R

G kR

LX IN IN

G

= =( ) − ( )[ ]

= +

+ −

1 149 4 1. Ω

Current Source

Figure 108 shows a simple, accurate, low power program-mable current source. The differential voltage across pins2 and 3 is mirrored across RG. The voltage across RG isamplified and applied across R1, defining the outputcurrent. The 50µA bias current flowing from pin 5 isbuffered by the LT1464 JFET operational amplifier, whichincreases the resolution of the current source to 3pA.

Nerve-Impulse Amplifier

The LT1167’s low current noise makes it ideal for ECGmonitors that have MΩ source impedances. Demonstrat-ing the LT1167’s ability to amplify low level signals, thecircuit in Figure 109 takes advantage of the amplifier’shigh gain and low noise operation. This circuit amplifiesthe low level nerve impulse signals received from a patientat pins 2 and 3 of the LT1167. RG and the parallelcombination of R3 and R4 set a gain of ten. The potentialon LT1112’s pin 1 creates a ground for the common modesignal. The LT1167’s high CMRR of 110db ensures thatthe desired differential signal is amplified and unwantedcommon mode signals are attenuated. Since the DCportion of the signal is not important, R6 and C2 make upa 0.3Hz highpass filter. The AC signal at LT1112’s pin 5 isamplified by a gain of 101 set by R7/R8 + 1. The parallelcombination of C3 and R7 forms a lowpass filter thatdecreases this gain at frequencies above 1kHz.

Figure 109. Medical ECG Monitor

–

+

–

+

+

+

+

–

PATIENT/CIRCUITPROTECTION/ISOLATION

+INPUT

PATIENTGROUND

–INPUT

1167_05.eps

LT1167G = 10

38

1

1

24

–3V

3V

3V

–3V

5

2

3

7

6

RG, 6k

R3, 30k

R4, 30k

R1

1/2 LT1112

5

64

8

7 OUTPUT1V/mV

AV = 101POLE AT 1kHz

C1

R7, 10k

R2, 1MR61M

1/2 LT1112 C3, 15nF

0.3Hz HIGHPASS

R8100

C2, 0.47µF

The ability to operate at ±3V on 0.9mA of supply currentmakes the LT1167 ideal for battery-powered applications.Total supply current for this application is 1.7mA. Propersafeguards, such as isolation, must be added to this circuitto protect the patient from possible harm.

Conclusion

The LT1167 instrumentation amplifier delivers the bestprecision, lowest noise, highest fault tolerance, plus theease of use provided by single-resistor gain setting. TheLT1167 is offered in 8-pin PDIP and SO packages. The SOuses significantly less board space than discrete designs.

Application Note 87

AN87-70

LEVEL SHIFT ALLOWS CFA VIDEO AMPLIFIER TOSWING TO GROUND ON A SINGLE SUPPLYby Frank Cox

A current feedback (CFA) video amplifier can be made torun off a single supply and still amplify ground-referencedvideo with the addition of a simple and inexpensive levelshifter. The circuit in Figure 110 is an amplifier and cabledriver for a current output video DAC. The video can becomposite or component but it must have sync. The singlepositive supply is 12V but could be as low as 6V for theLT1227.

The output of the LT1227 CFA used here can swing towithin 2.5V of the negative supply with a 150Ω load overthe commercial temperature range of 0°C to 70°C. Fivediodes in the feedback loop are used, in conjunction withC5, to level shift the output to ground. The video from theoutput of the LT1227 charges C5 and the voltage across itallows the output to swing to ground or even slightlynegative. However, the level of this negative swing willdepend on the video signal and so will be unpredictable.When the scene is black, there must be sync on the videofor C5 to remain charged. A zero-level component videosignal with no sync will not work with this circuit. The CFAoutput will try to go to zero, or as low as it can, and the

Figure 110. Amplifier and Cable Driver for Current-Output Video DAC

diodes will turn off. The load will be disconnected from theCFA output and connected through the feedback resistorto the network of R6 and R7. This causes about 150mVDCto appear at the output, instead of the 0V that should bethere.

The ground-referenced video signal at the input needs tobe level shifted into the input common mode range of theLT1227 (3V above negative supply). R4 and R5 shift theinput signal to 3V. In the process, the input video isattenuated by a factor of 2.5. For correct gain, no offset andwith a zero source impedance, R4 would be 1.5k. Tocompensate for the presence of R3, R4 is made 1.5kminus R3, or 1.46k. The trade off is a gain error of about1.5%. If R4 is left 1.5k, the gain is correct, but there is anoffset error of 75mV. R6, R7 and R8 set the gain and theoutput offset of the amplifier. A noninverting gain of five istaken to compensate for the attenuation in the input levelshifter and the cable termination.

The voltage offset on the output of this circuit is a rathersensitive function of the value of the input resistors. Forinstance, an error of 1% in the value of R6 will cause anoffset of 30mV (1% of 3V) on the output. This is in additionto the offset error introduced by the op amp. Precisionresistor networks are available (BI Technologies,

–

+LT1227

5× 1N4148

R9 75Ω LOAD

R1075Ω

C3 47µF

C40.1µF

C5 4.7µFFILM

R8 1.5kR71.5k

R6499Ω

C24.7µF

C110µF

FILMR51k

*R41.46k

*R338.1Ω

*R277.37Ω

R1 75Ω

SOURCE

5V12V

75Ω VIDEO SOURCE USED FOR TESTING

*RESISTORS ARE A COMBINATION OF TWO 1% VALUES, R2 IS A SERIES COMBINATION OF 75Ω AND 2.37ΩR3 IS A PARALLEL COMBINATION OF 75Ω AND 77.3ΩR4 IS A SERIES COMBINATION OF 1.3k + 160Ω = 1.46kALL RESISTORS ARE 1% METAL FILM

B

A

+

+

Application Note 87

AN87-71

714-447-2345) with matching specifications of 0.1% orbetter. These could be used for the level shifting resistors,although this would make adjustments like the one madeto R4 difficult.

Fortunately, there is always synchronization informationassociated with video. A simple circuit can be used to DCrestore voltage offsets produced by resistor mismatch, opamp offset or DC errors in the input video. Figure 111shows the additional circuitry needed to perform this

–

+

5V

0V

VIDEO

HOLD

SAMPLE

CLAMP PULSE

B

A

5V12V

1/2 LTC201A

13

2, 15

4, 51, 16

3, 14

R110k

R210k

R3 10k

5V

R41.40k

R550k

R620k

C4 0.1µF

1/2 LT1632

C2 6800pFFILM

C30.1µF

12V

R7 10k

C110µFFILM

TO FIGURE 110,POINT

TO FIGURE 110,POINT

DC RESTORE LEVEL(ADJUST FOR DESIRED BLANKING LEVEL)

Figure 111. DC Restore Subcircuit

function. The LTC201A analog switch and C1 store theoffset error during blanking. The clamp pulse should be3µs or wider and should occur during blanking. It canconveniently be made by delaying the sync pulse with oneshots. If the sync tip is clamped, the clamp pulse muststart after and end before the sync pulse or offset errorswill be introduced. The integrator made with the LT1632adjusts the voltage at point B (see Figure 110) to correctthe offset.

LT1468: AN OPERATIONAL AMPLIFIER FOR FAST,16-BIT SYSTEMSby George Feliz

Introduction

The LT1468 is a single operational amplifier that has beenoptimized for accuracy and speed in 16-bit systems.Operating from ±15V supplies, the LT1468 in a gain of–1 configuration will settle in 900ns to 150µV for a 10Vstep. The LT1468 also features the excellent DCspecifications required for 16-bit designs. Input offsetvoltage is 75µV max, input bias current is 10nA maximumfor the inverting input and 40nA maximum for the nonin-verting input and DC gain is 1V/µV minimum.

16-Bit DAC Current-to-Voltage Converterwith 1.7µs Settling Time

The key AC specification of the circuit of Figure 112 issettling time as it limits the DAC update rate. The settlingtime measurement is an exceptionally difficult problemthat has been ably addressed by Jim Williams, in LinearTechnology Application Note 74. Minimizing settling timeis limited by the need to null the DAC output capacitance,which varies from 70pF to 115pF, depending on code. Thiscapacitance at the amplifier input combines with thefeedback resistor to form a zero in the closed-loop fre-quency response in the vicinity of 200kHz–400kHz. With-out a feedback capacitor, the circuit will oscillate. Thechoice of 20pF stabilizes the circuit by adding a pole at

Application Note 87

AN87-72

1.3MHz to limit the frequency peaking and is chosen tooptimize settling time. The settling time to 16-bit accuracyis theoretically bounded by 11.1 time constants set by the6kΩ and 20pF. Figure 112’s circuit settles in 1.7µs to150µV for a 10V step. This compares favorably with the1.33µs theoretical limit and is the best result obtainablewith a wide variety of LTC and competitive amplifiers. Thisexcellent settling requires the amplifier to be free ofthermal tails in its settling behavior.

The LTC1597 current output DAC is specified with a 10Vreference input. The LSB is 25.4nA, which becomes 153µVafter conversion by the LT1468, and the full-scale outputis 1.67mA, which corresponds to 10V at the amplifieroutput. The zero-scale offset contribution of the LT1468 isthe input offset voltage and the inverting input currentflowing through the 6k feedback resistor. This worst-casetotal of 135µV is less than one LSB. At full-scale there is aninsignificant additional 10µV of error due to the 1V/µVminimum gain of the amplifier. The low input offset of theamplifier ensures negligible degradation of the DAC’soutstanding linearity specifications.

With its low 5nV/√Hz input voltage noise and 0.6pA/√Hzinput current noise, the LT1468 contributes only an addi-tional 23% to the DAC output noise voltage. As with anyprecision application, and particularly with wide band-width amplifiers, the noise bandwidth should be mini-mized with an external filter to maximize resolution.

ADC Buffer

The important amplifier specifications for an analog-to-digital converter buffer application (Figure 113) are lownoise and low distortion. The LTC1604 16-bit ADC signal-

to-noise ratio (SNR) of 90dB implies 56µVRMS noise at theinput. The noise for the amplifier, 100Ω/3000pF filter anda high value 10kΩ source is 15µVRMS, which degrades theSNR by only 0.3dB. The LTC1604 total harmonic distor-tion (THD) is a low –94dB at 100kHz. The buffer/filtercombination alone has 2nd and 3rd harmonic distortionbetter than –100dB for a 5VP-P, 100kHz input, so it doesnot degrade the AC performance of the ADC.

The buffer also drives the ADC from a low source imped-ance. Without a buffer, the LTC1604 acquisition timeincreases with increasing source resistance above 1k andtherefore the maximum sampling rate must be reduced.With the low noise, low distortion LT1468 buffer, the ADCcan be driven at maximum speed from higher sourceresistances without sacrificing AC performance.

The DC requirements for the ADC buffer are relativelymodest. The input offset voltage, CMRR (96dB minimum)and noninverting input bias current through the sourceresistance, RS, affect the DC accuracy, but these errors arean insignificant fraction of the ADC offset and full-scaleerrors.

Figure 112. 16-Bit DAC I/V Converter with 1.7µs Settling Time

–

+LTC1597

DACINPUTS

10V

VREF6k

20pF

DAC COUT70pF–115pF

LT1468

–15V

15V

2k

50pF

OPTIONAL NOISE FILTER

VOUT

16

1LSB = 25.4nAFULL SCALE = 1.67mA 10V

153µV

Figure 113. ADC Buffer

–

+VINRS

LT1468

15V

–15V

100Ω

3000pF

530kHz NOISE FILTER

LTC160416

ADCOUTPUTS

5V

–5V

Application Note 87

AN87-73

Telecommunications Circuits

HOW TO RING A PHONE WITH A QUAD OP AMPby Dale Eagar

Requirements

When your telephone rings, exactly what is the phonecompany doing? This question comes up frequently, as itseems everyone is becoming a telephone company.Deregulation opens many new opportunities, but if youwant to be the phone company you must ring bells. Thevoltage requirement for ringing a telephone bell is a87VRMS 20Hz sine wave superimposed on –48VDC.

An Open-Architecture Ring-Tone Generator

What the module makers offer is a solution to a problemthat, by its nature, calls for unusual design techniques.What we offer here is a design that you can own, tailor toyour specific needs, lay out on your circuit board and puton your bill of materials. Finally, you will be in control of theblack magic (and high voltages) of ring-tone generation.

Figure 115. Op Amp Intentionally OscillatesFigure 114. The Switching Power Supply

DI_RING_01.eps

1

60V3A60V

200T #3420T #26

70T #34

0.47µF

–180V

10k

2k

180V

5

4

2

1

4N28

60VMUR160

T1

MUR160

0.47µF

7

2

8

1

4

6 3

5220µF

4

5

2

3

10k 0.1µF

330Ω10k

RING

5V TO 30V

0.01

= PRIMARY GROUND = SECONDARY GROUND

GND

SW

LT1070

VIN

FB VC

2N3904

+

–

+

F

F

F

NOTE: REPRESENTS A FLOATING GROUND, NOT EQUAL TO OR

DI_RING_02.eps

R1 R2

R3

V–

V+

V–

V+

C1

LT1491

1FREQ

R1 = R2

FREQ =

DUTY FACTOR = 50%

23

1 R3 C1

Not Your Standard Bench Supply

Ring-tone generation requires two high voltages, 60VDCand –180VDC. Figure 114 details the switching powersupply that delivers the volts needed to run the ring-tonecircuit. This switcher can be powered from any voltagefrom 5V to 30V, and is shut down when not in use,conserving power. The transformer and optocouplingyield a fully floating output. Faraday shields in the trans-former eliminate most switcher noise, preventing mysterysystem noise problems later. Table 6 is the build diagramof the transformer used in the switching power supply.

Quad Op Amp Rings Phones

When a phone rings, it rings with a cadence, a sequenceof rings and pauses. The standard cadence is one secondringing followed by two seconds of silence. We use thefirst 1/4 of the LT1491 as a cadence oscillator (developedin Figures 115 and 116) whose output is at VCC for onesecond and then at VEE for two seconds (see Figure 120).

Application Note 87

AN87-74

Figure 116. Duty Factor is Skewed Figure 117. Gated 20Hz Oscillator

–

+F

DI_RING_03.eps

R147k

R210k

R31.6M

V–

V+

1 SEC

V–

V+

C11µF

LT1491R433k

2 SEC

FREQ = Hz

DUTY FACTOR = 33.3%

OUTPUT STARTS HIGH ON POWERUP.

13

This sequence repeats every three seconds, producing theall-too-familiar pattern.

The actual ringing of the bell is performed by a 20Hz ACsine wave signal at a level of 87VRMS, superimposed on–48VDC. The 20Hz signal is implemented with the secondamplifier in the LT1491 (Figure 117) which acts as a gated20Hz oscillator. Connecting the circuit shown in Figure116 to the circuit shown in Figure 117 and adding threeresistors yields the sequencer as shown in Figure 118. Thewaveform, labled “Square Out,” is the fourth trace inFigure 120. This waveform is the output of Figure 121.

–

+F

F

100K 150K

500KHIGH = OSCILLATE

V–

V+

0.1µF

LT1491

DI_RING_04.eps

V+

V+

V–

V–

GATE

OUT

DUTY FACTOR = 50%

120

S

Figure 118. Sequencer: Cadenced 20Hz Oscillator

–

+

–

+

F

F

DI_RING_05.eps

100K 150k

300k10k

500k

20Hz

1.6M

47k 33k

620k

300k

V–V–

0.1µF

CADENCE

CR1 1N4148

1µF

LT1491SQUAREWAVEOUT

LT1491

Square Wave Plus Filter Equals Sine Wave

Thevenin will tell you that the output impedance of thesequencer shown in Figure 118 is 120kΩ. This impedancecan be recycled and used as the input resistance of the filterthat follows. The filter detailed in Figure 119 uses theThevenin resistor on its input, yielding a slick, compactdesign while distorting the nice waveform on the nodelabeled “square out” to a half sine wave, half square wave.

Appending the filter to the waveform sequencer createsthe waveform engine detailed in Figure 119. The output ofthis waveform engine is shown in the bottom trace in

Application Note 87

AN87-75

Figure 120. This waveform engine is shown in block formin Figure 122.

Mapping Out the Ring-Tone Generator in Block Form

We now build a system-level block diagram of our ringtone generator. We start with the waveform engine ofFigure 122, add a couple of 15V regulators and a DC offset(47k resistor), then apply some voltage gain with a highvoltage amplifier to ring the bell. This hypothetical sys-tem-level block diagram is detailed in Figure 123. Figure124 shows the output waveform of the ring tone genera-tor; the sequenced ringing starts when the high voltagesupply (Figure 114) is turned on, and continues as long asthe power supply is enabled.

What’s Wrong with This Picture (Figure 123)

Careful scrutiny of Figure 123 reveals an inconsistency:even though the three fourths of the LT1491 in thewaveform engine block are powered by ±15V, the finalamplifier is shown as powered from 60V and –180V; thisposes two problems: first the LT1491 is a quad op ampand all four sections have to share the same supply pins,and second, the LT1491 will not meet specification whenpowered from 60V and –180V. This is because 240V isgreater than the absolute maximum rating of 44V (V+ toV-). Linear Technology products are noted for theirrobustness and conservative “specmanship,” but this isgoing too far. It is time to apply some tricks of the trade.

–

+

F

DI_RING_06.eps

C40.047µF

R1110k

RTHEVEVIN 120k

C30.068µF

LT1491 SINEOUT

OUTPUT IMPEDANCE OF

FIGURE 118

DI_RING_07.eps

V+

V–

V+

V–

V+

V–

V+

V–

SINEOUT

25

25

SQUAREOUT

20Hz

CADENCE

25

25

1 SEC 2 SEC

NEXTRING

ON

OFFPOWER

slairetaM

2 seroC8F3–51–02DFE

1 nibboBP8–51–02DFE

2 pilC–02DFE

2 paGrofepaTxemoN"700.0

1gnidniW

43#T0021niPtratS

8niPmreT

epaTralyM"200.0parW1

2gnidniW

43#T072niPtratS

7niPmreT


sdleihS

dleihSyadaraFepaTlioFT13niPtcennoC


dleihSyadaraFepaTlioFT16niPtcennoC


3gnidniW

62#T024niPtratS

5niPmreT

epaTralyMhtiwhsiniF

Figure 119. Filter to Remove the Sharp Edges

Figure 120. Timing of Waveform Engine

Table 6. Ring-Tone High Voltage Transformer Build Diagram

Application Note 87

AN87-76

Building High Voltage Amplifiers

Setting aside the waveform engine for a moment, we willdevelop a high voltage amplifier. We start with the ±15Vregulators shown in Figure 123; these are not your run-of-the-mill regulators, these are high differential voltageregulators, constructed as shown in Figure 125. Usingthese regulators and the final section of the LT1491 quadop amp, we can build a high voltage amplifier. We will usethe ±15V regulators as the “output transistors” of our

–

+

–

+–

+

F

F

F

F

DI_RING_08.eps

100K 10k

620k10k

16k1.6M

47k 33k

620k

300k 150k

0.068µF

V–

0.47µF

1N4148

1µF

LT1491

0.47µF

LT1491GATEDSINE WAVEOUTPUT

LT1491

amplifier, because they can both take the voltage anddissipate the power required to provide the ring voltageand current. By connecting the op amp to the regulators,one gets a free cascode high voltage amplifier. This isbecause the supply current for the op amp is also theregulator current. The trouble one encounters when sodoing is that the input common mode range of the op ampis not wide enough to accommodate the full output voltagerange of the composite amplifier. This would not be aproblem if the amplifier were used as a unity-gain nonin-verting amplifier, but in this system we need gain to getfrom our 12VP-P to 87VRMS.

Figure 121. Waveform synthesizer

Figure 122. Waveform Engine

F

DI_RING_09.eps

V+

V–

SINEOUT

SINEOUTWAVEFORM

ENGINEREF

–15V

15V

6V

–6V

VREF

20Hz

F

–

+F

F

FF

DI_RING_10.eps

47k

10k

COM

15V REG

V+

V–

OUT IN

SINEOUTWAVEFORM

ENGINEREF

COM

–15V REG–15V

15V

OUT IN

150k

60V

–180V

0.01µF

RL

HV

Figure 123. High Voltage Amplifier

Figure 124. System Output

Figure 125. High Differential Voltage Regulators

DI_RING_11.eps

42V

–138V

–48VSINEOUT

3 SEC

ON

OFFPOWER

REF

DI_RING_12.eps

IRF620

IRF962015V 15V

620Ω 100k

620Ω

2N3904

100k

+VIN

–VINREF +15VREF

REF –15V

2N3906

Application Note 87

AN87-77

Moving the amplifier’s output transistor function out of theop amp and into the ±15V regulators moves the effectiveamplifier output from the op amp output to the center ofthe two supplies sourcing the ±15V regulators. This is atransformative step in the evolution of amplifiers from lowvoltage op amps to high voltage, extended supplyamplifiers.

Inverting Op Amp Circuit Gets Morphed

Let’s focus on this transformative step as it relates to thesimple inverting amplifier shown in Figure 126.* Were weto look at the amplifier in Figure 126 in some strange

Darwinistic mood, we might see that the power supplies(batteries) are in fact an integral part of our amplifier. Suchan observation would lead us to redraw the circuit to looklike Figure 127 where the center of the two batteries arebrought out of the amplifier as the negative terminal of theoutput.

Once that is done, one is free to swap the polarities of theinputs and outputs, yielding the circuit shown in Figure128. Finally we pull the two batteries back out of theamplifier to get our morphed inverting amplifier (Figure129). Isn’t assisting evolution fun?†

Figure 126. Standard Op Amp Form

Figure 127. Hide the Batteries Inside the Op Amp

Figure 128. Trade Inputs and Outputs

Figure 129. Pull the Batteries Back out of the Amplifier

–

+

X X X

X

X

DI_RING_13.eps

RFF

IN

RFB RL

V+

V–

RFBRFF

AV = –

–

–+

+

XXX X DI_RING_14.eps

RFF

IN

RFB

RL

RFBRFF

AV = –

+

+–

–

YYY Y

DI_RING_15.eps

RFF

IN

RFB

RL

RFBRFF

AV = –

–

+ Y

Y

DI_RING_16.eps

RFF

IN

RFB

RL

V+

V–

RFBRFF

AV = –

–

+

F

F

DI_RING_17.eps

150k

0.01µF

60V

C6

180V

10k

47k

R18 R21

COM

15V REG

V+

V–

OUT IN

SINEOUTWAVEFORM

ENGINEREF

COM

–15V REG

–15V

15V

OUT IN

RL

LT1491

Figure 130. Post-Evolution Block Diagram

Application Note 87

AN87-78

–

+

–

+

–

+

–

+

DI_RING_18.eps

R610k

R247k

R716k

R8620k

R41.6M

R133k

R310k

R5100k

R10620k

C40.068µF

9

10

6

7

81

5

C30.047µF

C50.01µF

R13130k

R1210k

R1547k

R1410k

R24430Ω

C747µF

LOAD UP TO TEN PHONES

R234.7k

R262k

Q52N3904

Q42N3906

Q2IRF9620

–180V

POWER AMPLIFIER

SMOOTHING FILTER

20Hz OSCILLATORCADENCE OSCILLATOR *

*LED OF OPTO 1 ILLUMINATES WHEN THE PHONE IS OFF THE HOOK

R18100

R17620

R16100k

Z1

15V 100k

R254.7k

C60.033µF

R21150

R19620

Z215V

R9300k

R1110kD1

1N4148

C20.47µF

C11µF

2

3 U1BLT1491

U1CLT1491

12

4

11

13

Q1IRF628 Q3

2N3904

60V

14U1DLT1491

U1ALT1491

OPTO1

R20100K

+

Applying the evolutionary forces just described to theblock diagram in Figure 123, we get the block diagram inFigure 130. Actually Figure 130 contains three strangers,R18, R21 and C6, parts not predicted by our evolutionarypath (unless R18 = 0Ω and R21 is open) These parts areneeded because, in our metamorphosis going from Figure127 to Figure 128, the amplifier’s internal compensationnode was moved from ground to the amplifier’s output.These parts correct the compensation for the new con-figuration.

Ring-Trip Sense

Now that we can ring the telephone, we must sense whenthe phone is picked up. This is done by sensing the DCcurrent flowing to the phone while it is ringing, using thering-trip sense circuit comprising R23–R26, C7, Q5 andOpto1 of Figure 131, the complete ring-tone generator.This circuit will ring more than ten phones at once, and is

protected on its output from shorts to ground or to eitherthe +60V or the –180V supply.

Conclusion

Here is a ring tone generator you can own, a robust circuitthat is stable into any load. If your system design requiresa circuit with different specifications, you can easily tailorthis circuit to meet your needs. Don’t hesitate to call us ifwe can help you with your design.

Editor’s Notes:

* The grounds X and Y, shown in Figures 126–129, are for illustrating theeffects of “evolution.” Ground X may be regarded as “arbitrary exemplaryground,” and ground Y as “postmetamorphic exemplary ground.” Ground Xand ground Y are not the same.

† Evolutionary theory invloves pure, random chance. What you have donehere requires purposeful thought and design.

Figure 131. Ring-Tone Generator

Application Note 87

AN87-79

A LOW DISTORTION, LOW POWER, SINGLE-PAIRHDSL DRIVER USING THE LT1497by George Feliz and Adolfo Garcia

Introduction

High speed digital subscriber line (HDSL) interfaces sup-port full-duplex data rates up to 1.544Mbps over 12,000feet using two standard 135Ω twisted-pair telephonewires. The high data rate is achieved with a combination ofencoding 2 bits per symbol using two-binary, one-quater-nary (2B1Q) modulation, and sophisticated digital signalprocessing to extract the received signal. This perfor-mance is possible only with low distortion line drivers andreceivers. In addition, the power dissipation of the trans-ceiver circuitry is critical because it may be loop-poweredfrom the central office over the twisted pair. Lower powerdissipation also increases the number of transceivers thatcan placed in a single, non-forced–air enclosure. Single-pair HDSL requires the same performance as two-pairHDSL over a single twisted pair and operates at twice thefundamental 2B1Q symbol rate. In HDSL systems that use2B1Q line coding, the signal passband necessary to carrya data rate of 1.544Mbps is 392kHz. This signal rate will beused to quantify the performance of the LT1497 in thisarticle.

Figure 132. LT1497 HDSL Driver

Low Distortion Line Driver

The circuit of Figure 132 transmits signals over a 135Ωtwisted pair through a 1:1 transformer. The LT1497 dual125mA, 50MHz current feedback amplifier was chosenfor its ability to cleanly drive heavy loads, while consum-ing a modest 7mA maximum supply current per amplifierin a thermally enhanced SO-8 package. The driveramplifiers are configured in gains of two (A1) and minusone (A2) to compensate for the attenuation inherent in theback-termination of the line and to provide differentialdrive to the transformer. The transmit power requirementfor HDSL is 13.5dBm (22.4mW) into 135Ω, correspond-ing to a 1.74VRMS signal. Since 2B1Q modulation is a 4-level pulse amplitude modulated signal, the crest factor(peak to RMS) of this signal is 1.61. Thus, a 13.5dBm,2B1Q modulated signal yields 5.6VP-P across the 135Ωload. The corresponding output signal current is ±20.7mApeak. This modest drive level increases for varying lineconditions and is tested with a standardized collection oftest loops that can have line impedances as low as 25Ω.The LT1497’s high output current and voltage swing drivethe 135Ω line at the required distortion level of –72dBc.For a data rate of 1.544Mbps and 2-bit-per-symbolencoding, the fundamental frequency of operation is392kHz.

A21/2 LT1497

–

+

–

+

–

+

560Ω

5V

A11/2 LT1497

560Ω

560Ω

560Ω

68.1Ω

135ΩVOUT

5.6VP-P

68.1Ω

1.1*VIN

–5V

*MIDCOM 671-7807(800) 643-2661

DI 1497 01.eps

Application Note 87

AN87-80

Figure 134. 2-Tone Intermodulation for Figure 132’s CircuitFigure 133. Harmonic Distortion of Figure 132’s Circuit with a400kHz Sine Wave and an Output Level of 5.6VP-P into 135Ω

The LT1497 provides such low distortion because it oper-ates at only a fraction of its output current capability andis well within its voltage swing limitations. There are otherLTC amplifiers that can achieve this performance, but atthe expense of higher power dissipation or a larger package.

Performance

The circuit of Figure 132 was evaluated for harmonicdistortion with a 400kHz sine wave and an output level of5.6VP-P into 135Ω. Figure 133 shows that the secondharmonic is –72.3dB relative to the fundamental for the135Ω load. Third harmonic distortion is not critical, becausereceived signals are heavily filtered before being digitizedby an A/D converter. Performance with a 50Ω load (tosimulate more challenging test loops) is slightly better at–75dB. The output signal was attenuated to obtain maxi-mum sensitivity of the HP4195A network analyzer used forthe measurements.

0

–50

–100

FREQUENCY (kHz)

2HD

AMPL

ITUD

E (d

Bm)

DI 1497 02

100 200 300 400 500 600 700 800 900 1000 1100

0

–50

–100

FREQUENCY (Hz)

AMPL

ITUD

E (d

Bm)

DI 1497 03

100 200 300 400 500 600

3IMD3IMD

With multicarrier applications such as discrete multitonemodulation (DMT) becoming as prevalent as single-car-rier applications, another important measure of amplifierdynamic performance is 2-tone intermodulation. Thisevaluation is a valuable tool to gain insight to amplifierlinearity when processing more than one tone at a time.

For this test, two sine waves at 300kHz and 400kHz wereused with levels set to obtain 5.6VP-P across the 135Ωload. Figure 134 shows that the third-order intermodula-tion products are well below –72dB. With a 50Ω load,performance is within 1dB–2dB of that with the 135Ωload.

Conclusion

The circuit presented provides outstanding distortion per-formance in an SO-8 package with remarkably low powerdissipation. It is ideally suited for single pair digital sub-scriber line applications, especially for remote terminals.

Comparators

ULTRALOW POWER COMPARATORSINCLUDE REFERENCEby James Herr

The LTC1440–LTC1445 family features 1µA comparatorswith adjustable hysteresis and TTL/CMOS outputs thatsink and source current and a 1µA reference that can drivea bypass capacitor of up to 0.01µF without oscillation. Theparts operate from a 2V to 11V single supply or a ±1V to±5V dual supply.

Undervoltage/ Overvoltage Detector

The LTC1442 can be easily configured as a windowdetector, as shown in Figure 135. R1, R2 and R3 form aresistive divider from VCC so that comparator A goes lowwhen VCC drops below 4.5V, and comparator B goes lowwhen VCC rises above 5.5V. A 10mV hysteresis band is setby R4 and R5 to prevent oscillations near the trip points.

Application Note 87

AN87-81

Single-Cell Lithium-Ion Battery Supply

Figure 136 shows a single cell lithium-ion battery to 5Vsupply with the low-battery warning, low-battery shut-down and reset functions provided by the LTC1444. TheLT1300 micropower step-up DC/DC converter boosts thebattery voltage to 5V using L1 and D1. Capacitors C2 andC3 provide input and output filtering.

The voltage-monitoring circuitry takes advantage of theLTC1444’s open-drain outputs and low supply voltage

Figure 135. Window Detector

operation. Comparators A and B, along with R1, R2 andR3, monitor the battery voltage. When the battery voltagedrops below 2.65V comparator A’s output pulls low togenerate a nonmaskable interrupt to the microprocessorto warn of a low-battery condition. To protect the batteryfrom over discharge, the output of comparator B is pulledhigh by R7 when the battery voltage falls below 2.45V. P-channel MOSFET Q1 and the LT1300 are turned off,dropping the quiescent current to 20µA. Q1 is needed toprevent the load circuitry from discharging the batterythrough L1 and D1.

Comparators C and D provide the reset input to themicroprocessor. As soon as the boost converter outputrises above the 4.65V threshold set by R8 and R9, com-parator C turns off and R10 starts to charge C4. After200ms, comparator D turns off and the Reset pin is pulledhigh by R12.

Conclusion

With their built-in references, low supply current require-ments and variety of configurations, Linear Technology’sLTC1440–45 family of micropower comparators is idealfor system monitoring in battery-powered devices such asPDAs, laptop and palmtop computers and hand-heldinstruments.

OVERVOLTAGE(5.5V)

8OUT B

V+

V–

2

LTC1442

IN+ A3

IN– B

UNDERVOLTAGE(4.5V)

POWERGOOD

4

1OUT A

7

HYST5

REF

R42.4M

5%

R3392k1%

R284.5k1%

R11.33M1%

VCC

R510k5% C1

0.01µF

6

–

+

–

+

Figure 136. Single-Cell to 5V Supply

NC

NC

3

6

7

5

4

11

10

3

14

6

2, 4

16

15

13

12

7

5

1

2

3

14

8 REF

9 V–

C2, C3: AUX TPSD107M010R0100 ORSANYO OS-CON 16SA100M

R551k5%

2

8 1

C2100µF

C3100µF

R8732k1%

R9267k

1%

PWR GND GND

VIN SW

L110µH

SUMIDACD54-100

D11N5817

ILIM

SEL

SENSE

SHDN

LT1300Q1

MMFT2955ETI

C11µF

R103.37M5%

R1151k5%

R1251k5%–

+C

1/4 LTC1444

–

+A

1/4 LTC1444

–

+D

1/4 LTC1444

C40.22µF

VCC

µP

NMI

RESET

R751k5%

R282.5k1%

R11.1M

5%

R31M1%

1 CELLLITHIUM- IONBATTERY

R42.4M5%

R6430Ω5%

LTC1444REF

–

+B

1/4 LTC1444HYST

V+

+

+

+

Application Note 87

AN87-82

A 4.5ns, 4mA, SINGLE-SUPPLY, DUAL COMPARATOROPTIMIZED FOR 3V/5V OPERATIONby Joseph G. Petrofsky

Introduction

The LT1720 is an UltraFast™ (4.5ns), low power (4mA/comparator), single-supply, dual comparator designed tooperate on a single 3V or 5V supply. These comparatorsfeature internal hysteresis, making them easy to use, evenwith slowly moving input signals. The LT1720 is fabri-cated in Linear Technology’s 6GHz complementary bipo-lar process, resulting in unprecedented speed for its lowpower consumption.

Applications

Crystal Oscillators

Figure 137 shows a simple crystal oscillator using one halfof an LT1720. The 2k–620Ω resistor pair set a bias pointat the comparator’s noninverting input. The 2k–1.8k–0.1µF path sets the inverting input node at an appropriateDC average level based on the output. The crystal’s pathprovides resonant positive feedback and stable oscillationoccurs. Although the LT1720 will give the correct logicoutput when one input is outside the common moderange, additional delays may occur when it is so operated,opening the possibility of spurious operating modes.Therefore, the DC bias voltages at the inputs are set nearthe center of the LT1720’s common mode range and the220Ω resistor attenuates the feedback to the noninvertinginput. The circuit will operate with any AT-cut crystal from1MHz to 10MHz over a 2.7V to 6V supply range.

The output duty cycle for the circuit of Figure 137 isroughly 50% but it is affected by resistor tolerances and,to a lesser extent, by comparator offsets and timings.

Timing Skews

For a number of reasons, the LT1720 is an excellent choicefor applications requiring differential timing skew. The twocomparators in a single package are inherently wellmatched, with just 300ps ∆tPD typical. Monolithic con-struction keeps the delays well matched vs supply voltage

and temperature. Crosstalk between the comparators,usually a disadvantage in monolithic duals, has minimaleffect on the LT1720 timing due to the internal hysteresis.

The circuits of Figure 138 show basic building blocks fordifferential timing skews. The 2.5k resistance interactswith the 2pF typical input capacitance to create at least±4ns delay, controlled by the potentiometer setting. Adifferential and a single-ended version are shown. In thedifferential configuration, the output edges can be smoothlyscrolled through ∆t = 0 with negligible interaction.

Fast Waveform Sampler

Figure 139 uses a diode-bridge-type switch for clean, fastwaveform sampling. The diode bridge, because of itsinherent symmetry, provides lower AC errors than othersemiconductor-based switching technologies. This cir-cuit features 20dB of gain, 10MHz full power bandwidthand 100µV/°C baseline uncertainty. Switching delay is lessthan 15ns and the minimum sampling window width forfull power response is 30ns.

The input waveform is presented to the diode bridgeswitch, the output of which feeds the LT1227 widebandamplifier. The LT1720 comparators, triggered by the samplecommand, generate phase-opposed outputs. These sig-

–

+1/2 LT1720

VCC2.7V–6V

2k

620Ω220Ω

1MHz–10MHzCRYSTAL (AT-CUT)

1.8k

2k

0.1µF

GROUNDCASE

OUTPUT

Figure 137. Simple 1MHz to 10MHz Crystal Oscillator

Application Note 87

AN87-83

nals are level shifted by the transistors, providing comple-mentary bipolar drive to switch the bridge. A skew com-pensation trim ensures bridge-drive signal simultaneitywithin 1ns. The AC balance corrects for parasitic capaci-tive bridge imbalances. A DC balance adjustment trimsbridge offset.

The trim sequence involves grounding the input via 50Ωand applying a 100kHz sample command. The DC balanceis adjusted for minimal bridge ON vs OFF variation at theoutput. The skew compensation and AC balance adjust-ments are then optimized for minimum AC disturbance inthe output. Finally, unground the input and the circuit isready for use.

Coincidence Detector

High speed comparators are especially suited for interfac-ing pulse-output transducers, such as particle detectors,to logic circuitry. The matched delays of a monolithic dualare well suited for those cases where the coincidence oftwo pulses needs to be detected. The circuit of Figure 140is a coincidence detector that uses an LT1720 and discretecomponents as a fast AND gate.

The reference level is set to 1V, an arbitrary threshold. Onlywhen both input signals exceed this will a coincidence bedetected. The Schottky diodes from the comparator out-puts to the base of the MRF-501 form the AND gate, while

the other two Schottkys provide for fast turn-off. A logicAND gate could instead be used, but would add consider-ably more delay than the 300psec contributed by thisdiscrete stage.

This circuit can detect coincident pulses as narrow as2.5ns. For narrower pulses, the output will degrade grace-fully, responding, but with narrow pulses that don’t rise allthe way to high before starting to fall. The decision delayis 4.5ns with input signals 50mV or more above thereference level. This circuit creates a TTL compatibleoutput but it can typically drive CMOS as well.

Pulse Stretcher

For detecting short pulses from a single sensor, a pulsestretcher is often required. The circuit of Figure 141 acts asa one-shot, stretching the width of an incoming pulse to aconsistent 100ns. Unlike a logic one-shot, this LT1720-based circuit requires only 100pV-s of stimulus to trigger.

The circuit works as follows: Comparator C1 functions asa threshold detector, whereas comparator C2 is configuredas a one-shot. The first comparator is prebiased with athreshold of 8mV to overcome comparator and systemoffsets and establish a low output in the absence of aninput signal. An input pulse sends the output of C1 high,which in turn latches C2’s output high. The output of C2 isfed back to the input of the first comparator, causing

–

+

–

+

LT1720

DIFFERENTIAL ±4nsRELATIVE SKEW

CIN

CIN

CIN

CIN

VREF

2.5k

2.5k

INPUT

–

+

–

+

LT1720

0ns–4ns SINGLE-ENDED DELAY

CIN

CIN

CIN

CIN

VREF

INPUT

Figure 138. Timing-Skew Generation is Easy with the LT1720

Application Note 87

AN87-84

regeneration and latching both outputs high. Timingcapacitor C now begins charging through R and, at the endof 100ns, C2 resets low. The output of C1 also goes low,

latching both outputs low. A new pulse at the input of C1can now restart the process. Timing capacitor C can beincreased without limit for longer output pulses.

–

+

5V

2.2k2.2k

INPUT±100mV FULL SCALE

1k LT1227

909Ω

100Ω

OUTPUT±1V FULL-SCALE

5V

AC BALANCE2.5k

3pF

3.6k1.5k

0.1µF

CIN

CIN

2k

2k

10pF

SKEWCOMP

2.5k

1.1k

1.1k

1.1k

1.1k

820Ω820Ω

MRF501 MRF501

LM3045

11

9 6

8

DC BALANCE

500Ω

51Ω 51Ω

10 7

680Ω

–5V

13

= 1N5711

= CA3039 DIODE ARRAY(SUBSTRATE TO –5V)

–

+1/2 LT1720

–

+1/2 LT1720

SAMPLECOMMAND

Figure 139. Fast Waveform Sampler Using the LT1720 for Timing-Skew Compensation

Application Note 87

AN87-85

This circuit has an ultimate sensitivity of better than 14mVwith 5ns–10ns input pulses. It can even detect an ava-lanche generated test pulse of just 1ns duration withsensitivity better than 100mV.1 It can detect short eventsbetter than the coincidence detector above because theone-shot is configured to catch just 100mV of upwardmovement from C1’s VOL, whereas the coincidencedetector’s 2.5ns specification is based on a full, legitimatelogic high.

5V3.9k

1k

0.1µF

51Ω

51Ω

300Ω

300Ω

5V 5V

4× 1N5711

MRF501(GROUND CASE LEAD)

OUTPUT

COINCIDENCE COMPARATORS 300ps AND GATE

1/2 LT1720

–

+

–

+1/2 LT1720

Figure 140. A 2.5ns Coincidence Detector

–

+

–

+PULSE SOURCE C1

1/2 LT1720

C21/2 LT1720

50Ω51Ω

6.8k

1N5711

24Ω

15k

R 1k

2k 2k

2k

C100pF

0.01µFOUTPUT

100ns

5V

Conclusion

The new LT1720 dual 4.5ns single-supply comparatorsfeature high speeds and low power consumption. They areversatile and easy-to-use building blocks for a wide vari-ety of system design challenges.

1 See Linear Technology Application Note 47, Appendix B. This circuit candetect the output of the pulse generator described after 40dB of attenuation.

Figure 141. A 1ns Pulse Stretcher

Application Note 87

AN87-86

Instrumentation Circuits

LTC1441-BASED MICROPOWERVOLTAGE-TO-FREQUENCY CONVERTERby Jim Williams

Figure 142 is a voltage-to-frequency converter. A 0V–5Vinput produces a 0Hz–10kHz output, with a linearity of0.02%. Gain drift is 60ppm/°C. Maximum current con-sumption is only 26µA, 100 times lower than currentlyavailable units.

To understand the circuit’s operation, assume that C1’snegative input is slightly below its positive input (C2’soutput is low). The input voltage causes a positive-goingramp at C1’s input (trace A, Figure 143). C1’s output ishigh, allowing current flow from Q1’s emitter, throughC1’s output stage to the 100pF capacitor. The 2.2µFcapacitor provides high frequency bypass, maintaininglow impedance at Q1’s emitter. Diode connected Q6 pro-

Figure 142. 0.02% V/F Converter Requires only 26µA Supply Current

Figure 143. Waveforms for the Micropower V/F Converter:Charge-Based Feedback Provides Precision Operation withExtremely Low Power Consumption.

DIVF_01.eps

+

–

10kHzTRIM200k

C11/2 LTC1441

+

–C2

1/2 LTC1441

1.2M*

15k

10M

100Hz TRIM3M TYP

100pF†

INPUT0–5V

0.01

100k

= HP5082-2810

= 1N4148

= 2N5089= 2N2222= POLYSTYRENE= 1% METAL FILM

Q1, Q2, Q8ALL OTHER

†

*

6.04k*

LM334

2.7M

0.1

50pF

+V = 6.2 → 12V

74C14

2.2µF

0.47µF

LT10041.2Vx 3

Q7Q5

Q1

Q6

Q4

Q8

Q3

Q2

GROUND ALL UNUSED 74C14 INPUTS

OUTPUT

+

A = 50mV/DIV

B = 5V/DIV

C = 5V/DIV

E = 5V/DIV

D = 1mA/DIV

HORIZ = 20µs/DIV

vides a path to ground. The voltage to which the 100pF unitcharges is a function of Q1’s emitter potential and Q6’sdrop. C1’s CMOS output, purely ohmic, contributes novoltage error. When the ramp at C1’s negative input goeshigh enough, C1’s output goes low (trace B) and theinverter switches high (trace C). This action pulls currentfrom C1’s negative input capacitor via the Q5 route (traceD). This current removal resets C1’s negative input ramp

Application Note 87

AN87-87

to a potential slightly below ground. The 50pF capacitorfurnishes AC positive feedback (C1’s positive input is traceE) ensuring that C1’s output remains negative long enoughfor a complete discharge of the 100pF capacitor. TheSchottky diode prevents C1’s input from being drivenoutside its negative common mode limit. When the 50pFunit’s feedback decays, C1 again switches high and theentire cycle repeats. The oscillation frequency dependsdirectly on the input-voltage-derived current.

Q1’s emitter voltage must be carefully controlled to getlow drift. Q3 and Q4 temperature compensate Q5 and Q6while Q2 compensates Q1’s VBE. The three LT1004s arethe actual voltage reference and the LM334 current sourceprovides 12µA bias to the stack. The current drive providesexcellent supply immunity (better than 40ppm/V) and alsoaids circuit temperature coefficient. It does this by usingthe LM334’s 0.3%/°C tempco to slightly temperature

modulate the voltage drop in the Q2–Q4 trio. Thiscorrection’s sign and magnitude directly oppose the–120ppm/°C 100pF polystyrene capacitor’s drift, aidingoverall circuit stability. Q8’s isolated drive to the CMOSinverter prevents output loading from influencing Q1’soperating point. This makes circuit accuracy independentof loading.

The Q1 emitter-follower delivers charge to the 100pFcapacitor efficiently. Both base and collector current endup in the capacitor. The 100pF capacitor, as small asaccuracy permits, draws only small transient currentsduring its charge and discharge cycles. The 50pF–100kpositive feedback combination draws insignificantly smallswitching currents. Figure 144, a plot of supply currentversus operating frequency, reflects the low power de-sign. At zero frequency, comparator quiescent current andthe 12µA reference stack bias account for all current drain.There are no other paths for loss. As frequency scales up,the 100pF capacitor’s charge-discharge cycle introducesthe 1.1µA/kHz increase shown. A smaller value capacitorwould cut power, but effects of stray capacitance andcharge imbalance would introduce accuracy errors.

Circuit start-up or overdrive can cause the circuit’s AC-coupled feedback to latch. If this occurs, C1’s output goeslow; C2, detecting this via the 2.7M–0.1µF lag, goes high.This lifts C1’s positive input and grounds the negativeinput with Q7, initiating normal circuit action.

To calibrate this circuit, apply 50mV and select the indi-cated resistor at C1’s positive input for a 100Hz output.Complete the calibration by applying 5V and trimming theinput potentiometer for a 10kHz output.

FREQUENCY (kHz)

0

5

10

15

20

25

35

30

CURR

ENT

CONS

UMPT

ION

(µA)

12

DIVF_03.eps

0 1 2 3 4 5 6 7 8 9 10 11

SLOPE = 1.1µA/kHz

Figure 144. Current Consumption vs Frequency for theV/F Converter: Charge/Discharge Cycles Account for1.1µA/kHz Current Drain Increase

BRIDGE MEASURES SMALL CAPACITANCEIN PRESENCE OF LARGE STRAYSby Jeff Witt

Capacitance sensors measure a wide variety of physicalquantities, such as position, acceleration, pressure andfluid level. The capacitance changes are often much smallerthan stray capacitances, especially if the sensor is re-motely placed. I needed to make measurements with a50pF cryogenic fluid level detector, with only 2pF full-scalechange, hooked to several hundred pF of varying cable

capacitance. This required a circuit with high stability,sensitivity and noise rejection, but one insensitive to straycapacitance caused by cables and shielding. I also wantedbattery operation and analog output for easy interfacing toother instruments. Two traditional circuit types havedrawbacks: integrators are sensitive to noise at the com-parator and voltage-to-frequency converters typically mea-sure stray as well as sensor capacitance. The capacitancebridge presented here measures small transducer capaci-tance changes, yet rejects noise and cable capacitance.

Application Note 87

AN87-88

The bridge, shown in Figure 145, is designed around theLTC1043 switched-capacitor building block. The circuitcompares a capacitor, CX, of unknown value, with areference capacitor, CREF. The LTC1043, programmedwith C1 to switch at 500Hz, applies a square wave ofamplitude VREF to node A, and a square wave of amplitudeVOUT and opposite phase to node B. When the bridge isbalanced, the AC voltage at node C is zero, and

VOUT = VREFCX

CREF

Balance is achieved by integrating the current from nodeC using an op amp (LT1413) and a third switch on theLTC1043 for synchronous detection. With CREF = 500pFand VREF = 2.5V, this circuit has a gain of 5mV/pF, andwhen measured with a DMM achieves a resolution of 10fFfor a dynamic range of 100dB. It also rejects stray capaci-tance (shown as ghosts in Figure 145) by 100dB. If thisrejection is not important, the switching frequency f canbe increased to extend the circuit’s bandwidth, which is

CREF

COUTBW = f

COUT should be larger than CREF.

Figure 145. A Simple, High Performance Capacitance Bridge

The circuit operates from a single 5V supply and con-sumes 800µA. If the capacitances at nodes A and C arekept below 500pF, the LT1078 micropower dual op ampmay be used in place of the LT1413, reducing supplycurrent to just 160µA.

If the relative capacitance change is small, the circuit canbe modified for higher resolution, as shown in Figure 146.A JFET input op amp (LT1462) amplifies the signal beforedemodulation for good noise performance, and the outputof the integrator is attenuated by R1 and R2 to increase thesensitivity of the circuit. If ∆CX << CX, and CREF ≈ CX, then

VOUT – VREF ≈ VREF∆CX (R1 + R2)

CREF R2

With CREF = 50pF, the circuit has a gain of 5V/pF and canresolve 2fF. Supply current is 1mA. The synchronousdetection makes this circuit insensitive to external noisesources and in this respect shielding is not terribly impor-tant. However, to achieve high resolution and stability,care should be taken to shield the capacitors being mea-sured. I used this circuit for the fluid level detector men-tioned above, putting a small trim cap in parallel with CREFto adjust offset and trimming R2 for proper gain.

–

+1/2

LT1413

–

+1/2

LT1413

5V

100k

VREF

LT1004-2.51µF

5

6

7 7

8

13

14

5V

4 16

17

11

12

C10.01µF

V+

V–

COSC

A

C

B

CX

CREF

1/2 LTC1043

1/4 LTC1043

2

5

6

2

3

COUT2.2nF

5V

8

4

1

VREF

VOUT

NOTE: SHADED PARTS REPRESENT PARASITIC CAPACITANCES

Application Note 87

AN87-89

Bridge circuits are particularly suitable for differentialmeasurements. When CX and CREF are replaced with twosensing capacitors, these circuits measure differentialcapacitance changes, but reject common mode changes.

CMRR for the circuit in Figure 146 exceeds 70dB. In thiscase, however, the output is linear only for small relativecapacitance changes.

–

+ –

+

1/2LT1413 –

+

5V

100k

VREF

LT1004-2.51µF

5

6

7 7

8

13

14

VIN

4 16

17

11

12

0.01µF

V+

V–

COSC

CX

CREF

1/2 LTC1043

1/4 LTC1043

5

6

2

5V

8

4

7

–

+

1

8

4

2

3

5V

1µF

1/2LT1413

10k 10k

10M

100Ω

VREF

VREF

VREF

VREF

5

6

1/2LT1462

1/2LT1462

VOUT

R110.0k 1%

R2100Ω 1%

2

3

1

10k

100K

Figure 146. A Bridge with Increased Sensitivity and Noise Performance

WATER TANK PRESSURE SENSING,A FLUID SOLUTIONby Richard Markell

Introduction

Liquid sensors require a media compatible, solid statepressure sensor. The pressure range of the sensor isdependent on the height of the column or tank of fluid thatmust be sensed. This article describes the use of the E G& G IC Sensors Model 90 stainless steel diaphragm, 0 to15psig sensor used to sense water height in a tank orcolumn.

Because large chemical or water tanks are typically locatedoutside in “tank farms,” it is insufficient to provide only ananalog interface to a digitization system for level sensing.

This is because the very long wires required to intercon-nect the system cause IR drops, noise and other corrup-tion of the analog signal. The solution to this problem is toimplement a system that converts the analog to digitalsignals at the sensor. In this application, we implement a“liquid height to frequency converter.”

Circuit Description

Figure 147 shows the analog front-end of the system,which includes the LT1121 linear regulator for poweringthe system. The LT1121 is a micropower, low dropoutlinear regulator with shutdown. For micropowerapplications of this or other circuits, the ability to shutdown the entire system via a single power supply pinallows the system to operate only when taking data (perhapsevery hour), conserving power and improving battery life.

Application Note 87

AN87-90

Figure 147. Pressure-Sensor Amplifier

–

+–

+

–

+

–

+

DI_WT_01.eps

OUT

OUT

IN

SHDN

812V

C10.1µF C2

1µF

C30.1µF

12 4

11

GND

U1DLT1079

14

13

5

U1BLT1079

7

6

2

U1ALT1079

1

3

5

1 9V

TO FIGURE 148(9V)

2

R113k

5kINSIDE SENSOR IN MODEL 93REPLACES R13 AND 10k POT

MODEL 90/MODEL 93E G & G IC SENSORS (408) 432-1800

R218k

R335.7k

LT1034-1.2

R54.99k

R44.99k

10kPOT

R14100k

R133.32k

R21100k

R16100k

R20100k

10kPOT

R15100k

R18249k

R17100k

R19249k

R83.01k

R6823Ω

U3LT1121

GND3

PRESSURESENSOR

MODEL 902 7

3 6

51 2

U2ALT1490

1

VO3

Figure 148. This 0.02% V/F Converter Requires only 26µA Supply Current

+

–

10kHzTRIM200k

C11/2 LTC1441

+

–C2

1/2 LTC1441

1.2M*

15k

10M

100Hz TRIM3M TYP

100pF†

INPUTFROM

PRESSURESENSOR

AMPLIFER(FIG 147)

0.01µF

100k

= HP5082-2810 OR 1N5711

= 1N4148

= 2N5089= 2N2222= POLYSTYRENE= 1% METAL FILM

Q1, Q2, Q8ALL OTHER

†

*

6.04k*

LM334

2.7M

100k

0.1µF

50pF

FROM LT1121 (FIGURE 147) +9V

74C14

2.2µF

0.47µF

0.1

LT10041.2Vx 3

Q7Q5

Q1

Q6

Q4

Q8

Q3

Q2

GROUND ALL UNUSED 74C14 AND 74C74 INPUTS PINS

DI_WT_02.eps

CLK

D

QVCC

74C74

CLR

7

Q6

5 390k

2

3

14 14

PRE

+

Application Note 87

AN87-91

In Figure 147, U3, the LT1121, converts 12V to 9V topower the system. The 12V may be obtained from a wallcube or batteries.

The LT1034, a 1.2V reference, is used with U1D, 1/4 of anLT1079 quad low power op amp, to provide a 1.5mAcurrent source to the pressure sensor. The referencevoltage is also divided down by R5, R8, R4 and the 10kpotentiometer and used to offset the output amplifier,U2A, so that the signals are not too close to the supplyrails.

Op amps U1A and U1B (each 1/4 of an LT1079) amplify thebridge pressure sensor’s output and provide a differentialsignal to U2A (an LT1490). Note that U2A must be a rail-to-rail op amp. The system’s analog output is taken fromU2A’s output.

Figure 149 plots the output voltage for the sensor system’sanalog front end versus the height of the water column thatimpinges on the pressure transducer. Note that the pres-sure change is independent of diameter of the watercolumn, so that a tank of liquid would produce the sameresulting output voltage. Figure 150 is a photograph of ourtest setup.

The remainder of the circuitry, shown in Figure 148, allowstransmission of analog data over long distances. Thecircuit was designed by Jim Williams. The circuit takes aDC input from 0V to 5V and converts it to a frequency. Forthe pressure circuit in Figure 147, this translates toapproximately 0Hz to 5kHz.

Figure 149. Output Voltage vs Column Height

Figure 150. Test Setup for Water-Column Sensor

Figure 151. Output Frequency vs ColumnHeight for Two Model 90 Sensors

FEET

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0VO

LTS

16

DI_WT_03.eps

0 2 4 6 8 10 12 14

FEET

0

1000

2000

3000

4000

5000

6000

FREQ

UENC

Y (H

z)

16

DI_WT_05.eps

0 2 4 6 8 10 12 14

SENSOR #2

SENSOR #1

The voltage-to-frequency converter shown in Figure 148has very low power consumption (26µA), 0.02% linearity,60ppm/˚C drift and 40ppm/V power supply rejection.

In operation, C1 switches a charge pump, comprising Q5,Q6 and the 100pF capacitor, to maintain its negative inputat 0V. The LT1004s and associated components form atemperature-compensated reference for the charge pump.

Application Note 87

AN87-92

0.05µV/˚C CHOPPED AMPLIFIER REQUIRESONLY 5µA SUPPLY CURRENTby Jim Williams

Figure 152 shows a chopped amplifier that requires only5.5µA supply current. Offset Voltage is 5µV, with 0.05µV/˚C drift. A gain exceeding 108 affords high accuracy, evenat large closed-loop gains.

The micropower comparators (C1A and C1B) form abiphase 5Hz clock. The clock drives the input-relatedswitches, causing an amplitude-modulated version of theDC input to appear at A1A’s input. AC-coupled A1A takes

The 100pF capacitor charges to a fixed voltage; hence, therepetition rate is the circuit’s only degree of freedom tomaintain feedback. Comparator C1 pumps uniform pack-ets of charge to its negative input at a repetition rateprecisely proportional to the input-voltage-derived cur-rent. This action ensures that circuit output frequency isdetermined strictly and solely by the input voltage.

Figure 151 shows the output frequency versus columnheight for two different Model 90 transducers. Note thestraight lines, which are representative of excellent linearity.

Conclusion

A cost effective system is shown here consisting of a fluidpressure sensor, IC Sensors Model 90. This sensor’soutput is fed to signal processing electronics that convertthe low level DC output of the bridge-based pressuresensor to a frequency in the audio range depending on theheight of the fluid column impinging on the pressuretransducer.

a gain of 1000, presenting its output to a switcheddemodulator similar to the aforementioned modulator.

The demodulator output, a reconstructed, DC-amplifiedversion of the circuit’s input, is fed to A1B, a DC gain stage.A1B’s output is fed back, via gain setting resistors, to theinput modulator, closing a feedback loop around the entireamplifier. The configuration’s DC gain is set by the feed-back resistor’s ratio, in this case 1000.

The circuit’s internal AC coupling prevents A1’s DC char-acteristics from influencing overall DC performance,accounting for the extremely low offset uncertainty noted.

–

+–

+

–

+–

+LTC1440

LTC1440

10M

10M

10M

0.047µF

Ø2

Ø1

5V

–5V

LT1495 LT1495

1/2 CD4016 1/2 CD4016

1µF

1µF

CCOMP0.1µF

1M

1M

1M

10M

10k

10M

10k

1

2

3

4

5

13

Ø2

Ø1

Ø1

Ø2

1112

10

9

6

8

A1A A1B

–5V

5V

OUT

IN

C1A

C1B

Figure 152. 0.05µV/˚C Chopped Amplifier Requires only 5µA Supply Current

Application Note 87

AN87-93

The high open-loop gain permits 10ppm gain accuracy ata closed-loop gain of 1000.

The desired micropower operation and A1’s bandwidthdictate the 5Hz clock rate. As such, the resultant overall

4.5ns DUAL-COMPARATOR-BASED CRYSTALOSCILLATOR HAS 50% DUTY CYCLE ANDCOMPLEMENTARY OUTPUTSby Joseph Petrofsky and Jim Williams

Figure 153’s circuit uses the LT1720 dual comparator in a50% duty cycle crystal oscillator. Output frequencies of upto 10MHz are practical.

The circuit of Figure 153 creates a pair of complementaryoutputs with a forced 50% duty cycle. Crystals are narrow-band elements, so the feedback to the noninverting inputis a filtered analog version of the square wave output.Changing the noninverting reference level can thereforevary the duty cycle. C1 operates as in the previous ex-ample, where the 2k–600Ω resistor pair sets a bias pointat the comparator’s noninverting input. The 2k–1.8k–0.1µF path sets the inverting input at the node at anappropriate DC-average level based on the output. The

Figure 154. Output Skew Varies Only800ps Over a 2.7V–6V Supply Excursion

–

+

–

+

–

+

C11/2 LT1720

C21/2 LT1720

A1LT1636

2.7V–6V

2k

620Ω220Ω

1MHz–10MHzCRYSTAL (AT-CUT)

100k

100k

2k

1k

0.1µF

0.1µF

0.1µF

OUTPUT

OUTPUT

GROUNDCASE

1.8k

SUPPLY VOLTAGE (V)2.5

OUTP

UT S

KEW

(ps)

4.5 6.0

1000

800

600

400

200

0

AN70 F52

3.5 5.53.0 4.0 5.0

crystal’s path provides resonant positive feedback, andstable oscillation occurs. The DC bias voltages at theinputs are set near the center of the LT1720’s commonmode range and the 220Ω resistor attenuates the feedbackto the noninverting input. C2 creates a complementaryoutput by comparing the same two nodes with the oppo-site input polarity. A1 compares band-limited versions ofthe outputs and biases C1’s negative input. C1’s onlydegree of freedom to respond is variation of pulse width;hence, the outputs are forced to 50% duty cycle. Thecircuit operates from 2.7V to 6V and the skew between theedges of the of the two outputs is as shown in Figure 154.There is a slight duty-cycle dependence on comparatorloading, so equal capacitive and resistive loading shouldbe used in critical applications. This circuit works wellbecause of the two matched delays and rail-to-rail–styleoutputs of the LT1720

Figure 153. Crystal Oscillator has Complementary Outputs and50% Duty Cycle. A1’s Feedback Maintains Output Duty CycleDespite Supply Variations

bandwidth is low. Full-power bandwidth is 0.05Hz with aslew rate of about 1V/s. Clock-related noise, about 5µV,can be reduced by increasing CCOMP, with commensuratebandwidth reduction.

Application Note 87

AN87-94

LTC1531 ISOLATED COMPARATORby Wayne Shumaker

Introduction

The LTC1531 is an isolated, self-powered comparator thatreceives power and communicates through internal isola-tion capacitors. The internal isolation capacitors provide3000VRMS of isolation between the comparator and itsoutput. This allows the part to be used in applications thatrequire high voltage isolated sensing without the need toprovide an isolated power source. The isolated side pro-vides a 2.5V pulsed reference output that can deliver 5mA

Figure 155. Isolated Thermistor Temperature Controller

–5.6V

5.6V

AC120V

NEUTRAL

2N2222

LOAD25Ω

TECCORQ4008L4

OR EQUIVALENT

ISOGND

V1

ISOLATIONBARRIER

VALID

GND

390Ω

R5*1M

RTHERM =RO • eB (1/T – 1/TO)B = 3807TO = 297°K

2.5V

20µF50V

1µF

T

LTC1531

R247k

R1680k

150Ω 750Ω0.5W

+

–

THERM30kYSI 44008

R450k

VPWVCC SHDN

CMPOUT

VREGZCDATA

ZCPOS ZCNEG

DATA

LED

1k

Q D

C10.01µF3k

3W

1N4004

+

100µF+

+

1 1 1

1

*HYSTERESIS = 1°C AT TO

= ISOLATED GROUND1

V3

V4

V2

R622k

DANGER!LETHAL VOLTAGESIN THIS SECTION!

for 100µs using the power stored on the isolated externalcapacitor. A 4-input, dual-differential comparator samplesat the end of the reference pulse and transmits the resultback to the nonisolated side. The nonisolated, poweredside latches the result of the comparator and provides azero-cross comparator output for triggering a triac.

Applications

The LTC1531 can be used to isolate sensors such as in theisolated thermistor temperature controller in Figure 155.In this circuit, a comparison is made between the voltagesacross a thermistor and a resistor that is driven by the 2.5V

Figure 156. Overtemperature Detect

ISOGND

V1

V2

V3

V4

1531 TA08

VALID

GND

ISOLATIONBARRIER

10M

33k10.2k

1M

2.5V

2.2µF LT1389

LTC1531

+

–

VPWVCC

VCC

VTRIP

SHDN

CMPOUT

VREG

ZCDATA

ZC + ZC –

DATAQ D

+

–

+

–

+

LT1495

1.74M

1.13k

GAIN SET FOR 0°C TO 200°C

UNUSEDOP AMP

10.7k

K

THERM30kYSI 44008

–

+

LT1495COLD JUNCTION COMPENSATES 0°C TO 60°COUTPUT, VTRIP = 1 AT ≥100°CRESPONSE TIME = 10 secRESOLUTION = 4mV ≥ 0.5°C

Application Note 87

AN87-95

VREG output. As the thermistor resistance rises withtemperature, the voltage across the thermistor increases.When it exceeds the voltage across R4, the comparatoroutput becomes zero and the triac control to the heater isturned off. Hysteresis can be added in the temperaturecontrol by using CMPOUT and R5. A 10° phase-shifted ACline signal is supplied through R1, R2 and C1 to the zero-cross comparator for firing the triac.

In the overtemperature detect application in Figure 156, anisolated thermocouple is cold junction compensated withthe micropower LT1389 reference and the Yellow Springsthermistor. The micropower LT1495 op amp providesgain to give an overall 0°C–200°C temperature range,adjustable by changing the 10M feedback resistor. Theisolated comparator is connected to compare at 1.25V orthe center of the temperature range. In this case, VTRIPgoes high when the temperature exceeds 100°C.

Figure 157. Isolated Voltage Detect

The LTC1531 can use the high impedance nature ofCMPOUT as a duty-cycle modulator, as in the isolatedvoltage sense application in Figure 157. The duty-cycleoutput of the comparator is smoothed with the LT1490rail-to-rail op amp to reproduce the voltage at VIN. Theoutput time constant, R2 • C2, should approximately equalthe input time constant, 35 • R1 • C1. The factor of 35results from CMPOUT being on for only 100µs at anaverage sample rate of 300Hz.

Conclusion

The LTC1531 is a versatile part for sensing signals thatrequire large isolation voltages. The ability of the LTC1531to supply power through the isolation barrier simplifiesapplications; it can be combined with other micropowercircuits in a variety of isolated signal conditioning andsensing applications.

VOUT0V – VCC

FULL-SCALEOUTPUT

ISOGND

V1

V2

V3

V4

1531 TA05

VALID10k

GND R11M

ISOLATIONBARRIER RESOLUTION = 4mV

SETTLING TIME CONSTANT = 10 sec

2.5V

2.2µF

0V TO 2.5VFULL-SCALEINPUT

C10.22µF

VIN

LTC1531

+

–

VPWVCC

VCC

VCC

VCC

SHDN

CMPOUT

VREG

ZCDATA

ZC + ZC –

DATA

10k

R310M

Q D

R210M

C2, 1µF

+

–

+

LT1490

Application Note 87

AN87-96

Filters

THE LTC1560-1: A 1MHz/500kHz CONTINUOUS-TIME,LOW NOISE, ELLIPTIC LOWPASS FILTERby Nello Sevastopoulos

Introduction

The LTC1560-1 is a high frequency, continuous-time, lownoise filter in an SO-8 package. It is a single-ended input,single-ended output, 5th order elliptic lowpass filter witha pin-selectable cutoff frequency (fC) of 1MHz or 500kHz.

The LTC1560-1 delivers accurate fixed cutoff frequenciesof 500kHz and 1MHz without the need for internal orexternal clocks.

Applications and Experimental Results

The LTC1560-1 can be used as part of a more completefrequency-shaping system. Two representative examplesfollow.

Highpass-Lowpass Filter

As a typical application in communication systems, wherethere is a need to reject DC and some low frequencysignals, a 2nd order RC highpass network can be insertedin front of the LTC1560-1 to obtain a highpass-lowpassresponse. Figures 158 and 159 depict the network and itsmeasured frequency response, respectively. Notice thatthe second resistor in the highpass filter is the inputresistance of the LTC1560-1, which is about 8.1k.

–

+

–15V

15V

0.1µF

0.1µF

1

2

3

4

8

7

6

55V

31k

2

4

VOUT

7

LT13608

0.1µF

(OR 5V)

0.01µF

0.01µF

8.1k

0.1µF

LTC1560-1

VIN

300pF

–5V

1560_06.eps

300pF

Figure 158. A Highpass-Lowpass Filter

FREQUENCY (kHz)

–90

–70

–80

–60

–40

–50

0

–10

–20

–30

10

GAIN

(dB)

10000

1560_07.eps

20 100 1000

Figure 159. Measured FrequencyResponse of Figure 158’s Circuit

Delay-Equalized Elliptic Filter

Although elliptic filters offer high Q and a sharp transitionband, they lack a constant group delay in the passband,which implies more ringing in the time-domain stepresponse. In order to minimize the delay ripple in thepassband of the LTC1560-1, an allpass filter (delay equal-izer) is cascaded with the LTC1560-1, as shown in Figure160. Figures 161 and 162 illustrate the eye diagramsbefore and after the equalization, respectively.

An eye diagram is a qualitative representation of the time-domain response of a digital communication system. Itshows how susceptible the system is to intersymbolinterference (ISI). Intersymbol interference is caused byerroneous decisions in the receiver due to pulse overlap-ping and decaying oscillations of a previous symbol. Apseudorandom 2-level sequence has been used as theinput of the LTC1560-1 to generate these eye diagrams.The larger eye opening in Figure 162 is an indication of theequalization effect that leads to reduced ISI. Note that inFigure 160, the equalizer section has a gain of 2 for drivingand back-terminating 50Ω cable and load. For a simpleunterminated gain-of-1 equalizer, the 40.2k resistorchanges to 20k and the 49.9Ω resistor is removed fromthe circuit. The 22pF capacitors are 1% or 2% dipped silvermica or COG ceramic.

Application Note 87

AN87-97

Conclusion

The LTC1560-1 is a 5th order elliptic lowpass filter thatfeatures a 10-bit gain linearity at signal ranges up to 1MHz.Being small and user friendly, the LTC1560-1 is suitablefor any compact design. It is a monolithic replacement for

Figure 160. Augmenting the LTC1560-1 for Improved Delay Flatness

Figure 161. 2-level Eye Diagram of the LTC1560-1Before Equalization

Figure 162. 2-level Eye Diagram of the Equalized Filter

–

+

–

+

1

2

3

4

8

7

6

55V

26.49k

6.65k

49.9Ω

22pF0.1µF

0.1µF

22pF

9.75k

20k

40.2k

3VOUT

1/2 LT13641 6

5

4

8

5V

1/2 LT1364

–15V

7

0.1µF

(OR 5V)

0.01µF

0.01µF0.1µF

LTC1560-1

VIN

–5V 1560_08.eps

larger, more expensive and less accurate solutions incommunications, data acquisitions, medical instrumen-tation and other applications.

Application Note 87

AN87-98

THE LTC1067 AND LTC1067-50: UNIVERSAL 4THORDER LOW NOISE, RAIL-TO-RAIL SWITCHEDCAPACITOR FILTERSby Doug La Porte

LTC1067 and LTC1067-50 Overview

The LTC1067 and the LTC1067-50 are universal, 4th orderswitched capacitor filters with rail-to-rail operation. Eachpart contains two identical, high accuracy, very widedynamic-range 2nd order filter building blocks. Each build-ing block, together with three to five resistors, provides2nd order filter transfer functions, including lowpass,bandpass, highpass, notch and allpass. These parts can beused to easily design 4th order or dual 2nd order filters.

Linear Technology’s FilterCAD™ for Windows® filterdesign software fully supports designs with these parts.

The center frequency of each 2nd order section is tuned byan external clock. The LTC1067 has a 100:1 clock-to-center frequency ratio. The LTC1067-50’s clock-to-centerfrequency ratio is 50:1.

Figure 163. High Dynamic-Range Butterworth LPF with Track-and-Hold ControlFigure 164. Transfer Function of theLTC1067 5kHz Butterworth LPF

3.3V

0.1µF

1µF

VIN

R31, 49.9k

R41, 40.2k

R21, 40.2k

RL1, 59k

R42, 76.8k

R32, 40.2k

R22, 76.8kR11

52.3k

VOUT

CMOS LOGIC GATE

1067_03.EPS

V+

NC

V+

SA

LPA

BPA

HPA

INV A

CLK

AGND

V–

SB

LPB

BPB

HPB

INV B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LTC1067

500kHz

TRACK HOLD

1k 10k 100k

1067_04.EPS

–90.00

10.000

0

–10.00

–20.00

–30.00

–40.00

–50.00

–60.00

–70.00

–80.00

FREQUENCY (Hz)

GAIN

(dB)

Some LTC1067 and LTC1067-50 Applications

High Dynamic-Range Butterworth Lowpass Filter withBuilt-In Track-and-Hold Challenges Discrete Designs

Figure 163 shows an LTC1067 configured as a 5kHzButterworth lowpass filter. This circuit runs on a 3.3Vpower supply and uses an external logic gate to stop theclock for track-and-hold operation. The transfer functionfor this circuit, shown in Figure 164, is the classicalButterworth response. This circuit can be used with eitherthe LTC1067 or the LTC1067-50. The broad-band noise forthe LTC1067 circuit is 45µVRMS and the DC offset istypically less than 10mV. For the LTC1067-50, the broad-band noise is 55µVRMS and the DC offset is typically lessthan 15mV.

This circuit has tremendous dynamic range, even on lowsupply voltages. Figure 165 shows a plot of the LTC1067’ssignal-to-noise plus total harmonic distortion (SINAD) vsinput signal level for a 1kHz input at three different powersupply voltages. SINAD is limited for small signals by thenoise floor of the LTC1067, for medium signals by thepart’s linearity and for large signals by the output signalswing. The part’s low noise input stage and excellentlinearity allow the SINAD to exceed 80dB for signals assmall as 700mVP-P, while the rail-to-rail output stagemaintains this level for input signals approaching the

Application Note 87

AN87-99

supply rails. Previous parts could not attain this highdynamic range due to higher input noise levels, poorlinearity and limited output-stage signal swing. The lownoise and rail-to-rail output swing are especially crucial onthe lower 3.3V power supply, where every bit of detectablesignal range is precious. Figure 166 shows the same plotfor the LTC1067-50 circuit. The dynamic range is not quiteequal to that of the LTC1067, but is still very good. Recallthat, for the same clock frequency, the LTC1067-50 basedfilter has double the bandwidth and half the supply currentof the LTC1067.

The LTC1067 and LTC1067-50 also perform a track-and-hold function. Stopping the clock holds the output of thefilter at its last value. The LTC1067 is the best performingpart in this area. The LTC1067’s hold step is less than

–100µV and the droop rate is less than –50µV/ms over thefull temperature range. These numbers compare veryfavorably with dedicated track-and-hold amplifiers. Whenthe clock is restarted, the filter resumes normal operationwithin ten clock cycles and the output will then correctlyreflect the input as soon as the filter’s mathematicalresponse allows.

Elliptic Lowpass Filter

The LTC1067 family is capable of much more challengingfilters. Figure 167 shows the schematic for a 25kHz ellipticlowpass filter using the LT1067-50 operating on a 5Vsupply. Maximum attenuation one octave from the –3dBcorner is the design goal for this filter. Figure 168 showsthe frequency response of the filter with the –3dB cutoff at

0.1 1 10

1067_05.EPS

–100.00

–50.00

–55.00

–60.00

–65.00

–70.00

–75.00

–80.00

–85.00

–90.00

–95.00

INPUT VOLTAGE (Vp-p)

(NOI

SE +

THD

)/SIG

NAL

(dB)

VSUPPLY = 5V

VSUPPLY = ±5V

VSUPPLY = 3.3V

0.1 1 10–100.00

–50.00

–55.00

–60.00

–65.00

–70.00

–75.00

–80.00

–85.00

–90.00

–95.00

INPUT VOLTAGE (VP-P)

(NOI

SE +

THD

)/SIG

NAL

(dB)

1067_06.EPS

VSUPPLY = 3.3V

VSUPPLY = 5V

VSUPPLY = ±5V

V+

NC

V+

SA

LPA

BPA

HPA

INV A

CLK

AGND

V–

SB

LPB

BPB

HPB

INV B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LTC1067-50

–

+

5V

0.1µF

1µF

VIN

R61, 48.7k

R31, 49.9k

R21, 20k

R514.99k

RH1, 93.1k

RL1, 25.5k

R524.99k

1.25MHz

R62, 6.04k

R32, 21k

R22, 24.9k

RH2, 487k

RL2, 20k

RG, 21k

1/2 LT1498 VOUT

1067_07.EPS

R1153.6k

Figure 165. Dynamic Range of LTC1067 Butterworth LPF Figure 166. Dynamic Range of LTC1067-50 Butterworth LPF

Figure 167. 25kHz Elliptic Lowpass Filter

Application Note 87

AN87-100

25kHz and –48dB of attenuation at 50kHz. The broad-bandnoise of the filter is 85µVRMS and the DC offset is less than15mV typically.

Although Figure 167 shows the filter powered by a single5V supply, 3.3V or ±5V supply operation is also supported.The maximum cutoff frequency is 15kHz for the 3.3Vsupply and 35kHz for the ±5V supply. The same design andschematic used with an LTC1067 will achieve a somewhatlower noise, lower DC-offset filter. With the LTC1067, thebroad-band noise is 70µVRMS and the DC offset is typicallyless than 10mV. The maximum operating frequencies forthe LTC1067 are one half of those for the LTC1067-50.

Narrow-Band Bandpass Filter DesignExtracts Small Signals Buried in Noise

Narrow-band bandpass filters are difficult to design butare easily achievable with these parts. Most applicationsfor these filters involve extracting a low level signal froma noisy environment. The noise may be the standardbroad-band, Gaussian-type noise or it may consist ofmultiple interfering signals. For example, the signal maybe a low level tone or a narrow-bandwidth modulatedsignal, in a voice-band system. The presence of the tonemust be detected even while the large voice signals arepresent. A narrow-band bandpass filter will allow the toneto be separated and detected even in this hostile environ-ment. Numerous systems also require a narrow bandpassfilter to be swept across a band looking for the tones.Switched capacitor filters allow the filter to be swept bysimply changing the clock frequency.

To achieve success in designing narrow-band bandpassfilters, you must start with precision components. In an LCor RC design, you would have to start with 0.1% resistors,1% inductors and 1% capacitors to have any hope offinishing with a successful, repeatable design in produc-tion. A competing solution, a digital filter implementation,also requires precision components. The full input signal(signal, noise and out-of-band interference) must be cor-rectly digitized and then processed with a DSP device tofinally determine the tone’s presence. If an out-of-bandinterfering signal is 20dB greater than the desired tone, theADC must have an extra 20dB of dynamic range above thesignal’s requirement. To pull a small-signal tone from alarge signal interferer, you may need a 16-bit ADC todigitize the signal just to get 12-bit resolution of the toneafter processing. The added cost, power, board space anddevelopment time make this approach unattractive.

1k 10k 100k 200k

1067_08.EPS

–90.00

10.000

0

–10.00

–20.00

–30.00

–40.00

–50.00

–60.00

–70.00

–80.00

FREQUENCY (Hz)

GAIN

(dB) 0.1µF

1067_09.eps

LTC1067

V+

NC

V+

SA

LPA

BPA

HPA/NA

INV A

CLK

AGND

V–

SB

LPB

BPB

HPB/NB

INV B

3.3V

R32, 200k

R22, 10k

R31, 200k

R21, 10kR11200k

IN

R12, 200k

OUT

1µF

fCLK = 500kHz1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FREQUENCY (kHz)4.0

GAIN

(dB)

6.0

1067_10.eps

4.5 5.0 5.5

0

–10

–20

–30

–40

Figure 168. Transfer Function of LTC1067-50 25kHz LPF Figure 169. Low Noise, Low Voltage Narrow BPF

Figure 170. Frequency Response of Narrow BPF

Application Note 87

AN87-101

A precision switched capacitor filter provides a simple,small, low power, repeatable, inexpensive solution. Theolder MF-10-type parts do not have the necessary fOaccuracy to achieve a reliable, repeatable design. Figure169 shows the schematic of a narrow-band bandpass filtercentered at 5kHz. The design uses two identical cascadedsections, each with a Q of 20. Multiply the individual Q ofeach section by 1.554 to calculate the total Q of a filter withtwo identical fO, identical Q sections. This filter has a totalQ of 31. For tunable filter applications, simply lowering theclock frequency lowers the center frequency of the filter.Figure 170 shows the frequency response of this filter. Thebroad-band noise of this filter is only 90µVRMS. Highlyselective bandpass filters are possible due to the LTC1067’sexcellent fO accuracy.

Higher Q, narrower bandwidth filters are achievable with0.1% resistors or matched resistor networks. An LTC1067mask-programmed part is ideal for these ultranarrowfilters. The well matched, on-chip resistors, coupled withspecified test conditions, yield a fully functioning filtermodule, in an SO-8 package, without any of the hassles orcost of procuring precision resistors or resistor networks.

Narrow-Band Notch Filter DesignReaches 80dB Notch Depth

Narrow-band notch filters are especially challenging de-signs. The requirement for most notch filters is to removea particular tone and not affect any of the remaining signalbandwidth. This requires an infinitesimally narrow filterthat can only be approximated by a reasonably narrowbandwidth. These types of filters, like the narrow-bandbandpass discussed above, require precision fO accuracy.Figure 171 shows the schematic of this type of filter. Thisfilter is a 1.02kHz notch filter that is often used in telecom-munication test systems.

One of the challenges of designing a switched capacitornotch filter involves the broad-band nature of a notch filter.The broad-band noise can be aliased down into the bandof interest. Optimal high performance notch filters shouldemploy some form of noise-band limiting. To accomplishthe noise-band limiting, the design in Figure 171 placescapacitors in parallel with the R2 resistors of each 2ndorder section. This forms a pole, set at fP = 1/(2 • π • R2 • C2), that will limit the bandwidth. This polefrequency must be low enough to have a band-limitingeffect but must not be so low as to affect the notch filter’sresponse. The pole should be greater than thirty times thenotch frequency and less than seventy-five times thenotch frequency for the best results. Figure 172 shows thefrequency response of the filter. Note that the notch depthis greater than –80dB. Without the use of the C21 and C22,the notch depth is only about –35dB.

Figure 171. Narrow-Band Notch FilterFigure 172. Measured Frequency Responseof Figure 171’s Narrow-Band Notch Filter

0.1µF

1067_11.eps

LTC1067

V+ CLK5V

R52*4.99k

R32464k

R2275k

R3261.9k

R51*4.99k

R61*9.88k

R2110k

R1118.7k

VIN***

1µF

fCLK = 125kHz

R51, R61, R52, R62 ARE 0.1% TOLERANCE RESISTORSC21 AND C22 IMPROVE THE NOTCH DEPTH WHERE

NC

V+

SA

LPA

HPA/NA

BPA

INV A

1

2

3

4

5

7

6

8

16

15

14

13

12

10

11

9

AGND

V–

SB

LPB

BPB

HPB/NB

INV B

200Ω

R62*10k

RH140.2k

C21** 300pF C22**

30pF

VOUT

***

***

12π(R2X)(C2X)

(30)(fNOTCH) < < (75)(fNOTCH) WITHOUT

C21 AND C22 THE NOTCH DEPTH IS LIMITED TO –35dB

VIN ≤ 1.25VP-P

FREQUENCY (Hz)800

GAIN

(dB)

900 1000 1100

LT1067_12.eps

1200

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Application Note 87

AN87-102

UNIVERSAL CONTINUOUS-TIME FILTERCHALLENGES DISCRETE DESIGNSby Max Hauser

The LTC1562 is the first in a new family of tunable, DC-accurate, continuous-time filter products featuring verylow noise and distortion. It contains four independent 2ndorder, 3-terminal filter blocks that are resistor program-mable for lowpass or bandpass functions up to 150kHz,and has a complete PC board footprint smaller than adime. Moreover, the part can deliver arbitrary continuous-time pole-zero responses, including highpass, notch andelliptic, if one or more programming resistors are replacedwith capacitors. The center frequency (f0) of the LTC1562is internally trimmed, with an absolute accuracy of 0.5%,and can be adjusted independently in each 2nd ordersection from 10kHz to 150kHz by an external resistor.Other features include:

Rail-to-rail inputs and outputs Wideband signal-to-noise ratio (SNR) of 103dB Total harmonic distortion (THD) of –96dB at 20kHz,

–80dB at 100kHz Built-in multiple-input summing and gain features;

capable of 118dB dynamic range Single- or dual-supply operation, 4.75V to 10.5V total “Zero-power” shutdown mode under logic control No clocks, PLLs, DSP or tuning cycles required

The LTC1562 provides eight poles of programmable con-tinuous-time filtering in a total surface mount board area(including the programming resistors) of 0.24 square

1

2

3

5

6

8

9

10

20

19

18

16

15

13

12

11

INV B

V1 B

V2 B

V+

SHDN

V2 A

V1 A

INV A

INV C

V1 C

V2 C

V–

AGND

V2 D

V1 D

INV D

LTC1562

RIN2, 10k

RIN4, 10k

RIN110k

VIN2

VIN1

VOUT1

VOUT2

RIN310k

–5V5V

RQ1, 5.62k

R21, 10k

R23, 10k

0.1µF 0.1µF

RQ3, 5.62k

R24, 10k

RQ4, 13k

RQ2, 13k

R22, 10k

V– ALSO AT PINS 4, 7, 14 &17ALL RESISTORS 1% METAL FILM

inches (155 mm2 )—smaller than a U.S. 10-cent coin. Thisfilter can also replace op amp–R-C active filter circuits andLC filters in applications requiring compactness, flexibil-ity, high dynamic range or fewer precision components.

Each of the four 3-terminal Operational Filter™ buildingblocks in an LTC1562 has a virtual ground input, INV, andtwo outputs, V1 and V2. These are described in detail in theLTC1562 data sheet.

Dual 4th Order 100kHz Butterworth Lowpass Filter

The practical circuit in Figure 173 is a dual lowpass filterwith a Butterworth (maximally-flat-passband) frequencyresponse. Each half gives a DC-accurate, unity-passband-gain lowpass response with rail-to-rail input and output.With a 10V total power supply, the measured output noisefor one filter is 36µVRMS in a 200kHz bandwidth, and thelarge-signal output SNR is 100dB. Measured THD at1VRMS input is –83.5dB at 50kHz and –80dB at 100kHz.Figure 174 shows the frequency response of one filter.

8th Order 30kHz Chebyshev Highpass Filter

Figure 175 shows a straightforward use of the highpassconfiguration. Each of the four cascaded 2nd order sectionshas an external capacitor in the input path. The resistors inFigure 175 set the f0 and Q values of the four sections torealize a Chebyshev (equiripple-passband) response with0.05dB ripple and a 30kHz highpass corner. Figure 176shows the frequency response. Total output noise for thiscircuit is 40µVRMS.

Figure 173. Dual, Matched 4th Order100kHz Butterworth Lowpass Filter Figure 174. Frequency Response of Figure 173’s Circuit

FREQUENCY (Hz)10k

GAIN

(dB)

10

0

–10

–20

–30

–40

–50

–60

–70

–80100k 1M

1562 TA02

Application Note 87

AN87-103

50kHz, 100dB Elliptic Lowpass Filter

Figure 177 illustrates how sharp-cutoff filtering can exploitthe Operational Filter capabilities of the LTC1562. In thisdesign, external capacitors are added and the virtual-ground inputs of the LTC1562 sum parallel paths to obtainthree notches in the stopband of a lowpass filter, as plottedin Figure 178. This response falls 100dB in a little morethan one octave; the total output noise is 60µVRMS with therail-to-rail output for a peak SNR of 95dB from ±5Vsupplies.

Quadruple 3rd Order 100kHz Butterworth Lowpass Filter

Another example of the flexibility of the virtual-groundinputs is the ability to add an extra, independent real polewith an R-C-R “T” network. In Figure 179, a 10k inputresistor has been split into two parts and the parallelcombination of the two forms a 100kHz real pole with the680pF external capacitor. Four such 3rd order Butterworth

1

2

3

5

6

8

9

10

20

19

18

16

15

13

12

11

INV B

V1 B

V2 B

V+

SHDN

V2 A

V1 A

INV A

NV C

V1 C

V2 C

V–

AGND

V2 D

V1 D

INV D

LTC1562

CIN1150pF

CIN

TO CIN3

1562 TA08

VOUT

–5V5V

FROMHP C

RQ1, 10.2k

R21, 35.7k

R23, 107k

0.1µF 0.1µF

RQ3, 54.9k

R24, 127k

RQ4, 98.9k

RQ2, 22.1k

R22, 66.5k

CIN3150pF

CIN4150pF

CIN2150pF

V– ALSO AT PINS 4, 7, 14 &17; ALL RESISTORS 1% METAL FILM

FREQUENCY (Hz)1k

GAIN

(dB)

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–9010k 100k 1M

1562 TA09

RQ1 30.1k

RQ3 34k

RIN3 31.6k

RIN148.7k

VINRQ2 13k

RIN2 37.4k

RIN4 32.4k

CIN2 24pF

RQ4 11.5k

R22 57.6k

R24 32.4k

0.1µF

VOUT

–5V5V

R21 31.6k

R23 31.6k

LTC156220-PIN SSOP

INVB

V1B

V2B

V+

SHDN

V2A

V1A

INVA

20

19

18

16

15

13

12

11

INVC

V1C

V2C

V –

AGND

V2D

V1D

INVD

1

2

3

5

6

8

9

10

0.1µF

CIN4 10pFCIN3 18pF V– ALSO AT PINS 4, 7, 14 &17

ALL RESISTORS 1% METAL FILM

FREQUENCY (kHz)

–120

–60

–80

–100

20

0

–20

–40

GAIN

(dB)

10 500100

lowpass filters can be built from one LTC1562. The sametechnique can add additional real poles to other filterconfigurations as well, for example, augmenting Figure173’s circuit to obtain a dual 5th order filter from a singleLTC1562.

Conclusion

The LTC1562 is the first truly compact universal activefilter, yet it offers instrumentation-grade performancerivaling much larger discrete-component designs. It servesapplications in the 10kHz–150kHz range with an SNR ashigh as 100dB or more (16+ equivalent bits). The LTC1562is ideal for modems and other communications systemsand for DSP antialiasing or reconstruction filtering.

Figure 175. 8th Order Chebyshev HighpassFilter with 0.05dB Ripple (fCUTOFF = 30kHz)

Figure 176. Frequency Response of Figure 175’s Circuit

Figure 177. 50kHz Elliptic Lowpass Filterwith 100dB Stopband Rejection

Figure 178. Frequency Response of Figure 177’s Circuit.

Application Note 87

AN87-104

HIGH CLOCK-TO-CENTER FREQUENCY RATIOLTC1068-200 EXTENDS CAPABILITIES OF SWITCHEDCAPACITOR HIGHPASS FILTERby Frank Cox

The circuit in Figure 180 is a 1kHz 8th order Butterworthhighpass filter built with the LTC1068-200, a switchedcapacitor filter (SCF) building block. In the past, commer-cially available switched capacitor filters have had limiteduse as highpass filters because of their sampled-datanature. Sampled-data systems generate spurious fre-quencies when the sampling clock of the filter and theinput signal mix. These spurious frequencies can include

sums and differences of the clock and the input, in additionto sums and differences of their harmonics. The input ofthe filter must be band limited to remove frequencies thatwill mix with the clock and end up in the passband of thefilter. Unfortunately, the passband of a highpass filterextends upward in frequency by its very nature. If you haveto band limit the input signal too much you will also limitthe passband of the filter, and hence its usefulness.

What makes this filter different is the 200:1 clock-to-centerfrequency ratio (CCFR) and the internal sampling schemeof the LTC1068-200. Figure 181a shows the amplituderesponse of the filter plotted against frequency from

Figure 180. LTC1068-200 1kHz 8th Order Butterworth Highpass Filter

INV B

HPB/NB

BPB

LPB

SB

NC

AGND

V+

NC

SA

LPA

BPA

HPA/NA

INV A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

INV C

HPC/NC

BPC

LPC

SC

V–

NC

CLK

NC

SD

LPD

BPD

HPD/ND

INV D

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LTC1068-200

RH3 1.47k

R22 10k

R32 24.3k

R42 10k

R44 16.9k

R34 10k

R24 16.9k

RH4 14.7k

R43 11.3k

R23 11.3k

R33 10k

R11 10k

R41 20k

R21 20k

R31 10k

–5V

200kHz

VOUT

5V

VIN

RH2 10k

0.1µF

0.1µF

1

2

3

5

6

8

9

10

20

19

18

16

15

13

12

11

IINV B

V1 B

V2 B

V+

SHDN

V2 A

V1 A

INV A

INV C

V1 C

V2 C

V–

AGND

V2 D

V1 D

INV D

LTC1562

RIN1B3.83k

RIN1A6.19k

RIN3A6.19k

VIN1

VIN3

CIN1680pF

VIN2

1562 TA07

VOUT2

VOUT3 VOUT4

VOUT1

RIN3B3.83k

–5V5V

RQ1, 10k

R21, 10k

R23, 10k

0.1µF 0.1µF

RQ3, 10k

R24, 10k

RQ4, 10k

RQ2, 10k

R22, 10k

CIN2680pF

CIN3680pF

ALL RESISTORS = 1% METAL FILM

RIN2B3.83k

RIN2A6.19k

VIN4CIN4680pF

RIN4B3.83k

RIN4A6.19k

Figure 179. Quad 3-Pole 100kHz Butterworth Lowpass Filter

Application Note 87

AN87-105

100Hz to 10kHz. For comparison, Figure 181b shows thesame filter built with an LTC1068-25. This is a 25:1 CCFRpart. The 200:1 CCFR filter delivers almost 30dB moreultimate attenuation in the stopband. A standard ampli-tude vs frequency plot of a highpass filter can be mislead-ing because it masks some of the aforementioned spuri-ous signals introduced into the passband. Figure 182a isa spectrum plot of the 200:1 filter with a single 10kHz toneon the input. This plot shows that the spurious freedynamic range (SFDR) of the LTC1068 highpass filter is inexcess of 70dB. In fact, the filter has a 70dB SFDR for allinput signals up to 100kHz. In a 200kHz sampled-datasystem, you would normally need to band limit the inputbelow 100kHz, the Nyquist frequency. Because theLTC1068 uses double sampling techniques, its usefulinput frequency range extends to the Nyquist frequency

200Hz 100kHz

10dB

/DIV

–10dB

DI_1068_03b. EPS

200kHz 100Hz

10dB

/DIV

–10dB

DI_1068_04. EPS

25kHz12.5kHz

Figure 182b. Spectrum Plot of Figure180’s Circuit with a Single 150kHz Input

Figure 183. Spectrum Plot of a Comparable FilterUsing the LTC1068-25 with a Single 10kHz InputShows a Respectable 55dB SFDR.

100Hz

10dB

/DIV

–10dB

DI_1068_02a. EPS

10kHz5kHz 100Hz

10dB

/DIV

–10dB

DI_1068_02b. EPS

10kHz5kHz 200Hz 100kHz

10dB

/DIV

–10dB

DI_1068_03a. EPS

200kHz

Figure 181a. Amplitude vsFrequency Response of Figure180’s Circuit

Figure 181b. Amplitude vs FrequencyResponse of Comparable Filter Usingthe LTC1068-25

Figure 182a. Spectrum Plot ofFigure 180’s Circuit with a Single10kHz Input

and even above, albeit with some care. Figure 182b showsthe LTC1068-200 highpass filter with an input frequencyof 150kHz. There is a spurious signal at 50kHz, but eventhough there is no input filtering, the SFDR is still 60dB.For input signals from 100kHz to 150kHz, the filter dem-onstrates an SFDR of at least 60dB. The SFDR plot of thesame filter built with the LTC1068-25 is shown in Figure183. Note that the lower CCFR (25:1) part still manages arespectable 55dB SFDR with a 10kHz input. The LTC1068-25 is used primarily for band-limited applications, such aslowpass and bandpass filters.

Note:

The filters for this article were designed using Linear Technology’s Filter-CAD™ (version 2.0) for Windows®. This program made the design andoptimization of these filters fast and easy.

Application Note 87

AN87-106

CLOCK-TUNABLE, HIGH ACCURACY, QUAD 2NDORDER, ANALOG FILTER BUILDING BLOCKS

by Philip Karantzalis

Introduction

The LTC1068 product family consists of four monolithic,clock-tunable filter building blocks. Each product containsfour matched, low noise, high accuracy 2nd order switchedcapacitor filter sections. An external clock tunes the centerfrequency of each 2nd order filter section. The LTC1068products differ only in their clock-to-center frequencyratio. The clock-to-center frequency ratio is set to 200:1(LTC1068-200), 100:1 (LTC1068), 50:1 (LTC1068-50) or25:1 (LTC1068-25). External resistors can modify theclock-to-center frequency ratio. Designing filters with anLTC1068 product is fully supported by the FilterCAD 2.0design software for Windows. The internal sampling rateof all the LTC1068 devices is twice the clock frequency.This allows the frequency of input signals to approachtwice the clock frequency before aliasing occurs. Maxi-mum clock frequency for LTC1068-200, LTC1068 andLTC1068-25 is 6MHz with ±5V supplies; that for theLTC1068-50 is 2MHz with a single 5V supply. For low

power filter applications, the LTC1068-50 power supplycurrent is 4.5mA with a single 5V supply and 2.5mA witha single 3V supply. The LTC1068 products are available ina 28-pin SSOP surface mount package. The LTC1068 (the100:1 part) is also available in a 24-pin DIP package.

LTC1068-200 Ultralow FrequencyLinear-Phase Lowpass Filter

Figure 184 shows an LTC1068-200 linear-phase 1Hzlowpass filter schematic and Figure 185 shows its gainand group delay responses. The clock frequency of thisfilter is 400 times the –3dB frequency (f–3dB or fCUTOFF).The large clock-to-fCUTOFF frequency ratio of this filter isuseful in ultralow frequency filter applications when mini-mizing aliasing errors could be an important consider-ation. For example, the 1Hz lowpass filter shown in Figure184 requires a 400Hz clock frequency. For this filter, theinput frequencies that can generate aliasing errors are ina band from 795Hz to 805Hz (2 • fCLK ±5 • f–3dB). For mostvery low frequency signal-processing applications, thesignal spectrum is less than 100Hz. Therefore, Figure184’s filter will process very low frequency signals withoutsignificant aliasing errors, since its clock frequency is400Hz and the aliasing inputs are in a small band around800Hz.

INV B

HPB/NB

BPB

LPB

SB

NC

AGND

V+

NC

SA

LPA

BPA

HPA/NA

INV A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

INV C

HPC/NC

BPC

LPC

SC

V–

NC

CLK

NC

SD

LPD

BPD

HPD/ND

INV D

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LTC1068-200RL2 14.3k

R22 15.4k

R32 10k

R34 10k

R24 15.4k

R43 12.4k

R23 10k

R33 12.4k

R11 14.3k

R41 15.4k

R21 12.4k

R31 10k

400kHz

VOUT

5V

VIN

RL1 23.2k

0.1µF

RB3 23.2k

RL3 23.2k

R52 5.11k

R62 9.09k

–5V

R54 5.11k

R64 9.09k0.1µF

Figure 184. Linear-Phase Lowpass Filter: f–3dB = 1Hz = fCLK/400Figure 185. Gain and Group DelayResponse of Figure 184’s Circuit.

GAIN

(dB)

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0.1 10FREQUENCY (Hz)

1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

GROUP DELAY (s)

GAIN

GROUPDELAY

Application Note 87

AN87-107

LTC1068-50 Single 3.3V Low PowerLinear-Phase Lowpass Filter

Figure 186 is a schematic of an LTC1068-50-based, single3.3V, low power, lowpass filter with linear phase. Theclock-to-fCUTOFF ratio is 50 to 1 (fCUTOFF is the –3dBfrequency). Figure 187 shows the gain and group delayresponse. The flat group delay response in the filter’spassband implies a linear phase. A linear-phase filter hasa transient response with very small overshoot that settlesvery rapidly. A linear-phase lowpass filter is useful forprocessing communication signals with minimumintersymbol interference in digital communications trans-mitters or receivers. The maximum clock frequency forthis filter is 1MHz with a single 3.3V supply and 2MHz witha single 5V supply. Typical power supply current is 3mAwith a single 3.3V supply and 4.5mA with a single 5Vsupply.

LTC1068-25 Selective Bandpass Filteris Clock Tunable to 80kHz

Figure 188 shows a 70kHz bandpass filter based on theLTC1068-25 operating with dual 5V power supplies. Theclock-to-center frequency ratio is 25 to 1. Figure 189shows the gain response of Figure 188’s bandpass filter.The passband of this filter extends from 0.95 • fCENTER to1.05 • fCENTER. The stopband attenuation is greater than40dB at 0.8 • fCENTER and 1.15 • fCENTER. The centerfrequency can be clock tuned to 80kHz with dual 5Vsupplies and to 40kHz with a single 5V supply. WithFilterCAD, the LTC1068-25 can be used to realize band-pass filters less selective than that shown in Figure 188,which can be clock tuned up to 160kHz with dual 5Vsupplies.

INV B

HPB/NB

BPB

LPB

SB

NC

AGND

V+

NC

SA

LPA

BPA

HPA/NA

INV A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

INV C

HPC/NC

BPC

LPC

SC

V–

NC

CLK

NC

SD

LPD

BPD

HPD/ND

INV D

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LTC1068-50

RH2 34k

RL2 9.09k

R22 43.2k

R32 43.2k

R42 196k

R44 34.8k

R34 14.3k

R24 16.9k

R43 48.7k

R23 10.7k

R33 12.7k

R11 22.6k

R41 22.6k

R21 20.5k

R31 10k

500kHz

VOUT

3.3V

VIN

RB1 13.3k

RA1 56.2k

0.1µF

1µF

RB3 24.9k

RL3 26.7k

GAIN

(dB)

10

0

–10

–20

–30

–40

–50

–60

–70

–80

1k 100kFREQUENCY (Hz)

10k

GAIN

GROUPDELAY

150

140

130

120

110

100

90

90

70

60

GROUP DELAY (µs)

Figure 186. Low Power, Single 3.3V Supply,10kHz, 8th Order, Linear-Phase Lowpass Filter

Figure 187. Gain and Group DelayResponse of Figure 186’s Filter

Application Note 87

AN87-108

INV B

HPB/NB

BPB

LPB

SB

NC

AGND

V+

NC

SA

LPA

BPA

HPA/NA

INV A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

INV C

HPC/NC

BPC

LPC

SC

V–

NC

CLK

NC

SD

LPD

BPD

HPD/ND

INV D

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LTC1068-25

RL2 23.2k

RH2 11.3k

R22 4.99k

R32 107k

R34 63.4k

R44 17.4k

R24 7.5k

R43 42.3k

R23 4.99k

R33 59k

R1129.4k

R41 20.5k

R21 4.99k

R31 24.9k

1.75MHz

VOUT

5V

VIN

RH1 28k

0.1µF

RH3 15.4k

RL3 45.3k

R52 4.99k R62 56.2k

–5V0.1µF

R544.99k

R64 10k

R61 11.3k

R51 4.99k GAIN

(dB)

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

20 100FREQUENCY (kHz)

6030 40 50 70 80 90

LTC1068 Square-Wave-to-Quadrature Oscillator Filter

Figure 190 shows the schematic of a LTC1068 based filterthat is specifically designed to produce a low harmonicdistortion sine and cosine oscillator from a CMOS-levelsquare wave input. The reference sine wave output ofFigure 190’s circuit is on pin 15 (BPD on the 24-pinLTC1068 package) and the cosine output is on pin 16(LPD on the 24-pin LTC1068 package). The output fre-quency of this quadrature oscillator is the filter’s clockfrequency divided by 128. The output of a CMOS CD4520divide-by-128 counter is coupled with a 0.47µF capacitorto the input to the LTC1068 filter operating with dual 5Vpower supplies. The filter’s clock frequency is the input tothe CD4520 counter. The LTC1068 filter is designed topass the fundamental frequency component of a squarewave and attenuate any harmonic components higherthan the fundamental. An ideal square wave (50% dutycycle) will have only odd harmonics (3rd, 5th, 7th and soon), whereas a typical practical square wave has a duty

cycle less or more than 50% and will also have evenharmonics (2nd, 4th, 6th and so on). The filter of Figure190 has a stopband notch at the 2nd and 3rd harmonics fora square wave input with a frequency equal to the filter’sclock frequency divided by 128. The filter’s sine waveoutput (pin 15) is 1VRMS for a ±2.5V square wave input andhas less than 0.025% THD (total harmonic distortion) forinput frequencies up to 16kHz and less than 0.1% THD forfrequencies up to 20kHz. The cosine output (on pin 16,referenced to pin 15’s sine wave output) is 1.25VRMS fora ±2.5V square wave input and has less than 0.07% THDfor frequencies up to 20kHz.

The 20kHz frequency limit is due to the CD4520; with a74HC type divide-by-128 counter, sine and cosine wavesup to 40kHz can be generated with the LTC1068-basedfilter of Figure 190.

Figure 188. 70kHz, 8th order, Bandpass Filter

Figure 189. Gain Responseof Figure 188’s Filter

Application Note 87

AN87-109

INV B

HPB/NB

BPB

LPB

SB

AGND

V+

SA

LPA

BPA

HPA/NA

INV A

1

2

3

4

5

6

7

8

9

10

11

12

INV C

HPC/NC

BPC

LPC

SC

V–

CLK

SD

LPD

BPD

HPD

INV D

24

23

22

21

20

19

18

17

16

15

14

13

LTC1068

RL2 12.4k

RH2 55.2k

R22 10k

R32 12.4k

R24 10k

R34 10k

R11 22.4k

R21 10k

R31 12.4k

RL1 12.4k

0.1µF

RH3 38.4k

RL3 16.5k

–5V

0.1µF

5V

R33 12.4k

R23 10k

fCLK = 128 × fOUT

*COSINE WAVE OUT

*SINE WAVE OUT

3

4

5

6

11

12

13

14

1

2

16

10

7

8

9

15

CD4520

1Q0

1Q1

1Q2

1Q3

2Q0

2Q1

2Q2

2Q3

CLK

GND

÷2

÷4

÷8

÷16

÷32

÷64

÷128

÷256

5V

0.47µF

0.1µF

fOUT =fCLK128

PIN 16'S COSINE WAVE OUTPUT IS REFERENCED TOPIN 15'S SINE WAVE OUTPUT

*

Figure 190. Square-Wave-to-Quadrature Oscillator Converter

Application Note 87

AN87-110

Miscelleaneous

BIASED DETECTOR YIELDS HIGH SENSITIVITY WITHULTRALOW POWER CONSUMPTIONby Mitchell Lee

RF ID tags, circuits that detect a “wake-up” call and returna burst of data, must operate on very low quiescent currentfor weeks or months, yet have enough battery power inreserve to answer an incoming call. For smallest size, mostoperate in the ultrahigh frequency range, where the designof a micropower receiver circuit is problematic. Familiartechniques, such as direct conversion, super regenerationor superheterodyne, consume far too much supply cur-rent for long battery life. A better method involves atechnique borrowed from simple field-strength meters: atuned circuit and a diode detector.

Figure 191 shows the complete circuit, which was tested at470MHz. It contains a couple of improvements over thestandard L/C-with-whip field-strength meter. Tuned circuitsaren’t easily constructed or controlled at UHF, so a trans-mission line is used to match the detector diode (1N5711)to a 6" whip antenna. The 0.22-wavelength section pre-sents an efficient, low impedance match to the base of thequarter-wave whip, but transforms the received energy toa relatively high voltage at the diode for good sensitivity.

Biasing the detector diode improves the sensitivity by anadditional 10dB. The forward threshold is reduced toessentially zero, so a very small voltage can generate ameaningful output change. The detector diode’s bias point

Figure 191. Micropower Field Detector for Use at 470MHz

is monitored by an LTC1440 ultralow power comparator,and by a second diode, which serves as a reference.

When a signal at the resonant frequency of the antenna isreceived, Schottky diode D1 rectifies the incoming carrierand creates a negative-going DC bias shift at the nonin-verting input of the comparator. Note that the bias shift issensed at the base of the antenna where the impedance islow, rather than at the Schottky where the impedance ishigh. This introduces less disturbance into the tunedantenna and transmission-line system. The falling edge ofthe comparator triggers a one-shot, which temporarilyenables answer-back and other pulsed functions.

Total current consumption is approximately 5µA. Mono-lithic one-shots draw significant load current, but thevenerable ‘4047 is about the best in this respect. Alterna-tively, a discrete one-shot constructed from a quad NANDgate draws negligible power.

Sensitivity is excellent. The finished circuit can detect200mW radiated from a reference dipole at 100'. Range,of course, depends on operating frequency, antenna ori-entation and surrounding obstacles; in the clear, a morereasonable distance, such as 10', can be covered at470MHz with only a few milliwatts.

All selectivity is provided by the antenna itself. Add aquarter-wave stub (shorted with a capacitor) to the baseof the antenna for better selectivity and improved rejectionof low frequency signals.

–

+

DI1440_01.EPS

CMOSONE-SHOT(CD4047)

LTC1440

9VDC

2X9.1MΩ

27kΩ

27kΩFB

λ /4

λ /0.22D1

1N5711

DETECTOR

Z0 = 50Ω

D21N5711

100pF

REFERENCE

100pF

Q

Q

Application Note 87

AN87-111

ZERO-BIAS DETECTOR YIELDS HIGHSENSITIVITY WITH NANOPOWER CONSUMPTIONby Mitchell Lee

RF ID tags, circuits that detect a “wake-up” call and returna burst of data, must operate on very low quiescentcurrent for months or years, yet have enough batterypower in reserve to answer an incoming call. For smallestsize, most operate in the ultrahigh frequency range, wherethe design of a micropower receiver circuit is problematic.Familiar techniques, such as direct conversion, superregeneration or superhetrodyne, consume far too muchsupply current for long battery life. A better methodinvolves a technique borrowed from simple field-strengthmeters: a tuned circuit and a diode detector.

Figure 192 shows the complete circuit, which was testedfor proof-of-concept at 445MHz. This circuit contains acouple of improvements over the standard L/C-with-whipfield-strength meter. Tuned circuits aren’t easily con-structed or controlled at UHF, so a transmission line isused to match the detector diode (1N5712) to a quarter-wave whip antenna. The 0.23λ transmission-line sectiontransforms the 1pF (350Ω) diode junction capacitance toa virtual short at the base of the antenna. At the same time,it converts the received antenna current to a voltage loopat the diode, giving excellent sensitivity.

Biasing the detector diode can improve sensitivity,1 butonly when the diode is loaded by an external DC resis-tance. Careful curve-tracer examination of the 1N5712 at

the origin reveals that it follows the ideal diode equation,with scales of millivolts and nanoamperes. To use a zero-bias diode at the origin, the external comparator circuitrymust not load the rectified output.

The LTC1540 nanopower comparator and reference is agood choice for this application because it not only pre-sents no load to the diode, but also draws only 300nA fromthe battery. This represents a 10-times improvement inbattery life over biased detector schemes.2 The input isCMOS, and input bias current consists of leakage in asmall ESD-protection cell connected between the inputand ground. The input leakage measures in the picoampererange, whereas the 1N5712 leaks hundreds of picoamperes.Any rectified output from the diode is loaded by the diodeitself, not by the LTC1540, and the sensitivity can matchthat of a loaded, biased detector.

The rectified output is monitored by the LTC1540 com-parator. The LTC1540’s internal reference is used to set upa threshold of about 18mV at the inverting input. A risingedge at the comparator output triggers a one-shot, whichtemporarily enables answer-back and any other pulsedfunctions.

Total supply current is 400nA, consuming just 7mAHbattery life over a period of five years. Monolithic one-shots draw significant load current, but the ’4047 is aboutthe best in this respect. A one-shot constructed fromdiscrete NAND gates draws negligible power.

Figure 192. Nanopower Field Detector

–

+CMOS ONE-SHOT

(CD4047)

Q

QLTC1540

12M

180k10nF10nF

10kFB

O.23λ

1N5712

λ/4

2V–11V

3

4

56

78

21

Application Note 87

AN87-112

Sensitivity is excellent, and the circuit can detect about200mW from a reference dipole at 100 feet. Range, ofcourse, depends on operating frequency, antenna orienta-tion and surrounding obstacles. Sensitivity is independentof supply voltage; this receiver will work just as well witha 9V battery as with a single lithium cell.

The length of the transmission line does not scale withfrequency. Owing to a decrease in diode reactance, theelectrical length will shorten as frequency increases. Adjustthe line length for minimum feed-point impedance at theoperating frequency. If an impedance analyzer is used to

measure the line, a 1pF capacitor can be substituted for thediode to avoid large signal effects in the diode itself.Consult the manufacturer’s data sheet for accurate charac-terization of diode impedance at the frequency of interest.

Notes:

1. Eccles, W.H. Wireless Telegraphy and Telephony, Second Edition. BenBrothers Limited, London, 1918, page 272.

2. Lee, Mitchell. “Biased Detector Yields High Sensitivity with Ultralow PowerConsumption.” Page 110 of this application note.

TRANSPARENT CLASS-D AMPLIFIERSFEATURING THE LT1336by Dale Eagar

Introduction

Efficiency in the field of power conversion is like transpar-ency in the field of light transmission. It is no wonder,then, that Class-D amplifiers are often called transparent,since they have no significant power losses. In contrast toclass-D amplifiers’ nearly lossless switching, class-Athrough class-C amplifiers are throttling devices thatwaste significant energy. Amplifiers of the “lower classes”(A–C) are modeled as rheostats (variable resistors),whereas class-D amplifiers are modeled as variacs (vari-able transformers). The ideal resistor dissipates power,whereas the ideal transformer does not. Like transformers(variacs), many class-D amplifiers can transfer energy inboth directions—input to output and output to input.

Class-D amplifiers also have a way of ignoring reactiveloads that can be uncanny. A class-D amplifier operatingwith an AC output will draw very little additional inputpower when a sizable capacitive or inductive load is placedat its output. This is because the reactive load has ACvoltage across it and AC current flowing through it, but thephase angle of the voltage and current is such that no realpower is dissipated. The class-D amplifier ends up shut-tling power back and forth between its input and its output,doing both with minimal loss. An ideal class-D amplifiercan be thought of as having no place to dissipate power,since all of its components are lossless; that is, it containsno resistors.

The Electric Heater—a Simple Class-D Amplifier

Class-D amplifiers can be simple or complex, dependingon what is required by the application. A simple class-Damplifier is the thermostatic switch in an electric heater.The thermostat controls the heater by turning it on or off.The switch is essentially lossless, dissipating practicallyno power. This class-D amplifier is remarkably efficient,since even the energy lost in the switch, power cord andhouse wiring contributes to the desired result. The dutyfactor, and hence the average amount of power deliveredto the heater, can assume an infinite number of values.This is true even though a constant amount of heat isdelivered when the heater is on.

Quadrants of Energy Transfer

Class-D amplifiers have a property that requires newterminology, a property that generally isn’t considered inlower-class amplifiers. This property, quadrants of energytransfer, describes the output characteristics of the class-D amplifier. The output characteristics are plotted on aimaginary X-Y plot (I’ve yet to see someone actually doone on paper), one axis representing output voltage andthe other axis representing output current, with the inter-section of the axes representing zero volts and zero amps.A simple switcher that can only provide a positive outputcurrent into a positive output voltage can be described asa 1-quadrant device. This 1-quadrant device could be acomputer power supply, a battery charger or any supplythat delivers a positive voltage into a device that can onlyconsume power.

Application Note 87

AN87-113

The 2-quadrant converter can be one of two differentthings: 1) A positive output voltage that can both sourceand sink current, or 2) A positive current that can complyboth positive and negative output voltage. Finally, the 4-quadrant converter can both source and sink current intoboth positive and negitive output voltages.

1-Quadrant Class-D Converter

To illustrate the 1-quadrant class-D amplifier, we willfocus on the boost mode converter detailed in Figure 193This circuit removes power from the source (12V automo-tive battery) and delivers it to the load (some as-yet-unknown 55V device) This circuit is classified as “1quadrant” because it can only regulate output voltage inone polarity (positive) and it can output current in only onepolarity (positive).

Figure 193. 200W, 12V to 55V Front End for Automotive Applications

–

+

COMPVIN

VREF GTDR

ISEN

R/C

FB

R351k

R71k

R515k

R111k

R120.01Ω1W

R11Ω

C70.1µF

R130.01Ω1W

R140.01Ω1W

R150.01Ω1W

C14

1000µF, 63V ×6

55V, 3.3A

C1133µF16V

C1233µF16V

C132200µF25V

12V

C522µF20V

C1HEFTYWIRES

FROM CARBATTERY

9V-15V 1200µF, 16V ×4

C2 C3 C4

C15 C19

C10220pF

C81µF

1

2

8 6

4Q12N3904

3

1

3

D11N5819

D2MBR1060

T1

D3MUR110

PRi 20T 2x#14SEC 4T #26MICROMETALS T150-52

D4MUR110

2

5

7C6

1500pF

C90.15

R2100k

R42.49k

R62.4k

R81k

R91k

R1620Ω Q2

IRFZ44Q3IRFZ44

PRi36µH

30A20 4

SEC

R1720Ω

R10100Ω

U1LT1243

U2BLT1215

GND

–

+U2A

LT12157

5 8

6

4

+

–

+ + + +

+ +

+

+ + +

+

Introducing the LT1336 Half-bridge Driver

Taking a side step from our main discussion, we willintroduce a component, the half-bridge power amplifier.Figure 194 details the LT1336 driving power MOSFETsand shows the symbolic representation of this subcircuitthat will appear in subsequent figures. Table 1 shows thelogical states of this half-bridge power driver.

4-Quadrant Class-D Amplifier

Class-D amplifiers are commonly used in subwoofer driv-ers. This is because subwoofers require a great deal ofpower. A class AB amplifier driving a subwoofer will putabout half of its input power into its heat sink. Driving thesame subwoofer at the same volume with the same music,a class-D amplifier will put about five percent of its input

Application Note 87

AN87-114

power into the heat sink. The difference is ten to one on theheatsink size and two to one on the input power supply.Figure 195 is the 200W class-D subwoofer driver. Thiscircuit uses the 200W front end developed in Figure 193 asits power source. The circuit in Figure 195 performs asfollows: U1a, R1–R4 and C7 implement a 75kHzpseudosawtooth oscillator. U1d is the input amplifier/filter, with a gain of 6.1 and 200Hz Butterworth lowpassresponse. U1b and U1c are comparators that compare thesawtooth and the amplified/filtered input signal to formtwo complimentary, pulse-width modulated square waves.X1 and X2 are two half-bridge power drivers and M1 is thesubwoofer driver.

One of the properties of Class-D, 4-quadrant amplificationis the ability to transfer power both to and from the load.In our subwoofer driver, this happens when the driverreaches the end of any given excursion and the combina-tion of the driver spring and the acoustic spring drive thecone back to center. During this time, energy is trans-ferred from the driver back to the input of the class-Damplifier stage. In the case shown in Figure 195, the

energy ends up on the 55V bus, where the bus voltageclimbs during these periods of “negative energy deliv-ered to the load.” Fortunately, C14–C19 of Figure 193 canstore this energy; otherwise the 55V bus would subject toexcessive voltage until someplace was found for theenergy to go.

Class-D for Motor Drives

Substituting a motor and an inductor for the subwoofer inFigure 195 and simplifying the control, we arrive at thecircuit shown in Figure 196. Connecting this circuit to thefront end shown in Figure 193 and then getting the motorup to speed is no problem, but when one wants to slow the

Figure 194. Half-Bridge Driver Subcircuit and Symbolic Representation

ISEN

BOOST

IN TOP

TSOU

IN BOTTOM

IN TOP

IN BOTTOM

SW

1

16

3

11

TGD13

TGF12

BGF8

BGD9

4

6

14

V+2

V+10

U1LT1336

SGND

15

SWGND

7

PGND

D11A60V

D21A60V

R2 2ΩD4

1N4148

D31N4148

D51N4148

T1COILTRONICS

CTX100-P

C2 0.1µF

C31µF

12VR16.2k

C11µF

R6, 10Ω

R5, 10Ω

R4, 10Ω

R3, 10Ω

Q3IRFZ44

Q1IRFZ44

Q4IRFZ44

Q2IRFZ44

55V

OUT

12V

INTOP

INBOTTOM

55V

OUT

(SYMBOLIC REPRESENTATION)

poTnI mottoBnI tuptuO

L L gnitaolF

L H dnuorG

H L V55

H H gnitaolF

Table 7. Half-Bridge Power Driver Truth Table

Application Note 87

AN87-115

12V 55V 55V

F110AM1

18" SUBWOOFERDRIVER

1mH, 6.5Ω

12V

–

+

–

+U1B

LT1365U1A

LT13658

12V

12V

C80.1µF

C50.022µF

C62.2µF

C40.015

C12.2µF

INPUT

4

R115k

R215k

5

6

10

R31.8k

R415k

R1051k

R1110k

R918k

R718k

R61.8k

R8100Ω

R515k 75kHz

9

7

–

+U1C

LT1365

C7220pF

3

2

1

11

–

+U1D

LT1365

3

2

1C30.1µF

C20.47µF

+

+

12V

12V

12V

POT 1

12V

55V 55V

L11mH

LOAD12V

–

+U1B

LT1365

0.1µF

4

–

+U1C

LT1365

3

2

MOTORSPEEDAND

DIRECTION

1

11

M

+

–U1D

LT1365

3

2

1

–

+U1A

LT13658

15k

15k

10

1.8k

15k

9

220pFX1 X2

Figure 195. 200W-Powered Subwoofer

Figure 196. Class-D Motor Drive

Application Note 87

AN87-116

COMPVIN

VREF GTDR

ISEN

R/C

FB

R351k

R71k

R515k

C70.1µF

C81µF

1

2

8 6

4Q12N3904

3

5

7C6

1.5µF

C90.15µF

R2100k

R42.49k

R62.4k

R81k

U1LT1243

GND

R11Ω

2k

C522µF20V

C1

+

–12V BATTERY

1200µF, 16V ×4

C2 C3 C4

–

+U2A

LT1215

5 8

6

4

C1133µF16V

C1233µF16V

C132200µF25V

12V

T1

D1MUR110

PRi 20T 2x#14SEC 4T #26MICROMETALS T150-52

D2MUR110

20 4

SEC

VN2222

C14

1000µF, 63V ×6

55V

C15 C19

–

+

R111k

R120.01Ω1W

R130.01Ω1W

R140.01Ω1W

R150.01Ω1W

C10220pF

1

3

2

R91k

R1649.9k

R10200Ω

U2BLT1215

+ +

+

+ + +

+

+

+ + +

+

Figure 197. 200W, 2-Quadrant Front End for Automotive Applications

motor down by turning pot 1 back toward its center,disaster strikes. Rotational energy stored in the inertia ofthe motor is converted back into electrical energy by themotor and is presented to the output of the class-Damplifier. L1, X1 and X2 do their job by transferring theenergy back into the 55V bus. The energy goes into C14–C19 of Figure 193, charging them to some voltagesignificantly above 55V, and something breaks. The prob-lem here is that the circuit in Figure 193 is only a 1-quadrantclass-D amplifier.

Managing the Negative Energy Flow

Sound like a course in management? The negative energytransferred through the class-D amplifier needs a home.One simple home is a 62V power Zener diode strapped

across the 55V bus and bolted to a massive heat sink. Onecould easily imagine the heat sink as the brake shoesheating up as the electric vehicle winds down the mountainroad. Another place to put the energy is back into the 12Vbattery. This will require upgrading the 12V to 55V front-end power converter from 1 quadrant to 2 quadrants.

The 2-Quadrant Class-D Converter

Converting Figure 193 to two quadrants involves replacingD2 with a switch and activating the switch out of phase withthe switch formed by Q2 and Q3. The half-bridge powerdriver shown in Figure 195 is just such a switch. Refer toFigure 197. The ISENSE signal (U1, pin 3) needs to be offsetto accommodate negative current (add R16, Figure 197)The ISENSE signal needs to be scaled for twice the range

Application Note 87

AN87-117

(–30A to 30A rather than 0A to 30A); this is done bychanging R10.

Now we are happily winding down the mountain road,watching the scenery unfold before us. We are happy inknowing that we are recycling the energy released fromthe descent by charging our batteries, while watching themountain bikers burn their descent energy off in brakelinings. Once again technology wins over sweat and brawn.

A Trip Over the Great Divide

Climbing the great divide in an electric vehicle requiressome planning. Stops to recharge are necessary. Once ontop, the whole scheme changes: descending the hill,charging our battery, all goes well until the battery is fullycharged; then we have to stop. Further descent wouldovercharge our battery, boiling out the electrolyte. Notonly would this ruin our battery, in the end we would haveno place to put the energy and our class-D amplifier would

find some way to fail. We need to stop and drain off somecharge, trade batteries with someone climbing the otherside or put a power Zener on our battery. Figure 198 detailsthe active Zener circuit. Using the reference in U1 of Figure197 and the unused half of U2 we are able to make ahysteretic clamp that puts all of the heat into a resistor, R5.This circuit will save the battery from destruction and dropour level of smugness back to that of the mountain bikers.

Conclusion

Class-D has been around for a long time: the venerableelectric heater with its bang-bang controller is a remark-ably efficient and reliable class-D amplifier. Class-D driveshave been used for decades in golf carts, fork lifts, cranesand industry. The advent of the half-bridge driver greatlysimplifies the Class-D Amplifier. Here at Linear Technol-ogy we have a family of half/full bridge MOSFET drivers.For further information, contact us at the factory or refer tothe LT1158, LT1160, LT1162 or LT1336 data sheets.

Figure 198. Wolf Creek Pass Adapter

–

+U2A

LT1215

R35M

R149.9k

R4100Ω

R51Ω200W

IRFZ40

R295k

VIN

8

VREF5.00V

U1FIG 5PIN 8

6

7

14.3V 14.6V

14A

0A

Application Note 87

AN87-118

SINGLE-SUPPLY RANDOM CODE GENERATORby Richard Markell

Presented here is a truly random code generator thatoperates from a single supply. The circuit allows operationfrom a single 5V supply with a minimum of adjustments.

The circuit produces random ones and zeroes by compar-ing a stream of random noise generated in a Zener diodeto a reference voltage level. If the threshold is correctly setand the time period is long enough, the noise will consistof a random but equal number of samples above andbelow threshold.

That Fuzz is Noise

The circuit shown in Figure 199 is the random noisegenerator. Optimum noise performance is obtained froma 1N753A Zener diode, which has a 6.2 volt Zener “knee.”The diode is used to generate random noise. We havefound that optimum noise output for this diode occurs atthe “knee” of the I-V curve, where the Zener just starts tolimit voltage to 6.2 volts.

Operating a 6.2V Zener from a 5V supply required somethought. Obviously, some type of voltage boosting schemewas needed to provide the diode with the 8V or more thatit requires in this circuit. U1, an LTC1340 low noise,voltage-boosted varactor driver, provides 9.2V at 20µAfrom an input of 5V. This Zener current is the optimal fornoise output from the diode (at 20µA the output is about20mVP-P).

The 1M and 249k resistors bias the input to operationalamplifier U2 to 1.25V to match the input common moderange of comparator U3. The 1µF capacitor provides an ACpath for the noise. Note: be careful where you place anyadditional capacitors in this part of the circuit or the noisemay be unintentionally rolled off. This is one circuit wherenoise is desirable.

U2 is an LT1215 23MHz, 50V/µs, dual operational amplifierthat can operate from a single supply. It is used as awideband, gain-of-eleven amplifier to amplify the noisefrom the Zener diode; the second op amp in U2 is unused.U3, an LT1116 high speed, ground-sensing comparator,

receives the noise at its positive input. A threshold is setat the negative comparator input and the output is ad-justed via the 2k potentiometer for an equal number ofones and zeroes. The 5k resistor and the 10µF capacitorprovide limited hysteresis so that the adjustment of thepotentiometer is not as critical. Latch U4, a 74HC373,ensures that the output remains latched throughout oneclock period. The circuit’s output is taken from U4’s Q0output.

Some Thoughts on Automatic Threshold Adjustment

Several circuit designers have asked about thresholdadjustment without manual knobs or potentiometers. Oneway to implement this would be to have the microproces-sor count the number of ones and zeroes over a given timeperiod and adjust the threshold (perhaps via a digital pot)to produce the required density of ones.

A more “analog” method of adjusting threshold might beto implement an integrator with reset. This circuit inte-grates the number of ones and zeroes over time toproduce a zero result for an adjustment that producesequal numbers of ones and zeroes. Again, a digital potcould be used to adjust threshold, with the threshold beingdecreased for the case of “not enough ones” and in-creased for the case of “too many ones.”

After many more conversations with the “cyber illumi-nati,” the circuit in Figure 200 was devised. This circuit canbe used to replace the pot shown in the dashed box inFigure 199. In operation, an LT1004-2.5 is used as areference at the front end of a precision voltage dividerstring. A series of voltages is generated along the dividerstring and a jumper is used to connect this voltage to abuffer and then to the negative input of the LT1116comparator. As was the case with the 2k pot, the voltageat pin 2 (the negative input of the comparator) sets thethreshold for the comparator. The selection of voltagetaps on the resistor string is arbitrary; they were selectedto allow a good adjustment range (defined as allowingjumper adjustment to 50% ones and 50% zeros) for asample of ten 1N753A Zener diodes used to producenoise. The jumper could (and probably should) be re-placed with analog switches controlled by a microprocessorin medium- to high-volume applications.

Application Note 87

AN87-119

Figure 199. Single-Supply Random Code Generator

–

+–

+

CP

VCC

SHDN

PGND

AVCC

OUT

AGND

IN

1

2

3

4

8

7

6

5

U1LTC1340

5V

5V0.1µF

0.1µF

1000pF

9.2V

1N753A6.2V

1µF

1M

249k1.25V

U2LT1215

U3LT1116

5V

1µF

470k

47k

1k

2k10 TURN

10µF10µF

CLOCK IN

0.1µF

1µF TANT

10pF

3

2

8

4

1 3

2

1

46

5 LE7

8 2-LEVELOUTPUT

0.1µF

3

11

10 1

20

2

U474HC373

5V

VCC

DO

LE

QO

OE

5V

~20mVP-PNOISE

GND

1µF 1µF

5k

+

+

+

+ ++

+

JUMPER SELECTSTHRESHOLD VOLTAGE

1µF

TO LT1116PIN 2 (FIGURE 1)

3

24

8

1

5V

GROUND PINS 5 AND 6

LT1004-2.5

15k

5V

0.01µF1µF+

+

–

+LT1490

12k1%

(1.30V)

4991%

(1.25V)

4991%

(1.20V)

4991%

(1.15V)

4991%

(1.10V)11k1%

Figure 200. Jumper Selects Threshold for Figure 199’s Circuit

Application Note 87

AN87-120

APPENDIX A: COMPONENT VENDOR CONTACTS

The tables on this and the following pages list contactinformation for vendors of non-LTC parts used in theapplication circuits in this publication. In some cases,

components from other vendors may also be suitable. Forinformation on component selection, consult the text ofthe respective articles and the appropriate LTC data sheets.

sroticapaC

rodneV tcudorP enohP LRU

XVA sroticapaCpihC 2630-649)348(sroticapac/stcudorp/moc.procxva.www

XVA sroticapaCmulatnaT 1115-282)702(

stpecnoCcinortcelE sroticapaCmliFV004 0887-245)809( moc.sroticapac-ice.wwwtemeK sroticapaCmulatnaT 4240-689)804( moc.temek.wwwnocraM sroticapaCV/ChgiH 0002-696)748( lmth.nocram/ynapmoc/niam/moc.noc-imehc.www

scinortcelEataruM sroticapaC 0031-634)077( hsilgne/stcudorp/atarum/pj.ro.tenjii.www

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amiW sroticapaCmliF/repaP 4742-743)419( moc.asuamiw.www

sedoiD

rodneV tcudorP rebmuNenohP LRUttelweHylremrof(tneligA

)drakcaP sDELRI 2130-532)008( ri/moc.tneliga.rotcudnocimes.www

rotcudnocimeSlartneC setercsiDlangiSllamS 0111-534)615( moc.imeslartnec.www

pmaLerutainiMogacihC sDEL 9898-984)102( lmc/moc.gnithgil-ils.www

stcudorPyalpsiDataD sDEL 5186-124)008( moc.sdel-pdd.www

ijuF sedoiDykttohcS 5550-217)102( lmth.e-xedni/gne/pj/oc/cirtceleijuf.www

rotcudnocimeSlareneG sedoiD 0003-748)615( moc.imesneg.www

*alorotoM setercsiD 7442-144)008( lmth.xedni/stcudorp/moc.sps-tom.www

*rotcudnocimeSNO setercsiD 0066-442)206( emoh/moc.imesno.www

cinosanaP sDEL 7125-843)102( /srotcudnocimes/meo_lairtsudni/moc.cinosanap.wwwmth.emoh_rotcudnocimes

cimeT sedoiDotohPRI 0075-079)804( moc.cimet.www

yahsiV langiSllamS/reneZsedoiD 8854-142)804( moc.yahsiv.www

xeteZ setercsiDlangiSllamS 0017-345)615( moc.xetez.www

0002yraunaJfosadeganahcneebtonevahsrebmuntraP.rotcudnocimeSNOybderutcafunamwoneraalorotoMybderutcafunamylremrofsetercsiD*

Application Note 87

AN87-121

sremrofsnarTdnasrotcudnI

rodneV tcudorP rebmuNenohP LRU

naveleDIPA srotcudnI 0063-256)617( moc.naveled.www

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seigolonhceTIB sremrofsnarT 6562-744)417( moc.seigolonhcetib.www

tfarclioC srotcudnI 0046-936)748( moc.tfarclioc.www

repooC sremrofsnarT/srotcudnI 0005-257)165( moc.scinortlioc.www

elaD sremrofsnarT/srotcudnI 7261-566)506( srotcudni#lmth.pf/pf/moc.yahsiv.www

adnawoG srotcudnI 4322-235)617( moc.adnawog.www

mocdiM sremrofsnarT/srotcudnI /5834-688)506(1662-346)008( moc.cni-mocdim.www

scinortcelEataruM srotcudnI 1341-732)418( moc.atarum.www

cinosanaP sremrofsnarT/srotcudnI 4337-373)417( /stnenopmoc_cinortcele/meo_lairtsudni/moc.cinosanap.wwwmth.sremrofsnart_dna_slioc_srotcudni_stnenopmoc_cinortcele

spilihP srotcudnI 1182-642)419( moc.spilihp.stnenopmoc.mca.www

spilihP srotcudnIranalP 6302-742)419( moc.spilihp.stnenopmoc.mca.www

esluP srotcudnI 0018-476)916( moc.gneeslup.www

adimuS srotcudnI 7660-659)748( adimus/moc.knilnapaj.www

nikoT srotcudnI 0208-234)804( moc.nikot.www

cigoL


dlihcriaF cigoL 2054-577)702( moc.imesdlihcriaf.www

)sirraHylremrof(lisretnI cigoL 7477-244)008( moc.lisretni.www

alorotoM* cigoL 7442-144)008( lmth.xedni/stcudorp/moc.sps-tom.www

rotcudnocimeSNO* cigoL 0066-442)206( emoh/moc.imesno.www

abihsoT cigoLcigoLetaGelgniS

/0002-554)949(0002-554)417( ceat/moc.abihsot.www

0002yraunaJfosasrebmuntrapnisegnahconneebevahereht;rotcudnocimeSNOybderutcafunamwoneraalorotoMybybderutcafunamylremrofseciveDcigoL*

srotsiseR

rodneV tcudorP rebmuNenohP LRUyeldarBnellA srotsiseRnobraC 8884-295)008( moc.ba.www

XVA srotsiseRpihC 4250-649)348( mth.rtsrpihc/srotsiser/stcudorp/moc.procxva.www

seigolonhceTIB rotsiseR/srotsiseRskrowteN 5432-744)417( moc.seigolonhcetib.www

snruoB sPIS,sretemoitnetoP 3527-057)108( moc.snruob.www

elaD srotsiseResneS 1039-566)506( moc.liofyahsiv.wwwmoc.yahsiv.wwwro

CRI srotsiseResneS 0097-299)163( moc.ttcri.www

nellAGR srotsiseRedixOlateM 0038-567)818( moc.ocagr.www

DAT srotsiseRpihC 1251-805)008( moc.mocdat.www

neduYoyiaT srotsiseRpihC 0514-375)804( moc.neduy-t.www

ygolonhceTmliFnihT srotsiseRpihCmliFnihT 5448-526)705( moc.mlif-niht.www

socoT sretemoitnetoPDMS 4666-488)748( moc.socot.www

Application Note 87

AN87-122

suoenallecsiM


divaA skniStaeH 5662-655)417( moc.divaa.www

nospE slatsyrC 0036-787)013( moc.nospe.aee.wwwnoenifnI

snemeiSylremrof()rotcudnocimeS

scinortceleotpO 0197-752)801( mth.tnetnoc/otpo/su/moc.noenifni.www

.cnI,scitengaM .cte,seroCdioroT 4893-542)008( moc.cni-gam.www

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Application Note 87

AN87-123

AADC. See Data Converters: D/AAmplifiers 46–72

16-Bit Accurate 71, 71–72ADC Buffer 72Battery Current Monitor 46, 63, 65Bridge 49C-Load 54–56Cable Driver 48CCD Clock Driver 50–53Chopped 92–93Class-D 112–117

2-Quadrant Automotive Front End 116–117200W, 12V to 55V Front End for Automotive

Applications 113200W-Powered Subwoofer 115Active Zener Circuit 117Half-Bridge 113–114Motor Drive 115

Current Feedback 47–49, 50–53, 70–71Differential to Single-Ended ADC Driver 68High Power 56–59Instrumentation 67–69. See also Instrumentation Circuits

Medical ECG Monitor 69Precision Current Source 69Pressure Monitor 67Single-Supply 67

JFET 54–56Multiplexer 60"Over-The-Top" 46, 65–66Peak Detector 54Photodiode, Logging 55Power Driver 57, 58Pressure Sensor 90Programmable Gain 11–12Rail-to-Rail 59–60, 62–63, 65–67Telescoping 56Track and Hold 54Twisted Pair Driver 47Video 61–62, 64–65, 70–71

DC-Restore Subcircuit 71Level Shifter 70Signal and Power Share Coax Cable 64–65Voltage Controlled Limiter 61

XDSL 47, 79–80

CC Language

Code to Configure PC Analog Interface 7–10Comparators 80–85

1MHz to 10MHz Crystal Oscillator 82Coincedence Detector 83, 85

Differential Timing Skew 82Fast Waveform Sampler 82–83, 84Isolated 94–95

Overtemperature Detector 94Thermistor Temperature Controller 94Voltage Detector 95

Low-Battery Warning, Shutdown and Reset for Li-IonSupply 81

Pulse Stretcher 83–85, 85Window Detector 81

ConverterRMS/DC 51

Converters, Data. See Data ConvertersCurrent Meter

0nA–200nA 62Current Source

Precision 69

DDAC. See Data Converters: D/A,Data Converters 3–19

A/D, 12-Bit 7–104-Channel 10–128-Channel 10–12Data Acquisition System 10Differential 12Differential to Single-Ended Conversion 68Micropower 10–12Multichannel 4Programmable Attenuator 14Programmable Gain Amplifier 11, 12, 14

A/D, 14-Bit 138-Channel 13Multiplexer 13

A/D, 16-BitBuffer 72

D/A, 10-Bit 19D/A, 12-Bit 3–4, 5, 7–10

4-Quadrant Multiplying 6Autoranging, with Shutdown 3Dual 14–15for Digital Control Loop 18

Data ConvertersD/A, 12-Bit (continued)

Micropower 5–6, 18Quad 5–6Wide Swing, Bipolar Output, with Digitally Controlled

Offset 4with Programmable Full Scale and Offset 6with Wide Output Swing 18

D/A, 16-Bit 16–182-Quadrant Multiplying 17

Index

Application Note 87

AN87-124Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear-tech.com

an87f LT/LCG 1100 4K • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 2000

4-Quadrant Multiplying 17I/V Converter with 1.6µs Settling Time 72

Digitally Controlled LCD Bias Generator 19

FField Detector

BiasedMicropower 110

Zero-BiasNanopower 111

Filters 96–109Antialiasing 4Bandpass

Low Voltage, Narrow 100–101Selective, Clock-Tunable to 80kHz 107

Continuous-TimeUniversal 102–103

Highpass1kHz 8th Order Butterworth 104–1058th Order 30kHz Chebyshev 102

Highpass-Lowpass 96Lowpass

1MHz/500kHz Continuous-Time, Low Noise, Elliptic 96–974th Order Butterworth 5950kHz, 100dB Elliptic 1036th Order Elliptic 63Butterworth, with Track and Hold 98–99Delay-Equalized Elliptic 96Digitally Controlled 16Dual 4th Order 100kHz Butterworth 102Elliptic, 25kHz 99Quad 3rd Order 100kHz Butterworth 103Single 3.3V Low Power Linear Phase 107Single-Supply 4th Order Butterworth 66Ultrlow Frequency, Linear-Phase 106

NotchNarrow-Band 101

Square-Wave-to-Quadrature Oscillator 108Switched Capacitor

Universal 98–101, 106–108

IInstrumentation Circuits 86–95. See also Amplifiers:

InstrumentationBridge

High Performance Capacitance 87–89with Increased Sensitivity 89

Chopped Amplifier 92–93Pressure Sensor

Water Tank 89–92Voltage-to-Frequency Converter 86, 90

Interface Circuits 20–451488 Line Driver with TVS Surge Protection 20IrDA 34–35

Receiver 34

Transmitter 34Multiprotocol 22–29, 36–37

Cable-Selectable DTE/DCE Port 32, 33, 42Controller-Selectable DCE Port 39, 45Controller-Selectable DCE Port with Ring-Indicate 31Controller-Selectable DTE Port 40Controller-Selectable DTE/DCE Port 30, 41Controller-Selectable DTE/DCE Port with RLL, LL, TM 43Mode Selection 26Net1 and Net2 Compliant 37–38, 44

Resistive Surge Protection for 20–22LT1137A 21Testing Line Driver Output Waveform 21

RS485 36, 37Standards 23–25Surge-Test Circuit 20V.10 (RS423) 23–24V.11 (RS422) 24, 36V.28 (RS232) 24, 36, 37V.35 25–29

LLCD Bias Generator

Digitally Controlled 19

MMiscelleaneous 110–119Multiplexer 4, 10–12, 60Multiplexing

Softwarelessfor 14-Bit A/D 13

Mux. See Multiplexer

OOperational Filter Blocks 102–103Oscillator

Crystal1MHz to 10MHz 82with Complementary Outputs and 50% Duty Cycle 93

Sequencer for Ring-Tone Generator 74Square-Wave-to-Quadrature 108

PPC Analog Interface 7–10PGA. See Amplifiers: Programmable GainPower Supply

60V and –180V, for Ring-Tone Generator 73Li-Ion with Low-Battery Warning, Shutdown and Reset 81

RRandom Code Generator

Single-Supply 118

TTelecommunications Circuits 73–79

HDSL Driver 79Ring-Tone Generator 73–78

Mixed-signal and digital signal processing ICs | …...data conversion, interface and signal conditioning circuits from issue VI:1 (February 1996) through issue VIII:4 (November 1998).

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