Mixed Analog-Digital Pulse-Width Modulator for Massive-MIMO Transmitters … · Pulse-Width Modulator for Massive-MIMO Transmitters ... ΣΔ or Pulse Width Modulation ... Sine Wave

Mixed Analog-Digital Pulse-Width Modulator for Massive-MIMO Transmitters

Nikolaos Alexiou Infineon Technologies AG Austria

OUTLINE

› All-digital transmitters overview

› Digital to Time Conversion

› Proposed mixed-signal Outphasing RF Pulse-Width Modulator

› Mixed-signal co-simulation environment and simulation results

› Conclusions

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› Conclusions

12.09.2016 3

Massive MIMO block diagram

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› Near linear increase of area and power consumption with array size

› Traditional analog/RF approach becomes inefficient

› Need for

• Multi-Band / Multi-Mode

• Wideband operation

• Power efficiency

• Less complexity

› Solution: All-digital transceivers

• PWM-based digital RF transceiver

• RF DAC - based IQ transmitter

All-Digital Transmitters

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IQ transmitter Polar transmitter

Upsampling

+

Filtering

RF-DACIBB

Upsampling

+

Filtering

RF-DACQBB

IQ LO

generation

I LO

Q LO

CORDIC

+

Polar

signal

processsing

1-bit or multi-

bit ΣΔ / PWM

Modulation

ADPLL /

DTC

Amplitude

data

Phase /

Frequency

data

I

QRF-DAC

SMPA

SMPA

+

CORDIC,

polar to

outphasing,

upsampling

to LO

frequency

)(1

ts

)(2

tsDTC

DTC

LO

I

Q

Outphased

φ+θ

Outphased

φ-θ

Outphasing transmitter

Ref. [1]-[4] Ref. [5]-[11]

Main modulation techniques

Direct digital to RF conversion

Two-point phase/frequency modulation in PLL

ΣΔ or Pulse Width Modulation for Amplitude modulation

Carrier phase modulation

All-Digital Modulators: Outphasing Architecture

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SMPA

SMPA

+

CORDIC,

polar to

outphasing,

upsampling

to LO

frequency

)(1

ts

)(2

ts

Digital to time

converter

Digital to time

converter

LO

I

Q

Outphased

φ+θ

Outphased

φ-θ

&

Digital to Time

converter

Digital to Time

converter

Output

driver

SMPA

φ+θ

N-bit

φ-θ

N-bit

LO

PWM

› Single-bit output for driving only one SMPA

› No power combining, no PA loading effect › Digital to Time Converter

Continuous time implementation:

1. Phase shifting φ+θ / φ-θ using tapped delay lines (coarse time delay) and Gm-RC blocks (fine time delay) in cascade

2. Phase Multiplexing

3. Synchronous or Asynchronous LO phase selection

› Traditional outphasing topology › PWM based outphasing topology

Ref. [12]-[16]

Pulse Width Modulation (time-domain)

› Two types:

– Baseband PWM

– RF PWM

› Main difference: Sampling frequency fpwm

› BB PWM:

– Bursts of phase modulated carrier pulses even for small/moderate amplitude values

– More efficient for switching class D/E PAs

› RF PWM:

– Each pulse is pulse width modulated

– Hard to produce narrow pulses in the output

– Pulse swallowing in PWM generation circuitry and output driver limits dynamic range

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Pulse Width Modulation (time-domain)

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BB Tpwm

RF Tpwm

PWM signal

PWM signal in

carrier frequency

Example waveforms

› Output carrier pulses in BB and RF PWM

› No phase modulation, only amplitude modulation

Pulse Width Modulation (frequency-domain)

› BB PWM

– Digital mixing of PWM signal

with Phase Modulated carrier.

– Intermodulation products close

to carrier.

› RF PWM

– PWM and Phase Modulation

on the same pulse inside

carrier period.

– Harmonic distortion peaks

@ multiples of fpwm = fcarrier

9 12.09.2016

fc 2fc

PS

D

f

BB PWM

intermodulation

products

PWM signal in

carrier frequency

fc 2fc

PS

D

f

RF PWM

harmonic

distortion

peak

PWM signal in

carrier frequency



– All-Digital implementation

– Mixed-Signal implementation



› Conclusions

12.09.2016 10

Digital to Time Conversion

11 12.09.2016

&

Digital to Time

converter

Digital to Time

converter

Output

driver

SMPA

φ+θ

N-bit

φ-θ

N-bit

LO

› Continuous-time

› Delay Line - based

› Two implementations

› Digital

› Mixed-signal







› Conclusions

12.09.2016 12

Ref. [16]: Continuous-Time Digital Phase Shifting

• 8/9-bit time resolution

• For finer resolution finer-node CMOS processes must be used

• Sensitive to supply/ground noise and temperature drift

• Differential implementation

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bit0 bit1 bitm-1 bitn-1bitm bit2m

LO IN

bit2m+1

Phase Modulated Output

Coarse phase shifting Fine phase shifting

Ref. [16]: All-Digital outphasing RF-PWM Modulator

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› Conclusions

12.09.2016 15

Continuous-Time Analog Phase Shifting

16 12.09.2016

› LC Delay Line

› Distributed transmission line model

› RF carrier: Sine Wave

› “Hair Pin” integrated inductor

Minimal footprint

Lunit ~ 70 pH

› Time-delay step below 2 ps

Technology independent

PVT variation-resilient

› Small amplitude sinusoid

For mitigating nonlinearities of conducting switch

Very low power consumed only on the termination resistors

50-Ohm

Load

In

Out

Lunit

Cunit

Phase

selection

Tapped output

Unit delay

Block input

Connection with

next unit delay block

nMOS switchCunit

Floorplan of mixed-signal Phase-Shifting core

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32 digital phase control signals

32 digital phase control signals

DL Out

LO in

50-Ohm

termination

› One-hot switching scheme

› One-level multiplexing scheme

› 8-bit time resolution

› Carrier: 2.65 GHz

› Synchronous continuous-time operation (CLK - LO)

› Trade-off due to output common node parasitics

• Frequency range

• Time resolution

• Dynamic behavior

“Hair Pin” integrated inductor

› Ind_1Xdimension = Ind_3Xdimension

› Ind_1Ydimension = Ind_2Ydimension

› Minimal X dimension

1. Compact layout

2. Interconnection parasitics minimization

› Higher time resolution

› Better dynamic response for the phase modulator

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› Conclusions

12.09.2016 19

Mixed-signal Outphasing RF PWM Modulator

20 12.09.2016

Balun

8bit control

data

64 LC unit delay cells delay line

Limiter

0°

180°

In

Hybrid

0°

-90°

In

Phase modulator

NAND Output

driver

LO

CLK

0°-90° LCDLIn Out

0°-90° LCDLIn Out

0°-90° LCDLIn Out

0°-90° LCDLIn Out

Balun

0°

180°

In

Balun

Limiter

0°

180°

In

Phase modulator

0°-90° LCDLIn Out

0°-90° LCDLIn Out

0°-90° LCDLIn Out

0°-90° LCDLIn Out

Balun

0°

180°

In

8bit control

data

50-Ohm

load

50-Ohm

Load

In

Out

Hybrid

0°

-90°

In


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Balun

8bit control

data

64 LC unit delay cells delay line

Limiter

0°

180°

In

Hybrid

0°

-90°

In

Phase modulator

NAND Output

driver

LO

CLK

0°-90° LCDLIn Out

0°-90° LCDLIn Out

0°-90° LCDLIn Out

0°-90° LCDLIn Out

Balun

0°

180°

In

Balun

Limiter

0°

180°

In

Phase modulator

0°-90° LCDLIn Out

0°-90° LCDLIn Out

0°-90° LCDLIn Out

0°-90° LCDLIn Out

Balun

0°

180°

In

8bit control

data

50-Ohm

load

50-Ohm

Load

In

Out

Hybrid

0°

-90°

In

PWM signal generation: Limiter

22 12.09.2016

ADP ADP ADP ADP

RFAF

CF

RFCF

Ibias

R R

Vsup

Vo- Vo

+Vin

+Vin

-

L

W

L

W

Vout

+

-

Cac

Cac

Vin

Vlow

Vhigh

Level shifter

Vin

Vbias

Vout

Analog inverter

Analog inverter

Vin+

Vin-

VLSin+ VLSin

-

M1 M1

M2 M2

Vsup

VLSout

Digital outphased

signal

Transmission gate

• Amplification to saturating levels of the input sine wave

• Maximum bandwidth design

• Generation of single ended continuous-time digital signal

0

VDD

0.56VDD

20mV

PWM signal generation: NAND gate / Output Driver Distortion

23 12.09.2016

Pulse swallowing region Pulse shrink/extend region

Minimum number of output driving elements

Equal rise/fall times @ NAND inputs

As small as possible rise/fall times @ NAND inputs

As small as possible rise/fall times @ NAND inputs

S1 S2

S1 S2

S2 S1

VsupVsup

M1 M1

M2 M2

M3 M3

P

M4

M5

PWM out


24 12.09.2016

LVDS

Phase modulator

Quad L

O

Phase modulator

Quad L

O

LVDS

› Process: 40nm CMOS

› Voltage Supply:

1.25 V

Lim

iters

MO

D

OU

T

Modulator: Power consumption

Part Power consumption (mW)

Delay Lines Nearly zero

Clock Distribution Tree, decoders, retiming circuitry *

107

Limiters 64

PWM generation 8

TOTAL 179

All Digital Outphasing RF PWM 40nm chip TOTAL power consumption for the same bandwidth and carrier frequency (Ref. [16])

120

25 12.09.2016

* Conservative design to assure predicted performance

(test chip for proof of concept)





› Conclusions

12.09.2016 26

Dynamic Performance Simulation

27 12.09.2016

DSP in MATLAB

PWM modulator IC

+ package parasitics

Spectre simulation

8 bit 8 bit

CW PWM

CLK

Calibration +

predistortion

CW - decoder CLK - delay line CLK synchronization

Dynamic Performance Simulation

28 12.09.2016

AM-AM AM-PM PM-PM

modulator nonlinearities

Predistortion of amplitude and phase in carrier

frequency

Generation of phase control data in carrier

frequency

Dynamic transient

simulation of modulator IC

Extraction of EVM + ACLR

Circuit design

optimization

Post-layout dynamic simulation results of modulator IC

29 12.09.2016

› 20 MHz baseband signal (10 tones)

› 2.65 GHz carrier

Conclusions

› Mixed-Signal outphasing PWM modulator

› “Hair Pin” inductors

• Minimal footprint

• Silicon implementation of analog LC delay lines

› 8-bit time resolution

• PVT variation-resilient

• Technology independent

• Low power consumption in the delay lines

› Simulated EVM = - 45 dBc

• 20 MHz baseband signal on a 2.65 GHz carrier

› IC under fabrication

› Pending measurements

30 12.09.2016

References

1. P. Eloranta et. all, “A multimode transmitter in 0.13 μm CMOS using direct-digital RF modulator”, IEEE J. Solid-State Circuits, vol. 42, no. 12, Dec. 2007.

2. A. Jerng, and C. Sodini, “A wideband ΔΣ digital-RF modulator for high data rate transmitters,” IEEE J. Solid-State Circuits, vol. 42, no. 8, Aug. 2007.

3. M. S. Alavi et. all, “A wideband 2×13-bit all-digital I/Q RF-DAC,” IEEE Trans. on Microwave Theory and Techniques, vol. 62, no. 4, Apr. 2014, pp. 732-752.

4. V. K. Parikh et. all, “A fully digital architecture for wireless transmitters,” in Proc. IEEE Radio and Wireless Symp., Jan. 2008, pp. 147-150.

5. R. B. Staszewski et. all, “All-digital TX frequency synthesizer and discrete-time receiver for bluetooth in 130-nm CMOS,” IEEE. J. Solid-State Circuits, vol. 39, no. 12, Dec. 2004.

6. P. Cruise et. all, “A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS,” in Proc. IEEE Radio Frequency Integr. Circuits Symp., Jun. 2005, pp. 21-24.

7. R. B. Staszewski et. all, “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, Dec. 2005.

8. Z. Boos et. all,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Fransisco, CA, Feb. 2011, pp. 376-378.

31 12.09.2016

References

9. J. Mehta et. all, “A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Fransisco, CA, Feb. 2010, pp. 58-59.

10.M. Park et.all, “An amplitude resolution improvement of an RF-DAC employing pulsewidth modulation,” IEEE Trans. Circuits and Systems I: Reg. Papers, vol. 58, no. 11, Jun. 2011, pp. 2590-2603.

11.Y.-C. Choi et. all, “A fully digital polar transmitter using a digital-to-time converter for high data rate system,” in Proc. IEEE Radio Frequency Integr. Technology Symp., Dec. 2009, pp. 56-59.

12.M. E. Heidari et. all, “All-digital outphasing modulator for a software-defined transmitter,” IEEE J. Solid-State Circuits, vol. 44, no. 4, Apr. 2009.

13.A. Ravi et. all, “A 2.4-GHz 20-40-MHz channel WLAN digital outphasing transmitter utilizing a delay-based wideband phase modulator in 32-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 12, Dec. 2012.

14.P. A. J. Nuyts et. all, “A fully digital delay line based GHz range multimode transmitter front-end in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 7, Jul. 2012.

15.P. A. J. Nuyts et. all, “A fully digital PWM-based 1 to 3 GHz multistandard transmitter in 40-nm CMOS,” in Proc. IEEE Radio Frequency Integr. Circuits Symp., Jun. 2013, pp. 419-422.

16.S. Kulkarni, I. Kazi, D. Seebacher, P. Singerl, F. Dielacher, P. Reynaert, and W. Dehaene, “Multi-standard wideband OFDM RF-PWM transmitter in 40nm CMOS, in Proc. IEEE ESSCIRC, Sep. 2015, pp. 88-91.

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Thank you

33 12.09.2016

Mixed Analog-Digital Pulse-Width Modulator for Massive-MIMO Transmitters … · Pulse-Width Modulator for Massive-MIMO Transmitters ... ΣΔ or Pulse Width Modulation ... Sine Wave

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