MIPS architecture (single cycle, no pipeline) - Eurecomsoc.eurecom.fr/CompArch/lectures/MIPS/main.pdfMIPS architecture (single cycle, no pipeline) S. Coudert and R. Pacalet January
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Computer Architecture
MIPS architecture (single cycle, nopipeline)
S. Coudert and R. PacaletJanuary 4, 2018
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Outline
Introduction
Data paths
Assembling data paths
Control logic
Examples
Designing the control logic
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Outline
Introduction
Data paths
Assembling data paths
Control logic
Examples
Designing the control logic
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Introduction
Instruction Set Architecture (ISA): functional descriptionCPU architecture: ISA hardware implementationMain architecture components:
• Combinatorial– Operators (computing units, data paths)– Multiplexors (select inputs depending on current instruction)
• Storage: registers, register files, on-chip and off-chip RAMs. . .• Wires and buses (connect storage and operators)• Finite state machines (controllers)
Main steps of CPU architecture design:• Identify data paths for each instruction and each instruction step• Assemble data paths with wires, buses and multiplexors• Design control and controllers
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The global picture
i
j
k$j
$ib
$k
21 3
a
Control
PC
reg1 (read)
reg2 (read)
reg3 (write)
RegistersProgram
memory
addressrdata1
rdata2
wdata
rdata
wdata
rdata
address
Data
memory
AL
U
Program counter provides address to program memoryInstruction fields specify operation (control) and operands (registers, immediate)ALU computes results
• To be stored in a register (a)• To be used as a memory address (b)
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Program Counter (PC) and instruction fetch
Instruction (32 bits)
AD
DMU
X
4PC+4
PC
Program
memory
address
rdata
MIPS addressing unit: byteRegisters and instructions: 32 bits (4 bytes)Pointing to next instruction: add 4 to PC
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.6/41 S. Coudert and R. Pacalet January 4, 2018
Outline
Introduction
Data paths
Assembling data paths
Control logic
Examples
Designing the control logic
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Data path for R-format instructionsAssembly: OP $k, $i, $j ($k ← $i OP $j)ALU function specified by func instruction field
k
j
i
$j
$k
$i
write enable
Instruction
0
shift
dst
src2src1
op
i j shiftkop funct
fun
ct
Registers
Control
wdata
wr
rd2
rd1
rdata1
rdata2
AL
U
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Data path for load instructionsAssembly: lw $j, 100($i) ($j ←Mem[$i +100])Address shift converted from 16 to 32 bits (signed extension)
$ij
i
100100
16 32
$i+100
$j :
add
Mem($i+100)write signalread signal
instruction
35
add
dest
address sh
ift
i j35 100
extended
Sign
Memory
MemData
dataWrite
AddressALUReadregister 2
Readregister 1
Writeregister
Writedata
Registers
Readdata 1
data 2Read
Control
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Data path for store instructions
Assembly: sw $j, 100($i) (Mem[$i +100]← $j)
$ij
i
100100
16 32
$i+100
add
$j :
write signal
instruction
i j 10043
add
add
ress shift
43
src
extended
Sign
ALU
Memory
MemData
dataWrite
AddressReadregister 2
Readregister 1
Writeregister
Writedata
Registers
Readdata 1
data 2Read
Control
Mem($i+100)
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Data path for branch instructionsAssembly: beq $i, $j, 100 (goto +100 instr. if $i == $j)n instructions = 4×n address shift (left shift by 2)
leftshift
2
PC+4
PC
$ij
i
$j :
16 32
100100
sele
cts
PC
so
urc
e
zero?
subtract
instruction
i j 1004
address sh
ift4
regreg
extended
Sign
ALU
AD
D
Readregister 2
Readregister 1
Writeregister
Writedata
Registers
Readdata 1
data 2Read
Control
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Outline
Introduction
Data paths
Assembling data paths
Control logic
Examples
Designing the control logic
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Assembling data paths
1
0
Readregister 1
Readregister 2
Writeregister
Writedata
Readdata 1
data 2Read
Registers
Ins 20−15
Ins 25−21
instruction
Ins 15−0
Combining R−format with load andimmediate arithmetic instructions:
a multiplexor to select the destination register
Ins 15−11
Ins 31−26
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Assembling data paths
16 32
Result
ZeroALU
1
0
1
0
Signextend
Combining R−format with load, writeand immediate arithmetic instructions:
a multiplexor to select the second ALU operand
Readregister 1
Readregister 2
Writeregister
Writedata
Readdata 1
data 2Read
Registers
Ins 20−15
Ins 25−21
instruction
Ins 15−0
Ins 15−11
Ins 31−26
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Assembling data paths
ALUCtrl
16 32
Result
ZeroALU
1
0
1
0
Signextend
Combining R−format with load andimmediate arithmetic instructions:
a multiplexor to select the signalto write in destination register