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MINOR PROJECT ADVANCED ENCRYPTION STANDARD ON Presentation by: HARDIK MANOCHA (04420902812) NIVEDITA WASSON (05620902812)
34

Minor Project- AES Implementation in Verilog

Apr 16, 2017

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Hardik Manocha
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Page 1: Minor Project- AES Implementation in Verilog

MINOR PROJECT

ADVANCED ENCRYPTION STANDARD

ON

Presentation by:HARDIK MANOCHA (04420902812)NIVEDITA WASSON (05620902812)

Page 2: Minor Project- AES Implementation in Verilog

What is encryption?In cryptography, encryption is the process of encoding messages or information in such a way that only authorized parties can read it.

Encryption does not of itself prevent interception, but denies the message content to the interceptor.

In an encryption scheme, the intended communication information or message, referred to as plaintext, is encrypted using an encryption algorithm, generating ciphertext that can only be read if decrypted.

Page 3: Minor Project- AES Implementation in Verilog

Advanced Encryption Standard (AES)The Advanced Encryption Standard (AES), also known as Rijndael (its original name), is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001.

AES is based on the Rijndael cipher developed by two Belgian cryptographers,

Joan Daemen and Vincent Rijmen,

who submitted a proposal to NIST during the AES selection process.

Rijndael is a family of ciphers with different key and block sizes.

Page 4: Minor Project- AES Implementation in Verilog

AES is based on a design principle known as

a substitution-permutation network, combination of both substitution and permutation, and is fast in both software and hardware.

The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data.

The Rijndael specification per se is specified with block and key sizes that may be any multiple of 32 bits, both with a minimum of 128 and a maximum of 256 bits.

AES is a variant of Rijndael which has a fixed block size of 128 bits, and a key sizeof 128, 192, or 256 bits.

Page 5: Minor Project- AES Implementation in Verilog

Description of the cipherAES operates on a 4×4 column-major order matrix of bytes, termed the state, although some versions of Rijndael have a larger block size and have additional columns in the state.

For instance, if you have 16 bytes, b0,b1,...,b15, thesebytes are represented as this matrix:

Page 6: Minor Project- AES Implementation in Verilog

The key size used for an AES cipher specifies the number of repetitions of transformation rounds that convert the input, called the plaintext, into the final output, called the ciphertext.

The number of cycles of repetition are as follows:

10 cycles of repetition for 128-bit keys. 12 cycles of repetition for 192-bit keys. 14 cycles of repetition for 256-bit keys.

Each round consists of several processing steps, each containing four similar but different stages, including one that depends on the encryption key itself.

A set of reverse rounds are applied to transform ciphertext back into the original plaintext using the same encryption key.

Page 7: Minor Project- AES Implementation in Verilog

PERFORMANCE

High speed and low RAM requirements were criteria of the AES selection process. Thus AES performs well on a wide variety of hardware, from 8-bit smart cards to high performance computers.

On a Pentium Pro, AES encryption requires 18 clock cycles per byte,[40] equivalent to a throughput of about 11 MB/s for a 200 MHz processor. On a 1.7 GHz Pentium M throughput is about 60 MB/s.

On Intel Core i3/i5/i7 and AMD APU and FX CPUs supporting AES-NI instruction set extensions, throughput can be over 700 MB/s per thread.

Page 8: Minor Project- AES Implementation in Verilog

APPLICATIONSAES has been adopted by the U.S. government and is now used worldwide.

In the United States, AES was announced by the NIST as U.S. FIPS PUB 197 (FIPS 197) on November 26,2001. This announcement followed a five-year standardization process in which fifteen competing designs were presented and evaluated, before the Rijndael cipher was selected as the most suitable.

AES became effective as a federal government standard on May 26, 2002 after approval by the Secretary of Commerce.

AES is included in the ISO/IEC 18033-3 standard.

AES is available in many different encryption packages, and is the first publicly accessible and open cipher approved by the National Security Agency (NSA) for top secret information when used in an NSA approved cryptographic module.

Page 9: Minor Project- AES Implementation in Verilog

SECURITYUntil May 2009, the only successful published attacks against the full AES were side channel attacks on some specific implementations. Side-channel attacks do not attack the underlying cipher, and thus are not related to security in that context.

They rather attack implementations of the cipher on systems which inadvertently leak data.

The National Security Agency (NSA) reviewed all the AES finalists, including Rijndael, and stated that all of them were secure enough for U.S. Government non-classified data. In June 2003, the U.S.Government announced that AES could be used to protect classified information.

AES has 10 rounds for 128-bit keys, 12 rounds for 192-bit keys, and 14 rounds for 256-bit keys.

By 2006, the best known attacks were on 7 rounds for 128-bit keys, 8rounds for 192-bit keys, and 9 rounds for 256-bit keys.

Page 10: Minor Project- AES Implementation in Verilog

DESCRIPTION

OF

THE ALGORITHM

FOR

AES

Page 11: Minor Project- AES Implementation in Verilog

AES Conceptual Scheme

AES

Plaintext (128 bits)

Cipher text (128 bits)

Key (128-256 bits)

Page 12: Minor Project- AES Implementation in Verilog

Multiple rounds Rounds are (almost) identical First and last round are a little different

Page 13: Minor Project- AES Implementation in Verilog

High Level Description

No MixColumns

Page 14: Minor Project- AES Implementation in Verilog

Overall Structure

Page 15: Minor Project- AES Implementation in Verilog

128-bit values Data block viewed as 4-by-4 table of bytes Represented as 4 by 4 matrix of 8-bit bytes. Key is expanded to array of 32 bits words

1 byte

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Changing Plaintext to State

Page 17: Minor Project- AES Implementation in Verilog

Details of Each Round

Page 18: Minor Project- AES Implementation in Verilog

SubBytes: Byte Substitution

A simple substitution of each byte provide a confusion

Uses one S-box of 16x16 bytes containing a permutation of all 256 8-bit values

Each byte of state is replaced by byte indexed by row (left 4-bits) & column (right 4-bits) e.g. byte {95} is replaced by byte in row 9 column 5 which has value {2A}

S-box constructed using defined transformation of values in Galois Field- GF(28)

Page 19: Minor Project- AES Implementation in Verilog

SubBytes OperationThe SubBytes operation involves 16 independent byte-to-byte transformations.

• Interpret the byte as two hexadecimal digits xy• SW implementation, use row (x) and column (y) as lookup pointer

Page 20: Minor Project- AES Implementation in Verilog

SubBytes Table

Implement by Table Lookup

Page 21: Minor Project- AES Implementation in Verilog

InvSubBytes Table

Page 22: Minor Project- AES Implementation in Verilog

Sample SubByte Transformation

The SubBytes and InvSubBytes transformations are inverses of each other.

Page 23: Minor Project- AES Implementation in Verilog

ShiftRows

Shifting, which permutes the bytes. A circular byte shift in each each

1st row is unchanged 2nd row does 1 byte circular shift to left 3rd row does 2 byte circular shift to left 4th row does 3 byte circular shift to left

In the encryption, the transformation is called ShiftRows

In the decryption, the transformation is called InvShiftRows and the shifting is to the right

Page 24: Minor Project- AES Implementation in Verilog

Shift Rows Scheme

Page 25: Minor Project- AES Implementation in Verilog

ShiftRows and InvShiftRows

Page 26: Minor Project- AES Implementation in Verilog

MixColumns

ShiftRows and MixColumns provide diffusion to the cipher

Each column is processed separately

Each byte is replaced by a value dependent on all 4 bytes in the column

Effectively a matrix multiplication in GF(28) using prime poly m(x) =x8+x4+x3+x+1

Page 27: Minor Project- AES Implementation in Verilog

MixColumns Scheme

Page 28: Minor Project- AES Implementation in Verilog

Mix Column and Inv Mix Column

Page 29: Minor Project- AES Implementation in Verilog

AddRoundKey

XOR state with 128-bits of the round key

AddRoundKey proceeds one column at a time.adds a round key word with each state column

matrix the operation is matrix addition

Inverse for decryption identicalsince XOR own inverse, with reversed keys

Designed to be as simple as possible

Page 30: Minor Project- AES Implementation in Verilog

AddRoundKey Scheme

Page 31: Minor Project- AES Implementation in Verilog

AES Round

Page 32: Minor Project- AES Implementation in Verilog

AES Key Scheduling

Takes 128-bits (16-bytes) key and expands into array of 44 32-bit words.

Page 33: Minor Project- AES Implementation in Verilog

References

Federal Information Processing Standards Publication 197 November 26, 2001 Specification for the ADVANCED ENCRYPTION STANDARD (AES)

https://en.wikipedia.org/wiki/Advanced_Encryption_Standard?oldid=683906082

Daemen Joan and Rijmen Vincent (1999) The Rijndael Block Cipher AES Version 2

Page 34: Minor Project- AES Implementation in Verilog

THANKYOU