Aug 31, '02 VDAT'02: Low-Power Design 1 Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set Tezaswi Raja, Rutgers University [email protected]Vishwani D. Agrawal, Agere Systems [email protected]http://cm.bell-labs.com/cm/cs/who/va Michael L. Bushnell, Rutgers University [email protected]Bangalore, August 31, 2002
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Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set
Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set. Tezaswi Raja, Rutgers University [email protected] Vishwani D. Agrawal, Agere Systems [email protected] http://cm.bell-labs.com/cm/cs/who/va Michael L. Bushnell, Rutgers University - PowerPoint PPT Presentation
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Aug 31, '02 VDAT'02: Low-Power Design 1
Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set
Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set
•Design a digital circuit for minimum transient energy consumption by eliminating hazards
Aug 31, '02 VDAT'02: Low-Power Design 3
Theorem 1Theorem 1•For correct operation with minimum
energy consumption, a Boolean gate must produce no more than one event per transition
Ref: Agrawal, et al., Proc. VLSI Design’99
Aug 31, '02 VDAT'02: Low-Power Design 4
• Given that events occur at the input of a gate (inertial delay = d ) at times t1 < . . . < tn , the number of events at the gate output cannot exceed
Theorem 2Theorem 2
min ( min ( n n , 1 + ), 1 + )ttnn – t – t11
----------------dd
ttnn - t - t11 + d + d
tt11 t t22 t t33 t tnn t tnn + +
dd
timetime
Aug 31, '02 VDAT'02: Low-Power Design 5
Minimum Transient Design
Minimum Transient Design
•Minimum transient energy condition for a Boolean gate:
| t| tii - t - tjj | < d | < d
Where tWhere tii and t and tjj are arrival times of input are arrival times of input
events and d is the inertial delay of gateevents and d is the inertial delay of gate
Aug 31, '02 VDAT'02: Low-Power Design 6
Linear Program (LP)Linear Program (LP)
•Variables: gate and buffer delays
•Objective: minimize number of buffers
•Subject to: overall circuit delay
•Subject to: minimum transient condition for multi-input gates
•AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)
Aug 31, '02 VDAT'02: Low-Power Design 7
Limitations of This LPLimitations of This LP
•Constraints are written by path enumeration.
•Since number of paths in a circuit is exponential in circuit size, the formulation is infeasible for large circuits.
•Example: c880 has 6.96M constraints.
Aug 31, '02 VDAT'02: Low-Power Design 8
A New LP ModelA New LP Model
•Introduce two new variables per gate output:
• ti Earliest time of signal transition at gate i.
• Ti Latest time of signal transition at gate i.
t1, T1
tn, Tn
.
.
.
ti, Ti
Aug 31, '02 VDAT'02: Low-Power Design 9
New Linear ProgramNew Linear Program
•Gate variables d4..d12
•Buffer Variables d15..d29
•Corresponding window variables t4..t29 and T4..T29.