Matsuzawa & Okada Lab. . Matsuzawa & Okada Lab. . Millimeter-Wave CMOS Device Modeling and Issues Kenichi Okada Tokyo Institute of Technology MOS-AK @ ESSCIRC 2012
Matsuzawa& Okada Lab.
Matsuzawa Lab.Tokyo Institute of Technology
Matsuzawa& Okada Lab.
Matsuzawa Lab.Tokyo Institute of Technology
Millimeter-Wave CMOS
Device Modeling and Issues
Kenichi Okada
Tokyo Institute of Technology
MOS-AK @ ESSCIRC 2012
1
Outline
• Motivation
& Brief introduction of 60GHz CMOS
transceiver
• Modeling issues
• Measurement issues
• Substrate modeling issues
• Layout optimization
• Transistor characterization
• Summary & Conclusion
2
Motivation
• 60GHz CMOS transceiver
for multi-Gbps wireless
communication
57.24GHz - 65.88GHz
2.16GHz/ch x 4channels
IEEE 802.11ad specification
QPSK 16QAM 64QAM
2.16GHz
x1ch 3.4Gbps 6.8Gbps 10.1Gbps
2.16GHz
x4ch 13.5Gbps 27.0Gbps 40.6Gbps
3
60GHz Direct-Conversion Transceiver
[1] K. Okada, et al., ISSCC 2012
LNA
LNAQ MIXER
I MIXER
LO BUF.
LO BUF.
Q.OSC.
Logic
I MIXER
Q MIXER
LO BUF.
LO BUF.
Q.OSC.PA
PLL LO BUF.
• 2.4GHz vs 60GHz (25x)
RF front-end (Tx/Rx/LO)
– Simulation/Modeling, Gain, Noise, Pout
65nm CMOS, 4.2x4.2mm
4
• TL-based design for simulation accuracy
• Low-loss TL & MIM TL
TL-Based Design
MIM TL for decoupling 50W, 0.8dB/mm
Z0=3W
W=1mm x40 1mm x40 2mm x20 2mm x20
GND
dummy
signal(10mm)
gap(15mm) GND
M1&M2 shield
GND GND
4-stage CS-CS LNA
[2] K. Okada, et al., ISSCC 2011
Performance Summary
5
-40
-30
-20
-10
0
10
57.24 60.48 63.72
Arch. Max. rate in 16QAM
Distance for BER <10-3
PDC (Tx/Rx)
IMEC[3] Direct 7Gb/s ch.1-4 (EVM < -17dB) (w/o PLL)
176mW / 112mW
SiBeam [4]
Hetero 7Gb/s ch.2-3 (EVM < -19dB) 50m(LOS), 16m(NLOS)
1,820mW / 1,250mW
This work
Direct 10Gb/s- ch.1-4 (EVM < -23dB) 1.3-1.6m (QPSK) 0.3-0.5m (16QAM)
319mW / 223mW
[3] V. Vidojkovic, et al., ISSCC 2012 [4] S. Emami, et al., ISSCC 2011
6dBi antennas
6
Outline
• Motivation
& Brief introduction of 60GHz CMOS
transceiver
• Modeling issues
• Measurement issues
• Substrate modeling issues
• Layout optimization
• Transistor characterization
• Summary & Conclusion
Issues of mmW Tr Modeling
• Bias scalability
• L & W scalability
• Linearity –Large-signal accuracy for RF and mmW
• Noise
caused by
• Measurement inaccuracy
• Complex physical and electrical
structure of miniaturized transistors –Substrate model
7
Substrate Coupling
8
GND
Input Output
p + n + n +
G
S D B
P sub
n + n + p +
G
S D B P well
N well
n +
N well
n +
P well
Vdd
Vdd
bias
Common-Source Common-Gate
0
5
10
15
20
25
0 20 40 60 80 100
Ma
xG
ain
(d
B)
Frequency (GHz)
CS+CG
Cascode
CS CG
Cascode
completely same layout but
different characteristics
connect S-parameters
measured individually
Substrate model issue
• Measurement through drain, gate and
source is not so reliable to build an
equivalent circuit of the substrate
network.
• Up to 10GHz
• CS meas. + CG meas. ≠ Cascode
meas.
• L, Wf-scalability, VB dependence
9
Current status & Target
DC (< 1GHz)
RF (< 10GHz)
mmW (> 10GHz)
Bias dep. (VG, VD)
Bias dep. (VS) partially
Bias dep. (VB)
#finger scalability
Wf scalability
L scalability
Non-linearity (IM3) partially
Large-signal partially
Noise partially 10
11
Outline
• Motivation
& Brief introduction of 60GHz CMOS
transceiver
• Modeling issues
• Measurement issues
• Substrate modeling issues
• Layout optimization
• Transistor characterization
• Summary & Conclusion
Finger Width Optimization
12
[5] T. Suzuki, ISSCC 2008
W=2umx8
•MAG peak
W=1umx16
• Rg
• Diffusion capacitance
• MAG
• NF
Asymmetric Source/Drain Layout
13
Dgd should be longer for smaller Cgdsw.
Dgs should be shorter for smaller Rs.
Gate
Cont.
M1
Source DrainP-Sub
M1
Dgs
Dgd
Drain
Source
Gate
Dgd
Dgs
Drain
Source
Dgd
Gate Dgs
Convertional Proposed
Dgd : Gate to drain contact distance
Dgs : Gate to source contact distance
[6] N. Li, et al., ESSCIRC 2010
Dgd Optimization
14
+0.6 dB
MAG is improved by 0.6 dB.
Small Cgdsw will increase fmax
Larger Dgd (e.g. 200 nm)
Large Rs will degenerate the transistor
Smallest Dgs (e.g. 60 nm)
Cdb
CgdswRdsw
RsswCgssw
Csb
Gate
Drain
Source
Rd
Rs
Cgdsw
Cgssw
15
Outline
• Motivation
& Brief introduction of 60GHz CMOS
transceiver
• Modeling issues
• Measurement issues
• Substrate modeling issues
• Layout optimization
• Transistor characterization
• Summary & Conclusion
Summary & Conclusion
• Device models for mmW design are still
not developed well as compared with
lower frequency.
• L, Wf, #finger, VB, VS scalability
• Noise and linearity are also headachy.
16
17
Acknowledgement
This work was partially supported by MIC,
MEXT, STARC, NEDO, Canon Foundation, and
VDEC in collaboration with Cadence Design
Systems, Inc., and Agilent Technologies Japan,
Ltd. The authors thank Dr. Hirose, Dr. Suzuki,
Dr. Sato, and Dr. Kawano of Fujitsu
Laboratories, Ltd., Dr. Taniguchi of JRC, Dr.
Hirachi of AMMSys Inc., Prof. Suga of Aoyama
Gakuin University, Dr. Fukuzawa and Prof.
Ando of Tokyo Institute of Technology for their
valuable discussions and technical supports.