www.coreriver.com (E-mail : [email protected]) SeJong Family CORERIVER Semiconductor reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time. CORERIVER shall give customers at least a three month advance notice of intended discontinuation of a product or a service through its homepage. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. The CORERIVER products listed in this document are intended for usage in general electronics applications. These CORERIVER products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury. Brief Manual of SeJong200 Family V1.9 September, 2012 Flash /ISP / IAP 16-bit DSP with Capacitive Touch Sensors and LCD Driver BM-SeJong200-V1.9
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CORERIVER Semiconductor reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time.
CORERIVER shall give customers at least a three month advance notice of intended discontinuation of a product or a service through its homepage.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
The CORERIVER products listed in this document are intended for usage in general electronics applications. These CORERIVER products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury.
XTAL1 Input Input to the Inverting Oscillator Amplifier • P3.06 : CLO / I2C1_SDA / TXD1 / XTAL1
XTAL2 Output Output to the Inverting Oscillator Amplifier • P3.05 : INT5 / I2C1_SCL / RXD1 / XTAL2
T_MOD Input Test Mode Pin -
SeJong200 Family [13]
5. Pin Descriptions
Symbol Direction Description Share Pins
P0[15:0] Input/Output
An 16-bit open-Drain or push-pull I/O port. Note that the output is fully driven (push-pull) when P0 drives PWM0 output. Each port must be used only one among ADC, LCDC and Touch
An 16-bit open-Drain or push-pull I/O port. Note that the output is fully driven (push-pull) when P1 drives PWM1 output. Each port must be used only one among ADC, LCDC and Touch
CORE MMR the internal registers of the core This area is used solely by the core. The user application may refer to the value of this area. However, it is strictly prohibited for the user application to modify this area.
Peripherals Each peripheral is allocated its own memory space in this area. Refer to the provided header file to identify the base address of each peripheral interface. In the following sections, only the offset addresses from the base address are specified in the section of each peripheral.
IAP hard-codes The program codes for IAP (In-Application Programming) reside in this area. If the application calls the function for writing to the embedded flash memory directly which are IAP operations, the core
executes the functions residing in this area.
Interrupt vectors The interrupt vector table for the core resides in this area. Programmers may set the function pointer for the interrupt vector in this area. By default, there are several pre-defined function names for interrupt service routines
Boot-up and Boot Initialization For the programmers, we provide boot-up and boot initialization routines. During boot-up, the processor state registers and stack are initialized. The boot initialization routine moves .data and .bss sections stored in the embedded flash memory into the SRAM area.
SeJong200 Family [19]
6.1. Memory Descriptions (2 of 2)
Application codes The area for application code include several types of data. First, the application codes include the code and read-only data for the core. Second, the application codes include the copy of the Time-Critical Function (TCF)'s code. The code for TCF resides in the application codes area during the programming of embedded flash memory and then copied
to the SRAM area just after entering the main function.
TCF or .data or .bss The SRAM area includes Time-Critical Function (TCF), .data, or .bss sections which are inherently readable and writable. The TCF is the time-critical function area where the function which has time-critical operations would be located. By locating TCF in SRAM area, programmers may enhance the function's execution speed. The .data section is the global data with initialization value. The compiler would locate .data section initially in the embedded flash memory area and then the boot initialization routine
would copy them to SRAM area. The .bss section is the global data which are not initialized. No initialization operation is needed for .bss.
Stack The stack are should be assigned in any compiled application code. In the current implementation, there is no exception handling for stack overflow or underflow. Therefore, programmers should be careful to set sufficient amount of stack area so that no stack overflow or underflow
occurs.
SeJong200 Family
Op. Mode ACTIVE By default, Op. mode becomes ACTIVE.
[20]
6.2. Reset Sequence (1 of 2)
POR Sequence The PoR macro generates PoR signal. PoR subsequently makes PoR_l signal which is several-clock-cycle wide. PoR_l triggers i_reset which persists for at least 32ms. During i_reset
• VDD, the power should be stabilized. • External crystal clock oscillators are stabilized through XTAL stabilizers.
VDD
PoR
PoR_I
i_reset
32ms
SeJong200 Family [21]
6.2. Reset Sequence (2 of 2)
Global Reset Sequence Power on reset by POR macro External reset pin : Setting ‘H’ and ‘L’ on the external reset pin does internal global reset of the
chip Reset from WDT (Watch-Dog Timer) : If Register of WDT is programmed accordingly, WDT
triggers the internal global reset. JTAG reset command : The reset command triggered by JTAG triggers the internal global reset.
PoR_I
i_reset
32ms
Op. Mode ACTIVE
PoR from PoR Macro
External Reset Pin
Reset from WDT
JTAG Reset Command
SeJong200 Family
6.3. Operating Modes
Active mode The processor core and all the peripherals configured accordingly by the firmware are active. The firmware of the core decides the peripherals to be active. The GPIOs are configured accordingly by the firmware.
Idle mode The clock of CPU is disabled. The clocks of peripherals are active. The clock of WDT is decided by the firmware. Wake-up source : an interrupt from any peripheral.
Weak Sleep mode The clock of CPU is disabled. The clocks of peripherals are disabled. The clock of WDT is active. Wake-up source : I2C / WDT / External 8-bit interrupts
Sleep mode The clock of CPU is disabled. The clocks of peripherals are disabled. The clock of WDT is disabled. Wake-up source : I2C / External 8-bit interrupts
[22]
SeJong200 Family
6.4. Clock Network : Block Diagram (1 of 2)
[23]
CPU Clock
Peripheral Clock
IDLE_ON
Internal 96MHz
XTAL
DIV
ISCLK_OFF
PD_ON
TSCLK_OFF
XTAL_EN XTUP
FOSC
TS Clock
IRDIV
TSDIV
0
1
TSCLK_SW
ISCLK_SW
DIV
ADCDIV
ADCLK_EN
TSCLK_OFF
Clock Stable Counter
0
1
ADCLK_EN
PD_ON
DIV
FDIV_TS
FDIV_SYS
FXTAL
FTS
ADC Clock
0
1
ADCLK_SW
FDIV_ADC
FADC
FSYS
PCK_DIS[0]
peri0
peri1
periN
PCK_DIS[1]
PCK_DIS[N]
UART Clock
0
1
UCLK_SW
FDIV_SYS
FUART
SeJong200 Family
6.4. Clock Network : Block Diagram (2 of 2)
[24]
Internal 32KHz
IR32K_ON
STOP Timer Clock
RTC_SLEEP_OFF
0
1
F32KHz
RTC_XTAL
RTC_XTAL_EN RTC_XTUP
0
1
ST_CLK_SW
Clock Stable Counter
RTC_XTAL setup time : ~ 200 us
0
1
RTC_CLK_SW
0
RTC Clock
RTC_SLEEP_OFF
0
1
0
SeJong200 Family
6.4. Clock Network : Registers (1 of 6)
- - - - - - - - - - - - - STPD_ON PD_ON IDLE_ON
R/W(0) R/W(0) R/W(0)
PCON (0100h) : Power Control Register
STPD_ON : Stop Timer Clock Enable/Disable ([0] : Disable [1] : Enable) PD_ON : Power down mode On ([0] : Not power down mode [1] : Power down mode) IDLE_ON : Idle mode On ([0] : Not idle mode [1] : Idle mode)
IRCLK_DIV (0101h) : Internal Ring Clock Divisor Register
Open-drain or push-pull output, pull-up control (Default : Pull-up OFF).
The alternative functions are available under the conditions The corresponding Data Register bit is “1”. The corresponding DIR bit is “1”. The corresponding PENB bit is “1”. The corresponding IOENB bit is “1”. The only one among ADCSELx for ADC, TSCHEN bit for Touch Sensor and LCD_IO_ENx bit for LCD must be selected exclusively to avoid collision each other
P0HDEN (030Ah) : Port 0 High Driving Control Register
0 = High Current Driving OFF (Default) / 1 = ON
IOENB0 & ADCSEL &ADCSEL2 : refer to ADC section
TSCHEN : refer to Touch section
SEG_IO_EN & COM_IO_EN : refer to LCDC section
SeJong200 Family
Open-drain or push-pull output, pull-up control.
The alternative functions are available under the conditions The corresponding Data Register bit is “1”. The corresponding DIR bit is “1”. The corresponding PENB bit is “1”. The corresponding IOENB bit is “1”. The only one among ADCSELx for ADC, TSCHEN bit for Touch Sensor and LCD_IO_ENx bit for LCD must be selected exclusively to avoid collision each other
P1HDEN (030Eh) : Port 1 High Driving Control Register
0 = High Current Driving OFF (Default) / 1 = ON
IOENB1 & ADCSEL & ADCSEL2: refer to ADC section
TSCHEN : refer to Touch section SEG_IO_EN & COM_IO_EN : refer to LCDC section
SeJong200 Family
Open-drain or push-pull output, pull-up control.
The alternative functions are available under the conditions The corresponding Data Register bit is “1”. The corresponding DIR bit is “1”. The corresponding PENB bit is “1”. The corresponding IOENB bit is “1”. The only one among ADCSELx for ADC, TSCHEN bit for Touch Sensor and LCD_IO_ENx bit for LCD must be selected exclusively to avoid collision each other
P2HDEN (0312h) : Port 2 High Driving Control Register
0 = High Current Driving OFF (Default) / 1 = ON
IOENB2 & ADCSEL &ADCSEL2 : refer to ADC section
TSCHEN : refer to Touch section SEG_IO_EN & COM_IO_EN : refer to LCDC section
SeJong200 Family
Open-drain or push-pull output, pull-up control.
The alternative functions are available under the conditions The corresponding Data Register bit is “1”. The corresponding DIR bit is “1”. The corresponding PENB bit is “1”.
The alternative functions are available under the conditions The corresponding Data Register bit is “1”. The corresponding DIR bit is “1”. The corresponding PENB bit is “1”. The corresponding IOENB bit is “1”. The only one among ADCSELx for ADC, TSCHEN bit for Touch Sensor and LCD_IO_ENx bit for LCD must be selected exclusively to avoid collision each other
P4HDEN (031Ah) : Port 4 High Driving Control Register
0 = High Current Driving OFF (Default) / 1 = ON
IOENB & ADCSEL & ADCSEL2 : refer to ADC section
TSCHEN : refer to Touch section SEG_IO_EN & COM_IO_EN : refer to LCDC section
SeJong200 Family [42]
6.6. The ESD Structure of Pads
Two ESD diodes and one ESD resister are contained in all pads except VDD.
One ESD diode are contained in VDD.
[VDD]
• Two ESD Diodes (VDD side, VSS side) • One ESD Resister
• One ESD Diode (GND side) • One ESD Resister
[All pads except VDD]
SeJong200 Family [43]
6.7. ST (Stop Timer)
Timer to wake up from stop mode
Use the internal 32 KHz oscillator or External crystal for saving power consumption
ST_CON (01C0h) : Stop Timer Control Register
ST_CLR : initialize Stop Timer Count , H/W clear it automatically (0 : not initialize , 1 : initialize) ST_OVF : Overflow event signal which internal stop timer match with ST_RT[15:0] value , H/W set and clear it (0 : not overflow, 1: overflow) ST_IF : Stop Timer Interrupt flag, S/W clear it , The interrupt is occurred when internal stop counter match with ST_RT[15:0] (0 : interrupt inactive, 1 : interrupt occurred) ST_EN : Stop Timer enable (0 : disable , 1 : enable)
- - - - - - - - - - - - ST_CLR ST_OVF ST_IF ST_EN
R/W(0) R(0) R/W(0) R/W(0)
ST_RTH (01C2h) : Stop Timer Timeout MSB Value Register
DLHR0 (01E1h) : Serial interface0 Divisor Latch High Register (when DLA bit in LCR0 register is set to ‘1’)
The firmware may set LC register bits to access Divisor Latch. The offset addresses of Divisor Latch are 0 for the LSB 8-bit and 1 for the MSB 8-bit. LSB and MSB comprise a whole 16-bit register. The firmware should turn off LC register bits to access normal registers. The Divisor Latch is set to ‘0’ on reset. In other words, all serial IO operations are disabled in order to ensure explicit setup of the register in the software. The value set should be equal to (system clock speed)/(16x desired baud rate). The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the MSB first and the LSB last.
FCR0 (01E2h) : Serial interface0 FIFO Control Register
RST_RXF : Clear Rx FIFO and reset its logic except for shift register (0 : not reset, 1 : reset) RST_TXF : Clear Tx FIFO and reset its logic except for shift register (0 : not reset, 1 : reset) RF_TR[1:0] : Receiver FIFO interrupt trigger level (00 : 1byte, 01 : 4bytes, 10 : 8bytes, 11 : 14bytes)
- - - - - - - - - - - - SID2 SID1 SID0 SIF
R (1) R (1) R(0) R(0) R(0) R(1)
IIR0 (01E2h) : Serial interface0 Interrupt Identification Register
SIF : Serial interface0 interrupt flag (0 : interrupt pending, 1 : no interrupt pending) SID[2:0] : Serial interface0 interrupt identification (011) Priority : 1st Interrupt type : Receiver line status Interrupt source : Parity overrun or Framing errors or Break interrupt Interrupt reset control : Reading the Line Status Register (010) Priority : 2nd Interrupt type : Receiver data available Interrupt source : FIFO trigger level reached Interrupt reset control : FIFO drops below trigger level (110) Priority : 2nd Interrupt type : Timeout indication Interrupt source : There’s at least 1 character in the FIFO but no character has been input to the FIFO or read from it for the last 4 Char times Interrupt reset control : Reading the Line Status Register (001) Priority : 4th Interrupt type : Transmitter Holding Register Empty Interrupt source : Transmit FIFO empty Interrupt reset control : Writing TX data to FIFO or Reading IIR0 when Transmitter Holding Register Empty interrupt is occurred (000) Reserved
LCR0 (01E3h) : Serial interface0 Line Control Register
NCH[1:0] : Select number of bits in each character (00 : 5bits, 01 : 6bits, 10 : 7bits, 11 : 8bits) NSB : Specify the number of generated stop bits (0 : 1 stop bit, 1 : 1.5 stop bits @ 5-bit char / 2 stop bits @ otherwise char) PE : Parity Enable (0 : no parity, 1 : parity in both Rx and Tx) EP : Select Even Parity (0 : odd parity, 1 : even parity) SP : Stick Parity (0 : stick parity disabled, 1 : If bits 3, 4 are logic ‘1’, the parity bit is transmitted and checked as logic ‘0’. If bit 3 is ‘1’ and bit 4 is ‘0’ then the parity bit is transmitted and checked as ‘1’.) BC : Break Control bit (0 : break is disabled, 1 : the serial out is forced into logic ‘0’) DLA : Divisor Latch Access (0 : the divisor latches can be accessed, 1 : the normal registers are accessed)
- - - - - - - - ERRI TEI TFE BII FEI PEI OEI DRI
R (0) R (0) R (0) R (0) R (0) R (0) R (0) R (0)
LSR0 (01E5h) : Serial interface0 Line Status Register
DRI : Data Ready (DR) indicator (0 : No char, 1 : At least one char is in FIFO ) OEI : Overrun Error (OE) indicator (0 : No overrun, 1 : If the FIFO is full and another character has been received in the receiver shifter register. If another character is starting to arrive, it will overwrite the data in the shifter register but the FIFO will remain intact. The bit is cleared upon reading from the register. This generates ‘receiver line status’ interrupt. ) PEI : Parity Error (PE) indicator (0 : No PE, 1 : The character currently at the top of FIFO has been received with parity error. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt. ) FEI : Framing Error (FE) indicator (0 : No FE, 1 : The character currently at the top of FIFO did not have a valid stop bit. It might be all the following data is corrupt. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt.) BII : Break Interrupt (BI) indicator (0 : No BI, 1 : A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character, i.e., start bit + data + parity + stop bit. In that case, one zero character enters the FIFO and the UART waits for a valid start bit to receive the next character. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt. ) TFE : Transmitter Ready Indicator (0 : No, 1 : The transmitter FIFO is empty. It generates ‘transmitter holding register empty’ interrupt. The bit is cleared when data is being been written to the transmitter FIFO. ) TEI : Divisor Latch Access (0 : No, 1 : Both the transmitter FIFO and transmitter shifter register are empty. The bit is cleared when data is being written to the transmitter FIFO. ) ERRI : Error Indicator (0 : No, 1 : At least one parity error, framing error or break indications have
been received and are inside the FIFO. The bit is cleared upon reading from the register. )
DLHR1 (0201h) : Serial interface1 Divisor Latch High Register (when DLA bit in LCR1 register is set to ‘1’)
The firmware may set LC register bits to access Divisor Latch. The offset addresses of Divisor Latch are 0 for the LSB 8-bit and 1 for the MSB 8-bit. LSB and MSB comprise a whole 16-bit register. The firmware should turn off LC register bits to access normal registers. The Divisor Latch is set to ‘0’ on reset. In other words, all serial IO operations are disabled in order to ensure explicit setup of the register in the software. The value set should be equal to (system clock speed)/(16x desired baud rate). The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the MSB first and the LSB last.
FCR1 (0202h) : Serial interface1 FIFO Control Register
RST_RXF : Clear Rx FIFO and reset its logic except for shift register (0 : not reset, 1 : reset) RST_TXF : Clear Tx FIFO and reset its logic except for shift register (0 : not reset, 1 : reset) RF_TR[1:0] : Receiver FIFO interrupt trigger level (00 : 1byte, 01 : 4bytes, 10 : 8bytes, 11 : 14bytes)
- - - - - - - - - - - - SID2 SID1 SID0 SIF
R (1) R (1) R(0) R(0) R(0) R(1)
IIR1 (0120h) : Serial interface1 Interrupt Identification Register
SIF : Serial interface0 interrupt flag (0 : interrupt pending, 1 : no interrupt pending) SID[2:0] : Serial interface0 interrupt identification (011) Priority : 1st Interrupt type : Receiver line status Interrupt source : Parity overrun or Framing errors or Break interrupt Interrupt reset control : Reading the Line Status Register (010) Priority : 2nd Interrupt type : Receiver data available Interrupt source : FIFO trigger level reached Interrupt reset control : FIFO drops below trigger level (110) Priority : 2nd Interrupt type : Timeout indication Interrupt source : There’s at least 1 character in the FIFO but no character has been input to the FIFO or read from it for the last 4 Char times Interrupt reset control : Reading the Line Status Register (001) Priority : 3rd Interrupt type : Transmitter Holding Register Empty Interrupt source : Transmit FIFO empty Interrupt reset control : Writing TX data to FIFO or Reading IIR1 when Transmitter Holding Register Empty interrupt is occurred . (000) Reserved
LCR1 (0203h) : Serial interface1 Line Control Register
NCH[1:0] : Select number of bits in each character (00 : 5bits, 01 : 6bits, 10 : 7bits, 11 : 8bits) NSB : Specify the number of generated stop bits (0 : 1 stop bit, 1 : 1.5 stop bits @ 5-bit char / 2 stop bits @ otherwise char) PE : Parity Enable (0 : no parity, 1 : parity in both Rx and Tx) EP : Select Even Parity (0 : odd parity, 1 : even parity) SP : Stick Parity (0 : stick parity disabled, 1 : If bits 3, 4 are logic ‘1’, the parity bit is transmitted and checked as logic ‘0’. If bit 3 is ‘1’ and bit 4 is ‘0’ then the parity bit is transmitted and checked as ‘1’.) BC : Break Control bit (0 : break is disabled, 1 : the serial out is forced into logic ‘0’) DLA : Divisor Latch Access (0 : the divisor latches can be accessed, 1 : the normal registers are accessed)
- - - - - - - - ERRI TEI TFE BII FEI PEI OEI DRI
R (0) R (0) R (0) R (0) R (0) R (0) R (0) R (0)
LSR1 (0205h) : Serial interface1 Line Status Register
DRI : Data Ready (DR) indicator (0 : No char, 1 : At least one char is in FIFO ) OEI : Overrun Error (OE) indicator (0 : No overrun, 1 : If the FIFO is full and another character has been received in the receiver shifter register. If another character is starting to arrive, it will overwrite the data in the shifter register but the FIFO will remain intact. The bit is cleared upon reading from the register. This generates ‘receiver line status’ interrupt. ) PEI : Parity Error (PE) indicator (0 : No PE, 1 : The character currently at the top of FIFO has been received with parity error. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt. ) FEI : Framing Error (FE) indicator (0 : No FE, 1 : The character currently at the top of FIFO did not have a valid stop bit. It might be all the following data is corrupt. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt.) BII : Break Interrupt (BI) indicator (0 : No BI, 1 : A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character, i.e., start bit + data + parity + stop bit. In that case, one zero character enters the FIFO and the UART waits for a valid start bit to receive the next character. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt. ) TFE : Transmitter Ready Indicator (0 : No, 1 : The transmitter FIFO is empty. It generates ‘transmitter holding register empty’ interrupt. The bit is cleared when data is being been written to the transmitter FIFO. ) TEI : Divisor Latch Access (0 : No, 1 : Both the transmitter FIFO and transmitter shifter register are empty. The bit is cleared when data is being written to the transmitter FIFO. ) ERRI : Error Indicator (0 : No, 1 : At least one parity error, framing error or break indications have
been received and are inside the FIFO. The bit is cleared upon reading from the register. )
Transfer Wait State Fully Programmable Slave Address SDA/SCL Schmitt-trigger input 256 Programmable Bit Rates Wake-up from IDLE mode Compatible with Phillips I2C protocol
R/W(0) R/W(0) R(0) R/W(0) R/W(0) R (0) R (0) R (0) R (0) R (0) R (0)
I2C0ST (0160h) : I2C0 Status Register
SDAHDT_OVF : I2C SDA Hold Timer Overflow (0 : No overflow, 1 : Overflow) SCLHDT_OVF : I2C SCL Hold Timer Overflow (0 : No overflow, 1 : Overflow) I2CBB : I2C byte transmission busy flag (0 : Not busy, 1 : Busy) I2CIF : I2C Master Interrupt Flag in slave & master mode. (0 : Idle, 1 : Interrupt occurred) It is set each time a byte is received or transmitted. If SP_IE flag in I2C_CFG register is set, it is set at Start/Stop condition. The flag is set by H/W and cleared by S/W. I2COF : I2C Overflow Flag in slave & master mode. (0 : Idle, 1 : Overflow occurred) It is set when a byte is received while I2C_BUF register is still holding the previous byte. It is set by H/W and cleared by S/W. I2CACK : I2C Acknowledge flag in slave & master mode. (0 : Receiving Acknowledge bit, 1 : Receiving Not Acknowledge bit) I2CRW : I2C Read/Write flag in slave mode (0 : Write state, 1 : Read state) I2CDA : Data / Address flag in slave mode
(0 : the last byte received or transmitted was Data, 1 : Indicates the last byte received or transmitted was Address) I2CP : Stop flag in slave & master mode (0 : Stop bit was not detected, 1 : Stop bit was detected) This flag is cleared when I2CS is set or I2CEN is cleared. I2CS : Start flag in slave & master mode (0 : Start bit was not detected, 1 : Start bit was detected) This flag is cleared when I2CP is set or I2CEN is cleared. I2CBF : Busy flag in slave & master mode
(0 : RX not complete (Receiver), TX not complete (Transmitter), 1 : RX complete (Receiver), TX complete (Transmitter))
SLA2ME : 2nd Byte Slave Address Match Enable in Slave mode (0 : 2nd Byte SLA Match Disable, 1 : 2nd SLA Byte Match Enable) SCLHD : Hold SCL ‘low’ for Wait State in Slave mode. (0 : Hold SCL ‘low’. The flag is cleared automatically by H/W, 1 : Release SCL ‘float’. The flag is set by S/W) LASTB : Indicate last byte in Master Receiver mode. (0 : Send Ack after last byte, 1 : Send Not Ack after last byte) In Master Receiver mode, before receiving last byte, the flag must be set. PGEN : Generate Stop bit. (0 : Start or Idle state, 1 : Generate Stop bit.) The flag is cleared automatically after Stop bit in Master mode and when I2CEN is cleared. SGEN : Generate Start bit (0 : Stop or Idle state, 1 : Generate Start bit) If the bus is not free, it waits for Stop bit condition. The flag is cleared automatically after Start bit in Master mode and when I2CEN is cleared. I2CIOENB0 : Enable I2C 1st PATH IO (0 : Disable I2C IO, 1 : Enable I2C IO) I2CEN : Enable I2C module (0 : Disable I2C module, 1 : Enable I2C module)
SLA[7:0] : I2C Slave Address Register. In 7-bit address mode and in 10-bit address mode (1st SLA), I2C_SLA[7:1] is used for matching address and I2C_SLA[0] is masked. In 10-bit address mode (2nd SLA), I2C_SLA[7:0] is used for matching address.
I2CIF : I2C Master Interrupt Flag in slave & master mode. (0 : Idle, 1 : Interrupt occurred) It is set each time a byte is received or transmitted. If SP_IE flag in I2C_CFG register is set, it is set at Start/Stop condition. The flag is set by H/W and cleared by S/W. I2COF : I2C Overflow Flag in slave & master mode. (0 : Idle, 1 : Overflow occurred) It is set when a byte is received while I2C_BUF register is still holding the previous byte. It is set by H/W and cleared by S/W I2CACK : I2C Acknowledge flag in slave & master mode. (0 : Receiving Acknowledge bit, 1 : Receiving Not Acknowledge bit) I2CRW : I2C Read/Write flag in slave mode (0 : Write state, 1 : Read state) I2CDA : Data / Address flag in slave mode
(0 : the last byte received or transmitted was Data, 1 : Indicates the last byte received or transmitted was Address) I2CP : Stop flag in slave & master mode (0 : Stop bit was not detected, 1 : Stop bit was detected) This flag is cleared when I2CS is set or I2CEN is cleared. I2CS : Start flag in slave & master mode (0 : Start bit was not detected, 1 : Start bit was detected) This flag is cleared when I2CP is set or I2CEN is cleared. I2CBF : Busy flag in slave & master mode
(0 : RX not complete (Receiver), TX not complete (Transmitter), 1 : RX complete (Receiver), TX complete (Transmitter))
I2CIOENB1 : Enable I2C 2nd PATH IO (0 : Disable I2C IO, 1 : Enable I2C IO) SLA2ME : 2nd Byte Slave Address Match Enable in Slave mode (0 : 2nd Byte SLA Match Disable, 1 : 2nd SLA Byte Match Enable) SCLHD : Hold SCL ‘low’ for Wait State in Slave mode. (0 : Hold SCL ‘low’. The flag is cleared automatically by H/W, 1 : Release SCL ‘float’. The flag is set by S/W) LASTB : Indicate last byte in Master Receiver mode. (0 : Send Ack after last byte, 1 : Send Not Ack after last byte) In Master Receiver mode, before receiving last byte, the flag must be set. PGEN : Generate Stop bit. (0 : Start or Idle state, 1 : Generate Stop bit.) The flag is cleared automatically after Stop bit in Master mode and when I2CEN is cleared. SGEN : Generate Start bit (0 : Stop or Idle state, 1 : Generate Start bit) If the bus is not free, it waits for Stop bit condition. The flag is cleared automatically after Start bit in Master mode and when I2CEN is cleared. I2CIOENB0 : Enable I2C 1st PATH IO (0 : Disable I2C IO, 1 : Enable I2C IO) I2CEN : Enable I2C module (0 : Disable I2C module, 1 : Enable I2C module)
SLA[7:0] : I2C Slave Address Register. In 7-bit address mode and in 10-bit address mode (1st SLA), I2C_SLA[7:1] is used for matching address and I2C_SLA[0] is masked. In 10-bit address mode (2nd SLA), I2C_SLA[7:0] is used for matching address.
Transfer Acknowledge Slave-Receiver generates an acknowledge bit after Master transfers each byte. If not, Master aborts the transfer. Master-Receiver generates an acknowledge bit after Slave transfers each byte except last byte. Transfer Wait State 1) If Slave needs to delay the transmission of the next byte, it can hold the SCL ‘low’ 2) Master must enter the wait state, if the SCL is held ‘low’. 3) When Slave releases the SCL, Master starts the transfer again.
Combined Format When Master does not want to release the bus, a repeated start condition must be generated without a stop condition. The condition is identical to a start condition The condition must occurs after a data transfer acknowledge pulse.
A : Acknowledge /A : Nor Acknowledge S : Start Sr : Repeated Start P : Stop SLA : Slave Address
SeJong200 Family [71] [71]
6.12. SPI : Registers (1 of 2)
Full-duplex, Three-wire Synchronous Data Transfer Slave Operation LSB First or MSB First Data Transfer Eight Programmable Bit Rates
Clock Polarity & Phase Selection Support Write Collision Protection Wake-up from IDLE mode
TXBV : TX buffer of SPIDR holds valid data. [1] : Set by H/W when user write SPIDR while SPI is enabled. [0] : Cleared by H/W when the data is moved to TX shift register or SPI is disabled. SPIF : SPI Interrupt Flag [1] : Serial transfer is complete. If SPIE is set and EA is set, SPI interrupt is generated. [0] : no interrupt SPICOL : SPI Write Collision Flag [1] : SPIDR is written when TXBV is set. The previous data is lost. [0] : no collision
SPIOF : SPI Read Overflow Flag [1] : If a new data is received while SPIDR is still holding the previous data, the flag is set. SPIF must be cleared before receiving a data again. [0] : no overflow
PWMA Two 8-bit PWM generation with 16 modules (Compatible to M1.0A 8-bit mode) PWM Data buffer Update (8-bit Counter Overflow Update) PWM Counter can be cleared by S/W. PWM is stopped or started (resumed) by S/W.
PWM0D0 (02A3h) : PWMA CH0 Duty Data Register of Module 0
Each Module has a internal buffer register for the duty data register. The buffer register is updated with the new data whenever the PWMA counter rolls over. When user write, the data register is written. When user read, the contents of buffer register is read out.
PWM0D1 (02A4h) : PWMA CH0 Duty Data Register of Module 1
PWM0D2 (02A5h) : PWMA CH0 Duty Data Register of Module 2
PWM0D3 (02A6h) : PWMA CH0 Duty Data Register of Module 3
PWM0D4 (02A7h) : PWMA CH0 Duty Data Register of Module 4
PWM0D5 (02A8h) : PWMA CH0 Duty Data Register of Module 5
PWM0D6 (02A9h) : PWMA CH0 Duty Data Register of Module 6
PWM0D7 (02AAh) : PWMA CH0 Duty Data Register of Module 7
PWM0D8 (02ABh) : PWMA CH0 Duty Data Register of Module 8
PWM0D9 (02ACh) : PWMA CH0 Duty Data Register of Module 9
PWM0D10 (02ADh) : PWMA CH0 Duty Data Register of Module 10
PWM0D11 (02AEh) : PWMA CH0 Duty Data Register of Module 11
PWM0D12 (02AFh) : PWMA CH0 Duty Data Register of Module 12
PWM0D13 (02B0h) : PWMA CH0 Duty Data Register of Module 13
PWM0D14 (02B1h) : PWMA CH0 Duty Data Register of Module 14
PWM0D15 (02B2h) : PWMA CH0 Duty Data Register of Module 15
PWM1D0 (02C3h) : PWMA CH1 Duty Data Register of Module 0
Each Module has a internal buffer register for the duty data register. The buffer register is updated with the new data whenever the PWMA counter rolls over. When user write, the data register is written. When user read, the contents of buffer register is read out.
PWM0D1 (02C4h) : PWMA CH0 Duty Data Register of Module 1
PWM0D2 (02C5h) : PWMA CH0 Duty Data Register of Module 2
PWM0D3 (02C6h) : PWMA CH0 Duty Data Register of Module 3
PWM0D4 (02C7h) : PWMA CH0 Duty Data Register of Module 4
PWM0D5 (02C8h) : PWMA CH0 Duty Data Register of Module 5
PWM0D6 (02C9h) : PWMA CH0 Duty Data Register of Module 6
PWM0D7 (02CAh) : PWMA CH0 Duty Data Register of Module 7
PWM0D8 (02CBh) : PWMA CH0 Duty Data Register of Module 8
PWM0D9 (02CCh) : PWMA CH0 Duty Data Register of Module 9
PWM0D10 (02CDh) : PWMA CH0 Duty Data Register of Module 10
PWM0D11 (02CEh) : PWMA CH0 Duty Data Register of Module 11
PWM0D12 (02CFh) : PWMA CH0 Duty Data Register of Module 12
PWM0D13 (02D0h) : PWMA CH0 Duty Data Register of Module 13
PWM0D14 (02D1h) : PWMA CH0 Duty Data Register of Module 14
PWM0D15 (02D2h) : PWMA CH0 Duty Data Register of Module 15
[82]
SeJong200 Family
6.13. PWMA : Pulse Generation Example
Clock Count 000h
Clock Count 100h
Clock Count 200h
Clock Count 300h
Clock Count 400h
PWM Clock (FSYS/1)
PWM Out
PWM Out
PWM Out
PWM Out
1 Clock Cycle
Low
(50% Duty)
1 Clock Cycle
(PWMxDy = 00h)
(PWMxDy = 01h)
(PWMxDy = 80h)
(PWMxDy = FFh)
[83]
SeJong200 Family [84] [84]
6.14. Self Touch Sensor : Registers (1 of 9)
Support capacitive sensing scheme Max. 26-channel Touch Sensor Max. 65,536 (16-bit) level sensitivity Extremely low power sensing solution
- - - - - - - - - - - - - - TSIF TS_RUN
R/W(0) R/W(0)
TSCON (0220h) : Touch Sensor Control Register
TS_RUN : [1] Run touch sensing. Set by S/W, cleared by H/W. TSIF : Touch sensing interrupt flag. [1] touch sensing interrupt occurred. Set by H/W, cleared by S/W
TSEN : Touch Sensing Enable [0] : Touch Sensing Disable (Default) / [1] : Touch Sensing Enable CHSEL[5:0] : touch channel number . when user use touch , ADC or LCDC must not be used at the same port
Ex) when VIH is sweep condition by VIMAK[1] and TSVIHOPT = 00000011, TS operation is enable VIH= 1.3V(0.936V) first And then enable VIH=1.4V(1.010V) option next
Ex) if TSDLYOPT have multi-options at the same time as TSDLYOPT = 00000011, TS operation is enable delay value = 5 ns first And then enable delay value 20 ns option next
Ex) when VIL is sweep condition by VIMAK[0] and TSVILOPT = 00000011, TS operation is enable VIL= 1.10V(0.792V) first And then enable VIL= 0,40(0.288V) option next
SeJong200 Family [93] [93]
6.15. ADC (Analog-to-Digital Converter) (1 of 6)
Differential Mode : Max. 21-channel , OPAMP + 12-bit ADC (SAR Type), LDO25 = 1.8 V only , input range 0~1.8 V
Single Ended Mode : Max. 14-channel , 12-bit ADC, LDO25 = 1.8 ~3.3 V, input range 0~ LDO25 V Max. 104ksps(samples per sec.) @ FADC = 24MHz & 3V. (Max. 52ksps @ FADC = 5MHz & 3V)
- - - - - - - - - - - - AD_EN AD_REQ AD_END ADIF
R/W(0) R/W(0) R/W(1) R/W(0)
ADCON (0386h) : ADC Control Register
AD_EN : ADC Ready Enable AD_REQ : ADC Start. Cleared by H/W when AD_END goes to 1 from 0. AD_END : Current ADC Status. 0 = ADC is running now. User must check the ADCF instead of AD_END. ADCF : ADC Interrupt Flag. Must be cleared by S/W.
SATB_CNT[9:0] : Stable time (> 20 us) after OPAMP enable
SeJong200 Family [99] [99]
6.15. ADC (Block Diagram)
Analog MUX
ADC0.xx (P0.xx)
ADC1.xx (P1.xx)
ADC4.xx (P4.xx)
Successive Approximation
Register
FADC
AD_END
ADCIF
ADC Interrupt Flag
SAR[11:0]
ADCR
D/A Converter
Control Circuit
Clock Divide
Internal RING Clock FOSC
Analog Comparator
AVREF (= VDDIO)
VSS
ADCSEL2[6:0] AD_EN AD_REQ
ADCON.3 ADCON.2 ADCFG[2:0]
ADCON.1
ADCON.0
ADCDIV2
ADCDIV1
ADCDIV0
ADC4.xx (P4.xx)
ADCLK_EN
ADCFG.3
9 8 7 6 5 4 3 2 11 10 1 0
Analog MUX ADC1.xx
(P1.xx)
ADC0.xx (P0.xx)
OP AMP
VP
VN
ADCSEL[6:0]
SeJong200 Family [100] [100]
Hold Time 11 10 9 8 7 4 3 2 1 0 Setup Time
6.15. ADC : Conversion Timing
AD_EN : ADC Block Enable Signal. Set or Cleared by S/W. AD_REQ : ADC Conversion Request Start Bit. Set by S/W and Cleared by H/W. This bit must be set at each sample conversion. AD_END : Set or Cleared by H/W. Clear when Conversion started. Set when Conversion ended. ADCIF : ADC Interrupt Flag. Set by H/W and Cleared by S/W. User should clear ADCIF bit in ADC interrupt routine. User must check the ADCIF flag instead of AD_END.
AD_EN
AD_REQ
ADCF
AD_END
Set by S/W
Cleared by H/W
16TADC (8TADC) x 12 bits = 96TADC 8TADC
120TADC
8TADC
Valid Bit
Set by H/W
Set by H/W
ADC Interrupt
Cleared by H/W Set by S/W
System Clock (FSYS)
Divide (ADCDIV[2:1]=111)
FADC TADC
(1/FADC) 1 Sample
Conversion Time
48MHz @ 3V FOSC/2 24MHz 41.66ns 5.0us
24MHz @ 3V FOSC/2 12MHz 83.33ns 10.0us
[An Example of ADC Conversion Table]
. . .
SeJong200 Family [101] [101]
6.16. I2S: Feature
Inter-IC Sound Bus that is a serial link for transmitting stereo audio between devices in a system.
The I2S bus was invented by Philips Semiconductor, but is now widely used by several semiconductor manufacturers.
Format 1~16bit I2S format / MSB-justified format
Sampling Frequency 16/32/48fs
FIFO for transmit and receive 64 word entries for left and right channel
Master only Notice
All 64 word must be filled before transmission. If not, empty interrupt can be occurred.
RX_HF_INT : RX Half Full Indicator ( set by logic , clear by S/W) RX_F_INT : RX Full Indicator (set by logic, clear by S/W) RX_HF_MASK : RX Half Full Interrupt enable (0 : Interrupt disable , 1 : Interrupt enable) RX_F_MASK : RX Full Interrupt enable ( 0 : Interrupt disable, 1 : Interrupt enable)
RXEN : Receiver Enable ( 0 : Disable , 1 : Enable) RXSWAP : Position of Left Channel ( 0 : Left channel is stored on even addresses, 1 : Left channel is stored on odd addresses) RXFORMAT : Data Format ( 0 : I2S format, 1 : MSB-justified format) RXRES[4:0] : TX Sample Data Resolution Number of bits (RES + 1) that are stored in each audio word in the sample buffer. If the received signal has fewer bits than set by RES, zero padding of LSB’s is used. If the received signal has more bits than set by RES, LSB’s are truncated. Valid range is 1 to 15. RXRATIO[7:0]: Clock Divider for the Receive Frequency , The ratio between bit clock and sampling frequency.
TXEN : Tansmitter Enable ( 0 : Disable , 1 : Enable) TXSWAP : Position of Left Channel ( 0 : Left channel is stored on even addresses, 1 : Left channel is stored on odd addresses) TXFORMAT : Data Format ( 0 : I2S format, 1 : MSB-justified format) TXRES[4:0] : TX Sample Data Resolution Number of bits (RES + 1) that are stored in each audio word in the sample buffer. If the received signal has fewer bits than set by RES, zero padding of LSB’s is used. If the received signal has more bits than set by RES, LSB’s are truncated. Valid range is 1 to 15. TXRATIO[7:0]: Clock Divider for the Transmit Frequency , The ratio between bit clock and sampling frequency.
COM_IO_EN0 : COM0 (P0.03) COM_IO_EN1 : COM1 (P0.04) , If duty is static, this is SEG34 COM_IO_EN2 : COM2 (P0.05) , If duty is static or 1/2, this is SEG33 COM_IO_EN3 : COM3 (P0.06) , If duty is static, 1/2 or 1/3, this is SEG32
EXTVLCD_EN[3:0] : External VLCD input IO Enable (0: Disable , 1 : Enable) This is used when LCDC_CON.INT_VLCD_EN = 0.
Carrier Generation The carrier frequency is calculated by the following equation. Length of Carrier Signal’s High Phase : tH = CGDH / FCGC Length of Carrier Signal’s Low Phase : tL = CGDL / FCGC Carrier Frequency : FCARR = 1/(tH + tL)
Envelope Generation : 8-bit Mode
Length of Envelope Signal’s High Phase : tEH = EGDH / FEGC Length of Envelope Signal’s Low Phase : tEL = EGDL / FEGC
Envelope Generation : 16-bit Mode Length of Envelope Signal’s High or Low Phase : tEH (tEL) = (EGDH * 256 + EGDL) / FEGC
ECGC
CAOF
tH tL
CGC 0 1 2 CGDH 1 2 …… CGDL …… 1
EEGC
EVOF
tEH tEL
EGC 0 1 2 EGDH 1 2 …… EGDL …… 1
Counter Module for Remote Control Application Generates REM output : modulated or not. Consists of two Counters
EGC can be used as 8-bit or 16-bit counter Each Counter has two compare data registers. Each Counter can be used independently.
SeJong200 Family [126] [126]
6.19. UR: Registers (1 of 2)
- - - - - - - - - - ECGI ECGC EGCM EEGI EEGC EVDE
R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)
CGCON (0401h) : Carrier Generator Control Register
- - - - - - - - - - CGIF CAOF - - EGIF EVOF
R(0) R(0) R(0) R(0)
CGSTS (0400h) : Carrier Generator Status Register
CGIF : CGC Interrupt Flag Set by H/W when CGC value matches with CGDL or CGDH. Cleared by H/W when ECGI is cleared by interrupt service routine. CAOF : Carrier Output Status Flag. If CAOF is 1, CGC runs to match CGDH, otherwise CGDL. This flag is toggled automatically and cleared if ECGC is cleared. EGIF : EGC Interrupt Flag Set by H/W when EGC value matches with EGDL or EGDH. Cleared by H/W when EEGI is cleared by interrupt service routine. EVOF : Envelope Output Status Flag. In 8-bit mode, if EVOF is 1, EGC runs to match EGDH, otherwise EGDL.
ECGI : Enable CGC Interrupt ECGC : Enable CGC. CGC is reset when disabled. EGCM : EGC operation Mode [0] = 8-bit counter, [1] = 16-bit counter. EEGI : Enable EGC Interrupt EEGC : Enable EGC. EGC is reset when disabled. EVDE : Envelope Data Enable [0] = S/W can update EVOF directly. REM waveform changes immediately. [1] = H/W automatically toggles EVOF. REM waveform is synchronized to CAOF.
REMOE : REM output enable to I/O PAD control INVREM : If set, invert REM output waveform. ECS[1:0] : Envelope Counter Clock Frequency (FEGC) Selection. [0,0] = FSYS (System Clock), [0,1] = Reserved, [1,0] = FCGC (CGC clock according to CCS), [1,1] = Carrier frequency EVOE : If set, REM outputs the envelope data without modulation by carrier. CCS[2:0] : Carrier Counter Clock Frequency (FCGC) Selection. FSYS: System clock frequency for peripheral. [0,0,0] = FSYS/1, [0,0,1] = FSYS/2, [0,1,0] = FSYS/3, [0,1,1] = FSYS/4, [1,0,0] = FSYS/6, [1,0,1] = FSYS/8, [1,1,0] = FSYS/12, [1,1,1] = FSYS/16
Carrier and Envelope Generation with 16-bit EGC Mode (EGCM = 1) During the interrupt routine, a new 16-bit compare value can be written to the compare register (EGDH & EGDL) Notice, however, that a write to EGDL clears the ECMP bit, which temporarily disables the comparator function while these registers
are being updated so an invalid match does not occur. A write to EGDH sets the ECMP bit and re-enables the comparator. For this reason, user software should write to EGDL first, then the EGDH.
Two independent Timer or PWM generator Each counter can run independent to each other. But, they shares the same interrupt vector address. CGC can be used as 8-bit timer or PWM generator (EVOE = 0, EVDE = 0, EVOF = 1). EGC can be used as 8-bit or 16-bit timer or PWM generator (EVOE = 1, EVDE = 1)
Operation Sequence Upon reception of peripheral or external interrupt with pre-programmed polarity, INTC (Interrupt Controller) immediately triggers DSP Core’s interrupt line. Note that the type of all peripheral interfaces is “level-triggered, high-level”, while the type of external
interrupts is “edge-triggered” with the polarity programmed by the configuration register. In the DSP core, the interrupt masking register should be setup correctly at initially core-booting sequence. After INTC triggers the DSP core’s interrupt line, the DSP core goes into the interrupt service routine (ISR). In the DSP core’s ISR, the INTC’s another interrupt triggering with higher priority preempts the current ISR
(interrupt preemption). At the end of DSP core’s ISR, the programmer should turn off the interrupt flag in register of the interrupt
source, i.e., the peripheral interface. For the external interrupts, the DSP core should turn off the corresponding bit(s) of IFR_EXT register. Note that the chip does not ensure the disabling of external interrupts which is up to the designer controlling
the external environments.
SeJong200 Family [144] [144]
6.21. System Power Scheme
LDO_18 S_LDO LDO_25
VD33A VDDINTA VD33 VDD
VS33
VSSA
Logic part
VSS
VD33
12bit ADC
OPAMP (1.8 V only)
When differential ADC , Set VDDINTA = 1.8 V (Trim LCO_25) When single ADC, Set OPAMP off
TRIM[7:0] : S_LDO output trimming value , the enable of S_LDO is set by the S_LDO_EN in LDO_LVR_SET Register TRIM_I : S_LDO current reduce option (0 : disable , 1 : enable)
ERC : Status flag of Erase Reference Cell operation IFREN_ST : Information Block Enable Status flag PGM : Status flag of Program operation PERS : Status flag of Page Erase operation RD : Status flag of Read operation
* TA = -40 oC to +125 oC, VDDIO = +1.8 to +3.6V unless otherwise specified.
External Interrupt Pin
RESETB 0.2VDD 0.2VDD
tRST
0.8VDD 0.8VDD
0.2VDD 0.2VDD
tINT
tINT
SeJong200 Family [159]
10. Package Dimensions : 48-MLF
TOP VIEW
D
E
BOTTOM VIEW
D2
E2
1 2
48
b
e
k
Exposed PAD
L
36
24
12
Pin #1 ID
Seating Plane
A
A1 A3
SIDE VIEW
DETAIL A
DETAIL A
0.20 REF. Terminal Thickness
0.00 ~ 0.05
3
24
48
Symbol Dimensions [mm]
Min. Nom. Max. A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20 REF
D 6.00 BSC
E 6.00 BSC
D2 4.20 4.30 4.40
E2 4.20 4.30 4.40
b 0.15 0.20 0.25
e 0.40 BSC
L 0.35 0.40 0.45
k 0.20 - -
[48-MLF]
Notes: 1. All Dimension are in mm. Angles in Degrees. 2. Dimension b applies to Plated Terminal & is measured. 3. BSC : Basic Dimension. Theoretically exact value shown without tolerances. REF : Reference Dimension, Usually without tolerance, for information purpose only.
1 2
12
3
36
SeJong200 Family
DETAIL A
0.20 REF. Terminal Thickness
0.00 ~ 0.05
[160]
10. Package Dimensions : 68-MLF
D
E
34
68
17
51 2
Pin #1 ID
TOP VIEW BOTTOM VIEW
1
3
E2
Exposed PAD
1
17
2 3
68
P
k
L
51
D2
34
b
e
Seating Plane
A
A1 A3
SIDE VIEW
DETAIL A
Symbol Dimensions [mm]
Min. Nom. Max. A 0.80 0.85 0.90
A1 0.00 0.01 0.05
A3 0.20 REF
D 8.00 BSC
E 8.00 BSC
D2 4.70 4.80. 4.90
E2 4.70 4.80. 4.90
b 0.15 0.20 0.25
e 0.40 BSC
L 0.30 0.40 0.50
k 0.20 - - P 0.24 0.42 0.60
[68-MLF]
Notes: 1. All Dimension are in mm. Angles in Degrees. 2. Dimension b applies to Plated Terminal & is measured. 3. BSC : Basic Dimension. Theoretically exact value shown without tolerances. REF : Reference Dimension, Usually without tolerance, for information purpose only.
SeJong200 Family [161]
10. Package Dimensions : 88-MLF
DETAIL A
0.20 REF. Terminal Thickness
0.00 ~ 0.05
D
E
44
88
22
66 2
Pin #1 ID
TOP VIEW BOTTOM VIEW
1
3
E2
Exposed PAD
1
22
2 3
88
P
k
L
66
D2
44
b
e
Seating Plane
A
A1 A3
SIDE VIEW
DETAIL A
Symbol Dimensions [mm]
Min. Nom. Max. A 0.80 0.85 0.90
A1 0.00 0.01 0.05
A3 0.20 REF
D 10.00 BSC
E 10.00 BSC
D2 4.20 4.30. 4.40
E2 4.20 4.30. 4.40
b 0.15 0.20 0.25
e 0.40 BSC
L 0.30 0.40 0.50
k 0.20 - - P 0.24 0.42 0.60
[88-MLF]
Notes: 1. All Dimension are in mm. Angles in Degrees. 2. Dimension b applies to Plated Terminal & is measured. 3. BSC : Basic Dimension. Theoretically exact value shown without tolerances. REF : Reference Dimension, Usually without tolerance, for information purpose only.
SeJong200 Family [162]
11. Supporting tools
In-Circuit Debugger (GENSYS & GenICE)
World Wide Programmable in Anywhere (Hi-Lo Systems, ADVANTECH, TOPMAX, CORERIVER)
Support Parallel / Serial Programming
ROM Writer
Easy-to-Use GUI (GENTOS)
Assembler & Linker for Windows Optimized Cross-C Compiler
On-board Application (with Touch & MCU Demo) Various Sample Test Program
Page 140 : Add Flash Power Switch Enable Reg(0x013F)
V1.4 RTC address change (0x03A- ~ 0x03B-)
(0x03C- ~ 0x03D-)
V1.5 Added the touch sensors
V1.6 touch sensors register update
V1.6.1 88 pin map update
V1.7 Ext counter port description update for Timer2,4 the power condition for differential ADC mode setting port exclusively among LCDC, ADC and Touch update system trimming option part