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This is information on a product in full production.
March 2015 DocID023768 Rev 6 1/73
L6482
Microstepping motor controller with motion engine and SPI
Datasheet - production data
Features Operating voltage: 7.5 V - 85 V Dual full bridge gate
driver for N-channel
MOSFETs Fully programmable gate driving Embedded Miller clamp
function Programmable speed profile Up to 1/16 microstepping
Advanced current control with auto-adaptive
decay mode Integrated voltage regulators SPI interface Low
quiescent standby currents Programmable non dissipative
overcurrent
protection Overtemperature protection
Applications Bipolar stepper motor
DescriptionThe L6482 device, realized in analog mixed signal
technology, is an advanced fully integrated solution suitable for
driving two-phase bipolar stepper motors with microstepping.
It integrates a dual full bridge gate driver for N-channel
MOSFET power stages with embedded non dissipative overcurrent
protection. Thanks to a new current control, a 1/16 microstepping
is achieved through an adaptive decay mode which outperforms
traditional implementations. The digital control core can generate
user defined motion profiles with acceleration, deceleration, speed
or target position easily programmed through a dedicated register
set. All application commands and data registers, including those
used to set analog values (i.e. current protection trip point,
deadtime, PWM frequency, etc.) are sent through a standard 5-Mbit/s
SPI. A very rich set of protections (thermal, low bus voltage,
overcurrent and motor stall) makes the L6482 device bullet proof,
as required by the most demanding motor control applications.
HTSSOP38
Table 1. Device summaryOrder code Package Packaging
L6482H HTSSOP38 Tube
L6482HTR HTSSOP38 Tape and reel
www.st.com
http://www.st.com
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Contents L6482
2/73 DocID023768 Rev 6
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 8
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 92.1 Absolute maximum
ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 9
2.2 Recommended operating conditions . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 10
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 10
3 Electrical characteristics . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 11
4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 16Pin list . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 16
5 Typical applications . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 18
6 Functional description . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 196.1 Device power-up . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 19
6.2 Logic I/O . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 Charge pump . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 19
6.4 Microstepping . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 20Automatic Full-step
and Boost modes . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 21
6.5 Absolute position counter . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 22
6.6 Programmable speed profiles . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 22
6.7 Motor control commands . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 236.7.1 Constant speed commands
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
6.7.2 Positioning commands . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 23
6.7.3 Motion commands . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 24
6.7.4 Stop commands . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 25
6.7.5 Step-clock mode . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 25
6.7.6 GoUntil and ReleaseSW commands . . . . . . . . . . . . . .
. . . . . . . . . . . . . 25
6.8 Internal oscillator and oscillator driver . . . . . . . . .
. . . . . . . . . . . . . . . . . . 266.8.1 Internal oscillator . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 26
6.8.2 External clock source . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 26
6.9 Overcurrent detection . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 27
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DocID023768 Rev 6 3/73
L6482 Contents
73
6.10 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 28
6.11 VS undervoltage lockout (UVLO_ADC) . . . . . . . . . . . .
. . . . . . . . . . . . . . 29
6.12 Thermal warning and thermal shutdown . . . . . . . . . . .
. . . . . . . . . . . . . . 29
6.13 Reset and standby . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 30
6.14 External switch (SW pin) . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 30
6.15 Programmable gate drivers . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 31
6.16 Deadtime and blanking time . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 32
6.17 Integrated analog-to-digital converter . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 32
6.18 Supply management and internal voltage regulators . . . . .
. . . . . . . . . . . 33
6.19 BUSY/SYNC pin . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 34
6.20 FLAG pin . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 34
7 Phase current control . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 357.1 Predictive current
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 35
7.2 Auto-adjusted decay mode . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 36
7.3 Auto-adjusted fast decay during the falling steps . . . . .
. . . . . . . . . . . . . . 38
7.4 Torque regulation (output current amplitude regulation) . .
. . . . . . . . . . . . 39
8 Serial interface . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 41
9 Programming manual . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 439.1 Register and flag
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 43
9.1.1 ABS_POS . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 44
9.1.2 EL_POS . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 44
9.1.3 MARK . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 45
9.1.4 SPEED . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 45
9.1.5 ACC . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1.6 DEC . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1.7 MAX_SPEED . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 46
9.1.8 MIN_SPEED . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 46
9.1.9 FS_SPD . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 47
9.1.10 TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC . . . . . . .
. . . . . 47
9.1.11 T_FAST . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 48
9.1.12 TON_MIN . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 48
9.1.13 TOFF_MIN . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 49
9.1.14 ADC_OUT . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 50
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Contents L6482
4/73 DocID023768 Rev 6
9.1.15 OCD_TH . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 50
9.1.16 STEP_MODE . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 50
9.1.17 ALARM_EN . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 52
9.1.18 GATECFG1 . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 52
9.1.19 GATECFG2 . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 54
9.1.20 CONFIG . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 55
9.1.21 STATUS . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 58
9.2 Application commands . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 609.2.1 Command management .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 61
9.2.2 Nop . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.3 SetParam (PARAM, VALUE) . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 62
9.2.4 GetParam (PARAM) . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 62
9.2.5 Run (DIR, SPD) . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 63
9.2.6 StepClock (DIR) . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 63
9.2.7 Move (DIR, N_STEP) . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 64
9.2.8 GoTo (ABS_POS) . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 64
9.2.9 GoTo_DIR (DIR, ABS_POS) . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 65
9.2.10 GoUntil (ACT, DIR, SPD) . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 65
9.2.11 ReleaseSW (ACT, DIR) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 66
9.2.12 GoHome . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 66
9.2.13 GoMark . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.14 ResetPos . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.15 ResetDevice . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 67
9.2.16 SoftStop . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.17 HardStop . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.18 SoftHiZ . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.19 HardHiZ . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 68
9.2.20 GetStatus . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 69
10 Package information . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 70HTSSOP38 package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 70
11 Revision history . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 72
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DocID023768 Rev 6 5/73
L6482 List of tables
73
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 1Table 2. Absolute maximum ratings . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 9Table 3. Recommended operating conditions . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 10Table 5. Electrical characteristics . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 11Table 6. Pin description . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 16Table 7. Typical application values. . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 18Table 8. CL values according to external
oscillator frequency . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 26Table 9. UVLO thresholds . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 29Table 10. Thermal protection summarizing table .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 30Table 11. Register map . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 43Table 12. EL_POS register . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 44Table 13. MIN_SPEED register . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 46Table 14. FS_SPD register . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 47Table 15. Torque regulation by
TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN
registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 48Table 16. FS_SPD register . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 48Table 17. Maximum fast decay times . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . 48Table 18. Minimum on-time . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 49Table 19. Minimum off-time . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 49Table 20. ADC_OUT value and torque regulation
feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 50Table 21. Overcurrent detection threshold . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 50Table 22. STEP_MODE register. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 50Table 23. Step mode selection . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 51Table 24. SYNC output frequency . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 51Table 25. SYNC signal source . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 52Table 26. ALARM_EN register . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 52Table 27. GATECFG1 register . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 52Table 28. IGATE parameter . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 53Table 29. TCC parameter . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 53Table 30. TBOOST parameter . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 54Table 31. GATECFG2 register (voltage
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 54Table 32. TDT parameter . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 54Table 33. TBLANK parameters. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 55Table 34. CONFIG register . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 55Table 35. Oscillator management
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 56Table 36. External switch
HardStop interrupt mode . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 56Table 37. Overcurrent event . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 57Table 38. Programmable VCC
regulator output voltage . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 57Table 39. Programmable UVLO
thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 57Table 40. External torque
regulation enable. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 57Table 41. Switching period
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 57Table 42. Motor
supply voltage compensation enable . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 58Table 43. STATUS
register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 44.
STATUS register TH_STATUS bits . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 59Table 45. STATUS
register DIR bit. . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 59Table 46.
STATUS register MOT_STATUS bits . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 59Table 47.
Application commands . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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List of tables L6482
6/73 DocID023768 Rev 6
Table 48. Nop command structure . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 62Table 49. SetParam command structure . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62Table 50. GetParam command structure . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62Table 51. Run command structure . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63Table 52. StepClock command structure . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63Table 53. Move command structure . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64Table 54. GoTo command structure . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64Table 55. GoTo_DIR command structure. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65Table 56. GoUntil command structure . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65Table 57. ReleaseSW command structure . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66Table 58. GoHome command structure . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66Table 59. GoMark command structure . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66Table 60. ResetPos command structure . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67Table 61. ResetDevice command structure . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67Table 62. SoftStop command structure . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67Table 63. HardStop command structure. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68Table 64. SoftHiZ command structure . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68Table 65. HardHiZ command structure. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68Table 66. GetStatus command structure . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69Table 67. HTSSOP38 package mechanical data . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table
68. Document revision history . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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DocID023768 Rev 6 7/73
L6482 List of figures
73
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 8Figure 2. Pin connection (top view) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 16Figure 3. Typical application schematic . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 18Figure 4. Charge pump circuitry. . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 20Figure 5. Normal mode and microstepping (16
microsteps) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 20Figure 6. Automatic Full-step switching in Normal mode. . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21Figure 7. Automatic Full-step switching in Boost mode . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure
8. Constant speed command examples . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 9.
Positioning command examples . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 10.
Motion command examples . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 11.
OSCIN and OSCOUT pin configuration . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 27Figure 12.
Overcurrent detection - principle scheme . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 28Figure 13.
External switch connection . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure
14. Gate driving currents . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32Figure 15. Device supply pin management . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33Figure 16. Predictive current control . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 35Figure 17. Non-predictive current control. . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 36Figure 18. Adaptive decay - fast decay tuning. . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 37Figure 19. Adaptive decay - switch from normal to slow + fast
decay mode and vice versa . . . . . . . . 38Figure 20. Fast decay
tuning during the falling steps . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 39Figure 21. Current sensing
and reference voltage generation. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 40Figure 22. SPI timings diagram . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 41Figure 23. Daisy chain
configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 42Figure 24. Command
with 3-byte argument . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 61Figure 25. Command with
3-byte response . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 61Figure 26. Command response
aborted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 61Figure 27. HTSSOP38 package
outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 70Figure 28. HTSSOP38 footprint
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 71
-
Block diagram L6482
8/73 DocID023768 Rev 6
1 Block diagram
Figure 1. Block diagram
ADC
Chargepump
Vdd
SP
I
Currentsensing
STBY/RESET
FLAG
CS
CK
SDO
SDI
BUSY/SYNC
SW
STCK
DGND
VDD
ADCIN
VCC CP VBOOT
PGND
VS
CORELOGIC
VCC
HVGA1
LVGA1
HVGA2
LVGA2
HVB1
LVGB1
OUTA1
OUTA2
OUTB1
HVGB2
LVGB2
OUTB2
Vboot
Vboot
Vboot
Vboot
VSENSEA
VSENSEB
AGND
VCC
VCC
VCC
Voltage reg. VCC
VSREG VCC REG
Ext. Osc. driver&
Clock gen.
OSCIN OSCOUT
16 MHzOscillator
Temperaturesensing
VREG
Voltage reg. VREG
AM15031v1
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DocID023768 Rev 6 9/73
L6482 Electrical data
73
2 Electrical data
2.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Test condition Value Unit
VDD Logic interface supply voltage 5.5 V
VREG Logic supply voltage 3.6
VS Motor supply voltage 95 V
VCC Low-side gate driver supply voltage 18 V
VBOOT Boot voltage 100 V
VBOOT High-side gate driver supply voltage (VBOOT - VS) 0 to 20
V
VSREG Internal VCC regulator supply voltage 95 V
VCCREG Internal VREG regulator supply voltage 18 V
VOUT1A VOUT2A VOUT1B VOUT2B
Full bridge output voltage
DC -5 to VBOOT V
AC -15 to VBOOT
SRout Full bridge output slew rate (10% - 90%) 10 V/ns
VHVG1A VHVG2A VHVG1B VHVG2B
High-side output driver voltage VOUT to VBOOT V
VHVG1A VHVG2A VHVG1B VHVG2B
High-side output driver to respective bridge output voltage(VHVG
- VOUT)
15 V
VLVG1A VLVG2A VLVG1B VLVG2B
Low-side output driver voltage VCC + 0.3 V
IGATE-CLAMP High-side gate voltage clamp current capability 100
mA
VADCIN Integrated ADC input voltage range (ADCIN pin) -0.3 to
3.6 V
Vout_diffDifferential voltage between VBOOT, VS, OUT1A, OUT2A,
PGND and VBOOT, VS, OUT1B, OUT2B, PGND pins 100 V
Vin Logic inputs voltage range -0.3 to 5.5 V
Ts TOP Storage and operating junction temperature -40 to 150
C
Ptot Total power dissipation (Tamb = 25 C) (1) 4 W
1. HTSSOP38 mounted on a four-layer FR4 PCB with a dissipating
copper surface of about 30 cm2.
-
Electrical data L6482
10/73 DocID023768 Rev 6
2.2 Recommended operating conditions
2.3 Thermal data
Table 3. Recommended operating conditionsSymbol Parameter Test
condition Min. Typ. Max. Unit
VDD Logic interface supply voltage3.3 V logic outputs 3.3
V5 V logic outputs 5
VREG Logic supply voltage 3.3 V
VS Motor supply voltage VSREG 85 V
VSREG Internal VCC voltage regulator VCC voltage internally
generated VCC +3 Vs V
VCC Gate driver supply voltageVCC voltage imposed by external
source (VSREG = VCC)
7.5 15 V
VCCREGInternal VREG voltage regulator supply voltage VREG
voltage internally generated 6.3 VCC V
VADCIntegrated ADC input voltage (ADCIN pin) 0 VREG V
Table 4. Thermal dataSymbol Parameter Package Typ. Unit
Rthj-a Thermal resistance junction to ambient HTSSOP38(1) 31
C/W
1. HTSSOP38 mounted on a four-layer FR4 PCB with a dissipating
copper surface of about 30 cm2.
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DocID023768 Rev 6 11/73
L6482 Electrical characteristics
73
3 Electrical characteristics
VS = 48 V; VCC = 7.5 V; Tj = 25 C, unless otherwise
specified.
Table 5. Electrical characteristicsSymbol Parameter Test
condition Min. Typ. Max. Unit
General
VCCthOn VCC UVLO turn-on thresholdUVLO_VAL set high(1) 9.9 10.4
10.9 V
UVLO_VAL set low(1) 6.5 6.9 7.3 V
VCCthOff VCC UVLO turn-off thresholdUVLO_VAL set high(1) 9.5 10
10.5 V
UVLO_VAL set low(1) 5.9 6.3 6.7 V
VBOOTthOn VBOOT - VS UVLO turn-on thresholdUVLO_VAL set high(1)
8.6 9.2 9.8 V
UVLO_VAL set low(1) 5.7 6 6.3 V
VBOOTthOff VBOOT - VS UVLO turn-off thresholdUVLO_VAL set
high(1) 8.2 8.8 9.5 V
UVLO_VAL set low(1) 5.3 5.5 5.8 V
VREGthOn VREG turn-on threshold (1) 2.8 3 3.18 V
VREGthOff VREG turn-off threshold (1) 2.2 2.4 2.5 V
IVREGquUndervoltage VREG quiescent supply current VCCREG = VREG
< 2.2 V 40 A
IVREGq Quiescent VSREG supply currentVCCREG = VREG = 3.3 V,
internal oscillator selected(1)
3.8 mA
IVSREGq Quiescent VSREG supply current VCCREG = VREG = 15 V 6.5
mA
Thermal protection
Tj(WRN)Set Thermal warning temperature 135 C
Tj(WRN)Rec Thermal warning recovery temperature 125 C
Tj(OFF)Set Thermal bridge shutdown temperature 155 C
Tj(OFF)RecThermal bridge shutdown recovery temperature 145 C
Tj(SD)Set Thermal device shutdown temperature 170 C
Tj(SD)RecThermal device shutdown recovery temperature 130 C
Charge pump
Vpump Voltage swing for charge pump oscillator VCC V
fpump,minMinimum charge pump oscillator frequency(2) 660 kHz
fpump,maxMaximum charge pump oscillator frequency(2) 800 kHz
-
Electrical characteristics L6482
12/73 DocID023768 Rev 6
RpumpHS Charge pump high-side RDS(on) resistance 10
RpumpLS Charge pump low-side RDS(ON) resistance 10
Iboot Average boot current 2.6 mA
Gate driver outputs
IGATE,SinkProgrammable high-side and low-side gate sink
current
VS = 38 VVHVGX - VOUTX > 3 VVLVGX > 3 V
2.4 4 5.6
mA
5.4 8 10.6
11.3 16 20.7
17.3 24 30.7
23.2 32 40.8
50.2 64 77.8
81 96 113
IGATE,SourceProgrammable high-side and low-side gate source
current
VS = 38 VVBOOTX - VHVGX > 3.5 VVCC-VLVGX > 3.5 V
2.8 4 5.2
mA
5.8 8 10.2
12 16 20
18 24 30
24 32 40
51 64 77
82 96 112
IOBHigh-side and low-side turn-off overboost gate current 85 103
117 mA
RCLAMP(LS)Low-side gate driver Miller clamp resistance 6.5
10
RCLAMP(HS)High-side gate driver Miller clamp resistance 3 10
VGATE-CLAMP High-side gate voltage clamp IGATE-CLAMP = 100 mA
16.7 v
tccProgrammable constant gate current time(2)
TCC = 00000 125ns
TCC = 11111 3750
tOBProgrammable. Turn-off overboost; gate current time(2)
TBOOST = 001, internal oscillator 62.5 ns
TBOOST =111 1000
IDSS Leakage currentOUT = VS 100 A
OUT = GND -100 A
tr Rise timeIGATE = 96 mAVCC = 15 VCGATE = 15 nF
2.5 s
Table 5. Electrical characteristics (continued)Symbol Parameter
Test condition Min. Typ. Max. Unit
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DocID023768 Rev 6 13/73
L6482 Electrical characteristics
73
tf Fall time IGATE = 96 mAVCC = 15 VCGATE = 15 nF
2.5 s
SRgate Gate driver output slew rateIGATE = 96 mAVCC = 15 VCGATE
= 15 nF
6 V/s
Deadtime and blanking
tDT Programmable deadtime(2) TDT = '00000' 125
nsTDT = 11111 4000
tblank Programmable blanking time(2) TBLANK = '000' 125
nsTBLANK = 111 1000
Logic
VIL Low level logic input voltage 0.8 V
VIH High level logic input voltage 2 V
IIH High level logic input current VIN = 5 V, VDDIO = 5 V 1
A
IIL Low level logic input current VIN = 0 V, VDDIO = 5 V -1
A
VOL Low level logic output voltage(3)VDD = 3.3 V, IOL = 4 mA
0.3
VVDD = 5 V, IOL = 4 mA 0.3
VOH High level logic output voltageVDD = 3.3 V, IOH = 4 mA
2.4
VVDD = 5 V, IOH = 4 mA 4.7
RPUCS CS pull-up resistor 430
kRPDRST STBY/RESET pull-down resistor 450
RPUSW SW pull-up resistor 80
thigh,STCK Step-clock input high time 300 ns
tlow,STCK Step-clock input low time 300 ns
Internal oscillator and external oscillator driver
fosc,int Internal oscillator frequency Tj = 25 C -5% 16 +5%
MHz
fosc,extProgrammable external oscillator frequency 8 32 MHz
VOSCOUTH OSCOUT clock source high level voltage Internal
oscillator 2.4 V
VOSCOUTL OSCOUT clock source low level voltage Internal
oscillator 0.3 V
trOSCOUTtfOSCOUT
OSCOUT clock source rise and fall time Internal oscillator 10
ns
thigh OSCOUT clock source high timeInternal oscillator
31.25 ns
Table 5. Electrical characteristics (continued)Symbol Parameter
Test condition Min. Typ. Max. Unit
-
Electrical characteristics L6482
14/73 DocID023768 Rev 6
textoscInternal to external oscillator switching delay 3 ms
tintoscExternal to internal oscillator switching delay 100 s
SPI
fCK,MAX Maximum SPI clock frequency(4) 5 MHz
trCKtfCK
SPI clock rise and fall time(4) 1 s
thCKtlCK
SPI clock high and low time(4) 90 ns
tsetCS Chip select setup time(4) 30 ns
tholCS Chip select hold time (4) 30 ns
tdisCS Deselect time(4) 625 ns
tsetSDI Data input setup time(4) 20 ns
tholSDI Data input hold time(4) 30 ns
tenSDO Data output enable time(4) 95 ns
tdisSDO Data output disable time(4) 95 ns
tvSDO Data output valid time(4) 35 ns
tholSDO Data output hold time(4) 0 ns
Current control
VREF, max Maximum reference voltage 1000 mV
VREF, min Minimum reference voltage 7.8 mV
Overcurrent protection
VOCDProgrammable overcurrent detection voltage VDS threshold
OCD_TH = 11111 800 1000 1100 mV
OCD_TH = 00000 27 31 35 mV
OCD_TH = 01001 270 312.5 344 mV
OCD_TH = 10011 500 625 688 mV
tOCD,Comp OCD comparator delay 100 200 ns
tOCD,Flag OCD to flag signal delay time 230 530 ns
tOCD,SD OCD to shutdown delay timeOCD_TH = '11111'OCD event to
90% of gate voltage
400 630 ns
Table 5. Electrical characteristics (continued)Symbol Parameter
Test condition Min. Typ. Max. Unit
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DocID023768 Rev 6 15/73
L6482 Electrical characteristics
73
Standby
ISTBYStandby mode supply current (VSREG pin)
VCC = VCCREG = 7.5 V VSREG = 48 V
42A
VCC = VCCREG = 7.5 V VSREG = 18 V
37.5
ISTBY,vreg Standby mode supply current (VREG pin) 6 A
tSTBY,min Minimum standby time 0.5 ms
tlogicwu Logic power-on and wake-up time 500 s
tcpwu Charge pump power-on and wake-up timePower bridges
disabled,Cp = 10 nF, Cboot = 220 nF, VCC= 15 V
1 ms
Internal voltage regulators
VCCOUTInternal VCC voltage regulator output voltage
Low (default), ICC = 10 mA 7.3 7.5 V
High, ICC = 10 mA 4 15
VCCREG, drop VSREG to VCC dropout voltage ICC = 50 mA 3 V
PCCInternal VCC voltage regulator power dissipation 2.5 W
VREGOUTInternal VREG voltage regulator output voltage IREG = 10
mA
3.135 3.3 V
VSREG, drop VCCREG to VREG dropout voltage IREG = 50 mA 3 V
IREGOUTInternal VREG voltage regulator output current
VREG pin shorted to ground 125 mA
IREGOUT,STBY
Internal VREG voltage regulator output standby current
VREG pin shorted to ground 55 mA
PREGInternal VREG voltage regulator power dissipation 0.5 W
Integrated analog-to-digital converter
NADC Analog-to-digital converter resolution 5 bit
VADC,refAnalog-to-digital converter reference voltage 3.3 V
fSAnalog-to-digital converter sampling frequency
(2) fOSC/512 kHz
VADC,UVLO ADCIN UVLO threshold 1.05 1.16 1.35 V
1. Guaranteed in the temperature range -25 to 125 C.2. The value
accuracy is dependent on oscillator frequency accuracy (Section 6.8
on page 26).
3. FLAG and BUSY open drain outputs included.
4. See Figure 22 on page 41.
Table 5. Electrical characteristics (continued)Symbol Parameter
Test condition Min. Typ. Max. Unit
-
Pin connection L6482
16/73 DocID023768 Rev 6
4 Pin connection
Pin list
Figure 2. Pin connection (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
VCCREG
VCC
CP
VBOOT
PGND
ADCIN
NC
HVGA1
LVGA1
OUTA1
HVGB1
OUTB1
LVGB1
VS
VSREG
VREG
OSCIN
OSCOUT
AGND
VDDIO
SW
STCK
DGND
SDO
SDI
CK
EPADHVGA2
SENSEA
SENSEB
LVGA2
OUTA2
HVGB2
OUTB2
LVGB2
CS
FLAG
STBY/RESET
BUSY/SYNC
AM15032v1
Table 6. Pin descriptionNo. Name Type Function
11 VCCREG Power supply Internal VREG voltage regulator supply
voltage
13 VREG Power supply Logic supply voltage
27 VDD Power supply Logic interface supply voltage
12 VSREG Power supply Internal VCC voltage regulator supply
voltage
10 VCC Power supply Gate driver supply voltage
14 OSCIN Analog input Oscillator pin1. To connect an external
oscillator or clock source.
15 OSCOUT Analog output Oscillator pin2. To connect an external
oscillator. When the internal oscillator is used, this pin can
supply a 2/4/8/16 MHz clock.
9 CP Output Charge pump oscillator output
7 VBOOT Power supply Bootstrap voltage needed for driving the
high-side power DMOS of both bridges (A and B).
5 ADCIN Analog input Internal analog-to-digital converter
input
6 VS Power supply Motor voltage
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DocID023768 Rev 6 17/73
L6482 Pin connection
73
3 HVGA1 Power output High-side half-bridge A1 gate driver
output
36 HVGA2 Power output High-side half-bridge A2 gate driver
output
17 HVGB1 Power output High-side half-bridge B1 gate driver
output
22 HVGB2 Power output High-side half-bridge B2 gate driver
output
1 LVGA1 Power output Low-side half-bridge A1 gate driver
output
38 LVGA2 Power output Low-side half-bridge A2 gate driver
output
19 LVGB1 Power output Low-side half-bridge B1 gate driver
output
20 LVGB2 Power output Low-side half-bridge B2 gate driver
output
8 PGND Ground Power ground pins. They must be connected to other
ground pins
35 SENSEA Analog input Phase A current sensing input
23 SENSEB Analog input Phase B current sensing input
2 OUTA1 Power input Full bridge A output 1
37 OUTA2 Power input Full bridge A output 2
18 OUTB1 Power input Full bridge B output 1
21 OUTB2 Power input Full bridge B output 2
16 AGND Ground Analog ground. It must be connected to other
ground pins
33 SW Logical input External switch input pin
29 DGND Ground Digital ground. It must be connected to other
ground pins
28 SDO Logical output Data output pin for serial interface
26 SDI Logical input Data input pin for serial interface
25 CK Logical input Serial interface clock
24 CS Logical input Chip select input pin for serial
interface
30 BUSY/SYNC Open drain output
By default, the BUSY / SYNC pin is forced low when the device is
performing a command.The pin can be programmed in order to generate
a synchronization signal.
31 FLAG Open drain output
Status flag pin. An internal open drain transistor can pull the
pin to GND when a programmed alarm condition occurs (step loss,
OCD, thermal pre-warning or shutdown, UVLO, wrong command,
non-performable command).
34STBY
RESETLogical input
Standby and reset pin. LOW logic level puts the device in
Standby mode and reset logic.If not used, it should be connected to
VREG.
32 STCK Logical input Step-clock input
EPAD Exposed pad Ground Exposed pad. It must be connected to
other ground pins.
Table 6. Pin description (continued)No. Name Type Function
-
Typical applications L6482
18/73 DocID023768 Rev 6
5 Typical applications
Figure 3. Typical application schematic
Table 7. Typical application valuesName Value
CVSPOL 220 F
CVS 220 nF
CBOOT 470 nF
CFLY 47 nF
CVSREG 100 nF
CVCC 470 nF
CVCCREG 100 nF
CVREG 100 nF
CVREGPOL 22 F
CVDD 100 nF
D1 Charge pump diodes
Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 STD25N10F7
RPU 39 k
RSENSE 0.2 (maximum phase current 5 A)
CK
SDO
SDI
SW
STCK
DGND
VDD
ADCIN
Analog signal
VCC CP VBOOT
PGND
VS
STBY/RESET
FLAG
CS
BUSY/SYNCHVGA1
L VGA1
LVGA2
HVGA2
HVGB1
LVGB1
OUTA1
OUTA2
OUTB1
LVGB2
HVGB2
SENSEB
OUTB2
SENSEA
AGND
VSREGVCCREG
OSCIN
OSCOUT
VREG
L6482
CFLY
CVS
CVCCCVCCREGCVDD
CVSREG
CBOOT CVSPOL
VS
C VREG
CVREGPOL
(10.5V - 85V )
D1
Q1 Q2
Q4Q3
RSENSE
RSENSE
Q5 Q6
Q8Q7
Motor
RPU
RPU
HOST
AM15033v1
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L6482 Functional description
73
6 Functional description
6.1 Device power-upDuring power-up, the device is under reset
(all logic IOs disabled and power bridges in high impedance state)
until the following conditions are satisfied: VREG is greater than
VREGthOn Internal oscillator is operative STBY/RESET input is
forced high.
After power-up, the device state is the following: Parameters
are set to default Internal logic is driven by internal oscillator
and a 2-MHz clock is provided by the
OSCOUT pin Bridges are disabled (high impedance). FLAG output is
forced low (UVLO failure indication).
After power-up, a period of tlogicwu must pass before applying a
command to allow proper oscillator and logic startup.
Any movement command makes the device exit from High Z state
(HardStop and SoftStop included).
6.2 Logic I/OPins CS, CK, SDI, STCK, SW and STBY/RESET are
TTL/CMOS 3.3 V -5 V compatible logic inputs.
Pin SDO is a TTL/CMOS compatible logic output. VDD pin voltage
imposes a logical output voltage range.
Pins FLAG and BUSY/SYNC are open drain outputs.
SW and CS inputs are internally pulled up to VDD and STBY/RESET
input is internally pulled down to ground.
6.3 Charge pumpTo ensure the correct driving of the high-side
gate drivers, a voltage higher than the motor power supply voltage
needs to be applied to the VBOOT pin. The high-side gate driver
supply voltage VBOOT is obtained through an oscillator and a few
external components realizing a charge pump (see Figure 4).
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Functional description L6482
20/73 DocID023768 Rev 6
Figure 4. Charge pump circuitry
6.4 MicrosteppingThe driver is able to divide the single step
into up to 16 microsteps. Stepping mode can be programmed by the
STEP_SEL parameter in the STEP_MODE register (Table 22 on page
50).
Step mode can only be changed when bridges are disabled. Every
time the step mode is changed, the electrical position (i.e. the
point of microstepping sine wave that is generated) is reset to
zero and the absolute position counter value (Section 6.5) becomes
meaningless.
Figure 5. Normal mode and microstepping (16 microsteps)
VS
VS + VCP D1 D2
VCP
fPUMP
to high-sidegate drivers
VS + VCP VD1
CBOOT
CFLYD1D2
VBOOT CP
VDD
V V
Charge pump oscillator
AM15034v1
step 1 step 1step 2 step 3 step 4 step 1
Resetposition
step 1step 2 step 3 step 4
Normal driving Microstepping
PHASE A currentPHASE B current
PHASE A currentPHASE B current
microsteps
1616
microsteps
16 16
Resetposition
microsteps microsteps microsteps
AM15035v1
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L6482 Functional description
73
Automatic Full-step and Boost modesWhen motor speed is greater
than a programmable full-step speed threshold, the L6482 device
switches automatically to Full-step mode; the driving mode returns
to microstepping when motor speed decreases below the full-step
speed threshold.
The switching between the microstepping and Full-step mode and
vice versa is always performed at an electrical position multiple
of /4 (Figure 6 and Figure 7).
Full-step speed threshold is set through the related parameter
in the FS_SPD register (Section 9.1.9 on page 47).
When the BOOST_MODE bit of the FS_SPD register is low (default),
the amplitude of the voltage squarewave in Full-step mode is equal
to the peak of the voltage sine wave multiplied by sine(/4) (Figure
6). This avoids the current drop between the two driving modes.
When the BOOST_MODE bit of the FS_SPD register is high, the
amplitude of the voltage squarewave in Full-step mode is equal to
the peak of the voltage sine wave (Figure 7). That improves the
output current increasing the maximum motor torque.
Figure 6. Automatic Full-step switching in Normal mode
Phase A
Phase B
(2N+1) x /4 (2N+1) x /4
Full-StepMicrostepping Microstepping
Vpeaksin( /4 )x Vpeak
AM15036v1
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Functional description L6482
22/73 DocID023768 Rev 6
Figure 7. Automatic Full-step switching in Boost mode
6.5 Absolute position counterAn internal 22-bit register
(ABS_POS) records all the motor motions according to the selected
step mode; the stored value unit is equal to the selected step mode
(full, half, quarter, etc.). The position range is from -221 to
+221-1 steps (see Section 9.1.1 on page 44).
6.6 Programmable speed profilesThe user can easily program a
customized speed profile defining independently acceleration,
deceleration, and maximum and minimum speed values by ACC, DEC,
MAX_SPEED and MIN_SPEED registers respectively (see Section 9.1.5
on page 45, 9.1.6 on page 45, 9.1.7 on page 46 and 9.1.8 on page
46).
When a command is sent to the device, the integrated logic
generates the microstep frequency profile that performs a motor
motion compliant to speed profile boundaries.
All acceleration parameters are expressed in step/tick2 and all
speed parameters are expressed in step/tick; the unit of
measurement does not depend on the selected step mode. Acceleration
and deceleration parameters range from 2-40 to (212-2) 2-40
step/tick2 (equivalent to 14.55 to 59590 step/s2).
Minimum speed parameter ranges from 0 to (212-1) 2-24 step/tick
(equivalent to 0 to 976.3 step/s).
Maximum speed parameter ranges from 2-18 to (210-1) 2-18
step/tick (equivalent to 15.25 to 15610 step/s).
Phase A
Phase B
(2N+1) x /4 (2N+1) x /4
Full-StepMicrostepping Microstepping
Vpeak
Vpeak
AM15037v1
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L6482 Functional description
73
6.7 Motor control commandsThe L6482 can accept different types
of commands: constant speed commands (Run, GoUntil, ReleaseSW)
absolute positioning commands (GoTo, GoTo_DIR, GoHome, GoMark)
motion commands (Move) stop commands (SoftStop, HardStop, SoftHiz,
HardHiz).
For detailed command descriptions refer to Section 9.2 on page
60.
6.7.1 Constant speed commandsA constant speed command produces a
motion in order to reach and maintain a user-defined target speed
starting from the programmed minimum speed (set in the MIN_SPEED
register) and with the programmed acceleration/deceleration value
(set in the ACC and DEC registers). A new constant speed command
can be requested anytime.
Figure 8. Constant speed command examples
6.7.2 Positioning commandsAn absolute positioning command
produces a motion in order to reach a user-defined position that is
sent to the device together with the command. The position can be
reached performing the minimum path (minimum physical distance) or
forcing a direction (see Figure 9).
Performed motor motion is compliant to programmed speed profile
boundaries (acceleration, deceleration, minimum and maximum
speed).
Note that with some speed profiles or positioning commands, the
deceleration phase can start before the maximum speed is
reached.
AM15039v1
SPD1
SPD2
SPD3
SPD4
Run(SPD2,FW)
time
Speed(step frequency)
Run(SPD3,FW)
Run(SPD1,FW)
Run(SPD4,BW)
Minimum speed
Minimum speed
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Functional description L6482
24/73 DocID023768 Rev 6
Figure 9. Positioning command examples
6.7.3 Motion commandsMotion commands produce a motion in order
to perform a user-defined number of microsteps in a user-defined
direction that are sent to the device together with the command
(see Figure 10).
Performed motor motion is compliant to programmed speed profile
boundaries (acceleration, deceleration, minimum and maximum
speed).
Note that with some speed profiles or motion commands, the
deceleration phase can start before the maximum speed is
reached.
Figure 10. Motion command examples
AM15040v1
Forwarddirection
0
-2 21 +2 21-1
0
-2 21 +2 21-1
Presentposition
Targetposition
Presentposition
Targetposition
GoTo(Target pos) GoTo_DIR(Target pos,FW)
programmedACCELERATION
SPEED
programmedmaximum
speed
programmedminimum
speed
time
programmedDECELERATION
programmed number of microsteps
programmedACCELERATION
SPEED
programmedmaximum
speed
programmedminimum
speed
time
programmedDECELERATION
programmed number of microsteps
Note: with someAcceleration/Decelaration profiles the programmed
maximum speed
is never reached
AM15041v1
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L6482 Functional description
73
6.7.4 Stop commandsA stop command forces the motor to stop. Stop
commands can be sent anytime.
The SoftStop command causes the motor to decelerate with a
programmed deceleration value until the MIN_SPEED value is reached
and then stops the motor keeping the rotor position (a holding
torque is applied).
The HardStop command stops the motor instantly, ignoring
deceleration constraints and keeping the rotor position (a holding
torque is applied).
The SoftHiZ command causes the motor to decelerate with a
programmed deceleration value until the MIN_SPEED value is reached
and then forces the bridges into high impedance state (no holding
torque is present).
The HardHiZ command instantly forces the bridges into high
impedance state (no holding torque is present).
6.7.5 Step-clock modeIn Step-clock mode the motor motion is
defined by the step-clock signal applied to the STCK pin. At each
step-clock rising edge, the motor is moved one microstep in the
programmed direction and the absolute position is consequently
updated.
When the system is in Step-clock mode, the SCK_MOD flag in the
STATUS register is raised, the SPEED register is set to zero and
the motor status is considered stopped regardless of the STCK
signal frequency (the MOT_STATUS parameter in the STATUS register
equal to 00).
6.7.6 GoUntil and ReleaseSW commandsIn most applications the
power-up position of the stepper motor is undefined, so an
initialization algorithm driving the motor to a known position is
necessary.
The GoUntil and ReleaseSW commands can be used in combination
with external switch input (see Section 6.14 on page 30) to easily
initialize the motor position.
The GoUntil command makes the motor run at target constant speed
until the SW input is forced low (falling edge). When this event
occurs, one of the following actions can be performed: ABS_POS
register is set to zero (home position) and the motor decelerates
to zero
speed (as a SoftStop command) ABS_POS register value is stored
in the MARK register and the motor decelerates to
zero speed (as a SoftStop command).
If the SW_MODE bit of the CONFIG register is set to 0, the motor
does not decelerate but it immediately stops (as a HardStop
command).
The ReleaseSW command makes the motor run at a programmed
minimum speed until the SW input is forced high (rising edge). When
this event occurs, one of the following actions can be performed:
ABS_POS register is set to zero (home position) and the motor
immediately stops
(as a HardStop command) ABS_POS register value is stored in the
MARK register and the motor immediately
stops (as a HardStop command).
If the programmed minimum speed is less than 5 step/s, the motor
is driven at 5 step/s.
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Functional description L6482
26/73 DocID023768 Rev 6
6.8 Internal oscillator and oscillator driverThe control logic
clock can be supplied by the internal 16-MHz oscillator, an
external oscillator (crystal or ceramic resonator) or a direct
clock signal.
These working modes can be selected by EXT_CLK and OSC_SEL
parameters in the CONFIG register (see Table 35 on page 56).
At power-up the device starts using the internal oscillator and
provides a 2-MHz clock signal on the OSCOUT pin.
Attention: In any case, before changing clock source
configuration, a hardware reset is mandatory. Switching to
different clock configurations during operation may cause
unexpected behavior.
6.8.1 Internal oscillatorIn this mode the internal oscillator is
activated and OSCIN is unused. If the OSCOUT clock source is
enabled, the OSCOUT pin provides a 2, 4, 8 or 16-MHz clock signal
(according to OSC_SEL value); otherwise it is unused (see Figure
11).
6.8.2 External clock sourceTwo types of external clock source
can be selected: crystal/ceramic resonator or direct clock source.
Four programmable clock frequencies are available for each external
clock source: 8, 16, 24 and 32-MHz.
When an external crystal/resonator is selected, the OSCIN and
OSCOUT pins are used to drive the crystal/resonator (see Figure
11). The crystal/resonator and load capacitors (CL) must be placed
as close as possible to the pins. Refer to Table 8 for the choice
of the load capacitor value according to the external oscillator
frequency.
If a direct clock source is used, it must be connected to the
OSCIN pin and the OSCOUT pin supplies the inverted OSCIN signal
(see Figure 11).
The L6482 integrates a clock detection system that resets the
device in the case of a failure of the external clock source
(direct or crystal/resonator). The monitoring of the clock source
is disabled by default, it can be enabled setting high the WD_EN
bit in the GATECFG1
Table 8. CL values according to external oscillator
frequencyCrystal/resonator frequency (1)
1. First harmonic resonance frequency.
CL(2)
2. Lower ESR value allows greater load capacitors to be
driven.
8 MHz 25 pF (ESRmax = 80 )
16 MHz 18 pF (ESRmax = 50 )
24 MHz 15 pF (ESRmax = 40 )
32 MHz 10 pF (ESRmax = 40 )
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DocID023768 Rev 6 27/73
L6482 Functional description
73
register (Section 9.1.18 on page 52). When the external clock
source is selected, the device continues to work with the
integrated oscillator for textosc milliseconds and then the clock
management system switches to the OSCIN input.
Figure 11. OSCIN and OSCOUT pin configuration
Note: When OSCIN is UNUSED, it should be left floating.When
OSCOUT is UNUSED, it should be left floating.
6.9 Overcurrent detectionThe L6482 measures the load current of
each half-bridge sensing the VDS voltage of all the Power MOSFETs
(Figure 12). When any of the VDS voltages rise above the programmed
threshold, the OCD flag in the STATUS register is forced low until
the event expires and a GetStatus command is sent to the device
(Section 9.1.21 on page 58 and Section 9.2.20 on page 69). The
overcurrent event expires when all the Power MOSFET VDS voltages
fall below the programmed threshold.
The overcurrent threshold can be programmed by the OCD_TH
register in one of 32 available values ranging from 31.25 mV to 1 V
with steps of 31.25 mV (Table 21 on page 50 and Section 9.1.17 on
page 52).
UNUSED
OSCIN OSCOUT OSCIN OSCOUT
OSCIN OSCOUT
2/4/8/16 MHz
8/16/24/32 MHz
8/16/24/32 MHz
External oscillatorconfiguration
External clock sourceconfiguration
Internal oscillatorconfiguration
with clock generation
OSCIN OSCOUT
Internal oscillatorconfiguration
without clock source
UNUSED UNUSED
OSC_SEL = "1xx"
OSC_SEL = "0xx"
CL CL
EXT_CLK = "0" EXT_CLK = "1"
AM15042v1
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Functional description L6482
28/73 DocID023768 Rev 6
Figure 12. Overcurrent detection - principle scheme
The overcurrent detection comparators are disabled, in order to
avoid wrong voltage measurements, in the following cases: The
respective half-bridge is in high impedance state (both MOSFETs
forced off) The respective half-bridge is commutating The
respective half-bridge is commutated and the programmed blanking
time has not
yet elapsed The respective gate is turned off.
It is possible to set, if an overcurrent event causes the bridge
turn-off or not, through the OC_SD bit in the CONFIG register.
When the power bridges are turned off by an overcurrent event,
they cannot be turned on until the OCD flag is released by a
GetStatus command.
6.10 Undervoltage lockout (UVLO)The L6482 provides a
programmable gate driver supply voltage UVLO protection. When one
of the supply voltages of the gate driver (VCC for the low sides
and VBOOT - VS for the high sides) falls below the respective
turn-off threshold, an undervoltage event occurs. In this case, all
MOSFETs are immediately turned off and the UVLO flag in the STATUS
register is forced low.
The UVLO flag is forced low and the MOSFETs are kept off until
the gate driver supply voltages return to above the respective
turn-on threshold; in this case the undervoltage event expires and
the UVLO flag can be released through a GetStatus command.
The UVLO thresholds can be selected between two sets according
to the UVLOVAL bit value in the CONFIG register.
HVGxx
OUTxx
LVGxx
Vs
GNDx
+
-
+
-
BLANKING
OCD_HSxx
OCD_LSxx
CURRENTDACOC
THRESHOLD
GND
Vs
GND
LOGIC CORE
VoltageComparator
VoltageComparator
AM15043v1
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L6482 Functional description
73
6.11 VS undervoltage lockout (UVLO_ADC)The device provides an
undervoltage signal of the integrated ADC input voltage (the
UVLO_ADC flag in the STATUS register). When VADCIN falls below the
VADC,UVLO value, the UVLO_ADC flag is forced low and it is kept in
this state until the ADCIN voltage is greater than VADC,UVLO and a
GetStatus command is sent to the device.
The ADCIN undervoltage event does not turn off the MOSFETs of
the power bridges.
The motor supply voltage undervoltage detection can be performed
by means of this feature, connecting the ADCIN pin to VS through a
voltage divider.
6.12 Thermal warning and thermal shutdownAn integrated sensor
allows detection of the internal temperature and implementation of
a 3-level protection.
When the Tj(WRN)Set threshold is reached, a warning signal is
generated. This is the thermal warning condition and it expires
when the temperature falls below the Tj(WRN)Rel threshold.
When the Tj(OFF)Set threshold is reached, all the MOSFETs are
turned off and the gate driving circuitry is disabled (Miller
clamps are still operative). This condition expires when the
temperature falls below the Tj(OFF)Rel threshold.
When the Tj(SD)OFF threshold is reached, all the MOSFETs are
turned off using Miller clamps, the internal VCC voltage regulator
is disabled and the current capability of the internal VREG voltage
regulator is reduced (thermal shutdown). In this condition, logic
is still active (if supplied). The thermal shutdown condition only
expires when the temperature goes below Tj(SD)ON.
The thermal condition of the device is shown by TH_STATUS bits
in the STATUS register (Table 10).
Table 9. UVLO thresholds
ParameterUVLOVAL
0 1
Low-side gate driver supply turn-off threshold (VCCthOff) 6.3 V
10 V
Low-side gate driver supply turn-on threshold (VCCthOn) 6.9 V
10.4 V
High-side gate driver supply turn-off threshold (VBOOTthOff) 5.5
V 8.8 V
High-side gate driver supply turn-on threshold (VBOOTthOff) 6 V
9.2 V
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Functional description L6482
30/73 DocID023768 Rev 6
6.13 Reset and standbyThe device can be reset and put into
Standby mode through the STBY/RESET pin. When it is forced low, all
the MOSFETs are turned off (High Z state), the charge pump is
stopped, the SPI interface and control logic are disabled and the
internal VREG voltage regulator maximum output current is limited;
as a result, the L6482 device heavily reduces the power
consumption. At the same time the register values are reset to
their default and all the protection functions are disabled. The
STBY/RESET input must be forced low at least for tSTBY,min in order
to ensure the complete switch to Standby mode.
On exiting Standby mode, as well as for IC power-up, a delay
must be given before applying a new command to allow proper
oscillator and charge pump startup. Actual delay could vary
according to the values of the charge pump external components.
On exiting Standby mode all the MOSFETs are off and the HiZ flag
is high.
The registers can be reset to the default values without putting
the device into Standby mode through the ResetDevice command
(Section 9.2.15 on page 67).
6.14 External switch (SW pin)The SW input is internally pulled
up to VDD and detects if the pin is open or connected to ground
(see Figure 13).
The SW_F bit of the STATUS register indicates if the switch is
open (0) or closed (1) (Section 9.1.21 on page 58); the bit value
is refreshed at every system clock cycle (125 ns). The SW_EVN flag
of the STATUS register is raised when a switch turn-on event (SW
input falling edge) is detected (Section 9.1.21). A GetStatus
command releases the SW_EVN flag (Section 9.2.20 on page 69).
By default, a switch turn-on event causes a HardStop interrupt
(SW_MODE bit of the CONFIG register set to 0). Otherwise (SW_MODE
bit of the CONFIG register set to 1), switch input events do not
cause interrupts and the switch status information is at the users
disposal (Table 36 on page 56 and Section 9.1.20 on page 55).
Table 10. Thermal protection summarizing tableState Set
condition Release condition Description TH_STATUS
Normal Normal operation state 00
Warning Tj > Tj(WRN)Set Tj > Tj(WRN)RelTemperature
warning: operation is
not limited 01
Bridge shutdown Tj > Tj(OFF)Set Tj > Tj(OFF)RelHigh
temperature protection: the MOSFETs are turned off and the
gate drivers are disabled10
Device shutdown Tj > Tj(SD)Set Tj > Tj(SD)Rel
Overtemperature protection: the MOSFETs are turned off, the gate
drivers are disabled, the internal
VCC voltage regulator is disabled, the current capability of
the
internal VREG voltage regulator is limited, and the charge pump
is
disabled
11
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L6482 Functional description
73
The switch input can be used by GoUntil and ReleaseSW commands
as described in Section 9.2.10 on page 65 and Section 9.2.11 on
page 66.
If the SW input is not used, it should be connected to VDD.
6.15 Programmable gate driversThe L6482 integrates eight
programmable gate drivers that allow the fitting of a wide range of
applications.
The following parameters can be adjusted: gate sink/source
current (IGATE) controlled current time (tCC) turn-off overboost
time (tOB).
During turn-on, the gate driver charges the gate forcing an
IGATE current for all the controlled current time period. At the
end of the controlled current phase the gate of the external MOSFET
should be completely charged, otherwise the gate driving circuitry
continues to charge it using a holding current.
This current is equal to IGATE for the low-side gate drivers and
1 mA for the high-side ones.
During turn-off, the gate driver discharges the gate sinking an
IGATE current for all the controlled current time period. At the
beginning of turn-off an overboost phase can be added: in this case
the gate driver sinks an IOB current for the programmed tOB period
in order to rapidly reach the plateau region. At the end of the
controlled current time the gate of the external MOSFET should be
completely charged, otherwise the gate driving circuitry discharges
it using the integrated Miller clamp.
Figure 13. External switch connection
AM15044v1
ExternalSwitch
SW
VDD
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Functional description L6482
32/73 DocID023768 Rev 6
The gate current can be set to one of the following values: 4,
8, 16, 24, 32, 64 and 96 mA through the IGATE parameter in the
GATECFG1 register (see Section 9.1.18 on page 52).
Controlled current time can be programmed within range from 125
ns to 3.75 s with a resolution of 125 ns (TCC parameter in the
GATECFG1 register) (see Section 9.1.18).
Turn-off overboost time can be set to one of the following
values: 0, 62.5, 125, 250 ns (TBOOST parameter in the GATECFG1
register). The 62.5 ns value is only available when clock frequency
is 16 MHz or 32 MHz; when clock frequency is 8 MHz it is changed to
125 ns and when a 24-MHz clock is used it is changed to 83.3 ns.
(see Section 9.1.18).
6.16 Deadtime and blanking timeDuring the bridge commutation, a
deadtime is added in order to avoid cross conductions. The deadtime
can be programmed within a range from 125 ns to 4 s with a
resolution of 125 ns (TDT parameter in the GATECFG2 register) (see
Section 9.1.19 on page 54).
At the end of each commutation the overcurrent and stall
detection comparators are disabled (blanking) in order to avoid the
respective systems detecting body diode turn-off current peaks.
The duration of blanking time is programmable through the TBLANK
parameter in the GATECFG2 register at one of the following values:
125, 250, 375, 500, 625, 750, 875, 1000 ns (see Section
9.1.19).
6.17 Integrated analog-to-digital converterThe L6482 integrates
an NADC bit ramp-compare analog-to-digital converter with a
reference voltage equal to VREG. The analog-to-digital converter
input is available through the ADCIN pin and the conversion result
is available in the ADC_OUT register (Section 9.1.14 on page
50).
The ADC_OUT value can be used for torque regulation or can be at
the users disposal.
Figure 14. Gate driving currents
Gate Current
Gate turn-on
Igate Igate
IOBtCC
tOBtCCGate charged
Gate discharged
Gate turn-offAM15045v1
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L6482 Functional description
73
6.18 Supply management and internal voltage regulatorsThe L6482
integrates two linear voltage regulators: the first one can be used
to obtain gate driver supply starting from a higher voltage (e.g.
the motor supply one). Its output voltage can be set to 7.5 V or 15
V according to the VCCVAL bit value (CONFIG register). The second
linear voltage regulator can be used to obtain the 3.3 V logic
supply voltage.
The regulators are designed to supply the internal circuitry of
the IC and should not be used to supply external components.
The input and output voltages of both regulators are connected
to external pins and the regulators are totally independent: in
this way a very flexible supply management can be performed using
external components or external supply voltages (Figure 15).
Figure 15. Device supply pin management
If VCC is externally supplied, the VSREG and VCC pins must be
shorted (VSREG must be compliant with VCC range).
If VREG is externally supplied, the VCCREG and VREG pins must be
shorted and equal to 3.3 V.
VSREG must be always less than VBOOT in order to avoid related
ESD protection diode turn-on. The device can be protected from this
event by adding an external low drop diode between the VSREG and VS
pins, charge pump diodes should be low drop too.
VCCREG must be always less than VCC in order to avoid ESD
protection diode turn-on. The device can be protected from this
event by adding an external low drop diode between the VCCREG and
VSREG pins.
Both regulators provide a short-circuit protection limiting the
load current within the respective maximum ratings.
VBOOT
CP
VS
VSREG
VCC
VCCREG
VREG
7V5 - 15V
3V3
VBOOT
CP
VS
VSREG
VCC
VCCREG
VREG
7V5 - 15V
3V3
VBUS
Using external components (zener diodes, resistors, ...) it is
possible to reduce internal power dissipation constrains.
VBUS
VCC
3.3 V
All voltages are internally generated All voltages are
externally supplied
AM15046v1
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Functional description L6482
34/73 DocID023768 Rev 6
6.19 BUSY/SYNC pinThis pin is an open drain output which can be
used as busy flag or synchronization signal according to the
SYNC_EN bit value (STEP_MODE register) (see Section 9.1.17 on page
52).
6.20 FLAG pinBy default, an internal open drain transistor pulls
the FLAG pin to ground when at least one of the following
conditions occurs: Power-up or standby/reset exit Overcurrent
detection Thermal warning Thermal shutdown UVLO UVLO on ADC input
Switch turn-on event Command error.
It is possible to mask one or more alarm conditions by
programming the ALARM_EN register (see Section 9.1.17 and Table 26
on page 52). If the corresponding bit of the ALARM_EN register is
low, the alarm condition is masked and it does not cause a FLAG pin
transition; all other actions imposed by alarm conditions are
performed anyway. In case of daisy chain configuration, FLAG pins
of different ICs can be OR-wired to save host controller GPIOs.
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L6482 Phase current control
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7 Phase current control
The L6482 performs a new current control technique, named
predictive current control, allowing the device to obtain the
target average phase current. This method is described in detail in
Section 7.1. Furthermore, the L6482 automatically selects the
better decay mode in order to follow the current profile.
Current control algorithm parameters can be programmed by
T_FAST, TON_MIN, TOFF_MIN and CONFIG registers (see Section 9.1.11
on page 48, 9.1.12 on page 48, 9.1.13 on page 49 and 9.1.20 on page
55 for details).
Different current amplitude can be set for acceleration,
deceleration and constant speed phases and when the motor is
stopped through TVAL_ACC, TVAL_DEC, TVAL_RUN and TVAL_HOLD
registers (see Section 9.1.10 on page 47). The output current
amplitude can also be regulated by the ADCIN voltage value (see
Section 7.4 on page 39).
Each bridge is driven by an independent control system that
shares with the other bridge the control parameters only.
7.1 Predictive current controlUnlike classical peak current
control systems, that make the phase current decay when the target
value is reached, this new method keeps the power bridge ON for an
extra time after reaching the current threshold.
At each cycle the system measures the time required to reach the
target current (tSENSE). After that the power stage is kept in a
predictive ON state (tPRED) for a time equal to the mean value of
tSENSE in the last two control cycles (actual one and previous
one), as shown in Figure 16.
Figure 16. Predictive current control
At the end of the predictive ON state the power stage is set in
OFF state for a fixed time, as in a constant tOFF current control.
During the OFF state both slow and fast decay can be
predictive ONstate
OFFstate
tSENSE (n-1) tOFFtOFF
tPRED(n) =tSENSE (n-1) + tSENSE(n)
2
Iref
Iout
tPRED
(n-1) tSENSE (n)
tPRED(n)
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performed; the better decay combination is automatically
selected by the L6482 device, as described in Section 7.2.
As shown in Figure 16, the system is able to center the
triangular wave on the desired reference value, improving
dramatically the accuracy of the current control system: in fact
the average value of a triangular wave is exactly equal to the
middle point of each of its segment and at steady-state the
predictive current control tends to equalize the duration of the
tSENSE and the tPRED time.
Furthermore, the tOFF value is recalculated each time a new
current value is requested (microstep change) in order to keep the
PWM frequency as near as possible to the programmed one (TSW
parameter in the CONFIG register).
The device can be forced to work using classic peak current
control setting low the PRED_EN bit in the CONFIG register (default
condition). In this case, after the sense phase (tSENSE) the power
stage is set in OFF state, as shown in Figure 17.
Figure 17. Non-predictive current control
7.2 Auto-adjusted decay modeDuring the current control, the
device automatically selects the better decay mode in order to
follow the current profile reducing the current ripple.
At reset, the off-time is performed turning on both the low-side
MOS of the power stage and the current recirculates in the lower
half of the bridge (slow decay).
If, during a PWM cycle, the target current threshold is reached
in a time shorter than the TON_MIN value, a fast decay of
TOFF_FAST/8 (T_FAST register) is immediately performed turning on
the opposite MOS of both half-bridges and the current recirculates
back to the supply bus.
After this time, the bridge returns to ON state: if the time
needed to reach the target current value is still less than
TON_MIN, a new fast decay is performed with a period twice the
previous one. Otherwise, the normal control sequence is followed as
described in Section 7.1. The maximum fast decay duration is set by
the TOFF_FAST value.
sense ONstate
OFFstate
tOFFtOFF
Iref
Iout
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Figure 18. Adaptive decay - fast decay tuning
When two or more fast decays are performed with the present
target current, the control system adds a fast decay at the end of
every off-time keeping the OFF state duration constant (tOFF is
split into tOFF,SLOW and tOFF,FAST). When the current threshold is
increased by a microstep change (rising step), the system returns
to normal decay mode (slow decay only) and the tFAST value is
halved.
Stopping the motor or reaching the current sine wave zero
crossing causes the current control system to return to the reset
state.
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7.3 Auto-adjusted fast decay during the falling stepsWhen the
target current is decreased by a microstep change (falling step),
the device performs a fast decay in order to reach the new value as
fast as possible. However, exceeding the fast duration could cause
a strong ripple on the step change. The L6482 device automatically
adjusts these fast decays reducing the current ripple.
At reset the fast decay value (tFALL) is set to FALL_STEP/4
(T_FAST register). The tFALL value is doubled every time, within
the same falling step, an extra fast decay is necessary to obtain
an on-time greater than TON_MIN (see Section 9.1.12 on page 48).
The maximum tFALL value is equal to FALL_STEP.
At the next falling step, the system uses the last tFALL value
of the previous falling step.
Stopping the motor or reaching the current sine wave zero
crossing causes the current control system to return to the reset
state.
Figure 19. Adaptive decay - switch from normal to slow + fast
decay mode and vice versa
Time
Time
reference current
1st fast decay
Target current is increased (raising step)
2nd fast decay
system returns to slow decay mode and tFAST vaule is halved
switch to fast + slow decay mode
tFASTtOFF,FAST
tOFF,SLOW
tOFF tOFF
reference current
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Figure 20. Fast decay tuning during the falling steps
7.4 Torque regulation (output current amplitude regulation)The
phase currents are monitored through two shunt resistors (one for
each power bridge) connected to the respective sense pin (see
Figure 21). The integrated comparator compares the sense resistor
voltage with the internal reference generated using the peak value,
which is proportional to the output current amplitude, and the
microstepping code. The comparison result is provided to the logic
in order to implement the current control algorithm as described in
previous sections.
The peak reference voltage can be regulated in two ways: writing
TVAL_ACC, TVAL_DEC, TVAL_RUN and TVAL_HOLD registers or varying the
ADCIN voltage value.
The EN_TQREG bit (CONFIG register) sets the torque regulation
method. If this bit is high, ADC_OUT prevalue is used to regulate
output current amplitude (see Table 20 on page 50 and Section
9.1.14 on page 50). Otherwise the internal analog-to-digital
converter is at the users disposal and the output current amplitude
is managed by TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC registers
(see Table 14 on page 47 and Section 9.1.10 on page 47).
The voltage applied to the ADCIN pin is sampled at fS frequency
and converted in an NADC bit digital signal. The analog-to-digital
conversion result is available in the ADC_OUT register.
Falling step1st fast decay:t FALL = FALL_STEP/4
Falling step1st fast decay:tFALL = FALL_STEP/2
2nd fast decay:tFALL = FALL_STEP/2
Time
reference current
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Figure 21. Current sensing and reference voltage generation
Load
Rsense
To gate drivers
To current control logic
Peak reference DAC
TVAL_X or ADCIN
MicrostepMicrostepping DAC
To gate drivers
To gate drivers
To gate drivers
SENSEX
Vref
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8 Serial interface
The integrated 8-bit serial peripheral interface (SPI) is used
for a synchronous serial communication between the host
microprocessor (always master) and the L6482 (always slave).
The SPI uses chip select (CS), serial clock (CK), serial data
input (SDI) and serial data output (SDO) pins. When CS is high the
device is unselected and the SDO line is inactive (high
impedance).
The communication starts when CS is forced low. The CK line is
used for synchronization of data communication.
All commands and data bytes are shifted into the device through
the SDI input, most significant bit first. The SDI is sampled on
the rising edges of the CK.
All output data bytes are shifted out of the device through the
SDO output, most significant bit first. The SDO is latched on the
falling edges of the CK. When a return value from the device is not
available, an all zero byte is sent.
After each byte transmission the CS input must be raised and be
kept high for at least tdisCS in order to allow the device to
decode the received command and put the return value into the shift
register.
All timing requirements are shown in Figure 22 (see Section 3 on
page 11 for values).
Multiple devices can be connected in daisy chain configuration,
as shown in Figure 23.
Figure 22. SPI timings diagram
AM15053v1
CK
SDI
SDO
CS
MSB LSB
LSB
N-1 N-2
MSBHiZ
N-1 N-2
tsetCS
tenSDOtsetSDI tholSDI
tvSDOtholSDO
trCK tfCKthCK tlCK
tdisSDOtholCS
tdisCS
MSB
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Figure 23. Daisy chain configuration
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9 Programming manual
9.1 Register and flag descriptionTable 11 shows the user
registers available (a detailed description can be found in the
respective paragraphs from Section 9.1.1 on page 44 to Section
9.1.21 on page 58):
Table 11. Register mapAddress
[Hex]Register
name Register functionLen.[bit]
Reset[Hex]
Resetvalue
Remarks(1)
h01 ABS_POS Current position 22 000000 0 R, WS
h02 EL_POS Electrical position 9 000 0 R, WS
h03 MARK Mark position 22 000000 0 R, WR
h04 SPEED Current speed 20 00000 0 step/tick (0 step/s) R
h05 ACC Acceleration 12 08A 125.5e-12 step/tick2 (2008 step/s2)
R, WS
h06 DEC Deceleration 12 08A 125.5e-12 step/tick2 (2008 step/s2)
R, WS
h07 MAX_SPEED Maximum speed 10 041 248e-6 step/tick (991.8
step/s) R, WR
h08 MIN_SPEED Minimum speed 12 000 0 step/tick (0 step/s) R,
WS
h15 FS_SPD Full-step speed 11 027 150.7e-6 step/tick (602.7
step/s) R, WR
h09 TVAL_HOLD Holding reference voltage 7 29 328 mV R, WR
h0A TVAL_RUN Constant speed reference voltage 7 29 328 mV R,
WR
h0B TVAL_ACC Acceleration starting reference voltage 7 29 328 mV
R, WR
h0C TVAL_DEC Deceleration starting reference voltage 7 29 328 mV
R, WR
h0D RESERVED - 16 - - -
h0E T_FAST Fast decay settings 8 19 1 s / 5 s R, WH
h0F TON_MIN Minimum on-time 8 29 20.5 s R, WH
h10 TOFF_MIN Minimum off-time 8 29 20.5 s R, WH
h11 RESERVED - 8 - - -
h12 ADC_OUT ADC output 5 XX(2) 0 R
h13 OCD_TH OCD threshold 5 8 281.25 mV R, WR
h14 RESERVED - 8 - - -
h16 STEP_MODE Step mode 8 7 16 steps, SYNC mode disabled R,
WH
h17 ALARM_EN Alarms enabled 8 FF All alarms enabled R, WS
h18 GATECFG1 Gate driver configuration 11 0Igate = 4 mA, tCC =
125 ns, no
boost R, WH
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9.1.1 ABS_POSThe ABS_POS register contains the current motor
absolute position in agreement with the selected step mode; the
stored value unit is equal to the selected step mode (full, half,
quarter, etc.). The value is in 2's complement format and it ranges
from -221 to +221-1.
At power-on the register is initialized to 0 (HOME
position).
Any attempt to write the register when the motor is running
causes the command to be ignored and the CMD_ERROR flag to rise
(Section 9.1.21 on page 58).
9.1.2 EL_POSThe EL_POS register contains the current electrical
position of the motor. The two MSbits indicate the current step and
the other bits indicate the current microstep (expressed in
step/16) within the step.
When the EL_POS register is written by the user, the new
electrical position is instantly imposed. When the EL_POS register
is written, its value must be masked in order to match with the
step mode selected in the STEP_MODE register in order to avoid a
wrong microstep value generation (Section 9.1.17 on page 52);
otherwise the resulting microstep sequence is incorrect.
Any attempt to write the register when the motor is running
causes the command to be ignored and the CMD_ERROR flag to rise
(Section 9.1.21).
h19 GATECFG2 Gate driver configuration 8 0 tBLANK = 125 ns, tDT
= 125 ns R, WH
h1A CONFIG IC configuration 16 2C88
Internal 16 MHz oscillator (OSCOUT at 2 MHz),
SW event causes HardStop,motor supply voltage
compensation disabled, overcurrent shutdown,
VCC = 7.5 V, UVLO threshold low,tSW = 44 s
R, WH
h1B STATUS Status 16 XXXX(2)High impedance state,
motor stopped, reverse direction,all fault flags released
UVLO/Reset
flag set
R
1. R: readable, WH: writable, only when outputs are in high
impedance, WS: writable only when motor is stopped, WR: always
writable.
2. According to startup conditions.
Table 11. Register map (continued)Address
[Hex]Register
name Register functionLen.[bit]
Reset[Hex]
Resetvalue
Remarks(1)
Table 12. EL_POS registerBit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit
2 Bit 1 Bit 0
STEP MICROSTEP 0 0 0
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9.1.3 MARKThe MARK register contains an absolute position called
MARK, according to the selected step mode; the stored value unit is
equal to the selected step mode (full, half, quarter, etc.). It is
in 2's complement format and it ranges from -221 to +221-1.
9.1.4 SPEEDThe SPEED register contains the current motor speed,
expressed in step/tick (format unsigned fixed point 0.28).
In order to convert the SPEED value in step/s, the following
formula can be used:
Equation 1
where SPEED is the integer number stored in the register and
tick is 250 ns.
The available range is from 0 to 15625 step/s with a resolution
of 0.015 step/s.
Note: The range effectively available to the user is limited by
the MAX_SPEED parameter.
Any attempt to write the register causes the command to be
ignored and the CMD_ERROR flag to rise (Section 9.1.21 on page
58).
9.1.5 ACCThe ACC register contains the speed profile
acceleration expressed in step/tick2 (format unsigned fixed point
0.40).
In order to convert the ACC value in step/s2, the following
formula can be used:
Equation 2
where ACC is the integer number stored in the register and tick
is 250 ns.
The available range is from 14.55 to 59590 step/s2 with a
resolution of 14.55 step/s2.
The 0xFFF value of the register is reserved and it should never
be used.
Any attempt to write to the register when the motor is running
causes the command to be ignored and the CMD_ERROR flag to rise
(Section 9.1.21).
9.1.6 DECThe DEC register contains the speed profile
deceleration expressed in step/tick2 (format unsigned fixed point
0.40).
step/s SPEED 228
tick-------------------------------------=
step/s2 ACC 240
tick2-----------------------------=
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In order to convert the DEC value in step/s2, the following
formula can be used:
Equation 3
where DEC is the integer number stored in the register and tick
is 250 ns.
The available range is from 14.55 to 59590 step/s2 with a
resolution of 14.55 step/s2.
Any attempt to write the register when the motor is running
causes the command to be ignored and the CMD_ERROR flag to rise
(Section 9.1.21 on page 58).
9.1.7 MAX_SPEEDThe MAX_SPEED register contains the speed profile
maximum speed expressed in step/tick (format unsigned fixed point
0.18).
In order to convert it in step/s, the following formula can be
used:
Equation 4
where MAX_SPEED is the integer number stored in the register and
tick is 250 ns.
The available range is from 15.25 to 15610 step/s with a
resolution of 15.25 step/s.
9.1.8 M