MICROPROGRAMMED I/O INTERFACE - COREABSTRACT Thisthesispresentsabasichardwaremodelsuitablefor mostsequentialmicroprogrammeddevices.Asoftwaresystem isdescribedwhichallowstheuseofanassembly-level

A MICROPROGRAMMED I/O INTERFACE

Raimundo Nona to Daniel Duarte

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Monterey, California

A MICROPROGRAMMED I/O INTERFACE

by

Raimundo Nonato Daniel Duarte

Thesis Advisor: Raymond H. Brubaker

March 1974

AppAovzd fan. public neJLm&z; da>t/uhution unluniXtd.

I Z^'o'jO

A MICROPROGRAMMED I/O INTERFACE

by

RAIMUNDO NONATO DANIEL DUJRTELIEUTENANT - BRAZILIAN NAVY

Submitted in partial fulfillment of therequirements for the degree of

MASTER OF SCIENCE IN COMPUTER SCIENCE

from the

NAVAL POSTGRADUATE SCHOOL

March 1974

ABSTRACT

This thesis presents a basic hardware model suitable for

most sequential microprogrammed devices. A software system

is described which allows the use of an assembly-level

programming language instead of the binary representation of

microcodes. The implementation of a microprogrammed

input/output inter face is presented as an example of use of

both the hardware and software.

TABLE OP CONTENTS

I. INTRODUCTION 6

II. IEM SYSTEM/360 I/O INTERFACE 7

A. OVERVIEW 7

E. INTERFACE FUNCTIONS 8

III. IHE APPROACH 11

IV. MICROPROGRAMMING 12

A. INTRODUCTION 12

E. EASIC HARDWARE 13

C. OPERATION 14

1. Conditional Jump 16

2. Unconditional Jump 17

3. Execution of a Predefined Process. ... 17

V. AIMIC-AN ASSEMBLER-LEVEL LANGUAGE

FOR MICROPROGRAMMING 19

A. MOTIVATION 19

B. THE SOFTWARE PACKAGE 20

1. Introduction 20

2. Functional Description and use 21

a. The Data Generator... 21

(1) Purpose 21

(2) Input 21

(3) Output 22

b. The Table Generator 22

(1) Purpose 22

(2) Input 22

(3) Output 22

c. The Assembler 22

(1) Purpose 22

(2) Input 22

(3) Output 23

IV. IMPLEMENTATION OF A MICROEBOGP»AHSlE

INTERFACE 24

A. OVERVIEW 24

E. EXAMPLE 26

V. CONCLUSION 30

AEPENDIX A - Interface Flowchart 31

APPENDIX B - Flowchart Labeling Algorithm.... 40

AFPENDIX C - How to write an ALMIC program 42

APPENDIX D - Figures 43

COMPUTER PROGRAM 53

BIBLIOGRAPHY 81

INITIAL DISTRIBUTION LIST 82

FORM DD 1473 83

LIST OF DRAWINGS

1 - Bead-Only Memory representation 13

2 - Easic hardware 15

3 - Phase relation between clocks 16

4 - Control part of the interface 43

5 - Execution part of the interface 44

6 - Parallel-connection of ROM 45

7 - Farallel-connection of decoders 46

8 - Latch circuit for the "raise/drop line"

function 47

9 - Address-checking function 48

10 - Input to the Data Generator 49

11 - Output from the Table Generator 50

12 - Microprogram for the interface 52

I. INTRODUCTION

This thesis is part of a larger effort to implement a

communications network for present and future computer

systems at the Naval Postgraduate School. Microcomputers

will be used in this network to replace as many interface

hardware functions as possible with software, thus providing

a degree of flexibility not attainable with hardware-only

configurations. The need arose for a device which allows

exchange of data and control signals between any of the

computer systems and its associated microcomputer.

The aim of this thesis is to develop basic hardware that

can be used in any of these interfaces, as well as in most

sequential devices.

The IEi-1 System/360 interface was chosen as the guide for

design for the following reasons:

a) it has a standard I/O interface between the data

channel and the control units which activate I/O devices;

b) it is possibly one of the more complex interfaces,

thus providing a worst-case design.

During the course of work the need for a

microprogramming language was recognized; the software

designed to support it is described in chapter V.

II. IBM SYSTEM/36 I/O INTERFACE

A. OVERVIEW

Whenever the IBM System/360 channel wants to

receive/send information from/to a specific I/O device it

sends a command (Read/Write) to the device via its control

unit and logically disconnects as soon as the control unit

acknowledges the command. When the I/O device is ready to

send/receive the desired information it signals to the

channel which executes a polling sequence to find out which

unit is asking for service. If the control unit is tusy and

cannot accept the command, a "Control Unit Busy Sequence 11

takes place, whereby the channel is notified and defers its

request for a later point in time.

The control unit can also initiate a data exchange by

signalling to the channel and waiting until it is ready to

service the request.

Due to the number of signalling lines used, the detailed

operational description is quite involved. It is described

in Ref. 1. Reference 2 contains a somewhat more detailed

and readable explanation of some of the different sequences.

INTERFACE FUNCTIONS

The rules which constitute the I/O Interface are

physically i nplemented by 34 wires, or lines, whose state

can be either up (cne, high) or down (zero, low).

The lines are :

Bus Out - a set of nine lines used to transmit

information (data, I/O device address, commands) frcm the

channel to the control units. Eight lines are used to

convey the information itself and one line is a parity hit.

The type of information transmitted over Bus Out is

indicated by the state of other lines.

Bus In - a set of nine lines used to transmit

information (data, I/O device identification, status

infcrmation) from the control unit to the channel. Eight

lines are used to convey the information itself and cne line

is a parity bit. The type of information transmitted over

Bus In is indicated by the state of other lines.

Address In (abbreviated Adrln) - is a line from all

attached control units to the channel. Its rise indicates

that the address of the currently selected I/O device is

available on Busln .

Status In (abbreviated Stain) - is a line frcm all

attached control units to the channel. Its rise indicates

that the control unit has placed status information on

Busln.

Service in (abbreviated Serin) - is a line from all

attached control units to the channel. Its rise indicates to

the channel that the selected I/O device wants to transmit

or receive a byte of information.

Command Out (abbreviated ComOut) - is a line from the

channel to all attached control units. Its rise may

indicate

:

1) after the rise of Adrln - the contents of BusCut is a

command

.

2) after the rise of Serin - the channel is ending the

current operation.

3) after the rise of Stain - the control unit should

disconnect from the interface after the fall of SelOut.

Service Out (abbreviated SerOut) - is a line from the

channel to all attached control units. Its rise indicates to

the selected I/O device that the channel has accepted the

information on Busln or has provided on BusOut the data

requested by Serin.

Suppress Out (abbreviated SupOut) - is a line from the

channel to all attached control units and is used both alone

and in conjunction with other outbound lines to provide the

following special functions:

1) data suppression,

2) status suppression,

3) command chaining and

4) selective reset.

These functions are described in Ref. 1.

Operational Out (abbreviated OplOut) is a line from the

channel to all attached control units and is used for

interlocking purposes. Except for SupOut all lines from the

channel are significant only when OplOut is up. Whenever

OplOut is down, all inbound lines from the control units

must drop and any operation currently in process must be

reset.

Operational In (abbreviated Oplln) - is a line from all

attached control units to the channel and is used to signal

to the channel that an I/o device has been selected.

Select Out (abbreviated SelOut) - SelOut and Selln form

a closed loop from the channel through all attached control

units and back to the channel.

Select In (abbreviated Selln) - is the name givan to

SelOut when it reaches the channel after passing through all

control units.

Hold Out (abbreviated Holdout) - is a line from the

channel to all attached control units and is used in

conjunction with SelOut.

Address Out (abbreviated AdrOut) - is a line from the

channel to all attached control units. It provides two

functions

:

1. I/O Device Selection - AdrOut up is an order to all

attached control units to decode the I/O device address on

BusOut.

2. Disconnect Operation - whenever Holdout is down and

AdrOut rises, or AdrOut is up and Hold Out falls, the

presently connected control unit Bust drop Oplln, thus

disconnecting from the interface.

Reguest In (abbreviated Reqln) - is a line from all

attached control units to the channel. Its rise indicates

that a control unit is requesting a selection sequence.

Metering Cut is a

attached control units,

meter is recording time.

line from the channel to all

Its rise indicates that the CPU

Clock Out - is a line from the channel to all attached

control units. Control units should not be allowed to

switch from "On-line" to "Off-line" condition when ClcckOut

is up.

The functions implied by the list above were to be

implemented, resulting in the design of a device capable of

acting as a control unit.

10

III. THE APPROACH

An interface to the /360 channel certainly had to

include seme logical circuitry. Preliminary studies showed

that the state of the lines alone is not always sufficient

to decide the action to be taken by the device. Therefore

the nature of the functions to be performed was not strictly

combinational, and the device would have to keep track of

event sequences.

Another difficulty was that the number of variables

involved, even reducing the problem to the bare essentials,

was arcund seven; this implied the use of large reduction

maps, difficult to visualize and error-inducing. The needed

addition cf flip-flop counters to make up for the sequential

nature or some of the functions would aggravate the problem.

Furthermore, a troublesome and time- consuming

implementation phase was anticipated for the design. If

patchboards were to be used in the experimental

implementation, poor contacts and misrouted wires were

likely tc compound with design errors; on the other hand,

hardwired prototyping would be expensive if several

corrections cr changes were to be made.

These factors led to the use of microprogramming as

opposed tc hardwiring (or random logic).

11

IV. MICROPROGRAMMING

A. INIBCEUCTION

M icroprocrammming, as used in this report, is a design

technique substitute to hardwiring. The fundamental idea

behind microprogramming is that, given a truth table with n

inputs and one output, we can think of it as being a table

nof contents of a 2 word, one bit per word, storage device.

The state of the inputs determines one unique address in the

storage device and the content of this location is the

desired value of the function.

It is easily seen that if, instead of one-bit words, the

store had, say, eight-bit words, eight separate switching

(binary) functions could be implemented. In the application

described here, several binary function values are grouped

into a field to specify one of several values. For example,

a field of three bits can take eight different values. The

same table can simultaneously implement several such

functions

.

The need was for a device capable of implementing the

following basic flowchart operations:

1) Conditional branch - where the decision variable was

tc be one of the I/O interface lines.

2) Unconditional branch.

12

3) Execute predefined process - where the "predefined

process" would be of the form "RAISE LINE..." or "DROP

LINE. .. " only.

B. EA5IC HAFEWARE

Before introducing the complete model, its basic

components will be presented and briefly explained.

1) Read Only Memory (ROM) (Figure 1) - depicted in the

diagrams as a rectangle divided in three rows; the bottom

row represents the input section and contains a description

of the physical device as well as the input (address) bits.

The middle row is subdivided in three fields :

leftffcst field is the 'next basic address field' cr ADR

center field is the 'select field' or SEI

rightmost field is the 'opcode field* or OPCODE

The upper row is subdivided in as many sguares as the

number of bits in each word of the ROM. The number inside

the sguares represent the significance of the nit (i.e. the

binary order) .

7 6 5 4 3 2 1

ADR SEL OPCODE

2 1

Figure 1. An eight word, eight bits per word.

Read Only Memory.

2) Clock - depicted as the Greek. letter phi ( ) .

Subscripts are used to differentiate among phases cf the

clock, i.e. 01, <p2 1 ... <pn are all pulse generators with

the same f reguency ; however, the leading edge of the pulse

which prcduces changes in the circuits under their control

occurs at distinct time instants.

13

3) D flip-flops (Figure 2) - depicted as a square with

the letter * D* inside and subscripts whenever necessary to

differentiate among the various flip-flops. Whenever the

clock rises the output of the flip-flops becomes equal to

the input value immediately prior to the clock pulse.

4) Data Selector / Multiplexer (MX) (Figure 2) - logic

ncircuit with 2 input lines, n select lines and one output

line. It is the logical eguivalent of a single-pole,

n2 -position switch whose position is specified by a n-bit

input address. The output line presents the value of the

single input line selected by the select lines. In addition

to the input and select lines, the multiplexer has a strobe

or enable line. The output is valid only when the strobe

line is zero (low) .

5) Decoder / Demultiplexer (DMX) (Figure 2) - icgic

ncircuit with n inputs and 2 outputs. For each binary value

at the input, one different output line is dropped. In

addition, the demultiplexer has a strobe or enable line. The

selected output changes state only when the strobe line is

low (zero) .

C. OPERAIION

The operation of the model is better explained ty an

example. The following assumptions are made:

1) The hardware configuration is as depicted in

Figure 2.

2) The circuit is in steady-state operation.

14

U I » I I I »

BIHJtail M I I ! I I ! II— 3

<N

CM

u

o

cti

CM

0)

•H

15

3) The BOH has already been programmed and the

contents cf seme addresses are tabulated below:

ADDRESS

3

4

5

1

ADR FIELD

10

00

01

01

00

TABLE I

SEL FIELD

010

001

001

000

000

CECODE HELD000

011

001

000

000

5004) The two clocks ( 01 and <p2) run at, say,

their phase relationship being as shown in figure 3 .

KH:

01

02

Figure 3. Phase relation between 01 and <p2.

1 • Conditional Jump

Refer to Table I and assume that the address now

being accessed is number three. The inputs to D1 and D2 are

1 and respectively (see "ADR FIELD") ; line two (010) has

been selected (see- "SEL FIELD") and the operation coded as

000 is being executed by some hardware external to the model

(see "OPCODE FIELD"). Note that the outputs of D1, D2 and

D3 must currently be 011 respectively, since we assumed ROM

word three was being accessed.

16

Eventually the clock ( 01) will rise and the output

of D1D2 will be 10, which implies that the address to be

accessed is either 4 (100) or 5 (101) depending upcn the

output cf D3. The output of D3 is the value of its input

immediately prior to the 01 pulse, and this is the value of

input (to MX) line two (010) ; thus it cannot be said which

ROM word will be accessed next without specifying the

earlier state of this signal. The effect of this example can

be described by the ALGOL-like statement:

"IF INPUT (2) GO TO 5 ELSE GO TO 4"

where input (2) is treated as a logical variable.

Soon after 01 , the outputs of the ROM start to

change. Since it is not guaranteed that only one change in

state will take place, 02 is kept high at this point, thus

preventing the output of DMX from being affected by this

spurious input.

One microsecond later, 02 goes low; consequently,

the input of D3 is now defined and the right command is

being enatled by one of the output lines of DMX.

2. Unconditional Jump

In the example described above, if it was known that

input line two (010) had the value zero (it could be

physically connected to ground), then the next address would

have been forced to four. On the other hand, if it had the

value 1 (connected to the power supply) , an unconditional

jump to location five would have resulted.

Therefore, to implement the unconditional jump, it

suffices to save two input lines to MX and set them tc 1 and

respectively.

3- J*US]?11211 of 1 Pl^defj.ned Pl2£^ss

It can be seen from the two previous examples that

the output of DMX depends upon the particular address being

accessed. By proper selection of the contents of the "next

address" field, it is therefore possible to make the 30M

17

cause the execution cf sequences of processes, as will be

described.

Assuming that this hardware was to be used as

control unit for an Arithmetic and Logic Unit of a computer,

certain tasic functions would be needed, such as adder,

multiplier, divider, comparator, etc. These basic functions

are collectively called "raicrospec functions" by Husson

(Eef. 2). The microspec function has one enable lire that

activates it.

The hardware in the example allowed coding of eight

possible operations. Therefore, if the output lines of DMX

were connected to suitable microspec functions, up .to eight

different predefined processes could be selected and

executed

.

18

V.ALMIC - AN ASSEMBLY - LEVEL LANGUAGE FOE MICROPROGRAMMING

A. MOTIVATION

Given the basic hardware model described in chapter IV,

the next task was the actual programming of the ROM 's to

generate the control sequences required Dy the /360 channel.

This n>eant:

1) find the bit patterns to te stored in each field of

each address;

2) put them on paper;

3) actually write them into the ROM.

The last operation was relatively easy, because all that

is required is equipment already available. However, the

first two proved not only tedious but also highly

error-prone. In the case under study it was estimated that a

256 word, 16 bits per word, store would be needed, which

implied a sizable number of bit strings to be input via a

teletypewriter. In case an error was detected, or a change

sought, most of the work would have to be dene again.

It was decided that a higher level language would be

desirable to allow straightforward description of control

sequences and to automate their translation into HOM bit

patterns. Ihis required the design of a software package to

support it and, due to time constraints, it was agreed that

an assembler-level language would be more reasonable and

still helpful.

19

The general format of a statement in the assembler

language is given by the example:

34 : 26 , ADROUT,S2AIN.

where the number before the colon (34) is the address where

the statement is to be stored; the first field (28) is the

next address (not the "next basic address" mentioned in

chapter IV; tne assembler will take care of this detail)

;

ADROUT, in the example, stands for "select rhe decision line

ADRCUT" and the third field is the operation to be

performed, "raise line Stain (Status In)" in this case.

It is to be understood by this example that the next

instruction will be in the address given by:

{28 + (current value of ADROUT, 1 or 0)

}

therefore 28 or 29.

B. THE SOFTWARE PACKAGE

1 • Il2!.££j3.u£ t ion

The model presented in chapter IV was intended to be

used in any sequential microprogrammed circuit. Therefore,

before attempting to write programs for any specific

hardware configuration, it is necessary to furnish the

assembler with the following information:

1) number of addresses in the ROM;

2) number of bits in each field of a ROM word;

3) list of mnemonics used to represent the input

lines to KX;

4) list of mnemonics used to represent the opcodes

(or microspec functions ) .

20

2 • Functional Description and Use of the S eft ware

Package

The package is composed of three main programs:

a) the DATA GENERATOR

h) the TABLE GENERATOR

C) the ASSEMBLE?.

In addition there are 13 subroutines: INIT, GNC

,

CONV, GET, PUT, ICON, PAD, ERROR, tfRITEL, FORM, CCNCUT,

SCAN, PUNCH.

a. The Data Generator

(1) Pu££°.§.§- Generate input data fcr the

Table Generator.

(2) Inj?uj£- Input is in free-format 80-column

records, with different elements separated by commas, except

where otherwise noted. Blanks are always irrelevant,

therefore "256, 34." is the same as "256,3 4.". The

following data is required:

(a) one card with the number one in column

one ;

(b) the number of fields in a RCH word,

followed by a comma. This is necessary since it is allowed

to separate the opcode field into as many sub-fields as

wanted, thus providing the capacity to execute several

operations simultaneously;

(c) the number of bits in each field of the

ROM word;

(d) list of mnemonics used to represent the

input lines to MX. The last mnemonic is to be followed by a

period, net a comma;

(e) list of mnemonics used to represent the

microspec functions. The last mnemonic (in each sub-field,

if more than one is used) is to be followed by a period, not

a comma

.

21

(3) 0^t_gut. The output is in form of punched

cards ready to be fed to the Table Generator.

b. The Table Generator

C) Purpose. Sets up tables to be used hy the

Assembler .

(2) ln£]±t. Input is in free-format 80-coluran

records, with different elements separated by commas, except

where otherwise noted. Blanks are always irrelevant. The

following data is required :

(a) one card with the number two in column

one ;

(b) number of fields in each ECM word,

followed by a comma;

(c) number of bits in each field, followed

by a comma;

(d) list of mnemonics used to represent the

input lines to MX. Each mnemonic is to be followed (after a

comna) by its corresponding binary code;

(e) list of mnemonics used to represent the

microspec functions, each mnemonic being followed (after a

comma) by its corresponding binary code.

(3) Output. Fortran DATA statements ready to

be inserted into the "Block Data" subprogram for use with

the Assembler.

c. The Assembler

O) P-UE-Eose. Converts statements of the form:

<label> : <address>,<select line>,<opcode>.

for example: 25 : 36 , SELOUT, DPSELOUT.

into bit patterns suitable to program a BCM.

(2) IHEMt. The first card must have the

number three in column one. For the program itself, input is

in free-format 80-column records. Comments can be

interspersed with (and even within) statements, provided

22

they are enclosed between the signs "<" and ">" . The card

after the last in the program being assembled must have a

11*11 j n cclumn one.

(3) Output. Paper tape in a format suitable

to prograir a BOM.

23

VI. IJELEMENTAT ION OF A MI CJOPRO GRAM MED INTE RFACE

This section is composed of two parts; part A cortains a

description of the procedure used to implement the

interface. In part B an example is given to illustrate and

clarify the procedure described in part A.

A. OVERVIEW

The following steps should be adopted in designing a

microprogrammed device using the hardware and software

presented in chapters IV and V :

Step 1. Make a flowchart representation of the fcehavior

of the device. This flowchart is to use the "fcinary

decision" and the "predefined process" boxes only.

Step 2. Count the number of distinct decision variables.

Call it b.

Step 3. Count the number of distinct predefined

processes. Call it n.

Step 4. Count the number of decision boxes. Call it p.

Step 5. Eetermine the number of fields (not bits) to be

used in microprogramming the ROM. The least number is three,

and will te greater if and only if more than one microspec

function has to be activated at the same time.

Step 6. Determine the number of bits in each field.

For the "next basic address" field it will te:

[log2

2p] - 1

24

where [x] means the least integer not less than x.

For the "select field" the number of bits will be:

a = [ log m ]

2

For the "cpccde field" it will be [log n].2

Step 7. Choose the component to play the role of MX. It

will be a Data Selector/Multiplexer with at least "a" input

bits.

Step 8. Choose the component to play the role of DKX. It

will be a Decoder/Demultiplexer of capacity at least n to

2n .

Step 9. Design the hardware necessary tc implement the

microspec functions according to the specific needs of the

project.

Step 10. Run the Data Generator using as inputs:

a) number of fields in each ROM word, followed by a

comma;

b) number of bits in each field cf the ROM, each

followed ty a comma;

c) list of mnemonics used to represent the input

lines tc MX. Each mnemonic is to be followed by a comma,

except the last one, which shall be followed by a period;

d) list of mnemonics used to represent the microspec

functions. Each mnemonic is to be followed by a comma,

except the last one, which shall be followed by a period.

Step 11. Run the Table Generator using the output of the

Data Generator as its input.

Step 12. Insert the output of the Table Generator in

proper place within the "Block Data" subprogram for use with

the Assembler.

Step 13. Using the algorithm presented in Appendix B,

label the boxes of the flowchart.

Step 14. Using the algorithm presented in Appendix C,

write the microprogram and punch it.

25

Step 15. Run the Assembler using the microprogram as

input. The program is currently written in FORTRAN for a

XDS-9300 computer. To run the Assembler in ether computers

miner changes are necessary. As examples, the compiler may

not accept more than 20 continuation cards which reguires

breaking up the "DATA MEMORY" statement inside the "Block

Data" subprogram into smaller statements; the logical number

for the output unit (paper tape punch) was assumed to be

seven.

The output of the Assembler is a paper tape ready to be

fed to the MCS-8 PROM Programming System.

E. EXAMFIE

The I/O Interface for the System/360 will be used to

demonstrate the method just described. Figures 4 and 5

contain a blocK diagram of the complete circuit.

Frcm Figure 4 it can be seen that inputs to MX number

and 1 were reserved to implement unconditional jumps.

Inputs two thru six are outbound tags from the channel.

Input seven will be provided by the associated

microcomputer, naving the value of one whenever the

microcomputer , or the device attached to it, is busy. Inputs

nine and ten are provided by the hardware shown in Figure 5.

Input ten is tapped from the Status In line.

Figure 5 displays the executive part of the interface

hardware. Output line number zero for the DMX was reserved

to represent "no operation" to be performed. Lines one and

two respectively raise and drop the

"channel- initiated-seguence" line which is fed to MX in

Figure 4. The sguares with the letters R and D are latches

whose outputs switch to 1 when R (raise) is zero and tc zero

when D (drop) is zero.

Output lines three and four implement the SelOut

control. Lines five thru 13 control the multiplexing of

26

CHSEQ, OCRADR,

data, status and address into Busln. At the same time,

lines six and seven, nine and ten and 12 and 13 implement

Serin, Adrln and Stain respectively.

Whenever the microcomputer wants tc send/receive

information to/from the channel, it will raise Eeqln, which

will be dropped by output line 16.

In the sample design which follows the "reset" and the

"disconnect" sequences (described respectively under

"Operational Out" and "Address Out" in chapter II) were not

considered. Ihe action to be taken in case of wrong parity

on the address byte was also omitted.

Step 1. Ihe flowchart will be as shown in Appendix A.

Step 2. The decision variables are: 0, 1, AEROUT,

SELOUT, SUPCUT, COMOUT, SEROUT, CUBUSS,

STAIN; therefore m = 11.

Step 3. The predefined processes are

DCHSEQ, PSEIOUT, DPSELOUT, DATABOSIN,

STAEUSIN, DSTAIN, STAIN, ADRBUSIN, DADFIN,

DCPIIN, EBEQIN, TSTADR. Therefore n = 18.

Step 4. There are 20 decision boxes, thus p = 20.

Step 5. Three fields only will be used, as there is no

need for simultaneous execution of microspec functions.

Step 6. Number of bits in "next basic address field":

[log 2 x 20] - 1=52

number of bits in "select field": a = [log 11] = 4

number of bits in "opcode field": [log 18] = 5

The size of ROM address space will be the number of

5possible "next basic addresses", 2 = 32, doubled (for the

two different states of the address bit from D6 , Figure 4)

;

a total of 64 words in this case. Each word shall have at

least 14 tits. Intel's 1702A has 256 words, eight bits per

word, and is reprogrammable. Connecting two of them as in

figure 6 a 256 word, 16 bits per word, store is obtained.

NO OP,

DSERIN

,

ADRIN,

CHSEQ,

SERIN,

CPLIN,

27

Step 7. MX will have four inputs; Signetics N7H150 is

suitable

.

Step 8. DMX has 32 outputs; since no decoder is

available with so many outputs, two Signetics N74154's will

be used, connected as in Figure 7. Bit ex ROM will act as

"chip selector".

Step 9. There are eight microspec functions of the form:

"Baise/Drcp line ", namely, CHSEO/DCHSEQ,

PSELOUT/DPSELOUT, STAIN/DST AIM, SERIN/DSERIN , ADR IN/DADHI.H ,

OPLIN/DOPLIN, DREQIN, TSTADR.

The logic circuit to perform this operation will have

two inputs (Raise and Drop, or R and D) and one output. The

inputs should be level-triggered by the low signal, as this

is the output available from DMX. Therefore, the

corresponding truth table is as depicted in Figure 3a;

Figure 8b shows one possible implementation.

For the three functions which deal with Busln

(DATABUSIN, STABUSIN, ADRBUSIN) a set of eight AND-OB gates

working as a multiplexer will suffice. The data and status

bytes will be provided by the microcomputer, while the

address byte will come directly from BusOut.

The address of an I/O device can be any eight-bit

pattern. The address checking function (TSTADR) will have

eight inputs, to be fed by BusOut. It is necessary to have

some switching capability in order to select, at

installation time, the range for valid addresses. The output

is one line (OURADR) , which will have the value one whenever

the input address is within range. Figure 9 shews the

logical circuit to perform the function. The switch S will

be in position one for those bits which must be one fcr the

address to be accepted, in position two for those bits which

must be zero, and in position three for those bits which are

irrelevant.

Step 10. The input to the Data Generator is displayed in

Figure 10a, whereas part b of the same figure shows the

output obtained.

28

Step 11. The output of the Table Generator is displayed

in Figure 1 1

.

Step 12. The output of the Table Generator is inserted

in the "Block Data" subprogram.

Step 13. The flowchart of Appendix A was numbered using

the algorithm described in the previous section.

Step 14. The resulting microprogram is listed in Figure

12.

Step 15. Using the input shown in Figure 12 to run the

Assembler, the output will be a paper tape ready to

microprogram the BOM.

29

VII. CONCLUSION

This thesis dealt with the design cf a

microprogrammed I/O interface to be used in a communications

network at the Naval Postgraduate School.

A lasic hardware approach suitable to most

microprogrammed sequential applications was described along

with an assembler- level language for microprogramming.

The fact that it was possible to devise an algorithm to

write the AIMIC microprogram suggests that it might be

feasible tc improve the software package to the point where

the flowchart itself, and not the program, would be used as

input to the system; the flowchart, as used here, can be

represented by some sort of binary tree.

In order to implement and test the interface it is

necessary tc incorporate in this design the hardware and

also the microinstructions needed to handle the' exchange of

infcrmaticn between the device and the microcomputer.

30

APPENDIX A

This appendix contains the flowchart used to implement

the I/O interface between the System/360 channel and the

device described in this thesis. It was obtained from

Appendix C of Ref. 1 by eliminating all boxes "under

responsibility of the channel" and by adding ethers

necessary tc specify operations to be performed by the

device.

As to the mnemonics used, the following general rules

apply :

a) the name of a line inside a decision box means: "Is

the line up?";

b) the name of a line inside a process box means: "Raise

line"

;

c) the name of a line inside a process box when preceded

by the letter "D" means "Drop line".

The lines are :

ADRBUSIN-Address byte to Busln

ABRIN-Address In

ADROUT - Address Out

CHSEQ- Channel -Initiated- Sequence

COMOUI - Command Out

DATAEUSIN-Data byte to Bus In

OPLIN-Operational In

PSELCUT - Propagate Select Out

REQIN-Request In

SEIOUT -Select Out

SERIN-Service In

SEROUT - Service Out

STABUSIH-Status byte to Busln

STAIN-Status In

SUPOUT - Suppress Out

31

A channel-initiatedC32.ec+icn sentiencehas been initiated

The address onBusOut is withinrange of., this C U

32

NO

V

33

STA IN

^7

4*

YES

4-9

A 'CU Busy Sequence'takes place

34

VOPLIN

7 / 44

. The CU responds to thechannel "by sending the

ADRBUSIN

8/46

address to Busln

y10

YES QADR(

NO

ADR IN

10

-lITT ^<wNO rCCM12

YES 13 The CU processes

rhthe command onBus Out

35

Q

This selectionsequence wasaborted

36

YES

21 Transferinitialstatusbvte

$

38

o

Status

D STA IN

30

NO

24

YES

27

Note 1.

Data, if inbound,

was accepted.

Data, if outbound,

was on Bus Out.

The control unit

processes any-

outbound data.

26 STOP

NO

22

D OPLIN

28 / 3^

*

39

APPENDIX B

BEGININTEGER I ;

RECORD PGINTERC INTEGER LAST; REFERENC E( PCTNTER JNEXT )

;

REFERENCE(POINTER) TOP;

COMMENT : SET YOURSELF AT 'START' BOX ;

I := ; TCP := NULL ;

TAKE NEXT BOXIF RECTANGULARTHEN BEGIN

L^BEL ITI := I +GO TO AEND

ELSE BEGINIF ALREADYTHEN BEGIN

WITHl ;

VISITED

YOURSELF ATTO LAST(TOP)

ELSE

END;

IF TOP = NULLTHEN GO TC STOPELSE BEGIN

COMMENT : SETCORRESPONDINGTAKE NEXT BOX ;

IF RECTANGULARTHEN BEGIN

LABEL IT WITH LAST(TOP)TOP := NEXT(TOP) ;

GC TO AEND

ELSE GO TO CEND

ENDBEGINIF I IS ODD THEN I := I + 1 ;

LABEL 'NO' BRANCH WITH I ;

LABEL 'YES' BRANCH WITH I + 1 ;

I := I + 2 ;

GO TO BEND

'YES' BRANCH

kQ

TCP := POINTER (LABELTAKE BOX CONNECTED TCIF RECTANGULARTHEN BEGIN

OF 'YES 1 BRANCH,•NO' BRANCH ;

TOP)

LABEL ITGO TG AEND

ELSE BEGINIF ALREADYTHEN BEGIN

WITH I - 2

VISITED

ELSE

END

IF TOP = NULLTHEN GO TC STOPE L S t. BEGIN

COMMENT : SET YOURSELF AT 'YES'BRANCH CORRESPONDING TC LAST (top)TAKE NEXT BOX;IF RECTANGULARThEN BEGIN

LABEL IT WITH LAST(TOP) ;

TCP := NEXT(TCP) ;

GO TC A

ENDBEGINIF I I

LABELLABELI := I

GO TOEND

ELSEEND

ENDGO TO

S ODD THEN I

•NO' BRANCH'YES' BRANCH+ 2 ;

B

:= I +wITH I

KITH I + 1

STOP

TCP := NEXT (TOP J ;

IF ALREADY VISITEDTHEN BEGIN

COMMENT : SET Y n URSELF AT 'YES'BRANCH CORRESPONDING TO LAST(TCP)TOP := NEXT(TOP);GO TC AEND;

IF I IS OLD THEN I := I + 1 ;

LABEL 'NO' BRANCH WITH I ;

LABEL 'YES' BRANCH WITH I + 1 ;

I := I + 2 ;

GO TC B ;

: END.

41

APPENDIX C

In order to write an ALMIC statement, all that is needed

is to write the address nuaber followed by a colon and then:

a) for the "next address" field:

1) find the lacel in the flowchart corresponding to

the desired address;

2) the next address is the label of the next bcx if

it is a process box or the label of the "no" branch

otherwise

.

b) for the "select" field :

1) find the label in the flowchart corresponding to

the desired address;

2) if the next box is a decision box, use its

contents as "select" field;

3) if the next box is an even numbered process box,

use zero; otherwise use 1 for "select" field.

c) fcr the "opcode" field :

1) find the label in the flowchart corresponding to

the desired address.

2) if it belongs to a process box use its contents as

"opcode" ; otherwise leave blank.

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BIBLIOGRAPHY

1. IBH Form A22-6843-3, IBM Sy_stem/360 1^0 Interface

Channel to Control Unit^

2. The University of Michigan Memorandum 13, System/360

Interface Engineering Repcrt, by David "ills, pp. 3-39,

November 1967 (Defense Documentation Center AD 667655).

3. Husson, S.S. , Microprogramming^ P£iH2iHls§ and

ll§ctices, pp. 1-19, Prentice-Hall, 1970

4. Intel MCS-J Micro Computer Set Users Manual, March 1973

81

INITIAL DISTRIBUTION LISI

1. Defense Documentation Center

Cameron Station

Alexandria, Virginia 22314

2. library, Cede 0212

Naval Postgraduate School

Monterey, California 93940

3. Asst. Erof . K.H. Brubaker, Code 72BH(Thesis Advisor)

Computer Science Group

Naval Postgraduate School

Monterey, California 93940

4. Asst. Prof. V. M. Powers, Code 52PW (Second Reader)

Computer Science Group

Naval Postgraduate School

Monterey, California 93940

5. IT Eaiirundo Nonato Daniel Duarte, Brazil (student)

515 Eighth Street

Pacific Grove, California 93950

6. Chairman, Computer Science GroupNaval Postgraduate SchoolMonterey, California 93940

82

SECURITY CLASSIFICATION OF THIS PAGE fUTien Dnta Entered)

REPORT DOCUMENTATION PAGE READ INSTRUCTIONSBEFORE COMPLETING FORM

1. REPORT NUMBER 2. GOVT ACCESSION NO. 3. RECIPIENT'S CATALOG NUMBER

4. TITLE (and Subtitle)

A Microprogrammed I/O Interface

S. TYPE OF REPORT & PERIOD COVEREDMaster's Thesis;

March 1974

6. PERFORMING ORG. REPORT NUMBER

7. AuTHORfJ;

Raimundo Nonato Daniel Duarte

3. CONTRACT OR GRANT NUMBERf*)

9. PERFORMING ORGANIZATION NAME ANO ADDRESS

Naval Postgraduate SchoolMonterey, California 93940

10. PROGRAM ELEMENT, PROJECT, TASKAREA 6 WORK UNIT NUMBERS

It. CONTROLLING OFFICE NAME AND ADDRESS

Naval Postgraduate SchoolMonterey, California 93940

12. REPORT DATE

March 1974'3. NUMEER OF PAGES

1*. MONITORING AGENCY NAME A ADDRESSfJ/ dltlerenl lion Controlling Oitlce)

Naval Postgraduate SchoolMonterey, California 93940

15. SECURITY CLASS, (ol this report)

Unclassified

15«. DECL AST.IFI CATION/' DOWN GRADINGSCHEDULE

16. DISTRIBUTION STATEMENT (o! this Report)

Approved for public release; distribution unlimited.

17. DISTRIBUTION STATEMENT (of the abstract entered In Block 20, 11 dltlerenl trom Report)

18. SUPPLEMENTARY NOTES

19. KEY WORDS (Continue on reverse aide it necaasary and Identity by block number)

20. ABSTRACT (Continue on reverse aide It neceeaary and Identity by block number)

This thesis presents a basic hardware model suitable for most sequentialmicroprogrammed devices. A software system is described which allows the useof an assembly-level programming language instead of the binary representationof microcodes. The implementation of a microprogrammed input/output interfaceis presented as an example of use of both the hardware and software.

DD ,^73 1473(Page 1)

EOITION OF I NOV 65 IS OBSOLETES/N 102-014- 6601 |

SECURITY CLASSIFICATION OF THIS PAGE (\*hen Data Entered)

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84

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1 * tfAft^6 JA« CU

22 8

^3.Thesis

078325 Duarte^^^^^^ I/Q

interface.

!SJUH742 25 062 2 3

2HO**2529 1

ThesisD78325 Duarte

c# l A microprogrammed I/O

interface.

3363

lhesD78325

A microprogrammed I/O interface.

3 2768 001 89511 3DUDLEY KNOX LIBRARY