Microprocessors R2013

8/9/2019 Microprocessors R2013

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PREFACE

Dear Reader,

This book is designed for IV Sem B.E. CSE of Anna University Syllabus. It has 5

module. Every module is one unit. It is also helful for !CA Students "!odule #$ %$ &' for Unit ($ #

) %. It is also designed for dedi*ation urose to hel the student *ommunity. If a student "ese*ially

*ollege first rank' +ho is not affordable to ay "or' a student +ho makes the laudable *omment for the

imrovement of this book. ,e +ill be given book for free of *ost.

,oe you might be one among them +ith regards.

Author.


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UNIT I

(THE 8086 MICRO PROCESSOR)

Introdu*tion to --/ 0 !i*roro*essor ar*hite*ture 0 Addressing !odes 0 Instru*tion

set and assembler dire*tives 0 Assembly language rogramming 0 !odular rogramming 0

1inking and 2elo*ation 0 Sta*ks 0 3ro*edures 0 !a*ros 0 Interruts and interruts servi*e

routines 0 Byte and string maniulation.


4/253

41et us ass the light on the *on*et of introdu*tion to --/

Day I

In microprocessor


5/253

Itrodu!t"o to 8086 #"!ro$ro!e%%or&

It +as laun*hed during the year (67-.

A*tually the evolution of mi*roro*essor is

Intel && "& bit mi*roro*essor'

--5 "- bit mi*roro*essor'

--/ "(/ bit mi*roro*essor'

-#-/

-%-/

-&-/

3entium

3entium 0 8ual *ore

i%

i5

i7

9hen robing about mi*roro*essor --/$

De'""t"o o' M"!ro$ro!e%%or&

It is single *hi C3U. 9here C3U *ontains

i. !emory unit "2A!'

ii. Arithmeti* logi* unit "A1U'

iii. Control Unit

--/ has got ,!:S te*hnology.

Adatae%&

All internal register of --/ is ( bit and it has (/ bit data line so it is *alled (/

bit mi*roro*essor.

;rom In ort and :ut ort read and +rite (/ bit data

It has # address lines. So it *an ma ## --/ 0 (

ii. - !,> --/ 0 #

It runs under !inimum and !a?imum mode

M""#u# Mode&

It has only one --/ mi*roro*essor

Ma*"#u# Mode&


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It has more than one --/ mi*roro*essor

+ue%t"o ad A%er%

- Mar/ ue%t"o%&

(. 8ifferentiate bet+een --5$ --/@

Ans

--5 --/

i. - bit ro*essor i. (/ bit

ro*essor

ii. (/ Address

1ines

ii. (6 Address lines

#. 8efine !i*roro*essor@

Ans

It is single *hi C3U +here as C3U *ontains

i. !emory unit "2A!'

ii. Arithmeti* 1ogi* unit "A1U'

iii. Control Unit

%. 8es*ribe the fre=uen*ies of --/@

Ans

i. ( !,> --/ 0 (

ii. - !,> --/ 0 #

&. 8ifferentiate !in mode and !a? mode@

Ans

!in !ode !a? !ode

It has only one --/ mi*ro ro*essor It has more than one --/ mi*ro

ro*essor

E%%a1 +ue%t"o%&

(. 8es*ribe the evolution of mi*roro*essor@

Ans

Intel && "& bit mi*roro*essor'


7/253

O23e!t"e +ue%t"o%&

i. --/ +as laun*hed during

i. --/ ii. (67- iii. (6-/

ii. Intel && is mi*roro*essor

i. & bit ii. - bit iii. / bit

iii. The another name for !ain memory is

i. 2A! ii. 2:!

iv. --/ has got te*hnology

i. C!:S ii. ,!:S

v. --/ is bit mi*roro*essor

i. - bit ii. (/ bit

vi. The address lines # *an ma

i. ##0 ( ii. ## (

vii. The fre=uen*y of --/ 0 ( is

i. ( !,> ii. - !,>

viii. The fre=uen*y of --/ 0 # is

i. ( !h> ii. - !,>

i?. !in !ode needs

i. :nly one --/ ii. T+o --/

?. !a? !ode needs

i. :nly one --/ ii. !ore than one --/

Re%u4t Aa41%"%

(. ii #.i %.i &.ii 5.ii /.i 7.i -.ii 6.i ?.ii

In obDe*tive ans+ers

If your s*ore greater than - then only you *an go to 8ay #.


8/253

41et us robe about ar*hite*ture of --/

Day II

In microprocessor


9/253

Ar!h"te!ture o' 8086

--/ has # address lines and (/ data lines. 8ue to the resen*e of (/ data lines it is

*alled (/ bit mi*roro*essor. So --/ has in ort "or' out ort has (/ bit.

The general blo*k diagram of --/ is$

9e kno+ mi*roro*essor is a single *hi C3U. C3U *ontains

i. !emory "2A!'

ii. A1U

iii. Control Unit

eeing the above three units it refers (/ bit mi*roro*essor --/.

--/ has t+o logi*al units

i. E?e*ution unit

ii. Bus Interfa*e Unit

The simlified --/ Ar*hite*ture has

Execution Unit BIU

DATA, IR &

PRINTER

SEGMENT REG

AND

INSTRUCTION

POINTER

ALU

FLAGSBus Control Loic

Instruction !ueue

I

N

T

E

R

NA

L

B

U

S

Ti"in #n$

Control


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So analysing of C3U it *ontains memory. !emory is in the form of register ":n *hi

2A!'

The register

The another name for F32 is s*rat*had register

--/ Contains

Address register

Segment register

8ata register

;lag register

(. The s*rat*had registers

G 0 Indi*ates (/ bit register. There are four (/ bit F32 "Feneral 3uroseregister'

A?$ B?$ C?$ 8?

A? (/ bit register is bifur*ated.

A, and A1 +hi*h is t+o light bit register. This A,$ A1 or AG is *alled

a**umulator +hi*h is used vehemently in arithmeti* oeration.


11/253

+ue%t"o ad A%er%

- Mar/ ue%t"o%

(. --/ has got ho+ many address lines and ho+ many data lines@

Ans--/ has # address lines and (/ data line

#. --/ has +hat are the t+o logi*al units

Ans

i. E?e*ution Unit

ii. Bus interfa*e unit

%. 9hat are the & tyes of --/ register@

Ans

Address register

Segment register

8ata register

;lag register

&. 9hat are the & si?teen bit F32@

Ans

AGBG

CG

8G

E%%a1 ue%t"o%&

i. 8ra+ the basi* blo*k diagram of --/@

Ans

E?e*ution Unit BIU

O23e!t"e t1$e ue%t"o%&

i. --/ has address lines

i. (/ ii. #

ii. --/ has 8ata lines

i. - ii. (/

iii. --/ is *alled (/ bit ro*essor be*ause of

i. Address lines ii. 8ata lines


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iv. The t+o logi*al units in --/

i. E?e*ution Unit$ IH: Unit

ii. E?e*ution Unit$ Bus Interfa*e unit

v. The another name for F32 is

i. 2egister ii. S*rat*h ad register

vi. --/ *ontains register

i. # ii. &

vii. AG$ 8G$ CG$ 8G are *alled

i. F32 ii. Se*ial register

viii. AG is bit register

i. (/ bit ii. - bit

i?. AG is bifur*ated into

i. A,$ A1 ii. C,$ A,

?. The another name for AG is

i. ;lag ii. A**umulator

2esult Analysis

(. ii #. ii %. ii &. ii 5. ii /. ii 7. i -. i 6.i (.ii

If your s*ore greater than - go to 8ay III


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41et us have the rofit about --/ ar*hite*ture *ontinuation

Day IIIIn microprocessor


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2egarding register the follo+ing info.

AG A, A1 A**umulator

BG B, B1 Base register

CG C, C1 Count register

8G 8, 81 8ata register

BG$ CG$ 8G are temorary storage and also for arithmeti* oeration. It *an be used as

B,$ B1$ - bit or BG(/ bit

The ne?t is ointer and inde? register

S3 Sta*k ointer

B3 Base ointer

SI Sour*e inde?

8I 8estination inde?

The another name of above register is Address 2egister. It hels in addressing modes

S3 oints to of sta*k "T:S'

B3 oints any lo*ation of sta*k

SI ) 8T ;or addressing

;lag register

It is a (/ bit register

7 bit 0 Un used

/ bit 0 Conditional flags

% bits 0 Control flag

Conditional flag has

i. Carry "C;' ii. Jero "J;'

9hen addition overflo+ *omes >ero flag.

After the arithmeti* oeration if result is >ero.

iii. 3arity flag

if even number is the *ounter of one


15/253

iv. Sign flag

Che*k the !SB if

( 0 Kegative

0 3ositive

v. Au?iliary *arry flag

after the &thbit addition if *arry *omes

vi. :verflo+ flag

!SB "- bit or (/ bit' over flo+

vii. Control flags

it has

i. Tra flag Ste by ste debug

ii. Interrut flag Enable interrut

iii. 8ire*tional flag String oeration

Arithmeti* logi* unit

It does arithmeti* and logi* oeration.


16/253

+ue%t"o ad A%er%

- Mar/ ue%t"o%&

(. 9hat are the four F32 in --/@Ans

AG A, A1 A**umulator

BG B, B1 Base register

CG C, C1 Count register

8G 8, 81 8ata register

#. 9hat are the ointers and inde? registers in --/@

Ans

S3 Sta*k ointer

B3 Base ointer

SI Sour*e inde?

8I 8estination inde?

E%%a1 ue%t"o&

(. E?lain --/ flag register@

Ans

(/ bit reresentation.


i. The another name for AG is

i. Au?iliary ii. A**umulator

ii. The another name for BG is

i. Base register ii. Ko su*h register

iii. The another name for CG is

i. Counter register ii. Ko su*h register.

iv. The another name for 8ata register is i. 8G ii. AG


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v. The t+o ointers in --/

i. S3$ B3 ii. SI$ 8I

vi. The t+o inde? register in --/

i. S3$ B3 ii. SI$ 8I

vii. ;lag register in --/ is

i. - bit ii. (/ bit

Re%u4t Aa41%"%

(. ii #. i %.i &.i 5.i /.ii 7.ii

If your s*ore greater than / is allo+ed to day &


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Day IV

In microprocessor


19/253

In Ar*hite*ture of --/ +e had bus interfa*e unit

3erforming address *al*ulation$ re 0 fet*hing instru*tion for =ueing and se=uen*e one by

one

i. The instru*tion =ueue

It has / bytes of instru*tion in =ueue in ;I;:.

ii. !emory segmentation

it has # bit address line.

All register are only - bit or (/ bit for # bit segments are used segments are

various si>e of memory.

# Address lines in --/. So it *an ma ##addresses.

!emory divided by the follo+ing four segments

8ata Segment

1ogi*al address to hysi*al address maing is done. The flo+ "me*hanism' is

3hysi*al address L Base address :;; set

Code segment

It oints instru*tion by instru*tion ointer

iii. The sta*k segment and sta*k ointer

Sta*k is *onse=uently storing data in same data tye in a se*ial +ay. It erforms

3US, and 3:3 oeration. A*tually it i*ks the data 1I;:

Sta*k ointer oints the to of sta*k.

E?tra segment

It uses uer (/ bits of base address in ES

Advantage of segment

!a ##address lines

Address memory is relo*atable


20/253

EU

ControlS%ste"

' ( ) * +

A

AL

B

BL

C

CL

D

DL

SP

BP

SI

DI

Te"-or#r%

Reister

ALU

Fl#s

GPR

EU

+ .it

.us

IT

DS

SS

CS

ES

BIU

Bus

Control

loic

A$$ress

.us

Instructor

!ueue

Re/errin #.o0e -oints t1e $et#ile$ #rc1itecture


21/253

3-

8(&

8(%

8(#

8((

8(

86

8-

87

8/

85

8&

8%

8#

8(

8

C#rr% 2#

Unuse$

P#rit% 2#

Unuse$

Auxili#r% c#rr%

2#

Unuse$

3ero 2#

Sin 2#

Tre/ 2#

Interru-t 2#

Direction 2#

O0er2o4 2#

565+ Fl# reister is


22/253

+ue%t"o ad A%er%

- Mar/ ue%t"o%

(. 8efine hysi*al address@

Ans

3hysi*al address L Base Address :;; set

#. 9hat are the oeration for sta*k@

i. 3US, ii. 3:3

1I;: oeration.

E%%a1 ue%t"o%&

(. E?lain the ar*hite*ture of --/@

Ans

8ay 0 #$ 8ay 0 %$ 8ay 0 &

#. 8ra+ the flag register of --/@


(. BIU has

i. Ko oeration ii. AddressCal*ulation$ 3re fet*hing instru*tion

#. The instru*tion =ueue has bytes of instru*tion in =ueue

i. / bytes ii. & bytes

%. it oints instru*tion

i. B3 ii. Instru*tion oint

&. *ontinuous *onse=uently storing same tye data is

i. Sta*k ii. Mueue

5. Sta*k erforms

i. 1I;: ii. ;I;:

Re%u4t Aa41%"%

(. ii #. i %. ii &. i 5.i

If your s*ore greater than & is allo+ed to go day 5


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41et us NN about --/ addressing modes

Day V

In microprocessor


24/253

i. 8ire*t Addressing

*onsider the instru*tion !:V A1$ O,P

the *ontent is a**essed by

Ko+ A1*ontains ( A

A*tually in --/ has & segments. In that data segment al+ays multilied by (

ii. 2egister indire*t

*onsider the follo+ing instru*tion

!:V BG$ "CG'

,ere indire*t says *ontent of *ontent

A$$ressin Mo$es 7565+8

DirectA$$ress

Mo$e

In$irectA$$ress

Mo$e

B#se$A$$ress

Mo$e

B#se$In$exe$

A$$ress

Mo$e

StrinA$$ress

Mo$e

I9O -orts#ccessin

.%

A$$ress

Mo$e

St#c:Me"or%

A$$ress

Mo$e

66

D#t# Se"ent ; 6

6,66 ero'

KC "um no *arry'

C "um *arry'

3 "um ositive'

VII. 3ro*essor *ontrol instru*tion

i. STC

Set the status in flag *arry is (

ii. C1C

2eset the *arry flag to >ero

iii. C!C

Comlement *arry flag

iv. ST8

Set dire*tion flag

v. C18

2eset to dire*tion flag to >ero

VIII. Interrut instru*tion

IKT

" 0 #55 Tye'

IG. String instru*tion

i. 2E3 CG L

ii. !:V S BG$ CG

iii. C!3 BG$ CG


48/253


49/253

O23e!t"e t1$e ue%t"o&

(. 9hat are t+o *alling ro*edures

i. Kear$ far ii. Kone

#. The Dums are e EGT2K

Eg (

EGT2K name ( tye

3ass+ord *he*king

Stored ass+ord "39('

Entered se*ond ass+ord "39#'

3ass+ord a**essed 3UB1IC in module

Ko+ *he*k the mat*hes +ithout e*ho


55/253

+ue%t"o% ad A%er%

- #ar/ ue%t"o&

(. 8efine modular rogram@

Ans

8ivide a big task into so many sub tasks and e?e*uted arallerly.

#. 9hat is the assembler dire*tion 3UB1IC@

Ans

It shares data in different modules.

%. 9hat is the assembler dire*tive EGT2K@

Ans

If you +ant to share initiali>e EGT2K


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41et us have abstra*t *on*et about ro*edures and ma*ros

Day XII

In microprocessor


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PROCEDURES

In C$ or C flashes about fun*tion. Similarly a sub task reeatedly o**urred +e

eli*ited that named ro*edure.

A main rogram *alls different ro*edure

!ain 3rogram

.....

.....

CA11 ABC

.....

.....

CA11 BCC

.....

.....

CA11 CC8

.....

.....

EK8

But this e?amle only one ro*edure *alled reeatedly

!ain 3rogram

.....

.....

CA11 ABC

.....

.....

CA11 ABC

.....

.....

CA11 ABC

.....

.....

EK8

This ABC sub ro*edure *an be in main +hi*h is *alled near ro*edure.

This ABC sub ro*edure *an be in from other la*es for ro*edure.


58/253

So near is intra

;ar is iner

I3 "Instru*tion 3ointer' +ill be ointing to the ne?t instru*tion in the main

rogram.

i. 9hile returning I3 uses ne?t of *all

5.#.( 9riting a ro*edure

9hile e?e*ution

CA11 ABC

.

.

.

32:C ABC KEA2

.

.

2ET

I. Call and 2eturn instru*tion

8I2ECT CA11

It dire*tly Dum instru*tion

Indire*t CA11

CA11 BG

BG *ontains some value. There it +ill Dum. The reason is *alling *ontent of

*ontent.

II. Intersegment or far *all

8ire*t for Call

A far *all is an intersegment *all.

Indire*t far *all

Content of *ontent *alls an intersegment *all.

III. The 2ET instru*tion

9hen a ro*edure is *alled the *urrent value of I3 is ushed on to the sta*k.

2ET n

;rom oing sta*k +ith n time that value returns.


59/253

2ET %

((%

((#

(((

((

3:3 % so

(( address

It returns

IV. The use of the sta*k in ro*edure *alls.

Sta*k meant for saving return address.

!U1TI 32:C KEA2

USES 8G CG

!U1 BG

!:V 8G$ &5 ,

A88 AG$ 8G

A88 AG$ 8G

!:V CG$ 5 ,

A88 AG$ CG

2ET

!U1TI EK8

EK8

V. 3arameter assing me*hanism.

a. 3assing arameter through register

A$ B$ C Values

8ATA


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A 8B (

B 8B 5

C 8B (5

. C:8E

. STA2T U3

!:V B1$ A

!:V C1$ B

.

.

. EGIT

KT, TE2! A3 32:C KEA2

!U1 C1

A88 BG$ AG

2ET

KT, TE2! A3 EK8 3

EK8

b. 3assing arameter through memory

. 8ATA

K 9:28 6

KU!BE2 BQTE ($ #$ %$ &$ 5$ /$ 7$ -$ 6

. C:8E

. STA2T U3

*. 3assing arameter through sta*k

. !:8E1

. STAC ( ,

. 8ATA

A 89 6-7 ,

B 89 (# ,

2ESU1T 89

. C:8E

. STA2T U3

3US, A


61/253

3US, B

.

+ue%t"o ad A%er%

- Mar/ ue%t"o

(. 8efine ro*edure@

Ans

A sub task reeatedly o**urred +e eli*ited that named ro*edure.

#. 9hat is near and far ro*edure@

Ans

The sub ro*edure *an be in main +hi*h is *alled near ro*edure.

But the ABC sub ro*edure *an be in from other la*es far ro*edure.

So

Kear is intra

;ar is inter

%. 9hat is the instru*tion e?e*ution in instru*tion ointer@

Ans

Instru*tion ointer "I3' oints the ne?t instru*tion in the main rogram.

&. 8efine CA11 and 2ET instru*tion.

AnsCA11 BG

BG *ontains some value then it +ill Dum

2et 0 returns to main. 9hen a ro*edure is *alled the *urrent value of I3

is ushed on to sta*k.

2ET n

;rom oing sta*k +ill n time that value returns

2ET % or 3:3 % are same

((%

((#

(((


62/253

((

E%%a1 ue%t"o&

(. E?lain above ro*edure.

Ans 8ay GII

#. 8is*uss different arameter assing me*hanism in ro*edure@

Ans

i. 3assing arameter through register

ii. 3assing arameter through memoryiii. 3assing arameter through sta*k


63/253

41et us have ebullient *on*et about !AC2: s

Day XIII

In microprocessor


64/253

In the *on*et of subroutine there is oen subroutine and *losed sub routine. Close sub

routine is like fun*tion and it returns value. But oen subroutine it +onRt return a value

but asses arameters. 9herever the oen subroutine *alled it is inserted on that la*e.

The another name for oen subroutine is !AC2:Rs

E?amle (

9riting a !a*ro the general format of !AC2: is

!AC2: KA!E !AC2: O3arameter 1istP

IKST2UCTI:K

. "B:8Q'

.

EK8 !

;or e?amle

. !:8E1 S!A11

. C:8E

. STA2T U3

. EKT2 !AC2:

!:V AG$ O(P

A88 AG

EK8 !

!AC2: EKT2

EGIT

EK8

A some number of statements reeatedly o**urring. ;or making rogrammer easy first

the series of line named. 9henever they are *alled in main the ma*ro routine inserted so

no Dum$ return +ork 4 S,A !AC2: ) Arg ( ) Arg #.

,ere arameters +e *an ass in oen sub routine "!AC2:'

Even +e *an use nested !AC2:

M#cro $eniton


65/253

;or e?amle

!AC2: (

.

.

!AC2: #

.

.

# EK8

( EK8

So it is like bo? in bo?. Even +e *an say #8 also.

E%%a1 ue%t"o

(. E?lain about !AC2: "oen sub routine' @


66/253

Day 14th

In microprocessor


67/253

41et us have good *on*et in interrut in --/

Interrut brings meaning of temorary ste. In *omuter handling it is handling

of eriherals +hen key ressed then interrut servi*e routine "IS2' is *alled.

Interrut of --/

Interruts are hard+are and soft+are interrut.

After e?e*uting one *y*le the ro*essor *he*ks is there any interrut.

So

#. Interrut servi*e routine and interrut ve*tor

IS2 +hen e?e*uting man rogram if interrut *omes then it Dums IS2

Address of arti*ular IS2 is interrut ve*tor

%. Interrut ve*tor table

#5/ interrut ve*tor is available in --/

So 2A! lo*ation

.

MAIN PROG

PUS F

CLEAR IFPUS CS

POP IF

POP CS

POP F

IRET

ISR


68/253

.

%;;,

In ve*tor it *ontains *ode segment and instru*tion ointer. So

Interrut ve*tor table in --/

Still in & bytes

CS

IP

CS

IP

CS

IP

INT '** >ector

INT >ector

INT 6 >ector

CS IG

CS LO

IP IG

IP LO


69/253

8edi*ated Interrut Tyes

They are for C3U oeration

i. IKT "8ivide by >ero error'

In this interrut also *alled e?*etion

ii. IKT ( "Single steing'

It is like tra*ing +hi*h is an imortant idea in debugging

iii. IKT # "Kon mask able interrut'

iv. IKT % "Break oint interrut'

v. IKT & ":verflo+ interrut'

III. Soft+are interruts

The general synta? is

IKT tye number

Interrut ve*tor table allo*

IKT tye no. 1:C An divide by >ero

( & single ste interrut

# - K!I

% Break

& ( overflo+

5 to %( reserved by

%# to #55 available to user

ii. 8:S and BI:S interrut routine8:S

IKT #(,

BI:S

Basi* inut outut system


70/253

+ue%t"o ad A%er

- Mar/ ue%t"o

(. 8efine interrut@ 9hat is IS2@

Ans

Interrut brings meaning of temorary ste. In *omuter handling it is

handling of eriherals +hen key ressed then interrut servi*e routine "IS2' is

*alled.

#. 8efine IS2 and IV@

Ans

IS2 +hen e?e*uting main rogram if interrut *omes then it Dums IS2.

Address of arti*ular IS2 is IV "interrut ve*tor'

%. 8efine IVT in --/.

Ans

#5/ interrut ve*tor is available in --/ +hile in ve*tor it *ontains *ode

segment and instru*tion ointer.

&. 9hat are the fun*tions of dedi*ated interrut tyes@

Ans

i. IKT "8ivide by >ero error'ii. IKT ( "Single steing'

iii. IKT # "Kon mask able interrut'

iv. IKT % "Break oint interrut'

v. IKT & ":verflo+ interrut'

5. 9hat are the 8:S and BI:S interrut routines@

Ans

i. In 8:S IKT #( ,

ii. BI:S Basi* inut outut system.


71/253

O23e!t"e t1$e ue%t"o

(. Interrut means

i. Temorary sto ii. 3ermanent sto

#. IS2 is

i. Interrut sta*k register

ii. Interrut servi*e routine

%. Interruts are .

i. Soft+are$ hard+are ii. Ko su*h

&. 9hen e?e*uting main rogram it Dums to

i. IS2 ii. Ko su*h

5. IKT meant for

i. 8ivide by >ero error

ii. Single ste error

/. IKT ( meant for

i. Single ste error

ii. 8ivide by >ero error

7. IKT # means for

i. K!I ii. !I

-. IKT % meant for

i. Break oint interrut

ii. K!I

6. IKT &

i. K!I ii. :verflo+ interrut

(. BI:S is

i. Basi* inut outut system

ii. Ko su*h

Re%u4t aa41%"%

(.i #.ii %.i &.i 5.i /.i 7.i -.i 6.ii (.i

If your s*ore is greater than 6 go to day (5


72/253

41et us have an enti*ing *on*et in hard+are interruts

Day 15th

In microprocessor


73/253

Hardare Iterru$t%

--/ has IKT2 in K!I in

i. K!I "Kon maskable interrut'

ii. IKT2 "Kon ve*tored interrut in --/

IKT2 high riority interrut

Feneration of a tye number.

It is to ro*essor. 9hen IKT2 in is given the ro*essor resonds by

lo+ers the IKTA line.

There is 7&1S#&& tristate buffer ":K$ :;;$ ,igh 0 imedan*e'

Inut given by s+it*hes deends on that$ that tyes ro*essor "--/' gets

interruts.

Feneration of tye number

5

6

5

+

D6

D

D'

D(

D)

D*

D+

D

)

L

S

'

)

)

TAIN

COEO


74/253

VI. 3riority of interruts

i. Internal interruts and soft+are interruts

ii. K!I

iii. IKT2

+ue%t"o ad a%er%

- #ar/ ue%t"o

(. E?lain hard+are interrut@

Ans

--/ has IKT2 in and K!I in

i. K!I "Kon maskable interrut'

ii. IKT2 "Kon ve*tored interrut in --/

IKT2 high riority interrut

#. E?lain tri state buffer@

Ans

;or e?amle

7&1S#&& < Tri state buffer

i. State ( :KState # :;;

State % high imedan*e

%. 9hat are the riority interruts@

Ans

i. Internal interruts and soft+are interruts

ii. K!I "non maskable interrut'

iii. IKT2

E%%a1 ue%t"o

(. E?lain in detail about interruts@

Ans

8ay (& 0 day (5


75/253


(. --/ has $

i. IKT2$ K!I ii. Ko su*h

#. K!I is

i. Ke+ maskable interrut

ii. Kon maskable interrut

%. Kon ve*tored interrut in

i. IKT2 ii. Ko su*h

&. Tri state buffer is

i. 7&1S# ii. 7&1S#&&

Re%u4t aa41%"%

(.i #.ii %.i &.ii

If s*ore is greater than & you *an go to day (/th


76/253

41et us have ebullient *on*et in string instru*tion

Day 16th

In microprocessor


77/253

1ist of instru*tion "String'

SI.Ko instru*tion format fun*tion erformed

( !:V SB H !:V S9 move byte or +ord string

# C!3 SB H C!3 S9 *omare byte or lord string

% SCASB H SCA S9 s*an byte or +ord string

& 1:8 SB H 1:8 S9 load byte or +ord string

5 ST: SB H ST: S9 store byte or +ord string

/ C18 *lear dire*tion flag

7 SI8 set dire*tion flag

- 2E3

6 2E3 E H 2E3 #

( 2E3 KE H 2E3 KJ


78/253

+ue%t"o ad A%er

E%%a1 ue%t"o

(. E?lain about --/ string instru*tion@

Ans (/thday


(. !:V SB H !:V S9 is

i. !ove byte or +ord string ii. Comare

#. C!3 SB H S!3 S9 e of the

mi*roro*essor.

In startu main rogram Kum ( only - bit others are (/ bit so it relats BG$ CG.

%. Start the :2F rogram #,@

3rogram

.!:8E1 TIK &

. 8ATA

:2F # ,

&. 9rite a rogram to use !:V instru*tion@

3rogram

. !:8E1 TIK &

. 8ATA

C:ST 8B ( ,

SE11 8B

.C:8E

.STA2T U3

32:;IT EMU #5 ,

!:V A1$ C:ST

A88 A1$ 32:;IT

!:V SE11$ A1

EGIT

.EK8

5. Add 5 numbers in an array@

3rogram.!:8E1 TIK &

. 8ATA

A22AQ 8B ( , # , % , & , 5 ,

.C:8E

.STA2T U3

!:V C1$ 5


82/253

!:V A1$

!:V 81$

1::3 ( A88 A1$ A22AQ O8IP

IKC 81

8C2 C1

KJ 1::3

!:V 2ESU1T$ A1

/. Subtra*t & from /

3rogram

.!:8E1 S!A11

.C:8E

.STA2T U3

!:V A1$ / ,

!:V B1$ & ,

SUB A1$ 81

!:V 81$ A1

EGIT

EK8

7. !ultily rogram@ :B ? :;/,

3rogram

.!:8E1 TIK &

. 8ATA

!U1T 8B :B, H !U1TI31I

!U13 8B :;/,

32:8 89

.C:8E

.STA2T U3

!:V A1$ !U13

!U1 !U13

!:V 32:8$ AG

.EGIT

.EK8

E?lanation


83/253

The main instru*tion is

!V1R

!V1 A$ B L A N B


84/253

-. ;ind fa*torial of 5(@

3rogram

.!:8E1 TIK &

.8ATA

;ACT 89

.C:8E

.STA2T U3

!:V A&$ (

!:V C1$ 5

1::3 !U1 A1$ C1

8EC C1

KJ 1::3(

!:V ;ACT$ A1

6. 8ivision

!:V AG$ &&&& ,

!:V C1$ #

8IV C1

,ere

AG & & & &

C1 #

AG H C1 L &&&& H # L ####

Muotient in AG

2emainder in C1

(. Consider AG L 6C, BG L # , CG L A,

;ind various logi*al instru*tion@

Ans

i. AK8 oeration

AK8 AG$ BG


85/253

E?amle

(( (

2esult is ,

ii. :2 oeration

:2 AG$ BG

E?amle

((

(

(((

Ans B,

iii. G:2

(( (

(((

Ans B,

iv. TEST$ AG$ BG

(( (

(((

Ans 7,

This logi*al instru*tion mainly ali*able in mask in image ro*essing


86/253

((. Shift one bit right and left say +hat is the mathemati*al result@

3rogram

S,1 AG$ (

;or e?amle

AG (

#

Ko+ shift left one bit

(

&

So shift left is one bit relies multily by #. If shift left by # bits is multily by &

Similarly S,2 is shift right in bit divide by t+o. Shift right in t+o bit n divide by four.3rogram (%

2otate left or right is making interfa*e C3U +ith -#55 and dislay the 1E8 eight left to

right or right to left

3rogram (&

2E3 !:V SB

This is the high fre=uen*y move the tye string.

3rogram (5

C!3SB

Comare the string byte.

3ort oeration

3ort means *arry. In ort from inut devi*e to C3U. :utut C3U to outut devi*e

IK A1$ #7 , devi*e number

!:V #7 to A1

:UT A1$ #- ,devi*e number

!:V C3U buffer "or' a**umulator to #-


87/253

E?. Ko ( %# BIT A88ITI:K AK8 SUBT2ACT:K

AI!

To +rite an assembly language rogram to add and subtra*t t+o %#


88/253

!:V O#P$ AG

!:V AG$ O%#P

A8C AG$ O%/P

KC loo(IKC CG

1oo( !:V O##P$ AG

!:V O#&P$ CG

,1T

TAB1E (

!emory 1abel

!nemoni*s

8es*rition

Instru*tion :erand

( !:V CG$

!ove immediately , to CG

register

(& !:V AG$ O%P Coy *ontents of % to AG register

(- A88 AG$ O%&P

Add *ontent of memory %& +ith

*ontent of AG register

(C !:V O#P$ AG

Coy *ontent to AG register to t+o

memories from #

(( !:V AG$ O%#P

Coy *ontents of memory %# to

AG register

((& A8C AG$ O%/PAdd *ontent of memory %/ +ith


((- KC loo( um to se*ified memory C;L

((A IKC CG

In*rement *ontent of CG register

on*e

((B 1oo( !:V O##P$ AG


memories from ##

((; !:V O#&P$ CG

Coy *ontent to CG register to t+o

memories from #&


89/253

(#% ,1T ,alt

:UT3UT

IK3UT 8ATA :UT3UT 8ATA

% 6666 # %%%#

%# 6666 ## %%%%

%& 6666 #& (

%/ 6666


90/253

%# < BIT SUBT2ACTI:K

A1F:2IT,!

Ste( Start the rogram.

Ste# !ove immediately the number , to CG register.

Ste% Coy the *ontents of the memory % to AG register.

Ste& Add the *ontent of the memory %& +ith the *ontent of AG register.

Ste5 Coy the *ontent to AG register to t+o memories from #.

Ste/ Coy the *ontents of the memory %# to AG register. Ste7

Subtra*t the *ontent of the memory %/ from AG register.

Ste- um to se*ified memory lo*ation if there is no *arry i.e. C;L.

Ste6 In*rement the *ontent of CG register on*e.

Ste( Coy the *ontent to AG register to t+o memories from ##.

Ste(( Coy the *ontent to CG register to t+o memories from #&.

Ste(# End.

!KE!:KICS

!:V CG$

!:V AG$ O%PA88 AG$ O%&P

!:V O#P$ AG

!:V AG$ O%#P

SBB AG$ O%/P

KC loo(

IKC CG

1oo( !:V O##P$ AG

!:V O#&P$ CG

,1T


91/253

TAB1E #

!emory

1

label

!nemoni*s

8es*rition

Instru*tion :erand

( !:V CG$

!ove immediately , to CG

register

(& !:V AG$ O%P Coy *ontents of % to AG register

(- A88 AG$ O%&PAdd *ontent of memory %& +ith


(C !:V O#P$ AG


memories from #

(( !:V AG$ O%#PCoy *ontents of memory %# to

AG register

((& SBB AG$ O%/PSubtra*t *ontent of memory %/

from *ontent of AG register

((- KC loo( um to se*ified memory C;L

((A IKC CG

In*rement *ontent of CG register

on*e

((B 1oo( !:V O##P$ AG


memories from ##

((; !:V O#&P$ CGCoy *ontent to CG register to t+o

memories from #&

(#% ,1T ,alt


92/253

:UT3UT


% 6666 #

%# 6766 ## ;E

%& 6666

%/ 6666

2ESU1T

Thus an assembly language rogram to add and subtra*t t+o %#


93/253

E?. Ko # (/ BIT !U1TI31ICATI:K AK8 8IVISI:K

AI!

To +rite an assembly language rogram to multily and divide t+o unsigned (/


94/253

!emory

1

label

!nemoni*s

8es*rition

Instru*tion :erand

( !:V AG$ O%P Coy *ontents of % to AG register

(& !:V CG$ O%#P Coy *ontents of %# to CG register

(- !U1 CG!ultily the *ontent of the CG register+ith the *ontent of

a**umulator

(A !:V O#P$ AGCoy *ontent to AG register to the

memory #

(E !:V O#&P$ 8G

Coy *ontent to 8G register to the

memory ##

((# ,1T ,alt

:UT3UT


% (#%& # /

%# 5/7- ## /#/

8IVISI:K

A1F:2IT,!


95/253

Ste ( Start the rogram.

Ste# Coy the *ontents of the memory % to AG

register. Ste% Coy the *ontents of the memory %# to

CG register.

Ste& 8ivide the *ontent of the CG register from the *ontent of

a**umulator. Ste5 Coy the *ontent to AG register to the memory #.

Ste/ Coy the *ontents of 8G register to the memory

##. Ste7 End.

!KE!:KICS

!:V AG$ O%P

!:V CG$ O%#P

8IV CG

!:V O#P$ AG

!:V O##P$ 8G

,1T


96/253

TAB1E #

!emory

1

label

!nemoni*s

8es*rition

Instru*tion :erand

( !:V AG$ O%P Coy *ontents of % to AG register

(& !:V CG$ O%#P Coy *ontents of %# to CG register

(- 8IV CG

8ivide the*ontent of the CG register

+ith the *ontent ofa**umulator

(A !:V O#P$ AGCoy *ontent to AG register to the

memory #

(E !:V O#&P$ 8G

Coy *ontent to 8G register to the

memory ##

((# ,1T ,alt

:UT3UT


% (#%& #

%# 5/7- ## &&&&

2ESU1T

Thus an assembly language rogram to multily and divide t+o unsigned (/


97/253

E?. Ko % ;ACT:2IA1

AI!

To +rite an assembly language rogram to *al*ulate fa*torial of nero in CG

register. Ste- Coy the *ontent to AG register to t+o memories from

#. Ste( End.

!KE!:KICS

!:V AG$ (

!:V CG$ O%P

!:V AG$ (

1oo( !U1 CG

8EC CG


98/253

KJ loo(

!:V O#P$ AG

,1T

TAB1E (

!emory

1

label

!nemoni*s

8es*rition

Instru*tion :erand

( !:V AG$ (

!ove immediately the number

(, to AG register

(& !:V CG$ O%P

Coy the *ontents of memory % to

CG register

(/ !:V AG$ (

!ove immediately the number

, to AG register

(A loo( !U1 CG

!ultily *ontent of CG register+ith

*ontent of a**umulator

(B 8EC CG

8e*rement *ontent of CG register

on*e

(C KJ loo(

um to se*ified memory lo*ation if

there is no >ero in CG register

(E !:V O#P$ AGCoy *ontent to AG register to

memory #

((# ,1T ,alt


99/253

:UT3UT


% - # 6d-

2ESU1T

Thus an assembly language rogram to *al*ulate fa*torial of n


100/253


101/253

!:V BG$ #

!:V CG$ OBGP

!:V C,$ C1

1oo# IKC BG

IKC BG

!:V AG$ OBGP

IKC BG

IKC BG

C!3 AG$ OBGP

C loo(

!:V 8G$ OBGP

!:V OBGP$ AG

8EC BG

8EC BG

!:V OBGP$ 8G

IKC BG

IKC BG

1oo( 8EC BG

8EC BG

8EC C1

KJ loo#

!:V BG$ #

!:V C,$ C1

8EC C,

KJ loo#

,1T


102/253

TAB1E (

!emory

1

label

!nemoni*s 8es*rition

Instru*tion :erand

( !:V BG$ # !ove# to BG register

(& !:V CG$ OBGP !ove BG memory data to CG register

(/ !:V C,$ C1 !ove data from C1 to C,

(- 1oo# IKC BG In*rement BG register *ontent on*e

(6 IKC BG In*rement BG register *ontent on*e

(A !:V AG$ OBGP!ove BG memory data to AG

register

(C IKC BG In*rement BG register *ontent on*e(8 IKC BG In*rement BG register *ontent on*e

(E C!3 AG$ OBGP

Comare AG register *ontent and

BG memory

((( C loo(um to se*ified memory lo*ation

if *arry is (

((% !:V 8G$ OBGP

!ove BG memory data to 8G

register

((5 !:V OBGP$ AG!ove data from AG register to BG

memory data

((7 8EC BG 8e*rement BG register *ontent on*e

((- 8EC BG 8e*rement BG register *ontent on*e

((6 !:V OBGP$ 8G

!ove data from 8G register to BG

memory data

((B IKC BG In*rement BG register *ontent on*e

((C IKC BG In*rement BG register *ontent on*e

((8 1oo( 8EC BG 8e*rement BG register *ontent on*e

((E 8EC BG 8e*rement BG register *ontent on*e

((; 8EC C1 8e*rement C1 register *ontent on*e

(# KJ loo#

um to se*ified memory lo*ation

if there is no >ero in CG register


103/253

(## !:V BG$ # !ove# to BG register

(#/ !:V C,$ C1

Coy C1 register data to C, register

(#- 8EC C, 8e*rement C, register *ontent on*e

(#6 KJ loo#

um to se*ified memory lo*ation

if there is no >ero in CG register

(#B ,1T ,alt

:UT3UT


# & ## (

## % #& #

#& 5 #/ %

#/ & #- &

#- # #A 5

#A (

2ESU1T

Thus an assembly language rogram to sort n


104/253

E?. Ko 5 S:1VIKF AK EG32ESSI:K

AI!

To +rite an assembly language rogram for solving an e?ression using --/mi*roro*essor kit.

A33A2ATUS 2EMUI2E8

--/ !i*roro*essor it

3o+er Chord

ey Board

A1F:2IT,!

Ste ( Start the rogram.

Ste# 1oad dataRs from memory to AG

register. Ste% Set the *onditions to solve an

e?ression.

Ste& Solve the e?ression given belo+ using the *onditions

assumed. Ste5 Store the result in the memory.

Ste/ 8islay the sorted result from

memory. Ste7 End.


105/253

!KE!:KICS

!:V BG$ O#P

!U1 AG

!:V BG$ O##P

!U1 BG

!:V O%P$ AG

!:V AG$ O#P

!:V BG$ O#&P

!U1 BG

A88 AG$ O%P

A88 AG$ (

!:V O#/P$ AG

,1T


106/253

TAB1E (

!emory

1

label

!nemoni*s

8es*rition

Instru*tion :erand

( !:V AG$ O#P

!ove data from memory # to

AG register

(& !U1 AG!ultily *ontent of AG register +ith


(5 !:V BG$ O##P

!ove data from memory ## to

BG register

(6 !U1 BG

!ultily *ontent of BG register+ith


(A !:V O%P$ AG

Coy *ontent to AG register to

memory %

(E !:V AG$ O#P

!ove data from memory # to

AG register

((# !:V BG$ O#&P

!ove data from memory #& to

BG register

((/ !U1 BG

!ultily *ontent of BG register+ith


((7 A88 AG$ O%PAdd *ontent of memory % +ith


((B A88 AG$ (Add the number ( to AG

register

((; !:V O#/P$ AGCoy *ontent to AG register to

memory #/

(#% ,1T ,alt


107/253

:UT3UT


# # #/ (;

## &

#& 7

2ESU1T

Thus an assembly language rogram for solving an e?ression +as +ritten and

e?e*uted using --/ mi*roro*essor kit.


108/253

E? Ko / SU! :; K KU!BE2S IK AK A22AQ

AI!

To +rite a rogram to find sum of n numbers in an array.

A33A2ATUS 2EMUI2E8

--5 !i*roro*essor it

3o+er Chord

A1F:2IT,!

Ste( Start the rogram.

Ste# Initiali>e the *ounter.

Ste% Fet the first number.

Ste& 8e*rement the *ounter.

Ste5 1oad the base address of an array in to BG

Ste/ By using the loo get the ne?t number in to 8G and add it +ith AG.Ste7 In*rement the ointer and de*rement the *ounter.

Ste- If the *ounter value is not e=ual to >ero then go to ste/

Ste6 Else store the result.

Ste(Sto the rogram.


109/253

!KE!:KICS

!:V C1$O#P

!:V AG$O##P

8EC C1G:2 8($8(

1EA BG$O#&P

1::3( !:V 8G$OBG8(P

A88 AG$BG

IKC 8(

IKC 8(

8EC C1

KJ 1::3(

!:V O%P$AG

,1T


110/253

TAB1E

1ABE1 :3C:8E :3E2AK8 8ESC2I3TI:K

!:V C1$O#P !ove the memory *ontent to C1.

!:V AG$O##P !ove the memory *ontent to AG

8EC C1 8e*rement the C1 register.

G:2 8($8( G:2$8( registers

1EA BG$O#&P !ove the *ontent of #& to BG

!:V 8G$OBG8IP

!ove the *ontent of BG8( to

8G

A88 AG$BG Add AG +ith 8G *ontent.

IKC 8I In*rement 8(

IKC 8I In*rement 8(

8EC C1 8e*rement C1

1::3 ( KJ 1::3 ( If >ero flag is reseted go to loo(

!:V O%P$AG

!ove the *ontent to

memory

lo*ation

,1T ,alt


111/253

:UT3UT


#% %/

###

#&%

#/(

2ESU1T

Thus the sum of n numbers in an array has been done using --/ mi*roro*essor and the

outut is verified.


112/253

U"t II

8086 SSTEM 9US STRUCTURE

--/ 0 Signals 0 basi* *onfiguration 0 system bus timing 0 system design using --/ 0 IH:

rogramming 0 Introdu*tion to multirogramming 0 system bus stru*ture 0 multiro*essor

*onfigurations 0 *oro*essor$ *losely *ouled and loosely *ouled *onfigurations 0

introdu*tion to advan*ed ro*essors.


113/253

4Unit II signal toi* signals in *erebrum

Day 17th

In microprocessor


114/253

--/ signals

The advantage of --/ has (/ bit data bus. Instru*tion =ueue is / byte. It has memory and IH:

interfa*ing has got in !HI:. And also it has B,E H S7 for --/.

--/ has t+o mode oeration

i. !inimum mode

ii. !a?imum mode

!in mode for only one ro*essor +hereas ma? mode is multiro*essor

(. !inimum mode ins

In --/

,ere A1E is address lat*h enables filters by lat*h to filter address and data lines.

There are % tyes of signal

i. Common mode for min and ma?

ii. :nly min mode

iii. :nly ma? mode

I. :nly min mode

i. A1E

A80 A8(5

A1E filters address and data lines

5

6

5

+

L

A

T

C

7H SHEB EBH

A6A

A+

A

S(

S+

AD6

AD*

D6D

*

ALE


115/253

ii. A(6H S/0 A(/H S%

S& S% e?tra segment

( sta*k segment( *ode segment

( ( data segment

;our segments *an be a**essed through S%) S&signals

ii. RD it is +hen signal is lo+ +e *an go for IH: read or memory read.

iii. WR +hen the signal is lo+ from buffer "lat*h' to memory or outut devi*e

iv. Clo*k it is used to set the fre=uen*y

v. 2eset

vi. 2eady

vii. Test

it *he*k +hether arithmeti* *oro*essor in the system

viii. A1E Address lat*h enable

i?. NED 8ata available or not

?. RDT H data re*eived or transmitted

?i.IOM H

!emory and IH: oeration?ii. ,:18 +hen it is high 8!A "dire*t memory a**ess' taken la*e

?iii. ,18A A*kno+ledgement in 8!A

?iv XMMN H it is min and ma?. In min mode only one ro*essor ma? mode has more than

one ro*essor.

?v STHEB H

?vi FK8 Fround signal

?vii V** The o+er suly

?viii IKT2 Interrut

?i? IKTA Interrut a*kno+ledgement

?? K!I non maskable interrut


116/253

The demultile? of address "or' data bus is by lat*h

7&1S%7%

And also it uses 7&1S#&5 for o*tal tri 0 state bi 0 dire*tional buffer.

Control signals for read and +rite

9hile read it needs tristate buffer and +rite it needs lat*h

!emory and IH:

It does

!E!2!emory read

!E!9!emory +rite

I:2I: read

I:9I: +rite

)

L

S

'

)

*

A

A'

A(

A)

A*

A+

A

A5

B

B'

B(

B)

B*

B+

B

B5

DIR


117/253

Clo*k generation

3ro*essor is syn*hroni>ed +ith *lo*k.

2eady

-#-& ready outut in is *onne*ted to 2EA8Q inut in of --/

5

6

5

+

IOM H

DR

RW

(5AD

-AD

7AD

AD

)

L

S

'))

IOM H

DR

RW

)

L

S

')*

(5D

-D

)

L

S

')*

7D

D

Buer

contro

l

.us

Buer

$#t#

.us


118/253

So generally

The four signals I: read$ I: +rite$ !emory read and !emory +rite is given

In --/ 2ead ma*hine *y*le timing diagram

WR RDW

IOM H

DORI

RIMEM

RMEM

WRIO

AD6A

D#t# in

T T

'T

(T

)

Cloc:

AD6

AD6

ALE

RDTH

DR

END

READY


119/253

Similarly +rite *y*le

A$$ress

T T

'

T(

T)

A$$ress

$#t#

St#tus

A$$ress D#t#

RW


120/253

+ue%t"o ad A%er%

- Mar/ ue%t"o%

(. 9hat are the advantages of --/@Ans

(/ bit data bus

Instru*tion =ueue is / byte

It has memory and IH: interfa*e in OIM H

It has 7HSBHE

#. 9hat are the t+o modes of oerations in --/@

Ans

i. !inimum mode

ii. !a?imum mode

!inimum mode for only one ro*essor

!a?imum mode is for multiro*essor

%. 8efine A1E@

Ans

Address lat*h enable$ the lat*h filters address and data lines.&. 9hat are % tyes of signals in --/@

Ans

:nly !in mode

:nly !a? mode

Common mode for min and ma?.

5. E?lain briefly *ontrol signals for read and +rite@

Ans

9hile read it needs tristate buffer and +rite in needs lat*h.

In IOM H it does

!emory 2ead !E!2

!emory 9rite!E!9

I: read I:2

I: +rite I:9


121/253

E%%a1 ue%t"o

(. a. 8es*ribe signals of --/@

b. In --/ read ) +rite ma*hine *y*le timing diagram@

Ans 8ay GVI ) GVII

O23e!t"e ue%t"o&

(. B,E is

i. Bus high enable ii. Bus high interrut

#. --/ has $

i. !inimum mode$ ma? mode

ii. Ko su*h

%. !in mode for

i. :ne ro*essor ii. T+o or more ro*essor

&. !a? mode for

i. :ne ro*essor ii. T+o or more ro*essor

5. ,:18 +hen it is high

i. 8!A taken la*e ii. 3IC taken la*e

/. IKT2 meant for

i. Interrut ii. Kon interrut

7. The demultile?er of address "or' data is by bat*h

i. 7&1S%7% ii. 7&(

Re%u4t aa41%"%

(.i #.i %.i &.ii 5.i /.i 7.i

If your s*ore is / or more go to 8ay (7


122/253

41et us engross the *on*et of !a? mode

Day 18th

In microprocessor


123/253

It is dedi*ated for multiro*essor *onfiguration. In multiro*essor it has inter 0 ro*essor

*ommuni*ation and bus *ontention.

The ma? mode --/ +ith numeri* *oro*essor "--7' and IH: ro*essor "--6'. In

that loosely *oules multiro*essor system.

The -#-- bus *ontroller ho+ lo*k *ontrol signal generated and *omatible +ith --/.

i. Mueue status ins

MS$MS(

ii. 1o*k

iii. Instru*tion *y*le has

a. ;I 0 ;et*h instru*tion "o*ode fet*h'

8I 0 8e*ode instru*tion

C: 0 Cal*ulate the oerand address

;: 0 ;et*h oerand

EI 0 E?e*ute instru*tion

9: 0 +rite in memory

So ma? mode has

5

65

+

5'55

Bus

controller

RMWM

ORI

OWI


124/253

In !a? mode

MS( MS Ko oeration

( ;irst byte of an o*ode

( Mueue is Emty( ( Subse=uen*e byte of an

o*ode

#S (S .S !HC *y*le

interrut

( I: 2ead

( I: +rite

( ( ,alf ( instru*tion fa*tor

( ( memory read

( ( memory +rite

( ( ( in a*tive

+ue%t"o ad A%er%

E%%a1 ue%t"o%

(. 9hat are the signals for !a? mode only@

Ans 8ay GVII


125/253

41et us get rudiment in the *on*et of IH: rogramming.

Day 19th

In microprocessor


126/253

I:O Prora##"&

--/ need IH: as +ell as memory for inter *onne*tion so memory read and memory

+rite also IH: read "kbd' and IH: +rite "V8U'.

There are so many IH: devi*es *onne*ted to the ro*essor.

;or that +e need ort. The meaning of ort is *arry. So transort has o**urred.

;or In ort keyboard give data. ;or out ort to rinter et*.

eeing the IH: orts +ith address bus and data bus and read and +rite *ontrol signals

565+

Tri st#te

.uer I9P

7In-ut -ort8

O9

P

7out-ut -ort8

565+

Tri st#te

.uer

565+

Out-ut

Port

In-ut

Port

DR

D6D

*


127/253

,ere relating "maing' ro*essor to IH: is

!emory maed IH:

3eriheral or Isolated IH:

i. !emory maed IH:.

,ere interfa*ing E32:!$ E32:! by memory read and memory +rite

ii. IH: maed IH:

565+

EPRAM

MR

M

565+

:.$

>DU

In-u

t

Out-u

t


128/253

+ue%t"o ad A%er%

- Mar/ ue%t"o%

(. --/ need +hat inter *onne*tionAns

i. !emory inter*onne*tion

ii. IH: inter *onne*tion

#. 9hat are the four *onne*tion@

Ans

i. IH: read

ii. IH: +rite

iii. !emory read

iv. !emory +rite

%. 9hat is atta*hed bet+een IH3 and ro*essor and also :H3 and ro*essor@

Ans

E%%a1 ue%t"o&

(. E?lain in brief IH: rogramming in that IH: interfa*ing memory interfa*ing@

Ans 8ay GVIII.

565+

Tri st#te

.uer I9P

7In-ut -ort8

O9

P

7out-ut -ort8

565+

Tri st#te

.uer


129/253

41et us eli*it the *on*et of multirogramming

Day 20th

In microprocessor


130/253

Mu4t"$rora##"&

!ore than one rogram e?e*uted by one ro*essor is *alled multirogramming. In

8:S it is eli*ited that only one rogram. In UKIG more than one rogram

i.e.

E?e*uted. It is also *alled stati* artition and another is dynami* artition.

!ultiro*essor

It is more than one ro*essor e?e*uting single Dob is *alled multi ro*essor.

And also *oro*essor augmentation is *alled multiro*essor

Bus *ontension

!ore than one ro*essor shares system memory and IH: through a *ommon system

bus.

I3C means inter ro*essor *ommuni*ate

OS

Pror#"

Pror#" '

RAM

T#s:

Su. t#s:

'

Su. t#s:

Processor

executes

Processor

'

executes

Out-ut


131/253

i. Closely *ouled *onfiguration be*ause --/ augmented +ith --7 numeri*

*oro*essor. ,en*e --7 %# bit floating oint oeration does "e?e*utes' very

easily

ii. 1oosely *ouled *onfiguration

It *ontains different modules. Ea*h module may *onsist of an --/

565+

565

Bus

control

loic

M IO

S%ste"

Bus

Cloc:

Loc#l I9O

$e0ices

Loc#l

"e"or%

Loc#l Bus

Loc#l .us

"e"or%

control loic

Cloc: 565+ &

565

S%ste" .us

control loic

Mo$ule

Mo$ule '


132/253

9hile in loosely *ouled system ea*h ro*essor runs indeendently. If more than one

ro*essor shares *ommon resour*es it is ossible by

i. 8aisy *hining

The bus +as re=uested. If bus is granted 4bus busy +ill be set. ,en*e other

masters have to +ait. The masters are sele*ted by if & markers are their # address

lines.

!aster

( !aster (

( !aster #

( ( !aster %

,en*e

ii. 3olling method

If for e?amle & masters are their the # address lines

Address line

!aster

( !aster (

( !aster #

( ( !aster %

Mo$ule

Bus #ccess

lo

Mo$ule '

Bus #ccess

lo

Mo$ule n

Bus #ccess

lo

Bus

Controller

Bus reHuest

Bus .us%


133/253

iii. Indeendent riority method

All masters get individual bus

Mo$ule 6 Mo$ule

Mo$ule n

Bus

ControllerBus reHuest

Bus .us%

Mo$ule

'

6

6

6

6

Mo$ule Mo$ule

'

Bus

ControllerBus reHuest

'

Mo$ule

n

Busst#rt Bus reHuest

Bus reHuest

'


134/253

+ue%t"o A%er%

- #ar/ ue%t"o%

(. 8efine multirogramming@Ans

!ore than one rogram e?e*uted by one ro*essor is *alled

multirogramming

#. 8efine multiro*essor@

Ans

It is more than one ro*essor e?e*utes single Dob is *alled multiro*essor

Augmentation of *oro*essor is *alled multiro*essor.

%. Say bus *ontension@

Ans

!ore than one ro*essor shares system memory and IH: through a *ommon

system bus.

&. 8efine *losely *ouled *onfiguration@

Ans

--/ augment +ith --7 numeri* *oro*essor.

T#s:

Su. t#s:

'

Su. t#s:

Processor

executes

Processor

'executes

Out-ut


135/253

5. Say loosely *ouled *onfiguration@

Ans

It *ontains different modules.

Ea*h module may *onsist of on --/.

/. 9hat are the methods for bus *ontrolling@

i. 8aisy *haining ii. 3olling method

iii. Indeendent riority method

E%%a1 ue%t"o&

(. E?lain bus *ontention@

Ans 8ay GIG

#. E?lain *losely *ouled and loosely *ouled@

Ans 8ay GIG

O23e!t"e ue%t"o%&

(. !ore than one rogram e?e*ution by a ro*essor is *alled

i. !ultirogramming ii. !ultiro*essor

#. !ore than one ro*essor e?e*ute single Dob is *alled

i. !ultirogramming ii. !ultiro*essor

%. !ore than one ro*essor shares system memory and IH: through a *ommon system

bus

i. Bus *ontension ii. Ko su*h

&. --7 is

i. :rdinary ro*essor ii. Kumeri* *o ro*essor

Re%u4t aa41%"%

(.i #.ii %.i &.ii

If your s*ore is e=ual to & you *an go to GG


136/253

4Ko battlement in the *on*et of --7

Day 21st

In microprocessor


137/253

--7

It is a numeri* *oro*essor. The main aim is in --/ (/ bit ro*essor but --7

suort %# bit floating oint a**ura*y.

--7 suorts %# bit a**ura*y. The --7 has - register instru*tion =ueue. A *o ro*essor must

have A1U. ,en*e it *ontains floating oint arithmeti* module.

Status register and *ontrol register is also available.

Instru*tion ointer and oerand ointers are available. It has address line A8


138/253

IH: ro*essor

Transferring data +ith IH: orts

Cl:5 reister

5

'

(

)

*

+

Re

6

'

(

)

*

+

6

TAG

Instructio

n Hueue Flo#tin -oint

#rit1"

etic

St#tus re

Control

re

I Pointer

O-er#n$

-ointer

INT

AD6

AD*

BE

S6S

GTORWH

GTRWH

Bus%

Re#$

Next

Me"or

%

CPU

5''

5'( DMA

5'*

USART

5'** PPI


139/253


140/253


141/253

U"t III

I:O Iter'a!"

!emory interfa*ing and IH: interfa*ing 0 3arallel *ommuni*ation interfa*e 0 Serial

*ommuni*ation interfa*e 0 8HA and AH8 interfa*e 0 Timer 0 eyboard H dislay *ontroller 0

Interrut *ontroller 0 8!A 0 Controller 0 3rogramming and ali*ations *ase studies Traffi*

light *ontrol$ 1E8 dislay$ 1C8 dislay$ keyboard dislay interfa*e and alarm *ontroller.


142/253

4The most ne?us *on*et in mi*ro ro*essor ---

Day 22nd

In microprocessor


143/253

Me#or1 "ter'a!"

Port&

The meaning of ort is *arry. Transort is *arry a*ross in etymology. Similarly in

mi*roro*essor to IH: or memory must be interfa*ed$ for that it needs ort. Using the ort

ins +e *an transmit "or' re*eive data from --/ W to memory or IH:. So transmit and

re*eive data by the ort *ommand out "ort' and in "ort'

Fenerally the interfa*ing has the follo+ing tye demands on the me*hanism

i' Serial *ommuni*ation interfa*e

ii' 3arallel *ommuni*ation interfa*e

In memory interfa*ing +e *an read and +rite in the some memory it is a *ombination of

registers +hi*h +ere sele*ted by address. !emory is generally bifur*ated into 2A!

"2andom A**ess !emory' and 2:! "2ead only !emory'.

;or 2:! e?amle is

E32:! "Erasable 3rogrammable 2ead only !emory'

;or e?amle *onsidering the E32:!

AA(A#A%A&A5A/A7A-A6

Totally ( add ress lines ma

#(L (

Similarly (( address lines ma

#((L # ? #(L # ? ( L # E32:!

(# Address 1ines

EPROM

SCDR

Intern#lDeco$er

A

A6

O9P

Buer

Out-ut $#t#


144/253

#(#L ##? #(L & ? ( L & E32:!

Similarly 2A!

It has not only read but also +rite

CS is meant for shi sele*t

;or +rite or 2ead memory interfa*ing +e need address

8e*oding te*hni=ue

i. Absolute de*oding

ii. 1inear de*oding

i. Absolute 8e*oding

After addressing the si>e of 2A!H2:! the remaining address lines are meant for CS

"Chi sele*t'

E?

Interfa*e --/ +ith

# E32:!

( E32:!

# E32:! L #((lines A0 A(

( 2A! L #(lines A0 A6

RAM

SC

DR

Intern#lDeco$er

A

A6

O9P

Buer

In-ut $#t#

I9PBuer

R


145/253

--/

1ATC,

MOI HH

RD

RW H

8e*oder7&1S(%-

IOR

IOMR

M

A6J A

6

D6J D

7&1S(%-8e*oder

# E32:!

A6J A

6

( 2A!

A'

A

A(

A)

A*

Iter'a!" Me#or1


146/253


147/253

So address maing # E32:!

A(6........................A

......................

Starting address

(.....................(

Ending address


148/253

+ue%t"o ad A%er%

- Mar/ ue%t"o%

(. 8efine ort@

Ans

The ort meaning is *arry. 9e *an in ort through keyboard. 9e *an out ort

the rinter.

#. 9hat are the t+o *ommuni*ation interfa*e@

Ans

Serial *ommuni*ation interfa*e

3arallel *ommuni*ation interfa*e%. 9hat are the t+o tyes of memory@

Ans

2A!

2:!

&. ;or maing ( ho+ many address lines@

Ans

#(L (#& bytes L (

So A0 A6Address lines

5. ;or interfa*e the ma remains address lines is used for +hat urose@

Ans

;or maing ( ma A 0 A6L ( Address lines remains address lines are

used for de*oder to go for *hi sele*t.

/. Using de*oder for *hi sele*t +hat are the de*oding te*hni=ue@

Ans

Absolute de*oding

1inear de*oding

E%%a1 +ue%t"o%

i' E?lain +ith e?amle about memory interfa*ing of # 2:!@

Ans GGI

ii' E?lain +ith e?amle about differing de*oding te*hni=ue@

Ans GGI


149/253

O23e!t"e ue%t"o%

(. The t+o Dobs of ort is


150/253

41et us adhesive in IH: inter fa*ing.

Day 23rd

In microprocessor


151/253

IH: Interfa*ing

It is the *ommuni*ation bet+een mi*roro*essor bet+een mi*roro*essor and IH:. ;or the

inut keyboard to ort similarly ort to dislay devi*es.

;or inut

;or outut

IH: Interfa*ing te*hni=ues

It is mainly of t+o byte

i. !emory maed IH:

ii. IH: !aed IH:

kbdTr#nsl#te

.uer--/ W

--/LATC :utut


152/253

;or e?amle

IH: maed IH: only inut is

,ere for inut (/ ins +ill be given. The data in form of in goes through tri state buffer.

Address line is meant for address de*ode.

Similarly the outut me*hanism is

Re#$ Tri

slot

.uer

MIOH

DR

Deco$er

A6

A

S*

S

S6

565+ D6 J

D*


153/253

Combining Inut and :utut maed IH: is *reate

Out-ut -ort

L#tc1

Deco$er

MIO H

RW

A6

A

D6

D*

565

+


154/253

Combining Inut and :utut maed IH: is *reated

565+ - In-ut Port

Out-ut Port

A6

D6

D*

A

@6

@

Deco$er

MOI HH

W

DR

RIO

WIO


155/253

Similarly memory maed IH:

565+ In-ut Port

Out-ut

Port

S6

S*

D6

D6

@6

Deco$er

@

MOI HH

W

DR

RM

WM


156/253

+ue%t"o% ad A%er%

- Mar/ +ue%t"o%

(. 9hat is IH: interfa*ing@

It is the *ommuni*ation bet+een mi*roro*essor and Inut.

It is

!emory maed IH:

IH: maed IH:

E%%a1 ue%t"o

(. E?lain +ith e?amle memory maed IH:@

Ans GGII

#. E?lain +ith e?amle IH: maed IH:@

Ans GGII


157/253

41et us have reali>e *on*et in arallel *ommuni*ation interfa*e

Day 24th

In microprocessor


158/253

In arallel *ommuni*ation interfa*e. All the data lines *onne*ted aralelly. ;or

e?amle rogrammable eriheral interfa*e "33I' 0 -#55. And also it has named arallel ort

*hi. ,ere the me*hanism is arallel data transfer. (/ bit *onne*tion and *ommuni*ation

bet+een --/ and 33T "-#55'. The -#55A is more advan*ed than -#55.

The -#55

It has three orts. They are ort A$ 3ort B and 3ort C

3ort A$ 3ort B both are eight bits.

3ort uer & bits

3ort lo+er & bits

;rom the ort keyboard$ dislay devi*es$ and rinter is *onne*ted.

It is interfa*ing *hi but it does not have any ro*essing *aability. ;or e?amle

The in diagram has

i. 8ata Bus buffer

It has three state bi dire*tional - 0 bit buffer +hi*h is used to interfa*e the *hi to the

data bus of the system.

ii. 2ead H 9rite *ontrol logi*

8ata transfer bet +ean the *hi and the ro*essor.

iii. Frou A and Frou B *ontrols

The lo+er data line of 80 87 *onne*ted to data bus buffer. 2ead$ +rite is

*onne*ted to DORI and RWIO

1o+er eight bit address line is used for *hi sele*t other+ise (/ bit address line is

used. AA(for & searate entities.

,en*e the blo*k diagram of -#55 "3rogrammable eriheral interfa*e'

5

6

5

+

5

'

*

*

PPI

e%.o#r$

Printer

LED

Dis-l#%

Port A

Port B

Port

C

D6D


159/253

D#t# .us

.uer

Grou- A

Control

Re#$

rite

Control

LoicGrou- B

Control

Grou- A

Port A

Grou- A

Port C u--er

Grou- B

Port C lo4er

Grou- B

Port B

PA6A

PC)

PC(

PC6C

(

PB6B

(

Cs

D6D

Itera4 94o!/ D"ara# o' 8-;;


160/253

The in diagram of -#55 % 3orts L % ? - L #& 3in

8ata buffer L - lines L - in remains$ - has V**$ Fnd et*.

PA(

PA'

PA(

PA6

DR

SC

GND

A

A'

PC

PC+

PC*

PC)

PC6

PC

PC'

PC(

PB6

PB

PB'

5

'

*

*

PA)

PA*

PA+

PA*

D6

D

D'

D(

D)

D*

D+

D

>cc

PB

PB+

PB*

PB)

PB(


161/253

,en*e address de*oding and *onne*tions bet+een the --/ and the -#55

The ort sele*tion is ossible in -#55 by used 3in AA(of -#55

A( A Status

3ort A Sele*ted

( 3ort B Sele*ted

( 3ort C Sele*ted

( ( Control register

565+

5'**

DR

RW

A

A6

A'

A

D6

D

D#t#Bus

RIOW RDIO

Port A

Port B

Port C

A

A+

A*

A)A

(

A6

SEL


162/253

+ue%t"o ad A%er%

- Mar/ +ue%t"o%

(. Five e?amle arallel *ommuni*ation interfa*e@

Ans 3rogrammable eriheral interfa*e -#55#. ,o+ many orts in -#55@

Ans % 3orts

i. 3ort A

ii. 3ort B

iii. 3ort C uer

iv. 3ort C lo+er

%. 9hat is Frou A and Frou B *ontrols@

Ans The lo+er data lines of 80 87*onne*ted to data bus buffer. 2ead$ +rite

is ORI WOI

E%%a1 ue%t"o%

(. 8ra+ the blo*k diagram of -#55@

#. Interfa*e bet+een --/ and -#55@

%. 8ra+ the in diagram of -#55@

Ans GGGIII

O23e!t"e ue%t"o%

(. -#55 is

i. 3arallel ort *hi ii. Kone

#. 3ort A$ 3ort B$ 3ort C Uer number of ins are $ $

i. -$-$& ii' -$-$-

%.8ata buffer is

i. - lines ii. & lines

&. 3orts are initiali>ed by

i. C92 ii. I2

5. In orts inut is read by by C92 says e ort C.

!odes of oeration

!ode Basi* inut H :utut

!ode ( Strobed inut H outut

!ode # Bidire*tional bus

Interfa*ing (/ bits IH: orts to the -#55

T+o rogrammable eriheral interfa*e +ith (/ bit ort. (/ bit relations that --/.

D'

D+

D*

D)

D(

D'

D

D6

Port C

lo4er

Port B

Mo$e selection

6 = Mo$e 6

= Mo$e

Port C

u--er

Port A

Mo$e selection

66 = Mo$e 6

6 = Mo$e

6 = Mo$e '

= I9O

Mo$e

6 = BSR

Mo$e

J In-ut, 6 Out-ut


166/253


167/253

Muestion and Ans+ers

Essay =uestion

(. E?lain +ith e?amle about initiali>e the orts of 33I "-#55' in C92@

Ans GGGIV 8ay

#. ,o+ to interfa*e (/ bits IH: rots to -#55 "33I'@

Ans GGGIV 8ay


168/253

41et us vie+ the ragmati* *on*et of --/ interfa*ed +ith AH8

Day 26th

In microprocessor


169/253

ADC&

Analog to digital interfa*ed +ith --/ is *an be serial "or' arallel interfa*e.

Imort and ali*ation in arallel ort "33I 0 -#55 0 3rogrammable eriheral interfa*e'.

A*tually the analog signal is *onverted into digital form for further referen*e.

A8C -- H -6

3arallel interfa*ing. The advantage is

2esolution good

Total unadDusted error

Single suly

1o+ o+er

Conversion time

,en*e the blo*k diagram dra+s the oeration

This analog to digital *onversion has follo+ing in diagram IKto IK7in "- in' 8ata lines

"80 87' V**$ FK8$ et*.

5

65

+

5

'*

*

A

D

C

In-ut

Port

Control

sin#l

Control

sin#l

D6J D

An#lo

in-ut


170/253

ADC 6565 9 656

IN6

IN

IN'

IN(

IN)

IN*

IN+

IN

>re/

7re/ 78

D6

D

D'

D(

D)

D*

D+

D

Eoc

OE

R

Re#$ ALG EOC

GN

D

Cloc

:

>cc

LSB

Cloc:

R

7SC8

RD7OE8

ALE

ADDR

EOC

D6

D

START CON>ERSION

Ti"in $i#r#" /or 656 9 6565


171/253

So referring the first figure the blo*k diagram detailed by follo+s in diagram

5

65

+ 8

2

5

5

D6

D

A

A6

PC6

PC

PC

PA6

PA

PA'

PA(

PA)

PA*

PA+

PCc

A

DC

6

5

6

AL

E

SO

C

EO

C

D6

D

D'

D(

D)

D*

D+

OE

PB6

PB'

A B C

ANALOG

INPUTS

A

'A


172/253

+ue%t"o ad A%er

E%%a1 +ue%t"o%

(. Interfa*e A8C +ith --/@

Ans 8ay GGV

O23e!t"e +ue%t"o

(. -- H -6 is

i. A8C ii. 8AC


173/253

41et us robe about 8HA *onversion interfa*ed +ith --/

Day 27th

In microprocessor


174/253

DAC&

Interfa*ing digital to analog *onversion

By using -#55 the --/ is interfa*ed +ith -.

,en*e *onversion me*hanism is digital to analog. It alludes

V L 2I

I L VH2

;rom the in 8to 87

+++++++=#5/(#-/&%#(/-

(#%&5/7 DDDDDDDD

II refo

+++++++=#5/(#-/&%#(/-

(#%&5/7 DDDDDDDD

Iref

The in diagram eli*ts

6

5

6

6

>LC

IOUT'

>(

IOUT)

B

B'

B(

B)

+

conur#tion>re/

78>re/ 7)

B

B+

B*


175/253

Iref is the referen*e inut *urrent *orresonding to V ref$

8AC "-H-#'

The outut of the 8AC is *urrent +hi*h is *onverted to a voltage by the oam at the

outut. If oam is used in a differen*e *onfiguration$ both ositive and negative values may

be obtained.

8AC *onne*ted +ith -#55 is

PA6

PA

PA'

PA(

PA)

PA*

PA+

PA

6

5

6

6

D

6

D

D

'

D

(

D

)

D

*

D

+

D

*

>< >re/

*

*+

IO

Co"

->

'>

+/

GN

D

78

TO

CR

O


176/253

+ue%t"o ad A%er%

E%%a1 ue%t"o

(. E?lain interfa*e 8AC +ith --/@

Ans GGVI


177/253

4,ave an imulse *on*et about rogrammable interval ( 0 timer -#5%H5&

Day 28th

In microprocessor


178/253

The *hi -#5% is a rogrammable timer *hi used for timing ali*ation -#5& +orks

in higher fre=uen*ies. Both timer *his -#5%H5& rovide three indeendent (/ -#5& e?e*ute fre=uen*y ( !,>. There are three

indeendent *ounters *ontrolled by *ontro l register.

So

CS A( A Status

Counter 0

( Counter 0 (

( Counter 0 #

( ( Control register

So the detailed in diagram of -#5% is

The detailed fun*tional blo*k diagram of -#5% H 5&

5

'*

(

D

D

+

D

*

D

)

D

(

D

'

D

D

6

GATE6GND

>cc

A

A6

Cl: '

OUT'

GATE '

Cl:

GATE

66


179/253

Counter

Every *ounter has three ins *lk$ gate and out

D#t# Bus

Buer

Re#$ 9

rite

Loic

Control

4or$

reister

COUNTER

6

COUNTER

COUNTER

'

I

N

T

E

R

N

A

L

B

U

S

RD

R

A6

A

Cl:6G#te

6Out 6

D6D

Cl:

G#te

Out

Cl:'G#te

'Out '


180/253

i. Clk

It is measuring fre=uen*y T L (Hf

;re=uen*y of -#5% #./ !h>

-#5& ( !h>

ii. FATE

Counter in al+ays status L (

iii. :UT outut resonse in +ave from obtained

Data ad Couter $"&

8ata 8


181/253

IH: Interfa*ing is very good in inter *onne*tion -#5& interfa*ed +ith data lines and

time measurement done by % *ounters. Address lines A#to A(5is meant for *hi sele*t.

!emory !aed IH:

IH: !aed IH:

565+ 5'*)

D6J D

A6

A

RIO

IO

RD

R

Cl: 6

G#te 6

OUT 6

Cl:

G#te

OUT

Cl: '

G#te '

OUT '

SCA'

A*


182/253

IH: interfa*ing very good in inter*onne*tion. That is % *ounter. Address line A #to A(6

is for *hi sele*t.

So memory maed IH: is

565+ 5'*)

D6J D

A6

A

RM RD

R

Cl: 6

G#te 6

OUT 6

Cl:

G#te

OUT

Cl: '

G#te '

OUT '

SCA'

A

WM


183/253

E%%a1 ue%t"o&

(. a. E?lain the blo*k diagram -#5%H5&@

b. 3in diagram -#5%H5&@

*. :eration modes from C92@

d. E?lain IH: interfa*e -#5& +ith --/@

i. IH: !aed IH:

ii. !emory !aed IH:

Ans

8ay GGVII

O23e!t"e ue%t"o%

(. -#5% is

i. 3rogrammable timer *hi ii. 33I

#. -#5%H5& has

i. (/ bit ii. - bit

%. -#5% e?e*utes fre=uen*y

i. #./ !,> ii. ( !,>

&. in -#5% H 5&

i. % Counter ii. Kone

5. $ $ ins in *ounter

i. Clk$ Fate and out ii. Ko su*h

/. :eration modes from C92 in mode $ !ode ( is

i. Interrut on terminal *ounter rogrammable one shot

ii. 2ate generator$ s=uare +ave generator

7. :eration modes from *lk in mode #$ !ode % is $

i. Kil $ Kil ii. 2ate generator $ s=uare +ave generator

-. :eration modes from C92 in mode & and mode 5 i s

i. Soft+are triggered mode$ ,ard+are triggered mode

ii. Kil$ Kil.

2esult Analysis

(. i. #. i %.i &.ii 5.i /.i 7.i -.ii 6.i

If your s*ore greater than - than go to GGVIII


184/253

41et us fas*inate in the *on*et of keyboard dislay *ontroller

Day 29th

In microprocessor


185/253

8-e12oard d"%$4a1 "ter'a!e

The --/ mi*roro*essor has keyboard is the inut and dislay the outut

9hen key is ressed

So simly keyboard interfa*e is

R

Out-ut

Le0el

Loic 6

In-ut Port

'

(

)

*

+

T5

D6D


186/253


187/253

They are t+o tyes

i. Common Anode

ii. Common Cathode

9e need multile?ed dislay

9e need ort A and 3ort B

A B C D E F G

A B C D E F G


188/253

Out-ut

Port A

D

E

C

O

D

E

R

A

B

C

D

#

.

c

$

e

/

# . c $ e

/

# . c $ e

/

# . c $ e

/

# . c $ e

/

Out-ut

Port B

#

.

c

$

e

/

!!

'!

(!

)

CS

>c

c


189/253

The rogrammable keyboard dislay interfa*e -#76Rs in diagram is

Iter'a!" 8-


190/253

Interfa*ing -#76 in !emory maed IH: +ith --/

Address lines A(...A(6

They are used for *hi sele*t

5

65

+

5'

D6 J

D

A6

RM

WM

Rest

OutCl: Out

II NT

S1i/t

CNT

LRL

6

L

Dis-l#%

Lines

A

A*

CS

SL6

L


191/253

E%%a1 ue%t"o&

i. E?lain keyboard and dislay interfa*e@

ii. E?lain -#76@

iii. Interfa*ed -#76 in IH: maed IH: +ith --/@

iv. Interfa*ing -#76 in memory maed IH: +ith --/@

Ans

GGVIII

O23e!t"e ue%t"o

i. -#76

i. 33I ii. eyboard$ 8islay interfa*e

ii. In -#76 has dislay

i. % segment ii. 7 Segment

iii. 8islay are

i. Common anode$ *ommon *athode

ii. Kil$ Kil

Re%u4t Aa41%"%

(. ii #. Ii %.i


192/253

41et us trigger about interrut *ontroller.

Day 30th

In microprocessor


193/253

-#56 3rogrammable interrut *ontroller.

-#56 has eight interrut re=uest I2 0 I27. 8eends on the riority the interrut is

*alled Ke?us "inter*onne*tion' bet+een a 3TC -#56 and the --/.

A*tually the fun*tional blo*k diagram of the 3TC

,ere eight ve*tored riority interruts for the C3U. It *an *ase *ade u to /& ve*tored

riority interruts +ithout additional *ir*uitry. It is in K!:S te*hnology.

565+ 5'*

D6D

TAIN

INTR

TAIN

INT

IR6

IR

IR'

IR(

IR)

IR*

IR+

IR

5'*

D6D

DR

INT

RW

SC

.A

INTA

C#sc#$

Inter/#ce

Interru-tin-uts

IR6J IR

>cc GND

CASO J CASL

SP9CN


194/253


195/253

-#56 has - blo*ks

It has eight interrut lines I20 I27

i. IKT "Interrut'

this outut goes dire*tly to ro*ess or interrut inut and *auses the ro*essor to

send ba*k the IKTA.

ii. Interrut re=uest register "I22' and Interrut servi*e register "IS2'

IS2 to store all interrut +hi*h are re=uested servi*e$ and IS2 is used to store the

interrut levels +hi*h are servi*ed.

iii. 3riority 2esolver

riority in I22. 8uring IKTA ulse highest riority is *alled

iv. Interrut !ask 2egister "I!2'

It +ill mask the arti*ular interrut

v. CAS 0 CAS 7

Cas*ading ma?imum /& interrut ins

vi. S3HEK

Slave rogram H Enable buffer "Buffer trans*eiver'

vii. 2H9 logi*

Adetermine address of register. 28$ 92 means for read and +rite

III. Interrut se=uen*e of an --/ based system.

- ? -/ family interfa*e +ith -#56

By sele*t is ossible by I!2 among I2. The needed I2nonly sele*ted. If so many riority

+ith hel +hi*h I2 should be sele*ted.

ISR PR IRR IMR

IR6

IR


196/253

E%%a1 ue%t"o&

(. Interfa*e --/ to -#56@

#. E?lain -#56@

%. 8ra+ the blo*k diagram of -#56.

Ans

8ay GGIG

O23e!t"e t1$e%

(. -#56 is

i. 3IC ii. 33C

#. -#56 has

i. I2


197/253

4The laudable interfa*e toi* 8!A

Day 31st

In microprocessor


198/253

i. Serial Communi*ation 3rin*ile

instead of arallel *ommuni*ation +hi*h is *omli*ated is rela*ed by serial

*ommuni*ation

i. Simle? *ommuni*ation

8ata flo+s only one *onne*tion "eg 3ro*essor to 3rinter'

ii. ,alf 8ule?

Both *an *ommuni*ate but at a time only one eg "9alkie Talkie'

iii. ;ull 8ule?

Both "or' *ommuni*ate at any time "3C *ommon'

8!A "8ire*t !emory A**ess'

8ata transfer bet+een eriherals and memory is a fre=uent a*tivity in any *omuter.

8ire*t memory a**ess means the data *an be transferred bet+een eriheral and memory

+ithout the intervention of the ro*essor

This is *alled *y*le stealing

,en*e 8!A *y*le timing

CPU I9O

M

DMA

OLD

CL


199/253

(. 8!A *ontroller

The Central dogma is transferring data in one of the follo+ing *ases.

i. ;rom memory to a eriheral

ii. ;rom eriheral to memory

iii. ;rom memory to memory 8!A oeration.

OLD A

T)

Or T

DMA c%cle

A$$ress

565+ CPU

ol$ P

ol$

DMA

Controller

Me"or%

Peri-1er#l

De0ice

D#t#

Bus

D#t#

Bus

Control

Bus

D#t#

Bus

A$$ress

Bus

Control

Bus

LDA

R#

ControlBus


200/253

There must be a 8!A *ontroller to *oordinate all the a*tivities.

8!A Controller attributes

The general blo*k diagram of 8!A *ontroller

Kot only blo*k diagram says *hannel but also riority resolver.

D#t# Bus

Buer

Re#$ 9 rite

loic

Control

loic #n$

"o$e set

reister

ORIOWI

clk

&A

.

7A

A6

A(

Counter

C1#nnel

C1#nnel

C1#nnel '

C1#nnel (

Priorit%

Resol0e

DR! 6

DAC

6


201/253

-#57 interfa*ed +ith --/

IH: maed IH:

It is on IH: Interfa*e

565+

Deco$er

DR

RW

MIO H

M

MR

5'*

OLD

OLD A

Cl:

ORI

WIO

De0 6

De0

De0 '

De0 (

ORI

WIORMWM

A)

A*

SC

(6. AA

7. DD


202/253

-#57 interfa*e memory maed IH:

In IH: !aed IH: Address I:2$ I:9

In !emory !aed IH: !2$ !9

Microprocessors R2013

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