Microprocessor.ppt

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Core i5

Safia Kalwar 11CS59

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Architecture

Chipset Model: core (Ivy Bridge) DRAM controller

Code name

core Die size(nm)

Date released

Arrandale 2 32 Jan 2010

Sandy Bridge

2 32 Fab 2011

Ivy bridge 2 22 May 2012

Haswell 4 22 June 2013

Haswell 2 22 June 2013

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Ivy Bridge MicroArchtecture

IVY Bridge supports two types of microarchitectures “IVY Bridge” (dual-core 22 nm) “IVY Bridge” (quad-core 32 nm)

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Processor

•Intel Core-i5 3210 Cores: 2 Processors: 4 (logical processor) Threads per core : 2 (units) Socket: FC PGA988

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Classification of processor on basis of Flynn’s taxonomy•The four classifications defined by Flynn

are based upon the number of concurrent instruction (or control) and data streams available in the architecture

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Classifiations

•Single intruction Single Data Stream (SISD)

•Single instruction multiple data stream (SIMD)

•Multiple instruction single data stream (MISD)

•Multiple instruction multiple data steam (MISD)

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Unit 1

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Unit 2

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Unit 3

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Unit 4

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Hyper Threading Technology

•Processor contains two execution units that contain a complete set of registers capable of running softwares independently or concuently.

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Processing Speed

•Peak processing performance(PPP): 24.8GFLOPS

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Flops

In late 1996 Intel's ASCI Red was the world's first computer to achieve one TFLOP and beyond, •and “was supercomputing’s high-water

mark in longevity, price, and performance.

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Processing speed table

•s

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Multiplier

•CPU multiplier is clock ratio speed b/w FSB and CPU

•Multiplier • Unit 1: 31*• Unit 2: 29*• Unit 3: 31*• Unit 4: 31*

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Co-Processor/FPU

•Floating point unit(FPU): part of computer designed to carry out opeartions on floating point numbers.

Microprocessor Coprocessor

8086/8088 8087

80186/80188 808187

80286 80287

80386 80387

80486SX 80487SX

80586 Bilitin into processor

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Supported technologies

•MMX: (single instruction multiple data) Instruction set. • SSE: Streaming SIMD extensions• SSSE3 was first introduced with Intel

processors based on the Core microarchitecture

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Architecture

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Cachel1 cache memory

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L2 cache

L3 - cache

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Turbo Speed

•Min/max/turbo-speed : 1.2 – 2.5- 3.1

•Advantage• long lasting battery• safe from halt

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References• ^ Flynn, M. (1972). "Some Computer Organizations and Their

Effectiveness". IEEE Trans. Comput. C–21: 948.• http://answers.yahoo.com/question/index?qid=20091030204749AA1F8qW.• http://www.pcmag.com/encyclopedia_term/0,2542,t=CPU+multiplier&i=5880

8,00.asp.

• http://en.wikipedia.org/wiki/FLOPS• http://www.techterms.com/definition/sram• http://en.wikipedia.org/wiki/MMX_(instruction_set)• http://www.tomshardware.com/forum/295287-30-simple-communication-contr

oller• http://gizmodo.com/5917500/what-is-intel-turbo-boost• http://www.google.com.pk/search?q=architecture+of+core+i5&hl=en&tbm=

isch&tbo=u&source=univ&sa=X&ei=6-9dUcrlN8_jrAf_1IHoAg&ved=0CCoQsAQ&biw=1366&bih=653#hl=en&tbm=isch&sa=1&q=internal+architecture+of+core+i5+&oq=internal+architecture+of+core+i5+&gs_l=img.3...21124.22572.4.23295.12.12.0.0.0.0.186.1040.10j2.12.0...0.0...1c.1.8.img.8uTE9XUqOAk&bav=on.2,or.r_qf.&bvm=bv.44770516,d.bmk&fp=c161a788912afaf3&biw=1366&bih=653&imgrc=2gS31A3HrYTMkM%3A%3B25bKznrUmkfwyM%3Bhttp%253A%252F%252Ftechreport.com%252Fr.x%252Fcore-i5-i7%252Fdie-shot.jpg%3Bhttp%253A%252F%252Ftechreport.com%252Freview%252F17545%252Fintel-core-i5-750-and-core-i7-870-processors%3B620%3B379

• http://en.wikipedia.org/wiki/Multi-core_processor.• Book: Intel Microprocessors by Barry B.Brey

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