Microprocessor Chapter-8

8/11/2019 Microprocessor Chapter-8

1/16

1

Microprocessors

8086/8088 Hardware Specifications


2/16

2

8088 pin outs and the pin functions

The 8088 microprocessor is housed in a 40-pin DIP chip.

Power is supplied between the Vcc and the GND pins. The

voltage at Vcc should be +5V 10%.

The clock at the CLK pin provides the basic timing to the

microprocessor. The clock must have a 33% duty cycle.

The microprocessor is reset if the RESET pin is held high for

at least four clock periods.Whenever the microprocessor is

reset, it begins executing instructions at memory location

FFFF0H. The READY signal is used to insert wait states, to enable the

communication between the microprocessor and slower

memory or peripheral devices.

Interrupts are supported by the signals NMI (Non-Maskable

Interrupt), INTR (Interrupt Request) and INTA (InterruptAcknowledge).

The HOLD and HLDA (Hold Acknowledge) signals are used

to enable DMA (Direct Memory Access).

A19/S6

A18/S5

A17/S4A16/S3

A15

A8

AD7

AD0

ALE

DEN'

DT/R'

RD'WR'

IO/M'

CLK

RESET

READY

NMI

INTR

INTA'

HOLD

HLDA

MN/MX'

TEST'SS0'

Vcc

GND

8088 CPU


3/16

3


The 8088 can operate in a minimum mode (MN/MX=1) or in a

maximum mode (MN/MX=0). The maximum mode is used in

multiprocessor applications or when a math coprocessor is used.

The 8088 has a 20 bit address bus and an 8-bit data bus.

The address lines A0..A7 are multiplexed with the data lines

D0..D7 on the pins AD0..AD7.

The address lines A16..A19 are multiplexed with status lines.

If the ALE (Address Latch Enable) signal is activated (logic 1),

the AD0..AD7 pins carry the addresses A0..A7. The DEN (Data Enable) signal is used to enable the external

data bus buffers.

The DT/R (Data Transmit/Receive) signal is used to specify the

direction of the external data bus buffers.

The IO/M signal is used to select between I/O and memorydevices.

The RD and WR signals are used in the Read and Write cycles.

A19/S6

A18/S5A17/S4

A16/S3

A15

A8

AD7

AD0

ALE

DEN'

DT/R'

RD'

WR'

IO/M'

CLK

RESET

READY

NMI

INTRINTA'

HOLD

HLDA

MN/MX'

TEST'

SS0'

Vcc

GND

8088 CPU


4/16

4


Most of the 8086 pins/signals function the same way as the

8088 pins/signals.

The main differences between the 8088 and the 8086 are:

The 8086 has a 16-bit data bus.

The address lines A0..A15 are multiplexed with the data

lines D0..D15 on the pins AD0..AD15.

The BHE (Bus High Enable) signal is used to enable the

most significant data bus bits (D8 ..D15) during a read or

write operation.

The IO/M signal is inverted in the 8086 microprocessor,

that is a memory is enabled if the IO/M is high, while an

I/O device is enabled if the IO/M signal is low.

A19/S6

A18/S5A17/S4

A16/S3

AD15

AD0

ALE

DEN'

DT/R'

RD'

WR'

IO'/M

CLK

RESET

READY

NMI

INTRINTA'

HOLD

HLDA

MN/MX'

TEST'

BHE'

Vcc

GND

8086 CPU


5/16 5

Clock/Reset/Ready Circuit

The 8284 chips serves three

purposes:

Generates the main clock

(CLK) for the processor

(fc/3 with 33% duty cycle)

and the clock for the

peripheral devices (fc/5).

Provides the Reset pulse

according to the state of theRC circuit connected at the

RES input.

Provides the Ready signal to

insert wait states whenever

the processor is accessing

slow memory or peripheral

I/O ports.

100

10K

10uF

+5V

15MHz

On/Off

Reset

8284

X1

X2

RES RESET

CLK

PCLK

OSC

READY

RDY

Wait State Circuit

15MHz

5MHz

3MHz

READY

RESET

CLK

8086/8088


6/16 6

Operation of the Reset Circuit

Initially the capacitor is uncharged. When power is switched on, the Reset signal is atlogic 1. The capacitor starts charging with time constant (10K*10uF). When the voltageacross the capacitor becomes equal to the minimum High voltage of the 8284 (2V), theReset signal goes to logic 0.

If the Reset button is pressed, the capacitor is discharged through the switch. When the

Button is released, the capacitor starts charging as before. Resistor R1 is used to reduce the current through C1 when the Reset button is pressed,

thus avoid damaging C1. The diode is used to short circuit R1 during switch off, thusdischarge C1 fast.

R2:100

R1

10K

C1

10uF

+5V

On/Off

Reset

VRES

VRES

Reset

Switch ON Reset Button Pressed Reset Button Released Switch OFF


7/16 7

DC Characteristics and Fan Out

It is essential to examine the DCcharacteristics of any devices involved in amicroprocessor design, before connectinganything on the microprocessors pins.

Failure to do so might result in malfunctionsor even damages on some components.

Fan-Out of a device is the maximum numberof similar devices that can be connected onthe output of that device without anyproblems.

The Fan-Out is limited by the current sink ofthe device (Fan-Out = IOLmax/IILmax)

For example the IOLmax of the 8088 is 2

mA and the IILmax of the 74LS family is

0.4 mA. Thus the fan out is 2.0/0.4 = 5.

The Fan-Out is also limited by the noise

immunity (VILmax- VOLmax) . The noiseimmunity of the 8088 is 0.8-0.45=0.35V.This reduces the maximum fan out to 10.

Input Characteristics of the 8086/8088

Logic Voltage Current

0

1

VILmax

= 0.8 V

VIHmin

= 2.0 V

IILmax

= 10 uA

IIHmax

= 10 uA

Output Characteristics of the 8086/8088

Logic Voltage Current

0

1

VOLmax

= 0.45 V

VOHmin

= 2.4 V

IOLmax

= 2.0 mA

IOHmax

= -400 uA

Recommended Fan-Out of the 8086/8088

Family ISINK

Fan-Out

TTL (74)

TTL (74LS)

-1.6 mA

ISOURCE

TTL (74ALS)

TTL (74F)

CMOS (74HC)

CMOS (CD4)

NMOS

-0.4 mA

-0.1 mA

-0.5 mA

-10 uA

-10 uA

-10 uA

40 uA

20 uA

20 uA

25 uA

10 uA

10 uA

10 uA

1

5

10

10

10

10

10


8/16 8

Bus Demultiplexing

The processor loads on the address bus (AD0 to AD7 and A8 to A19) the address to be used, andsets the ALE. Thus the address signals A0 to A7 are latched on the 74LS373.

On the next clock the processor resets the ALE and the AD0 to AD7 lines are used to carry data(D0 to D7). The DEN enables the buffers of the 74LS245, while the DT/R specifies the direction

(read/write)

CLK

A8..A15

AD0..AD7

ALE

RD'

DT/R'

DEN'

Float

Read Data

A8..A15

A0..A7 D0..D7

Timing Diagram for a Memory Read Cycle

A7A6A5A4A3A2A1A0

D7D6D5D4

D3D2D1D0

AD7AD6AD5AD4AD3AD2AD1AD0

ALE

DEN'DT/R'

8088CPU

LS373

D Q

EN

EN OE

LS245

GDIR


9/169

Bus Buffering

The 74LS373 and the 74LS245 are used to demultiplex the AD0 to AD7 lines. They also providethe necessary buffering for the A0 to A7 and the D0 to D7 lines.

The rest of the address lines (A8 to A15) as well as control lines (RD, WR, and IO/M) need to bebuffered using the 74LS244 octal buffer.

A15A14A13A12A11A10A9A8

A15A14A13A12A11A10

A9A8

8088CPU

LS244

E2E1

4

4

RDWR

IO/M'

LS244

E2E1

4

4

RDWRIO/M'


10/1610

A fully buffered/demultiplexed 8088 system

A19/S6A18/S5A17/S4

A16/S3

A15A14A13A12A11A10A9

A8

AD7AD6AD5

AD4

AD3AD2AD1AD0

ALE

DEN'

DT/R'

RD'

WR'IO/M'

CLK

RESET

READY

NMI

INTR

INTA'

HOLD

HLDA

MN/MX'

TEST'SS0'

Vcc

GND

8088 CPU

100

10K

10uF

+5V

15MHz

On/Off

Reset

15MHz

5MHz

3MHz

D0 . . D7

A0 . .A7

A8 . . A15

A16 . . A19

8284

X1

X2

RES

RESET

CLK

PCLK

OSC

READY

RDY1

LS373

D Q

EN

EN OE

x8

LS373

D Q

EN

EN OE

x8

LS245

GDIR

x8

RD, WR, IO/M

CS from memory devices

RDY2

AEN1

0w

1w

2w

3w

4w

5w

6w7w

Q0

Q1

Q3

Q4

Q5

Q6

Q7

Q2

CLK

CLR SI

LS164 (Shift Reg.)

'1'

LS244

E2E1

4

4

LS244

E2E1

4

4


11/1611

A fully buffered/demultiplexed 8086 system

D0..D7

A0..A7

A8..A15

A16..A19

LS373

D

Q

EN

EN

OE

x8

LS373

D

Q

EN

EN

OE

x8

LS245

G

DIR

x8

RD,WR,IO/M

LS244

E2

E1

44

A19/S6

A18/S5

A17/S4

A16/S3

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

ALE

DEN'

DT/R'

RD'

WR'

IO'/M

CLK

RESET

READY

NM

I

INT

R

INT

A'

HO

LD

HLDA

MN

/MX'

TEST'

SS0'

Vcc

GN

D8086CPU

LS373

D

Q

EN

EN

OE

x8

LS245

G

DIR

x8

D8..D15

The main difference with the 8086 processor is that it has a 16-bit data bus multiplexed with the16 lower address lines.

Thus the 16-bit data bus (AD0 to AD7 and AD8 to AD15) must be demultiplexed.

BASIC BUS OPERATION


12/16

12

BASIC BUS OPERATION

The 8086/88 processors use the memory and I/O in periods called bus cycles

Each bus cycle equals four system-clocking periods (T1-T4)

For a 5 MHz clock, one bus cycle lasts 800 ns

SIMPLIFIED 8086/88 WRITE BUS CYCLE


13/16

13

SIMPLIFIED 8086/88 WRITE BUS CYCLE

During the first clocking period (T1), the address is sent to the address and address/data

connections, and the ALE, DT/R and IO/Mor M/signals are also output

During T2 the WR, DENare asserted, and data appear on the bus

In T4 all bus signals are deactivated in preparation for the next bus cycle, and the WR

signal returns to logic 1.

ADDRESS/DATA

WR

SIMPLIFIED 8086/88 READ BUS CYCLE


14/16

14

SIMPLIFIED 8086/88 READ BUS CYCLE

1 2 3 4 5 6

VALID ADDRESS

ADDRESS DATA FROM MEMORY

Clock

ADDRESS

ADDRESS/DATA

RD

ONE BUS CYCLE

During the first clocking period (T1), the address is sent to the address and address/data

connections, and the ALE, DT/R and IO/Mor M/signals are also output

During T2 the RD, DENare asserted

In T3 the READY signal is sampled and if low, T3 becomes a wait state, to allow time to the

memory to access data

The bus is sampled at the end of T3

Finally, the RDsignal is deactivated

THE READY SIGNAL AND WAIT STATES


15/16

15

THE READY SIGNAL AND WAIT STATES

A wait state(Tw) is an extra clocking period, inserted between T2 and T3, to lengthen the

bus cycle, allowing slower memory and I/O components to respond.

The READY input is sampled at the end of T2, and again, if necessary in the middle of

Tw. If READY is 0 then a Tw is inserted.

At the end of T2 is sampled on the falling clock edge, while in the middle of Tw, it is

sampled on the rising clock edge.

1 2 3 4

Clock

READY

Tw

Wait state generator circuit


16/16

16

Wait state generator circuit

Wait states are extra clock pulsespulses inserted when the processor isaccessing slow memory or I/O

devices. The 8088/8086 allow approximately

3 clock pulses for a memory read ormemory write. If the access time ofthe memory (including the delaysinserted by the bus buffers andaddress decoders) is longer than theaccess time of the processor (3/f)then wait states are needed.

The circuit shown adds 1 wait statein each memory read or write cycle.The number of wait states can bechanged by changing the position ofthe jumper on the outputs of the74LS164 shift register.

0w

1w

2w

3w

4w

5w

6w

7w

Q0

Q1

Q3

Q4

Q5

Q6

Q7

Q2

CLK

CLRSI

LS164 (Shift Reg.)

Ready

Ready

8088

8086

CLK

CLK

RDY1

AEN1

RDY2

RD'

WR'INTA'

'1'

CS from memory devices

8284

Microprocessor Chapter-8

Documents