MICROPROCESSOR BASED SYSTEM DESIGN

MICROPROCESSOR BASED MICROPROCESSOR BASED SYSTEM DESIGNSYSTEM DESIGN

BYBY

PROF. DR. B. S. PROF. DR. B. S. CHOWDHRYCHOWDHRY

PROF. DR. WAJIHA SHAHPROF. DR. WAJIHA SHAH

Lecture # 09 - Lecture # 09 - 10 10

Memory Address Space & Data Memory Address Space & Data OrganizationOrganization

How information such as numbers, How information such as numbers, characters & instruction: are characters & instruction: are stored in Memory?stored in Memory?

8088 microcomputer supports 1M 8088 microcomputer supports 1M memory.memory.

Memory space organized as bytes Memory space organized as bytes of data stored at consecutive of data stored at consecutive address over address range address over address range 00000000001616 to FFFFF to FFFFF16. 16.

Memory in 8088-based Memory in 8088-based microcomputer is actually microcomputer is actually organized as 8-bit bytes, not a 16-organized as 8-bit bytes, not a 16-bit words.bit words.

Memory Address Space & Data Memory Address Space & Data Organization (Cont..)Organization (Cont..)

However, 8088 can access any two However, 8088 can access any two consecutive bytes of as a word of consecutive bytes of as a word of data.data.

The The lower-address bytelower-address byte is the is the Least Significant byte of the word Least Significant byte of the word and the and the higher addressed bytehigher addressed byte is is Most Significant byte of the word. Most Significant byte of the word.

Memory Address Space & Data Memory Address Space & Data Organization (Cont..)Organization (Cont..)

Fig. Storing a word of data in Fig. Storing a word of data in memorymemory

These two bytes represent the wordThese two bytes represent the word

01010101 0101 00000010 0101 0000001022 = 5502 = 55021616

Data formats of 8088 are:Data formats of 8088 are: - bytes (8-bit)- bytes (8-bit) - word (16-bit)- word (16-bit) - double word (32-- double word (32-

bit).bit).

The 8088 MP can directly process data The 8088 MP can directly process data expressed in number of different types:expressed in number of different types:

Unsigned integer numberUnsigned integer number Signed integer number.Signed integer number.

Each integer can be either byte wide or Each integer can be either byte wide or word wide:word wide:

Unsigned byte integer number (0 to Unsigned byte integer number (0 to 255)255)

Signed bytes integer number (-128 to Signed bytes integer number (-128 to +127)+127)

Unsigned word integer number (0 to Unsigned word integer number (0 to 65435)65435)

Signed word integer number (-32768 Signed word integer number (-32768 to +32767)to +32767)

ASCII numbers are stored one number ASCII numbers are stored one number byte.byte.

Generation a Memory Generation a Memory AddressAddress

A logical address in the 8088 system is A logical address in the 8088 system is described by a described by a SEGMENT & OFFSETSEGMENT & OFFSET..

Both the segment & offset are 16-bit size.Both the segment & offset are 16-bit size. This is because all registers and memory This is because all registers and memory

locations are 16-bits long.locations are 16-bits long. However, the However, the PHYSICAL ADDRESSESPHYSICAL ADDRESSES that that

are used to access memory are 20-bits in are used to access memory are 20-bits in length.length.

Addresses are expressed in one of two Addresses are expressed in one of two hexadecimal formats:hexadecimal formats:- A 32-bit - A 32-bit Segment-offsetSegment-offset address, which address, which combines a combines a base locationbase location (Segment) with (Segment) with an an OffsetOffset to represent an actual location. to represent an actual location.

e.g. 08F1: 0100.e.g. 08F1: 0100.

Generation a Memory Address Generation a Memory Address (Cont..)(Cont..)

A 20-bit Absolute address, which refers to an exact A 20-bit Absolute address, which refers to an exact memory location. e.g. 09010memory location. e.g. 090101616

To illustrate, let us start with a hypothetical To illustrate, let us start with a hypothetical segment-offset address of 08F1: 0100.segment-offset address of 08F1: 0100.

The CPU automatically converts this to a 20-bit The CPU automatically converts this to a 20-bit absolute address by adding the absolute address by adding the segmentsegment and and offsetoffset together. together.

The segment value is always understood to have 4 The segment value is always understood to have 4 implied zeroimplied zero bits to the right. bits to the right.

Therefore, a segment address of 08F1 h really Therefore, a segment address of 08F1 h really represents an absolute location of: represents an absolute location of: 08F10 h:08F10 h:

00 88 FF 1 (0) 4 implied 1 (0) 4 implied bitsbits

00000000 1000 1000 1111 1111 0001 0001 0000 0000

The MPU then adds the offset to the The MPU then adds the offset to the segment, yielding the segment, yielding the absolute addressabsolute address::

Segment valueSegment value 0 8 F 1 (0)0 8 F 1 (0)Add the offsetAdd the offset 0 1 0 0 0 1 0 0

________________________

0 9 0 1 00 9 0 1 0 Advantage: Program can access large Advantage: Program can access large

memory by setting the current segment memory by setting the current segment address to a new block of memory.address to a new block of memory.

The generation of physical address involves The generation of physical address involves combining a 16-bit offset value that is combining a 16-bit offset value that is located in a located in a Base Pointer (BP)Base Pointer (BP), , Index Index RegistersRegisters, (SI or DI) or a , (SI or DI) or a Instruction Instruction Pointer Register (IPPointer Register (IP), and a 16-bit base ), and a 16-bit base value that is located in one of the value that is located in one of the Segment Segment RegistersRegisters (CS, SS, DS, ES). (CS, SS, DS, ES).

For example, when an instruction acquisition For example, when an instruction acquisition takes place, the source of the takes place, the source of the base base addressaddress is always CS register & the source is always CS register & the source of the offset is always the IP. The of the offset is always the IP. The physical physical addressaddress can be denoted as CS: IP. can be denoted as CS: IP.

On the other hand, if the value of a variable On the other hand, if the value of a variable is being written to memory during execution is being written to memory during execution of an instruction, typically, the of an instruction, typically, the base base addressaddress will be in DS register, and the will be in DS register, and the offsetoffset will be in DS register. The will be in DS register. The physical physical addressaddress can be denoted as DS: DI. can be denoted as DS: DI.

Another example is the stack address that is Another example is the stack address that is needed when pushing parameters onto the needed when pushing parameters onto the stack. This address is formed from the stack. This address is formed from the contents of the (SS & SP).contents of the (SS & SP).

Problems:Problems: What would be the offset requires to map What would be the offset requires to map to physical location 002C3to physical location 002C31616 it the segment base it the segment base address is 002Aaddress is 002A1616??

Solutions:Solutions: The offset value can be obtained by The offset value can be obtained by shifting the segment base address left 4-bit and than shifting the segment base address left 4-bit and than subtracting it from subtracting it from physical addressphysical address..

Shifting left 4-bit gives:Shifting left 4-bit gives:002A0002A01616

Now, subtracting, we get the value of the Now, subtracting, we get the value of the offsetoffset..

0 0 2 C 30 0 2 C 3 - 0 0 2 A 0- 0 0 2 A 0

0 0 2 30 0 2 31616

Note: (1) This address calculation is automatically done Note: (1) This address calculation is automatically done within 8088 each time a memory access in within 8088 each time a memory access in initiated. initiated.

(2) Segment register are user accessible. This (2) Segment register are user accessible. This means that the programmer can change the value means that the programmer can change the value they hold through software.they hold through software.

The programming model of the 8086 The programming model of the 8086 through the Pentium Pro Processor is through the Pentium Pro Processor is considered PROGRAM VISIBLE because its considered PROGRAM VISIBLE because its registers are used during programming registers are used during programming and are specified by the instructions.and are specified by the instructions.

The 8086, 8088, and 80286 The 8086, 8088, and 80286 microprocessors contain 16-bit internal microprocessors contain 16-bit internal architectures.architectures.

The 80386, 80486, Pentium and Pentium The 80386, 80486, Pentium and Pentium Pro microprocessors contain full 32-bit Pro microprocessors contain full 32-bit internal architectures.internal architectures.

The PIII, PIV has got 64/128 bit internal The PIII, PIV has got 64/128 bit internal architectures (Data bus 64-bit only).architectures (Data bus 64-bit only).

The architectures of the earlier 8086 The architectures of the earlier 8086 through the 8086 are through the 8086 are full upward full upward compatiblecompatible to the 80386 through Pentium to the 80386 through Pentium Processors.Processors.

The extended 32-bit registers are lebled The extended 32-bit registers are lebled EAX, 1 BX, ECX, EDX, ESP, EBP, EDI, ESI, EAX, 1 BX, ECX, EDX, ESP, EBP, EDI, ESI, EIP, and EFLAGS.EIP, and EFLAGS.

FS, GS are also available on 80386 and FS, GS are also available on 80386 and above. The FS and GS are above. The FS and GS are supplemental supplemental segment registerssegment registers to allow two additional to allow two additional memory segment for accessmemory segment for access by programs. by programs.

Example:Example: Design an interface for heating Design an interface for heating control system of TPS based 8-bit control system of TPS based 8-bit microprocessor.microprocessor.

Choose a suitable memory allocation to Choose a suitable memory allocation to minimize the input and output address minimize the input and output address decoding for an application requiring a decoding for an application requiring a program of 4kpytes plus 2 input and output program of 4kpytes plus 2 input and output ports.ports.

Solution:Solution:• Program memory = 4kProgram memory = 4k• Can be stored in the bottom 32k Can be stored in the bottom 32k A15 = 0 RAM is selectedA15 = 0 RAM is selected = 1 I/O is selected. = 1 I/O is selected.

Address Decoder: Minimal Address Decoder: Minimal Address DecodingAddress Decoding

Address decoder is needed for both the input and Address decoder is needed for both the input and output output interface, to ensure that the interface interface, to ensure that the interface appears on the data bus only for one specific appears on the data bus only for one specific memory location otherwise memory location otherwise memory memory contentioncontention could occur between data and could occur between data and program memory & input and output ports.program memory & input and output ports.

Logic circuitry is needed to select one unique Logic circuitry is needed to select one unique memory location from a 64k bytes address memory location from a 64k bytes address space.space.

In a memory mapped input computer, this In a memory mapped input computer, this circuitry can be reduced by circuitry can be reduced by minimal minimal address decodingaddress decoding that means in a typical that means in a typical dedicated microprocessor application only a dedicated microprocessor application only a small part of the complete address space is small part of the complete address space is used.used.

A0-A1 are decoded to select one of 4 interfaces.A0-A1 are decoded to select one of 4 interfaces.

A2 to A14 are not connected to I/O Interfaces.A2 to A14 are not connected to I/O Interfaces. The I/O interface thus appears at the The I/O interface thus appears at the

addresses:addresses: $8000 $8001, $8002, $8003$8000 $8001, $8002, $8003 and replicated at,and replicated at, $8004, $8005 $8006, $8007 ………$8004, $8005 $8006, $8007 ……… $FFFC, $FFFD, $FFFE, $FFFF$FFFC, $FFFD, $FFFE, $FFFF

Comment: The solution is not Comment: The solution is not uniqueunique

I/O port addresses could equally be reversed.I/O port addresses could equally be reversed. Three address lines need to be decoded rather Three address lines need to be decoded rather

than all 16.than all 16. This is called minimal This is called minimal address decodingaddress decoding..