A microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique. The microprocessor is capable of performing various computing functions and making decisions to change the sequence of program execution. In large computers, a CPU performs these computing functions. The Microprocessor resembles a CPU exactly. The microprocessor is in many ways similar to the CPU, but includes all the logic circuitry including the control unit, on one chip. The microprocessor can be divided into three segments for the sake of clarity. – They are: arithmetic/logic unit (ALU), register array, and control unit. A comparison between a microprocessor, and a computer is shown below: Arithmetic/Logic Unit: This is the area of the microprocessor where various computing functions are performed on data. The ALU unit performs such arithmetic operations as addition and subtraction, and such logic operations as AND, OR, and exclusive OR. Register Array: This area of the microprocessor consists of various registers identified by letters such as B, C, D, E, H, and L. These registers are primarily used to store data temporarily during the execution of a program and are accessible to the user through instructions. Control Unit: The control unit provides the necessary timing and control signals to all the operations in the microcomputer. It controls the flow of data between the microprocessor and memory and peripherals. Memory: Memory stores such binary information as instructions and data, and provides that information to the microprocessor whenever necessary. To execute programs, the microprocessor reads instructions and data from memory and performs the computing operations in its ALU section. Results are either transferred to the output section for display or stored in memory for later use. Read-Only memory (ROM) and Read/Write memory (R/WM), popularly known as Random- Access memory (RAM). 1. The ROM is used to store programs that do not need alterations. The monitor program of a single-board microcomputer is generally stored in the ROM. This program interprets the information entered through a keyboard and provides equivalent binary digits to the microprocessor. Programs stored in the ROM can only be read; they cannot be altered. 2. The Read/Write memory (RIWM) is also known as user memory It is used to
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
A microprocessor is a clock-driven semiconductor device consisting of electronic logic
circuits manufactured by using either a large-scale integration (LSI) or very-large-scale
integration (VLSI) technique.
The microprocessor is capable of performing various computing functions and making
decisions to change the sequence of program execution.
In large computers, a CPU performs these computing functions. The Microprocessor
resembles a CPU exactly.
The microprocessor is in many ways similar to the CPU, but includes all the logic
circuitry including the control unit, on one chip.
The microprocessor can be divided into three segments for the sake of clarity. – They are:
arithmetic/logic unit (ALU), register array, and control unit.
A comparison between a microprocessor, and a computer is shown below:
Arithmetic/Logic Unit: This is the area of the microprocessor where various computing
functions are performed on data. The ALU unit performs such arithmetic operations as
addition and subtraction, and such logic operations as AND, OR, and exclusive OR.
Register Array: This area of the microprocessor consists of various registers identified
by letters such as B, C, D, E, H, and L. These registers are primarily used to store data
temporarily during the execution of a program and are accessible to the user through
instructions.
Control Unit: The control unit provides the necessary timing and control signals to all
the operations in the microcomputer. It controls the flow of data between the
microprocessor and memory and peripherals.
Memory: Memory stores such binary information as instructions and data, and provides
that information to the microprocessor whenever necessary. To execute programs, the
microprocessor reads instructions and data from memory and performs the computing
operations in its ALU section. Results are either transferred to the output section for
display or stored in memory for later use. Read-Only memory (ROM) and Read/Write
memory (R/WM), popularly known as Random- Access memory (RAM).
1. The ROM is used to store programs that do not need alterations. The monitor
program of a single-board microcomputer is generally stored in the ROM. This
program interprets the information entered through a keyboard and provides
equivalent binary digits to the microprocessor. Programs stored in the ROM can
only be read; they cannot be altered.
2. The Read/Write memory (RIWM) is also known as user memory It is used to
store user programs and data. In single-board microcomputers, the monitor
program monitors the Hex keys and stores those instructions and data in the R/W
memory. The information stored in this memory can be easily read and altered.
I/O (Input/Output): It communicates with the outside world. I/O includes two types of
devices: input and output; these I/O devices are also known as peripherals.
System Bus: The system bus is a communication path between the microprocessor and
peripherals: it is nothing but a group of wires to carry bits.
Microprocessor is a multi-use device which finds applications in almost all the fields. Here is
some sample applications given in variety of fields.
Electronics:
Digital clocks & Watches
Mobile phones
Measuring Meters
Mechanical:
Automobiles
Lathes
All remote machines
Electrical:
Motors
Lighting controls
Power stations
Medical:
Patient monitoring
Most of the Medical equipments
Data loggers
Computer:
All computer accessories
Laptops & Modems
Scanners & Printers
Domestic:
Microwave Ovens
Television/CD/DVD players
Washing Machines
ARCHITECHTURE or FUNCTIONAL BLOCK DIAGRAM OF 8085
The functional block diagram or architecture of 8085 Microprocessor is very important as it gives the
complete details about a Microprocessor. Fig. shows the Block diagram of a Microprocessor.
8085 Bus Structure:
Address Bus:
The address bus is a group of 16 lines generally identified as A0 to A15.
The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral
devices.
The MPU uses the address bus to perform the first function: identifying a peripheral or a
memory location.
Data Bus:
The data bus is a group of eight lines used for data flow.
These lines are bi-directional - data flow in both directions between the MPU and
memory and peripheral devices.
The MPU uses the data bus to perform the second function: transferring binary
information.
The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 =
256 numbers).
The largest number that can appear on the data bus is 11111111.
Control Bus:
The control bus carries synchronization signals and providing timing signals.
The MPU generates specific control signals for every operation it performs. These signals
are used to identify a device type with which the MPU wants to communicate.
Registers of 8085:
The 8085 have six general-purpose registers to store 8-bit data during program
execution.
These registers are identified as B, C, D, E, H, and L.
They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.
Accumulator (A):
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
This register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator.
Flags:
The ALU includes five flip-flops that are set or reset according to the result of an
operation.
The microprocessor uses the flags for testing the data conditions.
They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.
The most commonly used flags are Sign, Zero, and Carry.
The bit position for the flags in flag register is,
1.Sign Flag (S):
After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign
flag is set. Otherwise it is reset.
2.Zero Flag (z):
If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it
is reset.
3.Auxiliary Carry Flag (AC):
If D3 generates any carry when doing any arithmetic and logical operation, this flag is
set. Otherwise it is reset.
4.Parity Flag (P):
If the result of arithmetic and logical operation contains even number of 1's then this
flag will be set and if it is odd number of 1's it will be reset.
5.Carry Flag (CY):
If any arithmetic and logical operation result any carry then carry flag is set otherwise
it is reset.
Arithmetic and Logic Unit (ALU):
It is used to perform the arithmetic operations like addition, subtraction, multiplication,
division, increment and decrement and logical operations like AND, OR and EX-OR.
It receives the data from accumulator and registers.
According to the result it set or reset the flags.
Program Counter (PC):
This 16-bit register sequencing the execution of instructions.
It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
The function of the program counter is to point to the memory address of the next
instruction to be executed.
When an opcode is being fetched, the program counter is incremented by one to
point to the next memory location.
Stack Pointer (Sp):
The stack pointer is also a 16-bit register used as a memory pointer.
It points to a memory location in R/W memory, called the stack.
The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).
Temporary Register: It is used to hold the data during the arithmetic and logical operations.
Instruction Register: When an instruction is fetched from the memory, it is loaded in
the instruction register.
Instruction Decoder: It gets the instruction from the instruction register and decodes the
instruction. It identifies the instruction to be performed.
Serial I/O Control: It has two control signals named SID and SOD for serial data transmission.
Timing and Control unit:
It has three control signals ALE, RD (Active low) and WR (Active low) and three status
signals IO/M(Active low), S0 and S1.
ALE is used for provide control signal to synchronize the components of microprocessor
and timing for instruction to perform the operation.
RD (Active low) and WR (Active low) are used to indicate whether the operation is
reading the data from memory or writing the data into memory respectively.
IO/M(Active low) is used to indicate whether the operation is belongs to the memory or
peripherals.
If,
Interrupt Control Unit:
It receives hardware interrupt signals and sends an acknowledgement for receiving the
interrupt signal.
PIN DIAGRAM AND PIN DESCRIPTION OF 8085
The microprocessor is a clock-driven semiconductor device consisting of electronic logic
circuits manufactured by using either a large-scale integration (LSI) or very-large-scale
integration (VLSI) technique.
The microprocessor is capable of performing various computing functions and making
decisions to change the sequence of program execution.
In large computers, a CPU implemented on one or more circuit boards performs these
computing functions.
The microprocessor is in many ways similar to the CPU, but includes the logic circuitry,
including the control unit, on one chip.
The microprocessor can be divided into three segments for the sake clarity,
arithmetic/logic unit (ALU), register array, and control unit.
8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports
1. Power supply and Clock frequency signals:
Vcc + 5 volt power supply
Vss Ground
X1, X2 : Crystal or R/C network or LC network connections to set the frequency of
internal clock generator.
The frequency is internally divided by two. Since the basic operating timing frequency is
3 MHz, a 6 MHz crystal is connected externally.
CLK (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.
2. Address Bus:
A8 - A15 (output; 3-state)
It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address;
3. Multiplexed Address / Data Bus:
AD0 - AD7 (input/output; 3-state)
These multiplexed set of lines used to carry the lower order 8 bit address as well as data
bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the lower
order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
The CPU may read or write out data through these lines.
4. Control and Status signals:
ALE (output) - Address Latch Enable.
This signal helps to capture the lower order address presented on the multiplexed address
/ data bus.
RD (output 3-state, active low) - Read memory or IO device.
This indicates that the selected memory location or I/O device is to be read and that the
data bus is ready for accepting data from the memory or I/O device.
WR (output 3-state, active low) - Write memory or IO device.
This indicates that the data on the data bus is to be written into the selected memory
location or I/O device.
IO/M (output) - Select memory or an IO device.
This status signal indicates that the read / write operation relates to whether the memory
or I/O device.
It goes high to indicate an I/O operation.
It goes low for memory operations.
5. Status Signals:
It is used to know the type of current operation of the microprocessor.
6. Interrupts and Externally initiated operations:
They are the signals initiated by an external device to request the microprocessor to do a
particular task or work.
There are five hardware interrupts called,
On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active
low INTA (Interrupt Acknowledge) signal.
Reset In (input, active low)
This signal is used to reset the microprocessor.
The program counter inside the microprocessor is set to zero.
The buses are tri-stated.
Reset Out (Output)
It indicates CPU is being reset.
Used to reset all the connected devices when the microprocessor is reset.
7. Direct Memory Access (DMA):
Tri state devices:
3 output states are high & low states and additionally a high impedance state.
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is
1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters
into a high impedance state.
Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.
For both high and low states, the output Q draws a current from the input of the OR gate.
When E is low, Q enters a high impedance state; high impedance means it is electrically
isolated from the OR gate's input, though it is physically connected. Therefore, it does not
draw any current from the OR gate's input.
When 2 or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except the
one that is communicating at a given instant.
The CPU controls the data transfer operation between memory and I/O device. Direct
Memory Access operation is used for large volume data transfer between memory and an
I/O device directly.
The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the
control of the buses. After the HLDA signal the DMA controller starts the direct transfer
of data.
READY (input)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to handle
further data or control signal from CPU.
The processor sets the READY signal after completing the present job to access the data.
The microprocessor enters into WAIT state while the READY pin is disabled.
8. Single Bit Serial I/O ports:
SID (input) - Serial input data line
SOD (output) - Serial output data line
These signals are used for serial communication.
TIMING DIAGRAM
Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.
Instruction Cycle: The time required to execute an instruction is called instruction cycle.
Machine Cycle: The time required to access the memory or input/output devices is called machine cycle.
T-State:
The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as T-state.
MACHINE CYCLES OF 8085:
The 8085 microprocessor has 5 (seven) basic machine cycles. They are
1. Opcode fetch cycle (4T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
Each instruction of the 8085 processor consists of one to five machine cycles, i.e.,
when the 8085 processor executes an instruction, it will execute some of the machine
cycles in a specific order.
The processor takes a definite time to execute the machine cycles. The time taken by
the processor to execute a machine cycle is expressed in T-states.
One T-state is equal to the time period of the internal clock signal of the processor.
The T-state starts at the falling edge of a clock.
Opcode fetch machine cycle of 8085 :
Each instruction of the processor has one byte opcode.
The opcodes are stored in memory. So, the processor executes the opcode fetch
machine cycle to fetch the opcode from memory.
Hence, every instruction starts with opcode fetch machine cycle.
The time taken by the processor to execute the opcode fetch cycle is 4T.
In this time, the first, 3 T-states are used for fetching the opcode from memory and
the remaining T-states are used for internal operations by the processor.
Fig - Timing Diagram for Opcode Fetch Machine Cycle
Memory Read Machine Cycle of 8085:
The memory read machine cycle is executed by the processor to read a data byte
from memory.
The processor takes 3T states to execute this cycle.
The instructions which have more than one byte word size will use the machine
cycle after the opcode fetch machine cycle.
Fig - Timing Diagram for Memory Read Machine Cycle
Memory Write Machine Cycle of 8085:
The memory write machine cycle is executed by the processor to write a data byte in
a memory location.
The processor takes, 3T states to execute this machine cycle.
Fig - Timing Diagram for Memory Write Machine Cycle
I/O Read Cycle of 8085:
The I/O Read cycle is executed by the processor to read a data byte from I/O port or
from the peripheral, which is I/O, mapped in the system.
The processor takes 3T states to execute this machine cycle.
The IN instruction uses this machine cycle during the execution.
Fig - Timing Diagram for I/O Read Machine Cycle
I/O Write Cycle of 8085:
The I/O write machine cycle is executed by the processor to write a data byte in the
I/O port or to a peripheral, which is I/O, mapped in the system.
The processor takes, 3T states to execute this machine cycle.
Fig - Timing Diagram for I/O Write Machine Cycle
The 8085 instructions consist of one to five machine cycles.
Actually the execution of an instruction is the execution of the machine cycles of that
instruction in the predefined order.
The timing diagram of an instruction ate obtained by drawing the timing diagrams
of the machine cycles of that instruction, one by one in the order of execution.
Timing diagram for STA 526AH.
STA means Store Accumulator -The contents of the accumulator is stored in the
specified address(526A).
The opcode of the STA instruction is said to be 32H. It is fetched from the memory
41FFH(see fig). - OF machine cycle
Then the lower order memory address is read(6A). - Memory Read Machine Cycle
Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle
Assume the memory address for the instruction and let the content of accumulator
is C7H. So, C7H from accumulator is now stored in 526A.
Timing diagram for IN C0H.
Fetching the Opcode DBH from the memory 4125H.
Read the port address C0H from 4126H.
Read the content of port C0H and send it to the accumulator.
Let the content of port is 5EH.
Timing diagram for INR M
Fetching the Opcode 34H from the memory 4105H. (OF cycle)
Let the memory address (M) be 4250H. (MR cycle -To read Memory address and
data)
Let the content of that memory is 12H.
Increment the memory content from 12H to 13H. (MW machine cycle)
Timing diagram for MVI B, 43H.
Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
Read (move) the data 43H from memory 2001H. (memory read)
INTERRUPT STRUCTURE
Interrupt is signals send by an external device to the processor, to request the
processor to perform a particular task or work.
Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
The processor will check the interrupts always at the 2nd T-state of last machine
cycle.
If there is any interrupt it accept the interrupt and send the INTA (active low)
signal to the peripheral.
The vectored address of particular interrupt is stored in program counter.
The processor executes an interrupt service routine (ISR) addressed in program
counter.
It returned to main program by RET instruction.
Types of Interrupts:
It supports two types of interrupts.
Hardware
Software
Software interrupts:
The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.
The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.
Interrupt number * 8 = vector address
For RST 5,5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.
Hardware interrupts:
An external device initiates the hardware interrupts and placing an appropriate
signal at the interrupt pin of the processor.
If the interrupt is accepted then the processor executes an interrupt service routine.
STAX B : Store the result at destination memory location
INX D : Increment source memory pointer
INX B : Increment destination memory pointer
Flowchart for program
MOV A, C
CPI O5H : Check for last number
JNZ BACK : If not repeat
HLT : End of program
Statement: Write an assembly language program to convert the contents of the five
memory locations starting from 2000H into an ASCII character. Place the result in another
five memory locations starting from 2200H.
Sample Problem
(2000H) = 1
(2001H) = 2
(2002H) = 9
(2003H) = A
(2004H) = B
Result:(2200H) = 31
(2201H) = 32
(2202H) = 39
(2203H) = 41
(2204H) = 42
Source program:
LXI SP, 27FFH : Initialize stack pointer
LXI H, 2000H : Source memory pointer
LXI D, 2200H : Destination memory pointer
MVI C, O5H : Initialize the counter
BACK: MOV A, M : Get the number
CALL ASCII : Call subroutine ASCII
STAX D : Store result
INX H : Increment source memory pointer
INX D : Increment destination memory pointer
DCR C : Decrement count by 1
CJNZ : if not zero, repeat
HLT : Stop program execution subroutine ASCII
ASCII: CPI, OAH : Check if number is OAR
JNC NEXT : If yes go to next otherwise continue
ADI 30H
JMP LAST
NEXT: ADI 37H
LAST: RET : Return to main program
Subroutine:
Subroutine 'ASCII' converts a hexadecimal digit to ASCII.The digit is passed using
accumulator and the result is stored in accumulator.Stack starts From 27FEH to 27FDH.
Note: The ASCII Code (American Standard Code for Information Interchange) is
commonly used for communication. In such cases we need to convert binary number to its
ASCII equivalent. It is a seven bit code. In this code number 0 through 9 are represented as
30 through 39 respectively and letters A through Z are represented as 41H through 5AH.
Therefore, by adding 30H we can convert number into its ASCII equivalent and by adding
37H we can convert letter to its ASCII equivalent.
Statement: Convert the ASCII number in memory to its equivalent decimal number
Source program :
LXI H, 4150 : Point to data
MOV A, M : Get operand
SUI 30 : convert to decimal
CPI 0A : Check whether it is valid decimal number
JC LOOP : yes, store result
MVI A, FF : No, make result=FF
LOOP: INX H
MOV M, A
HLT : (A) = (4151)
Note: The ASCII Code (American Standard Code for Information Interchange) is
commonly used for communication. It is a seven bit code. In this code number 0 through 9
are represented as 30 through 39 respectively and letters A through Z are represented as
41H through 5AH. Therefore, by subtracting 30H we can convert an ASCII number into its
decimal equivalent.
Statement: Convert the HEX number in memory to its equivalent decimal number
Source program :
LXI H, 4150 ; Point to data
LXI B, 0000 ; Initialize hundreds= 0, Tens=0
MOV A, M ; Get hex data to A
LOOP: SUI 64
JC LOOP 1
INR B ; hundreds= hundreds+1
JMP LOOP
LOOP 1: ADI 64 ; if subtracted extra, add it clear carry flag
LOOP 2: SUI 0A
JC LOOP 3
INR C ; Tens=tens+1
JMP LOOP 2
LOOP 3: ADI 0A ; If subtracted extra, add it again
INX H ; A = Units
MOV M, B ; store hundreds
MOV B, A ; Combine Tens in C &
MOV A, C ; Units in A to form a
RLC ; Single 8-bit number
RLC
RLC
RLC
ADD B
INX H
MOV M, A ; Store tens & Units
HLT
Note: In this experiment the number is converted to its equivalent decimal number using
the following logic. First count the number of hundreds, the number of tens & units
present in that hex number. Then add up to get the equivalent decimal number.
Converting A9 we get:
A9 /64=45 Hundreds = 01
Since 64(100 decimal) cannot be subtracted from 45 no. of hundreds = 01. Now count tens
45/0A=3B Tens = 01 Now from 09, 0A cannot be subtracted. Hence tens = 06 the decimal
equivalent of A9 is 169.
Statement:Convert an 8 bit hex no to its binary form & store in memory
Source Program:
LXI H, 4150 : Initialize memory pointer
MVI B, 08 : count for 8-bit
MVI A, 54
LOOP : RRC
JC LOOP1
MVI M, 00 : store zero it no carry
JMP COMMON
LOOP2: MVI M, 01 : store one if there is a carry
COMMON: INX H
DCR B : check for carry
JNZ LOOP
HLT : Terminate the program
Statement: Write a program to output contents of B register LSB to MSB on the SOD pin.
Source program :
MVI C, 08H : Initialize count with 8
MOV A, B
BACK: RRC : Rotate B register contents right
MOV B, A : Save contents of register B
JNC SKIP : If no carry skip
MVI A, COH
SIM : If carry, send high on SOD
JMP NEXT
SKIP: MVI A, 40H
SIM : If no carry, send low on SOD.
NEXT: CALL DELAY : Wait for specific time
DCR C : Decrement count by 1
JNZ BACK : if count = 0 Stop, if not repeat
HLT : Stop program execution
Delay subroutine:
Delay: LXI D, Count
Back: DCX D
MOV A, D
ORA E
JNZ Back
RET
Flowchart for Program
Flowchart for Delay routine
Statement: Write a program to output square wave of 1 kHz frequency on the SOD pinof
8085 for 5 seconds. Operating frequency of 8085 is 2 MHz.
Source program :
LXI SP, 27FFH : Initialize stack pointer
LXI B, 1388H : Initialize counter with count 5000.
BACK: MVI A, COH
SIM : Send high on SOD pin
CALL DELAY : Wait for 0.5 msec
MVI A, 40H : Send low on SOD pin
CALL DELAY : wait for. 5 msec
DCX B : Decrement count by 1
MOV A, C
ORA B : Check if count = 0
JNZ BACK : If not, repeat
HLT : Stop program execution
Delay subroutine:
Delay: LXI D, Count
Back: DCX D
MOV A, D
ORA E
JNZ Back
RET
Flowchart for Program
Flowchart for Delay routine
Statement: An ASCII character is being received on SID pin of 8085. Write a program in
assembly language of 8085 to assemble this character and store it in memory. Write
comment for each instruction.
Source program :
LXI SP, 27FFH
LXI H, 2000H : Memory pointer
RIM : Read SID
ANI 80H : Check D7 bit of Accumulator
CALL Delay : 1/2 bit time delay for stop bit
MVI B, 08H : Initialize bit counter
MVI D, 00H : Clear data register
UP1: ALL Delay : 1 bit time
RIM : Read SID line
ANI 80H : Mask bits B6 - Bo
ORA D : OR data bit with previous bits
RRC
MOV D, A : Store data bit at appropriate position
DCR B
JNZ UP1
RLC : Shift left to correct result
MOV M, A : Store result
RIM : Read stop bit
ANI 8OH
CZ error : If not stop bit call error
HLT : Terminate program.
Delay subroutine:
Delay: LXI D, Count
Back: DCX D
MOV A, D
ORA E
JNZ Back
RET
Flowchart for Program
Flowchart for Delay routine
Statement: Write a assembly program to transmit a message from an 8085 to a CRT
terminal for the following requirements and draw the interfacing diagram.
i) A message of 50 characters is stored as ASCII characters (without parity) in memory
locations starting at 2200H.
ii) Baud rate x 16
iii) Stop bits 2
Solution Description:
CRT terminal uses normal RS 232C standard serial communication interface.
Therefore, to transmit data to CRT it is necessary to have RS 232C interface at the
sending end.
Fig. shows the interfacing of 8251 with RS 232C to 8085.
As shown in the Fig. three RS-232C signals (TxD, RxD are Ground) are used for
serial communication between the CRT terminal and the 8085 system.
Line drivers and receivers are used to transfer logic levels from TTL logic to RS-
232C logic.
For RS-232C the voltage level +3V to +15V is defined as logic 0 and voltage level
from -3V to -15V is defined as logic 1.
The line driver, MC 1488, converts logic 1 of TIL to approximately -9V and logic a
of TIL to approximately +9V. These levels at the receiving end are again converted
by the line receiver, MC1489, into TTL compatible logic.
Source program:
LXI H, 2200H : Initialize memory pointer to pointer the
message
MVI C, 32H : Initialize counter to send 50 characters
MVI A, 00H
OUT FFH
OUT FFH : Dummy mode word
OUT FFH
MVI A, 40H : Reset command word
OUT FFH : Reset 8251A
MVI A, CAH : Mode word initialization
OUT FFH
MVI A, 11H : Command word initialization
OUT FFH
CHECK: IN FFH
ANI 0lH : Check TxRDY
JZ CHECK : Is TxRDY I? if not, check again
MOV A, M : Get the character in accumulator
OUT FEH : Send character to the transmitter
INX H : Increment memory pointer
DCR C : Decrement counter
JNZ CHECK : if not zero, send next character
HLT : Stop program execution
Flowchart for Source Program
INTERFACING DIAGRAM
Statement:Write a assembly program to receive 25 bytes from an CRT terminal to 8085
for the following requirements.
i) Baud rate x 16
ii) Stop bits 2
Status Word:
Note: Reading of status word is necessary for checking the status of RxD line of 8085 that
whether receiver is ready to give data or not.
Source program:
LXI H, 2300 H : Initialize memory pointer
MVI C, FFH : Initialize counter to accept 25 characters
MVI A, 00H
OUT FFH
OUT FFH : Dummy mode word
OUT FFH
MVI A, 40H : Reset command word
OUT FFH : Reset 8251 A
MVI A, CAH : Mode word initialization
OUT FFH
MVI A, 14 H : Command word initialization
OUT FFH
CHECK: IN FFH
ANI 02 H : Check RxRDY
Flowchart for Source Program
JZ CHECK : Is RxRDY ? If not, check again
IN FEH : Get the character
MOV M, A : save the character
INX H : Increment memory pointer
DCR C : Decrement memory pointer
OUT FEH : Send character to the transmitter
JNZ CHECK : If not zero, accept next character
HLT : Stop program execution
Statement:Write a program to initialize 8255 in the configuration given below
Sample 1:
Write a program to initialize 8255 in the configuration given below:
1. Port A: Simple input
2. Port B: Simple output
3. Port CL: Output
4. Port Cu: Input
Assume address of the control word register of 8255 as 83H.
Solution:
Source Program 1:
MVI A, 98H : Load control word
OUT 83H : Send control word
Sample 2:
Write a program to initialize 8255 in the configuration given below:
1. Port A: Output with handshake
2. Port B: Input with handshake
3. Port CL: Output
4. Port Cu: Input
Assume address of the control word register of 8255 as 23H.
Source Program 2:
MVI A,AEH : Load control word
OUT 23H : Send control word
Statement:Write a program to blink Port C bit 0 of the 8255. Assume address of control
word register of 8255 as 83H. Use Bit Set/Reset mode.
Source Program:
BACK: MVI A, 0lH : Load bit pattern to make PCο high OUT 83H : Send it to control word register CALL DELAY : Call Delay subroutine MVI A, 00H : Load bit pattern to make PCο Low OUT 83H : Send it to control word register CALL Delay : Call Delay subroutine JMP BACK : Repeat
Delay subroutine:
Delay: LXI D, Count Back: DCX D MOV A, D ORA E JNZ Back RET
Flowchart
Statement: Design a system (both Software and Hardware) that will cause 4 LEDs to flash
10 times when a push button switch is pressed. Use 8255. Assume persistence of vision to be
0.1 seconds.
Source Program 1:
LXI SP, 2000 H : Initialize stack pointer
MVI A, 90H
OUT CR : Initialize 8255
BACK: IN PA : [Read status
ANI 01 : of push
JNZ BACK : button]
MVI B, 0AH : Initialize counter
AGAIN: MVI A, 00H : Load data to light LEDs
OUT PC : Send data on port C
CALL Delay : Call. Delay of 0.1 sec
MVI A, FFH : Load data to switch off LEDs
OUT PC : Send data on port C
CALL Delay : Call Delay of 0.1 sec
DCR B : Decrement count
JNZ AGAIN : If not zero repeat
JMP BACK : Jump back to read status
INTERFACING SCHEME
Statement: Design a microprocessor system to control traffic lights. The traffic light
arrangement is as shown in Fig. The traffic should be controlled in the following manner.
1) Allow traffic from W to E and E to W transition for 20 seconds. 2) Give transition period
of 5 seconds (Yellow bulbs ON) 3) Allow traffic from N to 5 and 5 to N for 20 seconds 4)
Give transition period of 5 seconds (Yellow bulbs ON) 5) Repeat the process.
HARDWARE FOR TRAFFIC LIGHT CONTROL
Fig. shows the interfacing diagram to control 12 electric bulbs. Port A is used to control
lights on N-S road and Port B is used to control lights on W-E road. Actual pin connections
are listed in Table 1 below.
The electric bulbs are controlled by relays. The 8255 pins are used to control relay on-off
action with the help of relay driver circuits. The driver circuit includes 12 transistors to
drive 12 relays. Fig. also shows the interfacing of 8255 to the system.
INTERFACING DIAGRAM
SOFTWARE FOR TRAFFIC LIGHT CONTROL
Source Program 1:
MVI A, 80H : Initialize 8255, port A and port B
OUT 83H (CR) : in output mode
START: MVI A, 09H
OUT 80H (PA) : Send data on PA to glow R1 and R2
MVI A, 24H
OUT 81H (PB) : Send data on PB to glow G3 and G4
MVI C, 28H : Load multiplier count (40ıο) for delay
CALL DELAY : Call delay subroutine
MVI A, 12H
OUT (81H) PA : Send data on Port A to glow Y1 and Y2
OUT (81H) PB : Send data on port B to glow Y3 and Y4
MVI C, 0AH : Load multiplier count (10ıο) for delay
CALL: DELAY : Call delay subroutine
MVI A, 24H
OUT (80H) PA : Send data on port A to glow G1 and G2
MVI A, 09H
OUT (81H) PB : Send data on port B to glow R3 and R4
MVI C, 28H : Load multiplier count (40ıο) for delay
CALL DELAY : Call delay subroutine
MVI A, 12H
OUT PA : Send data on port A to glow Y1 and Y2
OUT PB : Send data on port B to glow Y3 and Y4
MVI C, 0AH : Load multiplier count (10ıο) for delay
CALL DELAY : Call delay subroutine
JMP START
Delay Subroutine:
DELAY: LXI D, Count : Load count to give 0.5 sec delay
BACK: DCX D : Decrement counter
MOV A, D
ORA E : Check whether count is 0
JNZ BACK : If not zero, repeat
DCR C : Check if multiplier zero, otherwise repeat
JNZ DELAY
RET : Return to main program
Statement: Interface a Stepper Motor to the 8085 microprocessor system and write an
8085 assembly language program to control the Stepper Motor.
HARDWARE FOR STEPPER MOTOR CONTROL
A stepper motor is a digital motor. It can be driven by digital signal. Fig. shows the typical
2 phase motor rated 12V /0.67 A/ph interfaced with the 8085 microprocessor system using
8255. Motor shown in the circuit has two phases, with center-tap winding. The center taps
of these windings are connected to the 12V supply. Due to this, motor can be excited by
grounding four terminals of the two windings. Motor can be rotated in steps by giving
proper excitation sequence to these windings. The lower nibble of port A of the 8255 is used
to generate excitation signals in the proper sequence. These excitation signals are buffered
using driver transistors. The transistors are selected such that they can source rated
current for the windings. Motor is rotated by 1.80 per excitation.
Fig. shows the interfacing diagram to control 12 electric bulbs. Port A is used to control
lights on N-S road and Port B is used to control lights on W-E road. Actual pin connections
are listed in Table 1 below.
SOFTWARE FOR STEPPER MOTOR CONTROL
As port A is used as an output port, control word for 8255 is 80H.
Stepper Motor Control Program:
6000H Excite code DB 03H, 06H, 09H, OCH : This is the code sequence for clockwise rotation
Subroutine to rotate a stepper motor clockwise by 360° - Set the counts:
MVI C, 32H : Set repetition count to 50ıο
START: MVI B, 04H : Counts excitation sequence
LXI H, 6000H : Initialize pointer
BACK1: MOV A, M : Get the Excite code
OUT PORTA : Send Excite code
CALL DELAY : Wait
INX H : Increment pointer
DCR B : Repeat 4 times
JNZ BACK l
Delay Subroutine:
Delay: LXI D, Count
Back: DCX D
MOV A, D
ORA E
JNZ Back
RET
FLOWCHARTS
Source Program
Stepper Motor
Subroutine
Delay
Routine
Statement: Interface a 64-key matrix keyboard to the 8085 microprocessor using 8255.
Write an 8085 assembly language program to initialize 8255 and to read the key code.
HARDWARE FOR MATRIX KEYBOARD INTERFACE
Fig. shows a matrix keyboard with 64 keys connected to the 8085 microprocessor using
8255. A matrix keyboard reduces the number of connections, thus the number of
interfacing lines. In this example, the keyboard with 64 keys, is arranged in 8 x 8 (8 rows
and 8 columns) matrix. This requires sixteen lines from the microprocessor to make all the
connections instead of 64 lines if the keys are connected individually. The interfacing of
matrix keyboard requires two ports: one input port and other output port. Rows are
connected to the input port, port A and columns are connected to the output port, port B.
INTERFACING SCHEME
SOFTWARE FOR MATRIX KEYBOARD INTERFACE
As port A is used as an output port, control word for 8255 is 80H.
Source program:
MVI A, 90H : Initialize Port A as input and
OUT CR : Port B as Output
Flowchart for Source Program
START: MVI A, 00 : Make all scan lines zero
OUT PB
BACK: IN PA
CPI FF : Check for key release
JNZ BACK : If not, wait for key release
CALL DELAY : Wait for key debounce
BACK 1: IN PA
CPI FF : Check for key press
JZ BACK 1 : If not, wait for key press
CALL DELAY : Wait for key debounce
MVI L, 00H : Initialize key counter
MVI C, 08H
MVI B, FEH : Make one column low
NEXTCOL: MOV A, B
OUT PB
MVI D, 08H : Initialize row counter
IN PA : Read return line status
NEXTROW: RRC : Check for one row
JNC DISPLAY : If zero, goto display else continue
INR L : Increment key counter
DCR D : Decrement row counter
JNZ NEXTROW : Check for next row
MOV A, B
RLC : Select the next column
MOV B, A
DCR C : Decrement column count
JNZ NEXTCOL : Check for last column if not repeat
JMP START : Go to start
Delay Subroutine:
Delay: LXI D, Count
Back: DCX D
MOV A, D
ORA E
JNZ Back
RET
Delay Routine
Statement: Interface an 8-digit 7 segment LED display using 8255 to the 8085
microprocessor system and write an 8085 assembly language routine to display message on
the display.
HARDWARE FOR EIGHT DIGIT SEVEN SEGMENT DISPLAY
INTERFACE
Fig. shows the multiplexed eight 7-segment display connected in the 8085 system using
8255. In this circuit port A and port B are used as simple latched output ports. Port A
provides the segment data inputs to the display and port B provides a means of selecting a
display position at a time for multiplexing the displays. A0-A7 lines are used to decode the
addresses for 8255. For this circuit different addresses are:
PA = 00H PB = 01H
PC = 02H CR = 03H.
The register values are chosen in Fig. such that the segment current is 80 mA. This current
is required to produce an average of 10 mA per segment as the displays are multiplexed. In
this type of display system, only one of the eight display position is 'ON' at any given
instant. Only one digit is selected at a time by giving low signal on the corresponding
control line. Maximum anode current is 560 mA (7-segments x 80 mA = 560 mA), but the
average anode current is 70 mA.
INTERFACING SCHEME
SOFTWARE FOR EIGHT DIGIT SEVEN SEGMENT DISPLAY
For 8255, Port A and B are used as output ports. The control word format of 8255
according to hardware connections is:
Source program:
SOFTWARE TO INITIALIZE 8255:
MVI A, 80H : Load control word in AL
OUT CR : Load control word in CR
SUBROUTINE TO DISPLAY MESSAGE ON MULTIPLEXED LED DISPLAY:
SET UP REGISTERS FOR DISPLAY:
MVI B, 08H : load count
MVI C, 7FH : load select pattern
LXI H, 6000B : starting address of message
DISPLAY MESSAGE:
DISP 1: MOV A, C : select digit
OUT PB
MOV A, M : get data
OUT PA : display data
CALL DELAY : wait for some time
DISP 1: MOV A, C
RRC
MOV C, A : adjust selection pattern
INX H
DCR B : Decrement count
JNZ DISP 1 : repeat 8 times
RET
Note: This "display message subroutine" must be called continuously to display the 7-segment
coded message stored in the memory from address 6000H.
Delay Subroutine:
Delay: LXI D, Count
Back: DCX D
MOV A, D
ORA E
JNZ Back
RET
Statement: Interface an 8 x 8 matrix keyboard to 8085 through 8279 in 2-key lockout
mode and write an assembly language program to read keycode of the pressed key. The
external clock frequency is 2MHz. Use I/O mapped I/O technique. (Dont use any
Interrupts)
HARDWARE FOR 8 x 8 MATRIX KEYBOARD INTERFACE
SOFTWARE FOR 8 x 8 MATRIX KEYBOARD INTERFACE
The three steps needed to write the software are:
Step 1: Find keyboard/display
command word.
Step 2: Find program clock command word
Step 3: Find Read FIFO/sensor RAM command word.
Source program:
MVI A, 00H : Initialize keyboard/display
OUT 81H : in encoded scan keyboard-2 keylockout mode
MVI A, 34H
OUT 81H : Initialize prescaler count
BACK: IN 81H : Read FIFO status word
ANI 07H : Mask bit B3 to B7
JZ BACK : If 0, key is not pressed wait for key press else read FIFO
RAM
MVI A, 40H : Initialize 8279 in read
OUT 81H : FI FO RAM mode
IN 80H : Read FIFO RAM (keycode)
HLT : Stop program execution.
Flowchart
Statement: Interface an 8 x 8 matrix keyboard to 8085 through 8279 in 2-key lockout
mode and write an assembly language program to read keycode of the pressed key. The
external clock frequency is 2MHz. Use I/O mapped I/O technique.
HARDWARE FOR 8 x 8 MATRIX KEYBOARD INTERFACE(With Interrupt)
Fig. shows the interfacing of 8 x 8 matrix keyboard in interrupt driven keyboard mode. In
the interrupt driven mode interrupt line from 8279 is connected to the one of the interrupt
input of 8085 except INTR. Here, INT line from 8279 is connected to the interrupt RST 7.5
of 8085. Other signal connections are same as in the non interrupt mode.
SOFTWARE FOR 8 x 8 MATRIX KEYBOARD INTERFACE
The three steps needed to write the software are:
Step 1: Find keyboard/display command word.
Step 2: Find program clock command word
Step 3: Find Read FIFO/sensor RAM command word.
Source program:
MVI A, 00H : Initialize keyboard/display in encoded
OUT 81H : scan keyboard 2 key lockout mode
MVI A, 34H
OUT 81H : Initialize prescaler count
MVI A, 0BH : Load mask pattern to enable RST 7.5
SIM : mask other interrupts
EI : Enable Interrupt
HERE: JMP HERE : Wait for the interrupt
Interrupt Subroutine:
MVI A, 40H : Initialize 8279 in read FIFO
OUT 81H : RAM mode
IN 80H : Read FIFO RAM (keycode)
EI : Enable Interrupt
RET : Return to main program
Flowchart
Statement: Interface an 8 x 4 matrix keyboard to 8085 through 8279.
HARDWARE FOR INTERFACING 8x4 MATRIX KEYBOARD
Fig. shows the interfacing of 8 x 8 matrix keyboard in interrupt driven keyboard mode. In
the interrupt driven mode interrupt line from 8279 is connected to the one of the interrupt
input of 8085 except INTR. Here, INT line from 8279 is connected to the interrupt RST 7.5
of 8085. Other signal connections are same as in the non interrupt mode.
NOTE: As keyboard is having 8
rows and 4 columns, only 4 scan lines are required and we can avoid external decoder to
generate scan lines by selecting decoded scan keyboard mode.
SOFTWARE FOR INTERFACING 8x4 MATRIX KEYBOARD
Source program:
MVI A, 00H : Initialize keyboard/display in encoded
OUT 81H : scan keyboard 2 key lockout mode
MVI A, 34H
OUT 81H : Initialize prescaler count
MVI A, 0BH : Load mask pattern to enable RST 7.5
SIM : mask other interrupts
EI : Enable Interrupt
HERE: JMP HERE : Wait for the interrupt
Interrupt Subroutine:
MVI A, 40H : Initialize 8279 in read FIFO
OUT 81H : RAM mode
IN 80H : Read FIFO RAM (keycode)
EI : Enable Interrupt
RET : Return to main program
Statement: Interface 8/7-segment digits (common cathode) to 8085 through 8279 and write
an 8085 assembly language program to display 1 to 8 on the eight seven segment digits.
External clock frequency is 3 MHz.
HARDWARE FOR EIGHT SEVEN SEGMENT DIGITS INTERFACE
Fig. shows the interfacing of eight 7-segment digits to 8085 through 8279. As shown in the
figure eight display lines (Bo-B3 and Ao-A3) are buffered with the help of transistor and
used to drive display digits. These buffered lines are connected in parallel to all display
digits. So, Sl and S2 lines are decoded and decoded lines are used for selection of one of the
eight digits.
SOFTWARE FOR 8 x 7 SEGMENT DIGITS INTERFACE
To display 1 to 8 numbers on the eight 7-segment digits we have to load 7-segment codes
for 1 to 8 numbers in the corresponding display locations.
The three steps needed to
write the software are:
Step 1: Find keyboard/display command word.
Step 2: Find program clock command word
Step 3: Find Read FIFO/sensor RAM command word.
Source program:
LXI B, 6200B : Initialize lookup table pointer
MVI C, 08H : Initialize counter
MVI A, 00H : Initialize keyboard/display
OUT 8IH : Mode
MVI A, 3EH : Initialize pre-scalar count
OUT 8IH
MVI A, 90H : Initial size 8279 in write Display
OUT 8IH : RAM-mode
BACK : MOV A, M : Get the 7-segment code
OUT 80H : Write 7-segment code in display RAM
INX H : Increment lookup table pointer
DCR C : Decrement counter
JNZ BACK : if count = 0 stop, otherwise go to back
Flowchart
HLT : Stop program execution
Statement: Interface 4 x 4 matrix keyboard and 4 digit 7-segment display and write an
tssembly language program to read keycode of the pressed key and display same key on the
7 segment display.
HARDWARE FOR 4x4 MATRIX KEYBOARD & 4 DIGIT 7 SEGMENT
DISPLAY INTERFACE
Fig. shows interfacing diagram. Here, 4 scan lines are sufficient to scan matrix keyboard
and to select display digits. Hence decoded mode is used.
SOFTWARE FOR 4x4 MATRIX KEYBOARD & 4 DIGIT 7 SEGMENT
DISPLAY INTERFACE
To display 1 to 8 numbers on the eight 7-segment digits we have to load 7-segment codes
for 1 to 8 numbers in the corresponding display locations.
The three steps needed to write the software are:
Step 1: Find keyboard/display command word.
Step 2: Find program clock command word
Step 3: Find Read FIFO/sensor RAM command word.
Step 4: Find Write FIFO RAM command word.
Source program:
MVI A, 00H : Initialize keyboard/display in encoded
OUT 81H : scan keyboard 2 key lockout mode
MVI A, 34H
OUT 81H : Initialize pre-scalar count
MVI A, 0BH : Load mask pattern to enable RST 7.5
SIM : mask other interrupts
EI : Enable Interrupt
HERE: JMP HERE : Wait for the interrupt
Interrupt service routine:
MVI A, 40H : Initialize 8279 in read FIFO RAM mode
OUT 81H
IN 80H : Get keycode
MVI H, 62H : Initialize memory pointer to point
MOV L, A : 7-Segment code
MVI A, 80H : Initialize 8279 in write display RAM mode
OUT 81H
MOV A, M : Get the 7 segment code
OUT 80H : Write 7-segment code in display RAM
EI : Enable interrupt
RET : Return to main program
Flowchart for Source Program
and Interrupt Service Routine
Statement: Write an assembly language program to roll a message - 'HELL0123' from
right to left
To roll the above message we have to load 7-segment codes for characters within the
message and it is necessary to configure 8279 in right entry mode
Step 1: Find keyboard/display command word.
Note: DD = 10 = 8 8-bit character display right entry.
Step 2: Find program clock command word
Step 3: Find Read FIFO/sensor RAM command word.
Step 4: Find Write FIFO RAM command word.
Source program:
LXI B, 6200B : Initialize lookup table pointer
MVI C, 08H : Initialize counter
MVI A, 10H : Initialize keyboard/display in right entry mode
OUT 8IH : Mode
MVI A, 3EH : Initialize prescaler count
Flowchart for Source
Program
OUT 8IH
MVI A, D0H : Clear Display
OUT 8IH
MVI A, 90H : Initialize 8279 in write display
OUT 81H : RAM mode
BACK : MOV A, M : Get the 7-segment code
OUT 80H : Write 7-segment code in display RAM
INX H : Increment lookup table pointer
DCR C : Decrement counter
JNZ BACK : if count = 0 stop, otherwise go to back
HLT : Stop program execution
Statement: Write an assembly language program to roll a name – 'J.BINU' from right to
left
To roll the above message we have to load 7-segment codes for characters within the
message and it is necessary to configure 8279 in right entry mode
Hardware to Roll your NAME
Step 1: Find keyboard/display command word.
Note: DD = 10 = 8 8-bit character display right entry.
Step 2: Find program clock command word
Step 3: Find Read FIFO/sensor RAM command word.
Step 4: Find Write FIFO RAM command word.
Source program:
LXI B, 6200B : Initialize lookup table pointer
MVI C, 08H : Initialize counter
MVI A, 10H : Initialize keyboard/display in right entry mode
OUT 8IH : Mode
MVI A, 3EH : Initialize prescaler count
OUT 8IH
MVI A, D0H : Clear Display
OUT 8IH
MVI A, 90H : Initialize 8279 in write display
OUT 81H : RAM mode
BACK : MOV A, M : Get the 7-segment code
OUT 80H : Write 7-segment code in display RAM
INX H : Increment lookup table pointer
DCR C : Decrement counter
JNZ BACK : if count = 0 stop, otherwise go to back