Microproccesor and Microcontrollers hardware basics

Microprocessors, Microcontrollers Architecture And Programming Concepts….

Definitions

Microcomputer : A computer with a microprocessor as its CPU which includes memory and I/O etc

Microprocessor : It is a silicon chip which includes ALU, register circuits & control circuits

Microcontroller : It is again a silicon chip which includes microprocessor, memory & I/O in a single package

What is a Microprocessor?

The word comes from the combination micro and processor

Processor means a device that processes

In this context processor means a device that processes numbers, specifically binary numbers, 0’s and 1’s

To process means to manipulate

It means to perform certain operations on the numbers that depend on the microprocessor’s design

What about micro….?

Micro is a new addition……

In the late 1960’s, processors were built using discrete elements

These devices performed the required operation, but were too large and too slow

In the early 1970’s the microchip was invented

All of the components that made up the processor were now placed on a single piece of silicon

The size became several thousand times smaller and the speed became several hundred times faster

The Micro-Processor was “born”

Was there ever a “mini”-processor ?

No…

It went directly from discrete elements to a single chip i.e SILICON

However, comparing today’s microprocessors to the ones built in the early 1970’s you find an extreme increase in the amount of integration

So, the Microprocessor is a programmable device that takes in numbers, performs on them arithmetic or logical operations according to the program stored in memory and then produces other numbers as a result

Fig: Motherboard & Hardware Components

CPU: A central processing unit (CPU), is the hardware within a computer system which carries out the instructions of a computer program

ALU: In computing, an arithmetic and logic unit (ALU) is a digital circuit that performs arithmetic and logical operations , also ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors

Memory: In computing, memory refers to the physical devices used to store programs (sequences of instructions) or data (e.g. program state information) on a temporary or permanent basis for use in a computer or other digital electronic device

RAM: Random-access memory (RAM) is a form of computer data storage. A random-access device allows stored data to be accessed in very nearly the same amount of time for any storage location, so data can be accessed quickly in any random order

DRAM: Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit.

The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1

SRAM: Static random-access memory (SRAM) is a type of memory that uses bistable latching circuitry to store each bit

The term Static differentiates it from Dynamic RAM (DRAM) which must be periodically refreshed. SRAM exhibits data remanence, but data is eventually lost when the memory is not powered

ROM: Read-only memory (ROM) is a class of storage medium used in computers and other electronic devices. Data stored in ROM cannot be modified

EEPROM: EEPROM (also written E2PROM and pronounced "e-e-prom," "double-e prom," "e-squared," or simply "e-prom") stands for Electrically Erasable

PROM: Programmable Read-Only Memory and is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed

e.g, Calibration tables

PERIPHERAL: A device useful to generate either Output or to accept Input i e e.g (Display) or Input(Keyboard)

Signals

Types of Signals:

Analog Signal

Digital Signal

Analog Signal

V

t

Fig : Analog Signal

A signal that continuously varies with time is called as Analog Signal

In order to indicate the value of the signal at any instant, we require decimal numbers i.e digits 0 to 9

Digital Signal

V

t

Fig : Digital Signal

A signal that varies discretely is called as Digital Signal

It requires only two levels for representation i.e 1 or 0

There is less scope for any errors when it is to be transmitted or transferred from one device to another

It uses binary number system i.e (1 and 0)

0 represents logic low (0 Volts)

1 represents logic high (5 Volts)

V

1 0 1

t

Analog Signal Vs Digital Signal

# Analog Signal # Digital Signal

1)

2) Analog signal takes on continuous range of amplitude values

3) Analog signals create a circuit that connect to create and manipulate arbitrary electrical signals

4) Analog systems are less adaptable to variety of use

Whereas the Digital signal takes on finite set of discrete values often binary and frequently changes the values only at uniform spaced points in the time

Digital signals that create circuits tends to be easier implemented with IC technique

Digital signals are more adaptable for variety of use

Decimal Binary Octal Hexadecimal

0 0 0 0 0 0 0 0

1 0 0 0 1 0 1 1

2 0 0 1 0 0 2 2

3 0 0 1 1 0 3 3

4 0 1 0 0 0 4 4

5 0 1 0 1 0 5 5

6 0 1 1 0 0 6 6

7 0 1 1 1 0 7 7

8 1 0 0 0 1 0 8

9 1 0 0 1 1 1 9

10 1 0 1 0 1 2 A

11 1 0 1 1 1 3 B

12 1 1 0 0 1 4 C

13 1 1 0 1 1 5 D

14 1 1 1 0 1 6 E

15 1 1 1 1 1 7 F

Fig : Binary/ Octal/ Hexadecimal Counting

Number System Types

Decimal Number System:

The decimal numeral system (also called base ten or occasionally denary) has ten as its base. It is the numerical base most widely used by modern civilizations. Decimal numbers uses digits from 0..9. These are the regular numbers that we use

Example: 253810 = 2×103 + 5×102 + 3×101 + 8×100

Binary Number System:

The binary numeral system, or base-2 numeral system, represents numeric

values using two symbols: 0 and 1. More specifically, the usual base-2 system is

a positional notation with a radix of 2. i.e Binary numbers uses only 0 and 1

digits

Example: 101012 = 1×24 + 0×23 + 1×22 + 0×21 + 1×20 = 16+4+1= 21

Hexadecimal Number System:

In mathematics and computer science, hexadecimal (also base 16, or hex) is a

positional numeral system with a radix, or base, of 16

It uses sixteen distinct symbols, most often the symbols 0–9 to represent values

zero to nine,

&

A, B, C, D, E, F (or alternatively a–f) to represent values ten to fifteen

Example: The hexadecimal number 2AF3 is equal, in decimal, to:

(2 × 163) + (10 × 162) + (15 × 161) + (3 × 160)

Number System General Concept Understanding Binary and Decimal Numbers :

The binary (base two) numeral system has two possible values, often represented as 0 or 1

In contrast, the decimal (base ten) numeral system has ten possible values (0,1,2,3,4,5,6,7,8, or 9) for each place-value

For example, the binary number 10011100 may be specified as "base two" by writing it as 100111002

The decimal number 156 may be written as 15610 and read as "one hundred fifty-six, base ten"

Fig : Decimal to Binary Conversion System

Decimal to Binary: Divide by 2

* Rules :- Take the decimal number and divide it by two keeping track of the

remainder

Eg : For 11 / 2 Quotient is 5 and Remainder is 1

For 10 / 2 Quotient is 5 and Remainder is 0

Take the result and divide it by two in the same way, always keeping track of the remainder

Repeat Step 2 until you reach a result of 0. Your last step should always look like 1 / 2 = 0 r 1

Read the remainders (all 0 or 1) off in reverse order starting at the bottom with the one you just finished. This is the answer

Continued…

Decimal number:

87

87 / 2 = 43 rem 1

43 / 2 = 21 rem 1

21 / 2 = 10 rem 1

10 / 2 = 5 rem 0

5 / 2 = 2 rem 1

2 / 2 = 1 rem 0

1 / 2 = 0 rem 1

Result : (1010111)2

Decimal number:

105

105 / 2 = 52 rem 1

52 / 2 = 26 rem 0

26 / 2 = 13 rem 0

13 / 2 = 6 rem 1

6 / 2 = 3 rem 0

3 / 2 = 1 rem 1

1 / 2 = 0 rem 1

Result: (1101001)2

Note : (read remainders bottom to top):

Continued…

Decimal number:

(524.31)10 = (?)2

524 / 2 = 262 rem 0

262 / 2 = 131 rem 0

131 / 2 = 65 rem 1

65 / 2 = 32 rem 1

32 / 2 = 16 rem 0

16 / 2 = 8 rem 0

8 / 2 = 4 rem 0

4 / 2 = 2 rem 0

2 / 2 = 1 rem 0

1 / 2 = 0 rem 1

Result : (1000001100)2

Decimal number:

(.31)10

0.31 * 2 = 0.62 0

0.62 * 2 = 1.24 1

0.24 *2 = 0.48 0

0.48 *2 = 0.96 0

0.96 *2 = 1.92 1

0.92 *2 = 1.84 1

0.84 * 2 = 1.68 1

Result: (0.0100111)2

The Combine result is : (524.31) 10 = (1000001100.0100111)2

Continued…

Decimal number:

(153.61)10 = (?)2

153 / 2 = 76 rem 1

76 / 2 = 38 rem 0

38 / 2 = 19 rem 0

19 / 2 = 9 rem 1

9 / 2 = 4 rem 1

4 / 2 = 2 rem 0

2 / 2 = 1 rem 0

1 / 2 = 0 rem 1

Result : (10011001)2

Decimal number:

(.61)10

0.61 * 2 = 1.22 1

0.22 * 2 = 0.44 0

0.44 *2 = 0.88 0

0.88 *2 = 1.76 1

0.76 *2 = 1.52 1

0.52 *2 = 1.04 1

Result: (0.100111)2

The Combine result is : (524.31) 10 = (10011001. 100111)2

Continued…

Decimal number:

(37.125)10 = (?)2

37 / 2 = 18 rem 1

18 / 2 = 9 rem 0

9 / 2 = 4 rem 1

4 / 2 = 2 rem 0

2 / 2 = 1 rem 0

1 / 2 = 0 rem 1

Result : (100101)2

Decimal number :

(.125)10

0.125 * 2 = 0.25 0

0.25 * 2 = 0.5 0

0.5 *2 = 1.0 1

Result: (0.001)2

The Combine result is : (37.125) 10 = (100101.001)2

Binary to Decimal

The steps to be followed….

Multiply the binary digits with power of 2 according to their positional weight

(11100)2 = (?)10

= 1 * 24+ 1 * 2

3+1 * 2

2+ 0 * 2

1+ 0 * 2

0

= 16 + 8 + 4 + 0 + 0

= (28)10

(0.1011)2 = (?)10

= 1 * 2-1

+ 0 * 2-2

+ 1 * 2-3

+ 1 * 2-4

= 0.5 + 0 + 0.125 + 0.0625

= (0.6875)10

(11001011. 01101)2 = (?)

10 

(11001011)2

= 1 * 27

+ 1 * 26

+0 * 25

+ 0 * 24

+ 1 * 23

+ 0 * 22

+1 * 21

+ 1 * 20

= 128 + 64 + 8 + 2 + 1

= (203)10

(0.01101)2 = (?)10

= 0 * 2-1

+ 1 * 2-2

+ 1 * 2-3

+ 0 * 2-4

+ 1 * 2-5

= 0.25 + 0.125 + 0.03125

= (0.40625)10

(11001011. 01101)2 = (203.40625)

10

Decimal to HexadecimalSet of Rules:

Divide the decimal number by 16

Note the “quotient” and “remainder” as shown in the example below

Repeat the above procedure till the quotient is “zero”

The last remainder is “MSB” and the first remainder is “LSB”

(345)10 = (?)16

345 / 16 = Quo 21 rem 9

21 / 16 = Quo 1 rem 5

1 / 16 = Quo 0 rem 1

(345)10 = (159)16

(0.85)10 = (?)16

0.85 * 16 = 13.6 D

0.6 * 16 = 9.6 9

0.6 * 16 = 9.6 9

(0.85)10 = (0.D99)16

(1245.8)10 = (?)16

1245 / 16 = 77 rem 13(D)

77 / 16 = 4 rem 13(D)

4 / 16 = 0 rem 4

(1245.8)10 = (4DD)16

0.8 * 16 = 12.8 12(C)

0.8 * 16 = 12.8 12(C)

(0.8)10 = (0.CC)16

(1245.8)10 = (4DD.CC)16

Hexadecimal to DecimalSet of Rules:

Multiply the octal digits with powers of 16 according to their positional

weight

(A49)16 = (?)10

= 10 * 16 2

+ 4 * 16 1

+ 9 * 16 0

= 2560 + 64 + 9

= (2633)10

(2C.CD2)16 = (?)10

= 2 * 161 + 12 * 16

0 + 12 * 16

-1 + 13 * 16

-2 + 2 * 16

-3

= 32 + 12 + 0.75 + 0.05078125 + 0.00048828125

= (44.80126953125)10

Binary to Hexadecimal

Set of Rules:

We need to group the bits into four and write their hexadecimal equivalent …

The grouping must be done from the fraction or the decimal point on both

The sides of the point

In case of the number of bits not in the multiple of 4 the add zeroes

e.g:

(1010 0001 1101 . 1100 0101)2 = (A 1 D.C5)8

A 1 D . C 5  

Binary AdditionTo add binary numbers we follow the truth table as follows:

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Fig : Truth Table for Binary Addition

E.g :

Add (10110101) + (11101110)

1 1 1 1 1 CARRY

1 0 1 1 0 1 0 1 No 1 = (181)10

+ 1 1 1 0 1 1 1 0 No 2 = (238)10

------------------------------

1 1 0 1 0 0 0 1 1 SUM = (419)10

Binary SubtractionTo add binary numbers we follow the truth table as follows:

A B DIFFERENCE BORROW

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Fig : Truth Table for Binary Subtraction

E.g :

Sub (10110101) - (1101110)

1 0 1 1 0 1 0 1 No 1 = (181)10

- 0 1 1 0 1 1 1 0 No 2 = (110)10

1 . 1 1 1 . BORROW

------------------------------

0 1 0 0 0 1 1 1 DIFF = (71)10

One’s Compliment Subtract (35)10 - (23)10 using 1’s Compliment

35 / 2 = 17 rem 1 23 /2 = 11 rem 1

17 / 2 = 8 rem 1 11/2 = 5 rem 1

8 / 2 = 4 rem 0 5/2 = 2 rem 1

4 / 2 = 2 rem 0 2/2 = 1 rem 0

2 / 2 = 1 rem 0 1/2 = 0 rem 1

1 / 2 = 0 rem 1

So , (35)10 = (100011)2 (23)10 = (10111)2

Step 1: Take 1’s compliment of negative number

So taking 1’Compliment of negative number i.e

(23)10 = (10111)2 by subtracting each digit from 1

1 1 1 1 1 1

- 1 0 1 1 1

--------------------

1 0 1 0 0 0

Step 2: Add the positive i.e (35)10 = (100011)2

with 1’s compliment of negative number

1 0 0 0 1 1

+ 1 0 1 0 0 0

-------------------------

1 0 0 1 0 1 1

CARRY

Step 3: Since carry is generated, add the carry to

result and the result is in true form and also the

result is positive

1 1

0 0 1 0 1 1

+ 1

-------------------------

(0 0 1 1 0 0)2 = (12)10

Therefore result = (1 1 0 0)2 = (12)10

Basics of Microprocessor

When we hear the word “Microprocessor”, what comes in our

mind is small IC(Integrated Circuit)

that processes data i.e it

performs arithmetic and logical operations…..

ALU( Arithmetic and Logical Unit):

This unit is used to perform arithmetic operations (like +, - , *, /) and logical

operations like (AND, OR, EX-OR and many more..)

“A and B” are input operands while “F” is output operand

“S” are the select lines to select the lines to select the operation i.e (OPCODE)

INPUT

OPERANDS

OUTPUT

OPERANDS

OPCODE

Fig: ALU(Arithmetic Logic Unit)

ALURESULT

+ 5 Volts

Gnd

A3A2A1A1

B3B2

B1B0 S3 S2 S1 S0

F3F2

F1F0

0101

0

1

1

1

1

1

00

+5Volts

Fig: ALU Connections to implement 5 + 7

0 0 1 1

+ 5Volts

Gnd

Gnd

Opcode determines Add operation

Definitions :Opcode: A binary code, that indicates the operation to be performed is

called as an “opcode”

Operands: The data on which the operation is to be performed are termed as operands

Instruction: The combination of opcode and an operand, that can be used to instruct a system, is called as an instruction

Instruction Set: A list of all the instruction that can be issued to a system, is called as instruction set of that system

Program/Subroutine/Routine: A set of instruction written in a particular sequence, so as to implement a given task, a subroutine in assembly refers to function as in C/C++

Concept of Machine Cycle

Fig : Machine Cycle

Fig: Machine Cycle

Interrupts & Exceptions

When many I/O devices are connected to a microprocessor based system, one or more than one of the “I/O devices may request for service at a time”

The microprocessor stops the execution of the current program and gives service to the I/O devices , this feature is called as “Interrupt”

Once the I/O device is serviced, the microprocessor will continue with execution of its normal program

Contd…..

Microprocessor handles all the requests made by the peripherals following a

specific procedure in order to assure smooth functioning of the system

This procedure is known as “Interrupt Handling”

This is the procedure with the help of which the needy I/O devices conveys their service request to the processor and gets their work done

Interrupts are asynchronous events typically triggered by the external devices needing attention

Interrupts and Exceptions are alike in that both cause the processor to

temporarily suspend its present program execution in order to execute a

program of higher priority

The major difference between these two kinds of interrupts is the origin, i.e an Exception is always re-producible by re-executing with the program and data that caused the exception

An Interrupt is generally independent of the currently executing program

General procedure of Interrupt Handling:

Concern device raises the interrupt and waits for service from CPU Based on whether process is critical or higher priority work then the requested on If CPU is busy then device needs to wait else request is serviced..

Services performed by CPU:

o Determine what device wants serviceo Perform or start the service

Examples of Interrupts:

o Mouse movedo Keyboard key pressed o Printer out of papero Modem sending or receiving

Type of Interrupts

Synchronous: If it occurs at the same place, every time the program is executed with same data and memory allocation

Asynchronous: These interrupts are those that occur unexpectedly

Internal: These interrupts arise from illegal use of an instruction or data , it is also called as traps

External: These interrupts arise from I/O devices, i.e circuit generated from power supply

Software: These interrupts are initiated by executing an instruction

Exceptions

Exceptions are events that are the responses of the CPU to certain conditions detected during the execution of an instruction

It is forced transfer of control to the procedure

This mechanism allows interrupts/exceptions to be handled transparently to the executing process

1) When an interrupt is received or exception condition detection, the current task is suspended and transfer automatically goes to the procedure

2) After the procedure is complete, the interrupted task resumes without loss

of continuity

Exceptions can be classified as follows:

Fault: On generation of fault system reacts in the same as :

1) Return to the faulting instruction

2) Reported during the execution of the faulting instruction

3) Virtual Memory faults

E.g: page fault, protection

Trap: System is forced to follow the procedure on trap as :

4) Return to the next instruction after the trapping instruction

Abort: It is generally generated due to exception

5) Suspend the process at an unpredictable location

Fig: Exceptions

ISR: In systems programming an interrupt handler, also known as an Interrupt Service Routine (ISR), is a callback subroutine in microcontroller firmware

Operating system or device driver whose execution is triggered by the reception of an interrupt

Interrupt handlers have a multitude of functions, which vary based on the reason the interrupt was generated and the speed at which the interrupt handler or ISR completes its task

Vectored Interrupt:

Vectored Interrupts are type of I/O interrupts in which the device that generates the interrupt request (also called IRQ ) identifies itself directly to the processor

• Vectored interrupts can be achieved by having each I/O device a unique code

• When a device generates IRQ (Interrupt Request) , it sends its unique code over the bus to the processor

Non-Vectored Interrupt:

If a user has to provide the address of subroutine using CALL instruction when a processor is interrupted, then it is called Non- vectored interrupt

Subroutine or Functions :

It is a sequence of program instructions that perform a specific task, packaged as a unit. This unit can then be used in programs wherever that particular task should be performed. Subprograms may be defined within programs, or separately in libraries that can be used by multiple programs

Interrupts Interrupt is a process where an external device can get the attention of the

microprocessor

The process starts from the I/O device

Interrupts can be classified into two types:

Maskable (can be delayed)

Non-Maskable (can not be delayed)

An interrupt is considered to be an emergency signal

The Microprocessor should respond to it as soon as possible

When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine(ISR) to respond to the incoming interrupt

Each interrupt will most probably have its own ISR

Responding to an interrupt may be immediate or delayed , it is depending on whether the interrupt is maskable or non-maskable

Microprocessor Charactestics

The power of microprocessor is determined by following characteristics:

Processing Capability: It depends upon the number of instructions processed

Clock Frequency: The processing speed of microprocessor depends upon clock frequency

Width of Data Bus: This parameter decides word length of microcomputer

In computing, word is a term for the natural unit of data used by a particular processor

design. A word is basically a fixed-sized group of digits (binary or decimal) that are

handled as a unit by the instruction set and/or hardware of the processor

Width of Address Bus : This parameter decides memory addressing capability of the microprocessor, the maximum size of memory is decided by this parameter

I/O addressing capability: The maximum number of I/O ports accessed by the microprocessor

Data Types: The microprocessor handles various types of data formats like binary, integers etc…

Interrupt Capability: Interrupt are used to handle unpredictable and random events in the microcomputer

Microprocessor Architecture

Accumulator ALU Working Registers

Timing and clock

Stack Pointer

Program Counter

Interrupt Circuit

Fig: General Architecture of Microprocessor

Accumulator: In a computer's central processing unit (CPU), an accumulator is a register in which intermediate arithmetic and logic results are stored

ALU: In computing, an arithmetic and logic unit (ALU) is a digital circuit that performs integer arithmetic and logical operation

Working Registers: In computer architecture, a register is a small amount of storage available as part of a CPU or other digital processor

Clock signal: In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state, microprocessor speed depends on the clock

Stack Pointer: In a microprocessor, the stack can be used for both user data (such as local variables and passed parameters) and CPU data (such as return addresses when calling subroutines)

• The stack pointer stores the address of the most recent entry that was pushed onto the stack

• To push a value onto the stack, the stack pointer is incremented to point to the next physical memory address, and the new value is copied to that address in memory

Interrupt Circuit: This block accepts different interrupt request

inputs

• When a valid interrupt request is present it informs control logic to take

action in response to each signal

System bus (data, address & control signals)

Memory

Interrupt circuitrySerial I/OParallel I/O

Timing CPU

P + associated logic circuitry:

•Bus controller

•Bus drivers

•Coprocessor

•ROM (Read Only Memory)(start-up program)•RAM (Random Access Memory)

• DRAM (Dynamic RAM) - high capacity, refresh needed

• SRAM (Static RAM) - low power, fast, easy to interface

•Crystal oscillator•Timing circuitry(counters dividing to lower frequencies)

At external unexpected events, P has to interrupt the main program execution, service the interrupt request (obviously a short subroutine) and retake the main program from the point where it was interrupt.

Simple (only two wires + ground) but slow.•Printer (low resolution)•Modem•Operator’s console•Mainframe•Personal computer

Many wires, fast.•Printer (high resolution)•External memory

• Floppy Disk • Hard Disk• Compact Disk

•Other high speed devices

Fig : System Block Diagram

Interfacing Buses & Significance of Bus Width

Bus: A group of lines, pins or signals having common function is termed as bus

The number of lines in the bus is called as BUS WIDTH

In a system we come across three functions being carried out by the wires

These functions are address lines to select a memory or I/P location

These functions data lines to carry data between memory, CPU and I/O devices

Also they carry control and status signals like enabling read or write, memory or I/O etc…

Address Bus :

The bus over which the CPU sends out the address of memory location is called as Address Bus

The address may be consist of 16, 20, 24 or 32 parallel signal lines If there are N address lines, then it can directly address 2N memory

locations

Data Bus :

The data bus consists of 8, 16 or 32 parallel lines The data bus is a bi-directional bus , that means the data can get

transferred from CPU to memory and vice-versa The data bus also connects the I/O ports and CPU The number of data lines used in the data bus is equal to the size of data

word that can be written or read

Control Bus :

It is used for sending control signals to memory and I/O devices

Some of the control bus signals are as follows:

a. Memory read

b. Memory write

c. I/O read

d. I/O write

Fig 1 : Interfacing Buses

Fig 2: Interfacing Buses & Computer System

Fig: Simple Microprocessor Architecture

PC sends address to Memory Address Register

MAR points to the location of the memory where the content is to be fetched from

If the content is an instruction, IR decodes it

Applications of Microprocessor

They are used in industrial control applications , calculators, commercial appliances

It is used in CPU of a computer for controlling I/P , O/P and other devices of a computer

They are used for database management, storing information

They are used as controller for appliances and in automobiles

They are used in computers for railway, air-ticket reservations etc..

They are used to measure and control the temperature of a furnace, the pressure of boiler etc…

Types of Memories/Storage Devices

Fig : Types of Memories

Primary Memory :

Primary memory is computer memory that is directly accessible to the CPU of a computer without the use of computer's input/output channels

Primary storage is used to store data that is likely to be in active use

What is ROM? Read-only memory (ROM) is a

class of storage media used in computers

Data stored in ROM cannot be modified

ROM is a non-volatile storage. Data remains unchanged even after switching off the computer. (Wikipedia, 2007n)

E.g. EPROM, EEPROM Figure : An EPROM

What is RAM? Random access memory (RAM)

is a type of data storage used in computers

It takes the form of integrated circuits that allow the stored data to be accessed in any order (random)

Data stored in RAM can be modified

RAM is a volatile storage. Data will lose after switching off the computer

E.g. DDRam, DDR-2 Ram

Fig: Two 512 MB DDRam

Types of RAM Memories

There are two type of RAM, namely :

SRAM (Static RAM) & DRAM (Dynamic RAM)

SRAM (Static RAM) :

SRAM is made up of flip- flops SRAM is used in the cache memory SRAM is faster than DRAM

DRAM (Dynamic RAM) :

DRAM is made up of capacitors It requires Less number of components to make a one bit cell, hence also

requires less space on the silicon wafer DRAM is comparatively cheaper than SRAM Capacitors in DRAM require time for charging and discharging , charging is called

as refreshing the DRAM

Fig : DRAM & SRAM Cell Structure

Secondary Memory Secondary memory is computer memory that is not directly accessible to

the CPU of a computer

It is used to store data that is NOT in active use

It is usually slower than primary storage but it always has higher storage capacity

It is non-volatile. Data remains unchanged even after switching off the computer

Figure 14. A C-R disk.

Figure 15. A CD-RW disk.

Figure 16. A DVD-R disk.

Figure 17. A DVD+RW disk.

Fig: Secondary Memory

Cache Memory

• CPU requests contents of memory location

• Check cache for this data

• If present, get from cache (faster Memory)

• If not present, read required block from main memory to cache

• Then deliver from cache to CPU

• Cache includes tags to identify which block of main memory is in each cache slot

• Cache is small amount of fast memory

• It is situated between normal main memory and CPU

• May be located on CPU chip

Fig: Cache Memory

Cache Basics

Cache SRAMCache

Controller

Dual Ported DRAM

Controller

System DRAM

HOST CPU

Expansion Slots

Embedded Expansion

Device

Embedded Expansion

Device

Embedded Expansion

Device

Embedded Expansion

Device

Fig: Cache Architecture in a System

Implementation of cache memory subsystem is an attempt to achieve almost all accesses with zero wait state while accessing memory, but with an acceptable system cost

The cache controller maintains a directory to keep a track of the information and it has copied into the cache memory

When the processor initiates a memory read bus cycle, the cache controller checks the directory to determine if it has a copy of the requested information in cache memory

If the copy is present, the cache controller reads the information from the cache, sends

It to the processors data bus, and asserts the processor's ready signal. This is called as

READ HIT

If the cache controller determines that it does not have a copy of the requested information in its cache, the information is now read from main memory (DRAM) This is known as READ MISS and causes wait state due to slow access time of DRAM

The requested information is from the DRAM given to processor. The information is also copied into the cache memory by cache controller and it updates its directory to track the information stored in cache memory

Principles of Locality

**Definition**: Locality of reference is the term used to explain the characteristics of programs that run in relatively small loops in consecutive memory Locations

The locality of reference principle comprises of two components :

1) Temporal Locality :

Since the program have loops, the same instructions are required

frequently, i.e programs normally uses the most recently used

information again & again

If for a long time a information in cache is not used, then it is less likely to

be used again

This principal is known as temporal locality

2) Spatial Locality :

Programs and data accessed by the processor mostly reside in consecutive memory locations

This means the processor is likely to need code or data that are close to the locations already accessed

This is known as principle of Spatial Locality

Cache Performance

Performance of cache subsystems depends on the frequency of cache hits, usually termed as “Hit Rate”

If a program requires a small area of memory and consists of loops then maximum “Cache Hits” are possible

On the other hand, if the program has non-looping code, many accesses will result in “Cache Miss”

Fig: Functional Block diagram of 80386DX

Features of 80386 DX:

The 80386DX is a 32-bit processor

- i.e 32-bit processors can address upto 232 bytes of memory

- It also means that the processor can handle 32 bit code strings on every

clock cycle

- The 32 bit ALU allows to process 32-bit data

The has 32-bit address bus so, it can access up to 4 GB i.e (232 )physical memory or 64 terabytes 246 of virtual memory

The 80386DX runs with speed upto 20 MHz instructions per second

The pipelined architecture of 80386DX, allows simultaneous instruction fetching, decoding, execution and memory management

It can operate on 17 different data types

Microprocessor can operate in real mode , protection mode or variation of protection mode called as virtual 8086 mode

Microprocessor is compatible with their earlier 8086, 8088, 80186.. etc chips

Functional Block Diagram of 80386DXThe internal architecture of 80386 is divided into three sections :

Central Processing Unit

* Execution Unit

* Instruction Decode Unit

Memory Management Unit

* Segmentation Unit

* Paging Unit

Bus Interface Unit

Instruction Decode Unit:

Fig : Instruction Decode Unit

* Instruction Decode Unit:

This unit takes instruction bytes from code pre-fetch queue and translates them into microcode

The decoded instructions are then stored in the instruction queue Then they are passed to the control section for deriving necessary control

signals

* Instruction Decode Unit Continues….

Prefetcher and Prefetch Queue :

The prefetcher fetches the instruction from the external memory and stores

them in the prefetch queue to be executed further

The prefetch queue is 16-byte in size

Instruction Decoder & Decoded Instruction Queue :

The instruction decoder takes the instruction from the prefetch queue & after decoding it, stores them in the decoded instruction queue

The decoded instruction queue can store upto three decoded instructions

Execution Unit:

The execution unit reads the instruction from the instruction queue and executes the instructions. It consists of 3 subunits :

Control Unit Data Unit Protection Test Unit

• The execution unit consists of 8 , 32-bit general purpose registers for address & data

Fig : Execution Unit

* Execution Unit Continues…

Control Unit :

It contains microcode and special hardware The microcode & special hardware allows 80386DX to reduce time required

for execution of multiply & divide instructions

Data Unit :

It contains ALU, 8 , 32-bit general purpose registers & 64-Bit Barrel Shifter The Barrel Shifter is used for multiple bit shifts in 1- Clock This increases the speed of all shift and rotate operations The Multiply/Divide logic implements the bit-shift-rotate algorithm to

complete operation in minimum time The entire Data Unit is responsible for data operations requested by Control

Unit

Control ROM & Sequencing Logic :

The Control ROM provides the control signals to be issued for the corresponding instruction, which are then sequenced by Sequence Logic

The Memory Management Unit consists of

i. Segmentation Unit :

It allows the conversion of Logical Address to the Linear Address

ii. Paging Unit

It allows the conversion from Linear Address to the Physical Address if paging is

enabled

What we mean by Registers…? The main tools to write programs in x86 assembly are the Processor

Registers

The registers are like variables built in the processor

Using registers instead of memory to store values makes the process faster and cleaner

Some operations or programs need absolutely some kind of registers but, mostly they can be used freely

Programming Model of 80386

The INTEL 80386DX architecture register set has SIX 16-Bit registers & TWENTY FOUR 32-bit registers, they are divided as follows :

# Base Architecture Register :

a) General Purpose Registers

b) Instruction Pointer

c) Flag Registers

d) Segment Registers

# System Registers :

e) Memory Management Registers

f) Control Registers

# Debug & Test Registers :

g) DR0 to DR7

h) TR6 & TR7

AH AX AL

BH BX BL

CH CX CL

DH DX DL

SP

BP

DI

SI

EAX

EBX

ECX

EDX

ESP

EBP

EDI

ESI

Accumalator

Base Pointer

Counter

Data Register

Stack Pointer

Base Pointer

Destn Index

Source Index

32 Bit Names 16 Bit Names

32 Bits

IP

FLAGS

EIP

EFLAGS

16 Bits

Instn Pointer

Flag Register

CS

DS

ES

SS

FS

GS

Code SegmentData SegmentExtra Segment

Stack SegmentFig : Base Architecture Registers

General Purpose Registers

EAX 32 Bit Register

AX 16 Bit Register

AH & AL 8 Bit Register

EAX (Accumalator)

It usually accumulates the result of any ALU operation , but can be used as General Purpose Register

In 386 and above , EAX may hold an address to access a memory location

EBX (Base Index)

EBX 32 Bit Register

BX 16 Bit Register

BH & BL 8 Bit Register

It works as Base Index

In 386 and above EBX may also hold a address to access memory location

General register are the one we use most of the time

Most of the instructions perform on these registers

The "H" and "L" suffix on the 8 bit registers stand for high byte and low byte

ECX (Counter)

ECX 32 Bit Register

CX 16 Bit Register

CH & CL 8 Bit Register

It is used for repeated String Instructions, Shift, Rotate & Loop Instructions

In 386 and above ECX may also hold a address to access memory location

EDX (Data Register)

EDX 32 Bit Register

DX 16 Bit Register

DH & DL 8 Bit Register

It holds result after Multiplication or Division

In 386 and above EDX may also hold a address to access memory location

EBP (Base Pointer)

EBP 32 Bit Register

BP 16 Bit Register

It works as Random Pointer for Stack Segment

EDI (Destination Index)

EDI 32 Bit Register

DI 16 Bit Register

It holds the Destination data for String Instruction

ESI (Source Index)

ESI 32 Bit Register

SI 16 Bit Register

ESP (Stack Pointer)

ESP 32 Bit Register

SP 16 Bit Register

It is used to address memory location in the stack segment in association with Stack Segment Register

It holds the Source data for String Instruction

* Instruction Pointer :

i. The instruction pointer is a 32 bit register called as EIP

ii. It holds the offset address within a segment of next instruction to be executed

Flag Register

OF DF IF TF ZFSF AF PF CF

015

Control Flags Status Flags

IF: Interrupt enable flagDF: Direction flagTF: Trap flag

CF: Carry flagPF: Parity flagAF: Auxiliary carry flagZF: Zero flagSF: Sign flagOF: Overflow flag

Flag register contains information reflecting the current status of a Microprocessor

It also contains information which controls the operation of the Microprocessor

Fig : Flag Register

i. IF Flag : When IF =1, it allows recognition of external maskable interrupt i.e INTR pin . When IF =0, external maskable interrupt on INTR are not recognized

ii. DF Flag : It defines whether ESI(Source Index) and EDI(Destination Index) registers are auto-incremented or auto-decremented during the execution of string instructions

iii. TF Flag : When TF=1 the processor is put into single-step mode used for debugging , which allows a program to be inspected as it executes

iv. CF: The CF = 1 , if operation resulted in carryout of MSB

v. PF: The PF =1, if the lower 8 bits of the operation contain an even no of 1’s

vi. AF: It is used for BCD operations

vii. ZF: The ZF= 1 only if all bits of the result are zero

viii. SF: SF= 1, if the MSB of the result is 1 , the result is –ve i.e 0 in case of signed operation

ix. OF: The OF =1 , when a operation result in Carry/Borrow in the Sign Bit

Segment Register

Segment registers hold the segment address of various items

They are only available in 16 values

Six , 16-Bit segment registers CS, SS, DS, ES, FS, & GS holds segment selector values

In Protected Mode they are identified as currently addressable memory segments

In Real or Virtual Mode when multiplied by “10H”, provide starting address of corresponding segments

e.g:

In CS the selector indicates current Code Segment

In SS the selector indicates current Stack Segment

In DS , ES, FS, & GS indicate current four Data Segment

Memory Management Register

There are four Memory Management Registers as Follows:

i. GDTR (Global Descriptor Table Register) : It points to the segment of (64KB) in size which are common for all programs

ii. LDTR (Local Descriptor Table Register) : It points to the segment containing programs that are unique to an application

iii. TR (Task Register) : It holds a selector that accesses a descriptor that defines a Current Task to be Done

iv. IDTR (Interrupt Descriptor Table Register) : It can be loaded with instructions which get 6 byte of Data Item from memory & are used to point to GDTR and Interrupt Descriptor that points to ISR

Control & Debug RegistersThere are four Control Registers:

1) CR0

2) CR1

3) CR2

4) CR3

Only 4 of them are used for current implementations CR1 is reserved for the future use

80386DX architecture features 8 debug registers such as :

DR0 to DR7

Processing Modes of 80386Virtual Mode

Protected Mode

SMM Mode

Real Mode

VM = ‘0’ VM = ‘1’

PE = ‘1’

PE = ‘0’ SMM

RSM

Reset

Fig: Processing Modes of 80386

It is need to protect each and every application running inside the processor , when they are interfaced with “Operating System”

Therefore the processor makes certain Registers and Instructions inaccessible to the application programs

These level of Protection is done under the following three modes :

Real Mode:

* This is the mode of processor immediately after it is RESET

* It will appear to the programmers as a fast 8086 with some new

instructions

* Most applications of 80386 will use real mode for initialization only

Virtual Mode:

* It is a dynamic mode in the sense that the processor can switch repeatedly &

rapidly between Virtual & Protected Mode

* A processor is switched to virtual mode when running a DOS

application under Windows operating system

Protected Mode:

* The CPU enters Virtual Mode from Protected Mode to execute a program,

then leaves Virtual Mode and enters Protected Mode to continue executing a

native 80386 program

SMM (System Management Mode):

All the special tasks like power management, error handling and any specific platform related operations are performed

Entered in SMM by invoking SMI (System Management Interrupt)

Returns to normal execution by executing instruction RSM

RSM(Resume from System Management Mode) , Returns program control from system management mode (SMM) to the application program

Memory Management Unit :

Fig: Memory Management Unit

The memory management unit (MMU) :

Hardware device that maps Virtual address or Logical address to Physical address Note: Virtual address : Reside in the hard disk , as a pages Logical address : Generated by CPU. Programmer concern with this address. Physical address : Reside in the RAM. It is the actual address

In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory

The user program deals with logical addresses; it never sees the real physical addresses

Fig: MMU Scheme

# The memory management unit (MMU) :

• It consists of a segmentation unit & paging unit

IMP NOTE: • CPU generates logical address is given to “Segmentation Unit” which

produces linear addresses

• Linear address given to “paging unit” which generates physical address in main memory

• The segmentation unit allows the use of two address components, i.e segment and offset for relocability and sharing of code and data

• The segmentation unit allows segments of size 4 Gbytes at maximum

• The paging unit organizes the physical memory in terms of pages of 4Kbytes size each

Segmentation

A program is a collection of “Segments”

A segment is a logical unit such as:

main program procedure Function Method Object local variables, global variables Stack symbol table arrays

Fig : Logical Address generated by CPU

1Subroutine

2Stack

3Main Prog 4

Sqrt

User Space

1

4

2

3

Different Programs from CPU are placed in

Physical Memory Space i.e in RAM

Fig : Logical Address space is mapped to the Physical Address space in “Segmentation”

Fig: Example of Segmentation

Segment Selector Offset

SegmentDescriptor

+

Linear Address

Is Paging Enabled

?

Page Translation

Physical Address

015 031

031

No

Yes

Descriptor Table

Fig: Address Translation Overview

Virtual or Logical AddressLinear

Base Addr

031

The 80386DX has 3 distinct Address Spaces:

1) Logical Address(also known as Virtual Address)

2) Linear Address

3) Physical Address

A logical address consists of “Selector” & an “Offset” A selector is a content of “Segment Register” In Protected Mode, every Segment Selector has a “Linear Base Address”

associated with it & is stored in Segment Descriptor A selector is used to point a descriptor for the segment in table of descriptors The Linear Base Address from the descriptor is then added to 32-bit Offset

to generate 32-bit Linear Address, this is “Segmentation” If Paging is not enabled then 32-bit Linear Address corresponds Physical

Address But, If Paging is enabled Paging Mechanism translates Linear Address space

into the Physical Address Space by Paging Translation, this is “Paging”

Selector Offset

SegmentDescriptor

015 031

Index

0315

* 8

Access Rights (1 Byte)

Limit (20 Bits)

Base Address (32-Bits)

Segment Descriptor

Descriptor Table

RP

TI

+

Dir Page Offset

LinearAddrFig: Segment Translation

Mechanism

Linear Address= Dir + Page + Offset

The previous figure shows how selector is used to access a descriptor table..

The 13-bit index part of the “Selector” , is multiplied by “8”, & used as a pointer to the desired descriptor in a descriptor table

The index value is multiplied by 8 because each “Segment Descriptor” requires 8 bytes in the descriptor table

The “Segment Descriptor” in Descriptor Table contains mainly , Base Address, Segment Limit and access right byte

The 80386DX adds the Base Address of Segment from Segment Descriptor to the “Effective Address” OR “Offset Address” to generate Linear Address

Paging

Page 1,048,495

Page 1,048,494

. . Physical Address Space . .

Page 2

Page 1

Page 0

4 KB

4 KB

4 KB

4 KB

4 KB

Fig: Paged Organization of Physical Address Space

Paging or page translation is second phase of address translation

In this phase 80386 transforms

linear address generated by “Segmentation Unit” into physical address

Page Translation is in effect only when PG bit of CR0 is set i.e 1

When Paging enabled, the paging unit arranges the physical address space into 1,048,496 pages that are each of 4 Kb long

Paging Continues…

Directory Page Offset

31 22 21 12 11 0

Fig: Linear Address Format

Linear Address

Three components of Paging :

1) Page Directory 2) Page Table3) Page Itself

Like Segmentation , Paging is also dependable on special memory resident table i.e Page Directory & Page Table are in table form and contain 32-bit descriptor each

Page Directory & Page Table must contain exactly 1024 descriptors making each directory or page table of 4 Kb long and Page Frame is a 4 Kbyte unit of contiguous address of physical memory

When paging is enabled the linear address generated by the segment translation process is not used as a physical address

Processor internally divides a linear address into three fields :

Two fields i.e (Columns) of 10 bits each

One field i.e (Column) of 12 bits

The MSB 10 (Directory Field) bits of linear address are used as an index into a page directory

The next most significant 10 bits (Page Field) of linear address are used as index into page table determined by the page directory

The least significant 12 bits (Offset) selects one of 4 KB of memory segment from page frame determined by page table

The physical address of the current page directory is stored in the “Control Register” i.e CR3 which is referred as “Page Directory Base Register” (PDBR)

The descriptor in the page directory is referred as Page Directory Entry(PDE) The descriptor in the page table is referred as Page Table Entry(PTE)

Fig : Segmentation & Paging Unit

# The control and attribute PLA , checks the privileges at the page level

# The limit and attribute PLA, checks segment limits to avoid invalid accesses to code and data in the memory segments

The Bus Control Unit :

Fig: Bus Control Unit

The bus control unit has a prioritizer to resolve the priority of the various bus requests , this controls the access of the bus

# The address driver drives the bus enable and address signals A0-A31

# The pipeline bus sizing units handle the related control signals

Microcontroller

Microcontroller Chip

IntroductionThe Computer has three main elements :

1) Input

2) Output

3) Processor Used for calculations, handle data, memory which stores

program and data

Microprocessor: It consists of separate chips on a printed circuit board i.e PCB

Microcontroller: It contains all the elements in one chip

PIC (Peripheral Interface Controller) is a term introduced by “Microchip Technology”

Input & Output device which communicate with outside world

Lecture 21 -PIC Architecture 1339/20/6

Microcontroller Applications Automotive air bag systems

Remote control

Handheld tools

Appliances – coffee pot, mixer, stove, refrigerator, dish washer, washer, dryer

Major home systems – heating and cooling

Cordless phones and cell phones

Security systems

TV, DVD player/recorder, DVR, PVR

Sound system

Features PIC is family of low cost , high performance CMOS , fully-static

microcontroller They use Harvard Architecture which are high performance RISC

processors

Fig: Harvard Vs Von-Neumann block architectures

Complementary Metal–Oxide–Semiconductor (CMOS): It is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits

Reduced Instruction Set Computing, or RISC , is a CPU design strategy enables much faster execution of each instruction

Harvard Architecture has program memory & data memory as separate memories which are accessed through separate buses

“Bandwidth” is improved a lot in Harvard Architecture , over traditional Von-Neumann architecture in which program & data are fetched from same memory using same bus

Separate buses in Harvard Architecture allow one instruction to execute while next instruction is fetched

These Microcontrollers have reduced instruction set , which has 35 single word i.e data instructions

The instructions are “Othogonal” i.e it is possible to carry out any operation on any register using any addressing mode

High speed instruction execution The machine cycle of PIC consists of only 4 clock pulses PIC has built in power-on-reset PIC also has “Brown-Out-Reset” i.e it resets PIC when power supply voltage

drops below 4Volts PIC has “Watch-Dog” Timer , which prevents from Software Crashes PIC has power saving “Sleep Mode”, i.e it puts itself to sleep to save power during

intervals when it has nothing to do

PIC Families

PIC 10FXXX

PIC 12FXXX

PIC 16FXXX

PIC 18FXXX

PIC 24FXXX

Working Register (W)

ALU

Status (Flag) Register

Flash ROM

Program Memory8192*14

bits

Program counter

Stack 13

bits*8Levels

RAM File

Registers 368

* 8 Bits

Instruction Register

EEPROM 256 Bytes

Instruction Decode & CPU Control

Ports , Timers,ADC, Serial I/OTiming Control

File Select Register

CLK Reset

MCUControlLines

Addr

InstructionsFile Addr Prog Addr

Literal

StatusOpcode

Data Bus

Port

Fig:

PIC16F877MCUBlock Diagram

Flash ROM Program Memory: • It contains machine code , in location numbered from 0000h to 1FFFh (8k)

Program Counter: • The program counter holds address of current instruction & is incremented or

modified after each step • On reset or power up, it is reset to zero and first instruction at address 0000 is

loaded in instruction register

RAM File Register: • The program proceeds in sequence , operating on the contents of file registers,

executing data movement instructions to transfer data between ports & file registers or ALU

• RAM file register block is a set of 368, 8-bit file register• It consists of special function registers (SFR) which perform dedicated functions• It also consists of (GPR) general purpose registers

(GPR) general purpose registers :

• All general purpose registers are 8 bit registers, implemented as Static RAM• The GPR’s are accessed either directly or indirectly through “File Select Register”(FSR)• Variables in “C” Language are stored in GPR

Working registers (W) :

• The working register “W” , is 8 bits wide• It is used for ALU operations• In two operand instructions, typically one operand is in working register “W”

SFR) Special Function Registers : • The special function registers are used by CPU and other peripherals • These registers are implemented via Static RAM

Status Register: • It stores the result of operation from ALU

Timer0:• It is timer/counter register available in all PIC

Port Registers:• They are located in at the addresses 05H(Port A) to 09H(Port E) with data

direction register

Option Registers:• It is a readable and writeable register which contains various control bits to

configure “TIMER 0” register

Interrupt Control Register:• It is a readable and writeable register which contains various interrupt

enable bits , flag bits for TIMER 0 register

Address & Data Bus: • Address Bus in PIC16F877 is 14-bits wide• Data Bus is 8-bits wide

ALU:• The PIC16F877 contains 8-bit ALU, it is capable of performing arithmetic operations such as

add, subtract, shift and logical operations

Clock Modes: • The PIC16F877 microcontroller has two main clock modes CR and XT• The CR mode needs a simple capacitor and resistor circuit attached to CLKIN• In XT mode an external crystal and two capacitors are fitted to CLKIN and CLKOUT pins

Watchdog Timer: • It is usually used to prevent software crashes i.e endless loop• When enabled it automatically resets the processor after a given period• This allows a application to escape from an endless loop caused by program bug or error

EEPROM: • In EEPROM important data can be stored during power down

Power Up Timer: • This ensures that the supply voltage is stable before clock starts up

Oscillator Start Up: • Once power up process is finished , then due to the delay caused, allows the clock to stabilize

program and then execution begins

Brown Out Reset:• If supply voltage falls below 4.0 Volts , then Brown-Out detection circuit holds

Microcontroller in reset & releases it when supply has recovered

Code Protection: • The PIC Microcontroller can be configured during programming to prevent machine code

being read back from chip

In Circuit Programming and Debugging:• It allows program code to be downloaded and tested

Low voltage Programming Mode:• It allows programming mode to be programmed at +5Volts instead of +12 Volts

Microcontroller Peripherals Digital I/O

Timers

A/D converter

Comparator

Parallel slave port

Interrupts

Digital I/O

In microcontroller basic digital I/O pins are Bi-Directional

By default pin is configured as digital I/P

PIC16C6X & PIC16C7X have 5 I/O ports

i.e PORT A, PORT B, PORT C, PORT D, PORT E

Also there are 5 data direction registers

i.e TRIS A, TRIS B, TRIS C, TRIS D, TRIS E

To configure port pin as an I/P, the current driver output tristate gate is disabled by setting the corresponding data direction bit to 1

To configure port pin as an O/P, a 0 is loaded into data direction bit, enabling the current driver O/P tristate gate

Fig : Digital I/O Pin configuration

Digital I/O Ports

PORT PIN-NAME I/O PINS

Port A RA0-RA5 6 bits

Port B RB0-RB7 8 bits

Port C RC0-RC7 8 bits

Port D RD0-RD7 8 bits

Port E RE0-RE2 3 bits

Table: Digital I/O Ports

Timers

Fig : General Timer Operation

Most microcontrollers provide built-in timers It consists of hardware binary counters that allow measurement of time interval or counting to be

carried out In Timer Mode , Internal Instruction Clock is used to drive Timer Register In PIC 16F877 , Instruction Clock Frequency is 1/4th of Total Clock Frequency i.e One Instruction

takes 4 cycles to execute The Timer is Incremented after 1 Microseconds

Analog To Digital Converter

Fig : Analog to Digital Operation

Some PIC microcontrollers have built in Analog To Digital Converter (ADC)

The PIC16F877 has 10 Bit ADC with 8 Inputs, which are connected to POR A(RA0-RA3,RA5) pins & PORT E(RE0-RE2) pins

The PIC16F877 A/D module has 4 Registers :

A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL)A/D Control Register0 (ADCON0) A/D Control Register1 (ADCON1)

Comparator

Fig : Comparator Module

The PIC16F917 provides two Comparator Modules

Each Comparator Module Compares the voltage at a pair of Inputs

Status Bit is SET i.e 1 if Voltage at Vc+ Pin is Higher than Voltage at Vc- Pin

Parallel Slave Port (PSP)

Fig : Parallel Slave Port Operation

The PSP (Port D) on PIC16F877 Microcontroller allows Parallel Communications with external 8-Bit System Data Bus or Peripheral

It can directly interface to an 8-Bit Microprocessor Data Bus

Interrupts

o Interrupts can be generated by various Internal Or External Hardware Eventso There are two types of Interrupts:

Software Interrupt Hardware Interrupt

Software Interrupt:

• It comes from a Program that runs by the Processor• It requests the Processor to Stop running a Program• Goto make an Interrupt and then to return to continue to execute the Program

Hardware Interrupt:

• These are sent to Microcontroller by Hardware device• Some of Hardware Interrupts can be blocked by Interrupt Enable Bit (IE)• When Interrupt is blocked PIC Microcontroller ignores it and will not Execute it

Program Memory of PIC 16F877

PIC16F877 has two separate memory blocks, one for Data and the other for Program

EEPROM memory with GPR and SFR registers in RAM memory make up the Data Block

FLASH memory makes up the program block

Program Memory:

Program memory has been carried out in FLASH technology which makes it possible to program a microcontroller many times before it's installed into a device

Program Memory is divided into 4 pages

The Active Page is decided by Upper two Bits i.e e.g 4:3)

CALL & GOTO branch operations, instructions gives 11 bits of address

13 bit PC is capable to hold 8k*14 program memory space

Reset vector is at 000H

Interrupt vector at 0004H

Data Memory: Data memory consists of EEPROM and RAM memories EEPROM memory consists of 64 eight bit locations whose contents is not lost

during loosing of power supply Locations of RAM memory are also called GPR registers(General Purpose) SFR registers:

Registers which take up first 12 locations in banks 0 and 1 are registers of specialized function assigned with certain blocks of the microcontroller. These are called Special Function Registers

Fig: Data Memory Organization